QUARTUS 7常见错误剖析

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Quartus12007Top-leveldesignentityisundefined异常原因

Quartus12007Top-leveldesignentityisundefined异常原因好久没有⽤FPGA了，最近重新使⽤FPGA练习下数字电源。

可第⼀个Bug就花了我1个⼩时，惭愧ing。

为了以后⾃⼰能长个记性，也为了帮助学弟学妹们少⾛弯路。

因此，将这个问题记录下来。

过程：
使⽤Quattus 软件，⾃⼰建⽴⼯程并导⼊别家开发板例程的Led.V⽂件。

现象：
⾸次编译，出现下⾯的错误提⽰，添加该⽂件后再次编译，仍然报错。

可能原因：
1、没有定义Led.v⽂件
2、⼯程⾥⾯包含了Led.v⽂件。

但是，该⽂件的模块名不是⽂件名。

反思：
我检查了好⼏次，明明建的⼯程⽂件⾥⾯包含了“Led.v”⽂件，可实际编译还是这个错误提⽰。

最后检查了好久，才发现是导⼊的其他家的例程，模块名与⽂件名对不上。

这可能是与C语⾔编程的差异吧，C语⾔报错undefined，在⽂件⾥⾯定义⼀个头⽂件或者函数名就解决这个现象了。

Quartus使用问题及解决方法总结

Quartus使用问题及解决方法总结（转载）在QuartusII下进行编译和仿真的时候,会出现一堆warning,有的可以忽略,有的却需要注意,虽然按F1可以了解关于该警告的帮助,但有时候帮助解释的仍然不清楚,大家群策群力,把自己知道和了解的一些关于警告的问题都说出来讨论一下,免得后来的人走弯路.下面是我收集整理的一些,有些是自己的经验,有些是网友的,希望能给大家一点帮助,如有不对的地方,请指正,如果觉得好,请版主给点威望吧,谢谢1.Found clock-sensitive change during active clock edge at time <time> on register "<name>"原因：vector source file中时钟敏感信号（如：数据，允许端，清零，同步加载等）在时钟的边缘同时变化。

而时钟敏感信号是不能在时钟边沿变化的。

其后果为导致结果不正确。

措施：编辑vector source file2.Verilog HDL assignment warning at <location>: truncated value with size <number> to match size of target (<number>原因:在HDL设计中对目标的位数进行了设定,如:reg[4:0] a;而默认为32位,将位数裁定到合适的大小措施:如果结果正确,无须加以修正,如果不想看到这个警告,可以改变设定的位数3.All reachable assignments to data_out(10) assign '0', register removed by optimization原因:经过综合器优化后，输出端口已经不起作用了4.Following 9 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results原因:第9脚，空或接地或接上了电源措施:有时候定义了输出端口，但输出端直接赋‘0’，便会被接地，赋‘1’接电源。

Quartus常见错误警告分析

Quartus常见错误警告分析Quartus常见错误分析ErrorWarning: VHDL Process Statement warning at random.vhd(18): signal reset is in statement, but is not in sensitivity list----没把singal放到process（）中2 Warning: Found pins ing as undefined clocks and/or memory enablesInfo: Assuming node CLK is an undefined clock-=-----可能是说设计中产生的触发器没有使能端3 Error: VHDL Interface Declaration error in clk_gen.vhd(29): interface object "clk_scan" of mode outcannot be read. Change object mode to buffer or inout.------信号类型设置不对，out当作buffer来定义4 Error: Node instance "clk_gen1" instantiates undefined entity "clk_gen"-------引用的例化元件未定义实体－－entity "clk_gen"5 Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s)analyzed as buffer(s) resulting in clock skewInfo: Detected ripple clock "clk_gen:clk_gen1|clk_incr" as bufferInfo: Detected ripple clock "clk_gen:clk_gen1|clk_scan" as buffer6 Warning: VHDL Process Statement warning at ledmux.vhd(15): signal or variable "dataout" may not be assigned a new in every possible path through the Process Statement. Signal or variable "dataout" holdsits previous in every path with no new assignment, whichmay create a combinational loop in the currentdesign.7 Warning: VHDL Process Statement warning at divider_10.vhd(17): signal "cnt" is read inside the Process Statement but isn't in the Process Statement's sensivitity list -----缺少敏感信号8 Warning: No clock transition on "counter_bcd7:counter_counter_clk|q_sig[3]" register9 Warning: Reduced register "counter_bcd7:counter_counter_clk|q_sig[3]" with stuck clock port to stuckGND10 Warning: Circuit may not operate. Detected 1 non-operational path(s) clocked by clock "class[1]" withclock skew larger than data delay. See Compilation Report for details.11 Warning: Circuit may not operate. Detected 1 non-operational path(s) clocked by clock "sign" withclock skew larger than data delay. See Compilation Report for details.12 Error: VHDL error at counter_clk.vhd(90): actual port "class" of mode "in" cannot be associated withformal port "class" of mode "out"------两者不能连接起来13 Warning: Ignored node in vector source file. Can't find corresponding node name"class_sig[2]" indesign.------没有编写testbench文件，或者没有编辑输入变量的值testbench里是元件申明和映射14 Error: VHDL Binding Indication error at freqdetect_top.vhd(19): port "class" in design entity does not have std_logic_vector type that is specified for the same generic in the associated component ---在相关的元件里没有当前文件所定义的类型15 Error: VHDL error at tongbu.vhd(16): can't infer register for signal "gate" because signal does nothold its outside clock edge16 Warning: Found clock high time violation at 1000.0 ns on register"|fcounter|lpm_counter:temp_rtl_0|dffs[4]"17 Warning: Compiler packed, optimized or synthesized away node "temp[19]". Ignored vector source filenode.---"temp[19]"被优化掉了18 Warning: Reduced register "gate~reg0" with stuck data_in port to stuck GND19 Warning: Design contains 2 input pin(s) that do not drive logicWarning: No output dependent on input pin "clk"Warning: No output dependent on input pin "sign"------输出信号与输入信号无关，20 Warning: Found clock high time violation at 16625.0 ns on register "|impulcomp|gate1"21 Error: VHDL error at impulcomp.vhd(19): can't implement clock enable condition specified using binaryoperator "or"22 Error: VHDL Association List error at period_counter.vhd(38): actual parameter assigned to formal parameter "alarm", but formal parameter is not declared-------连接表错误，形参"alarm"赋值给实参，形参没定义，可能是形参与实参的位置颠倒了，规定形参在实参之前。

Quartus常见问题

Quartus常见错误1.Error (10028): Can't resolve multiple constant drivers for net ……解析：不能在两个以上always内对同一变量赋值，这个细节一般看书看资料会看到，但是编程时，就是没想到。

2.Error (10158): Verilog HDL Module Declaration error at clkseg.v(1): port"XXXX" is not declared as port解析：大意了，端口类型还没定义啊！3.Error (10110): variable "en" has mixed blocking and nonblocking ProceduralAssignments -- must be all blocking or all nonblocking assignments解析:en在程序中有时用非阻塞赋值，有时用阻塞赋值，这是禁止的。

在初学的时候，可能分得不是很清楚，所以在检查时，一定要一步步观察慢慢来。

4.Error (10161): Verilog HDL error at clkseg.v(36): object "count" is notdeclared解析：这个错误应该很明显啦，只要能读得懂。

5．Error (10170): Verilog HDL syntax error at clkseg.v(37) near text "***";expecting ";"解析：意思应该也很简单，就是检查的时候要细心点。

6.Error (10171): Verilog HDL syntax error at ir_ctrl.v(149) near end of file ;expecting an identifier, or "endmodule", or a parallel statement解析：最后上了endmodule。

自己整理的：学习verilogDHL问题笔记——Quartus常见错误

⾃⼰整理的：学习verilogDHL问题笔记——Quartus常见错误我初学verilog语⾔，很多细节都没注意，按着⾃⼰的思想就写了，编译的时候才发现各种问题。

这些都是我在学习中遇到的问题，还是很常见的。

1.Error (10028): Can't resolve multiple constant drivers for net ……解析：不能在两个以上always内对同⼀变量赋值，这个细节⼀般看书看资料会看到，但是编程时，就是没想到。

2.Error (10158): Verilog HDL Module Declaration error at clkseg.v(1): port "XXXX" is not declared as port解析：⼤意了，端⼝类型还没定义啊！3.Error (10110): variable "en" has mixed blocking and nonblocking Procedural Assignments -- must be all blocking or all nonblocking assignments解析:en在程序中有时⽤⾮阻塞赋值，有时⽤阻塞赋值，这是禁⽌的。

在初学的时候，可能分得不是很清楚，所以在检查时，⼀定要⼀步步观察慢慢来。

4.Error (10161): Verilog HDL error at clkseg.v(36): object "count" is not declared解析：这个错误应该很明显啦，只要能读得懂。

5.Error (10170): Verilog HDL syntax error at clkseg.v(37) near text "***"; expecting ";"解析：意思应该也很简单，就是检查的时候要细⼼点。

Quartus错误大全

Quartus常见错误分析1 Warning: VHDL Process Statement warning at random.vhd(18): signal reset is in statement, but is not in sensitivity list----没把singal放到process（）中2 Warning: Found pins ing as undefined clocks and/or memory enables Info: Assuming node CLK is an undefined clock-=-----可能是说设计中产生的触发器没有使能端3 Error: VHDL Interface Declaration error in clk_gen.vhd(29): interface object "clk_scan" of mode out cannot be read. Change object mode to buffer or inout.------信号类型设置不对，out当作buffer来定义4 Error: Node instance "clk_gen1" instantiates undefined entity "clk_gen" -------引用的例化元件未定义实体－－entity "clk_gen"5 Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skewInfo: Detected ripple clock "clk_gen:clk_gen1/clk_incr" as buffer Info: Detected ripple clock "clk_gen:clk_gen1/clk_scan" as buffer6 Warning: VHDL Process Statement warning at ledmux.vhd(15): signal or variable "dataout" may not be assigned a new in every possible path through the Process Statement. Signal or variable "dataout" holds its previous in every path with no new assignment, which may create a combinational loop in the current design.7 Warning: VHDL Process Statement warning at divider_10.vhd(17): signal "cnt" is read inside the Process Statement but isn''t in the Process Statement''s sensivitity list-----缺少敏感信号8 Warning: No clock transition on"counter_bcd7:counter_counter_clk/q_sig[3]" register9 Warning: Reduced register "counter_bcd7:counter_counter_clk/q_sig[3]" with stuck clock port to stuck GND10 Warning: Circuit may not operate. Detected 1 non-operational path(s) clocked by clock "class[1]" with clock skew larger than data delay. See Compilation Report for details.11 Warning: Circuit may not operate. Detected 1 non-operational path(s) clocked by clock "sign" with clock skew larger than data delay. See Compilation Report for details.12 Error: VHDL error at counter_clk.vhd(90): actual port "class" of mode "in" cannot be associated with formal port "class" of mode "out"------两者不能连接起来13 Warning: Ignored node in vector source file. Can''t find corresponding node name "class_sig[2]" in design.------没有编写testbench文件，或者没有编辑输入变量的值 testbench里是元件申明和映射14 Error: VHDL Binding Indication error at freqdetect_top.vhd(19): port "class" in design entity does not have std_logic_vector type that is specified for the same generic in the associated component---在相关的元件里没有当前文件所定义的类型15 Error: VHDL error at tongbu.vhd(16): can''t infer register for signal "gate" because signal does not hold its outside clock edge16 Warning: Found clock high time violation at 1000.0 ns on register "/fcounter/lpm_counter:temp_rtl_0/dffs[4]"17 Warning: Compiler packed, optimized or synthesized away node "temp[19]". Ignored vector source file node.---"temp[19]"被优化掉了18 Warning: Reduced register "gate~reg0" with stuck data_in port to stuck GND19 Warning: Design contains 2 input pin(s) that do not drive logic Warning: No output dependent on input pin "clk"Warning: No output dependent on input pin "sign"------输出信号与输入信号无关，20 Warning: Found clock high time violation at 16625.0 ns on register "/impulcomp/gate1"21 Error: VHDL error at impulcomp.vhd(19): can''t implement clock enable condition specified using binary operator "or"22 Error: VHDL Association List error at period_counter.vhd(38): actual parameter assigned to formal parameter "alarm", but formal parameter is not declared-------连接表错误，形参"alarm"赋值给实参，形参没定义，可能是形参与实参的位置颠倒了，规定形参在实参之前。

Quartus常见警告分析

Quartus常见警告分析1.Found clock-sensitive change during active clock edge at time<time> on register "<name>"原因：vector source file中时钟敏感信号（如：数据，允许端，清零，同步加载等）在时钟的边缘同时变化。

而时钟敏感信号是不能在时钟边沿变化的。

其后果为导致结果不正确。

措施：编辑vector source file2.Verilog HDL assignment warning at <location>: truncatedwith size <number> to match size of target (<number>原因:在HDL设计中对目标的位数进行了设定,如:reg[4:0] a;而默认为32位,将位数裁定到合适的大小措施:如果结果正确,无须加以修正,如果不想看到这个警告,可以改变设定的位数3.All reachable assignments to data_out(10) assign '0', registerremoved by optimization原因:经过综合器优化后，输出端口已经不起作用了4.Following 9 pins have nothing, GND, or VCC driving datain port --changes to this connectivity may change fitting results原因:第9脚，空或接地或接上了电源措施:有时候定义了输出端口，但输出端直接赋‘0’，便会被接地，赋‘1’接电源。

如果你的设计中这些端口就是这样用的，那便可以不理会这些warning5.Found pins ing as undefined clocks and/or memory enables原因:是你作为时钟的PIN没有约束信息。

Quartus常见问题分析

Quartus常见问题分析QuartusQuartus常见问题分析转一个，刚刚学确实会遇到不少的问题，郁闷呀。

1 Warning: VHDL Process Statement warning at random.vhd(18): signal reset is in statement, but is not in sensitivity list----没把singal放到process（）中2 Warning: Found pins ing as undefined clocks and/or memory enables Info: Assuming node CLK is an undefined clock-=-----可能是说设计中产生的触发器没有使能端3 Error: VHDL Interface Declaration error in clk_gen.vhd(29): interface object "clk_scan" of mode out cannot be read. Change object mode to buffer or inout.------信号类型设置不对，out当作buffer来定义4 Error: Node instance "clk_gen1" instantiates undefined entity"clk_gen"-------引用的例化元件未定义实体－－entity "clk_gen"5 Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skewInfo: Detected ripple clock "clk_gen:clk_gen1|clk_incr" as buffer Info: Detected ripple clock "clk_gen:clk_gen1|clk_scan" as buffer6 Warning: VHDL Process Statement warning at ledmux.vhd(15): signal or variable "dataout" may not be assigned a new in every possible path through the Process Statement. Signal or variable "dataout" holds its previous in every path with no new assignment, which may create a combinational loop in the current design.7 Warning: VHDL Process Statement warning at divider_10.vhd(17): signal "cnt" is read inside the Process Statement but isn't in the Process Statement's sensivitity list -----缺少敏感信号8 Warning: No clock transition on"counter_bcd7:counter_counter_clk|q_sig[3]" register9 Warning: Reduced register "counter_bcd7:counter_counter_clk|q_sig[3]" with stuck clock port to stuck GND10 Warning: Circuit may not operate. Detected 1 non-operational path(s)clocked by clock "class[1]" with clock skew larger than data delay. See Compilation Report for details.11 Warning: Circuit may not operate. Detected 1 non-operational path(s) clocked by clock "sign" with clock skew larger than data delay. See Compilation Report for details.12 Error: VHDL error at counter_clk.vhd(90): actual port "class" of mode "in" cannot be associated with formal port "class" of mode "out"------两者不能连接起来13 Warning: Ignored node in vector source file. Can't find corresponding node name "class_sig[2]" in design.------没有编写testbench文件，或者没有编辑输入变量的值 testbench里是元件申明和映射14 Error: VHDL Binding Indication error at freqdetect_top.vhd(19): port "class" in design entity does not have std_logic_vector type that is specified for the same generic in the associated component---在相关的元件里没有当前文件所定义的类型15 Error: VHDL error at tongbu.vhd(16): can't infer register for signal "gate" because signal does not hold its outside clock edge16 Warning: Found clock high time violation at 1000.0 ns on register "|fcounter|lpm_counter:temp_rtl_0|dffs[4]"17 Warning: Compiler packed, optimized or synthesized away node "temp[19]". Ignored vector source file node.---"temp[19]"被优化掉了18 Warning: Reduced register "gate~reg0" with stuck data_in port to stuck GND19 Warning: Design contains 2 input pin(s) that do not drive logic Warning: No output dependent on input pin "clk"Warning: No output dependent on input pin "sign"------输出信号与输入信号无关，20 Warning: Found clock high time violation at 16625.0 ns on register "|impulcomp|gate1"21 Error: VHDL error at impulcomp.vhd(19): can't implement clock enable condition specified using binary operator "or"22 Error: VHDL Association List error at period_counter.vhd(38): actual parameter assigned to formal parameter "alarm", but formal parameter is not declared-------连接表错误，形参"alarm"赋值给实参，形参没定义，可能是形参与实参的位置颠倒了，规定形参在实参之前。

Quartus常见错误

Quartus常见错误2009-10-17 17:161.Found clock-sensitive change during active clock edge at time <time> on register "<name>"原因：vector source file中时钟敏感信号（如：数据，允许端，清零，同步加载等）在时钟的边缘同时变化。

而时钟敏感信号是不能在时钟边沿变化的。

其后果为导致结果不正确。

措施：编辑vector source file2.Verilog HDL assignment warning at <location>: truncated with size <number> to match size of target (<number>原因:在HDL设计中对目标的位数进行了设定,如:reg[4:0] a;而默认为32位,将位数裁定到合适的大小措施:如果结果正确,无须加以修正,如果不想看到这个警告,可以改变设定的位数3.All reachable assignments to data_out(10) assign '0', register removed by optimization原因:经过综合器优化后，输出端口已经不起作用了4.Following 9 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results 原因:第9脚，空或接地或接上了电源措施:有时候定义了输出端口，但输出端直接赋‘0’，便会被接地，赋‘1’接电源。

如果你的设计中这些端口就是这样用的，那便可以不理会这些warning5.Found pins ing as undefined clocks and/or memory enables原因:是你作为时钟的PIN没有约束信息。

Quartus常见警告和错误集锦

我们一起爱~主页博客相册个人档案好友查看文章FPGA错误集锦2009-05-07 10:151) QuartusII对代码进行时序仿真时出现Error: Can't continue timing simulation because delay annotation information for design is missing.原因：如果只需要进行功能仿真，不全编译也是可以进行下去的，但时序仿真就必须进行全编译（即工具栏上的紫色实心三角符号那项）。

全仿真包括四个模块：综合器（Synthesis）、电路装配器（Fitter）、组装器（Assember）和时序分析器（Timing Analyzer），任务窗格中会有成功标志（对号）。

2) 在下载运行的时候，出现下面的错误：Warning: The JTAG cable you are using is not supported for Nios II systems.You may experience intermittent JTAG communicationfailures with this cable. Please use a USB Blaster revision B.在运行之前已经将.sof文件下载到开发板上面了，但是依然出现上面的问题。

解决：在配置的时候，在run之后，进行配置，选择target connection，在最后一项：NIOS II Terminal Communication Device中，要选择none（不要是Jtag_uart）如果采用USB Blaster，可以选择Jtag_uart。

之后再run就ok了！3）Error: Can't compile duplicate declarations of entity "count3" into library "work"此错误一般是原理图文件的名字和图中一个器件的名字重复所致，所以更改原理图文件的名字保存即可。

Quartus常见警告和错误

Quartus常见警告和错误【转】2009-08-07 14:00Quartus常见警告和错误1 Warning: VHDL Process Statement warning at random.vhd(18): signal reset is in statement, but is not in sensitivity list----没把singal放到process（）中2 Warning: Found pins ing as undefined clocks and/or memory enables Info: Assuming node CLK is an undefined clock-=-----可能是说设计中产生的触发器没有使能端3 Error: VHDL Interface Declaration error in clk_gen.vhd(29): interface object "clk_scan" of mode out cannot be read. Change object mode to buffer or inout.------信号类型设置不对，out当作buffer来定义4 Error: Node instance "clk_gen1" instantiates undefined entity "clk_gen" -------引用的例化元件未定义实体－－entity "clk_gen"5 Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skewInfo: Detected ripple clock "clk_gen:clk_gen1|clk_incr" as buffer Info: Detected ripple clock "clk_gen:clk_gen1|clk_scan" as buffer6 Warning: VHDL Process Statement warning at ledmux.vhd(15): signal or variable "dataout" may not be assigned a new in every possible path through the Process Statement. Signal or variable "dataout" holds its previous in every path with no new assignment, which may create a combinational loop in the current design.7 Warning: VHDL Process Statement warning at divider_10.vhd(17): signal "cnt" is read inside the Process Statement but isn't in the Process Statement's sensivitity list-----缺少敏感信号8 Warning: No clock transition on"counter_bcd7:counter_counter_clk|q_sig[3]"register9 Warning: Reduced register "counter_bcd7:counter_counter_clk|q_sig[3]" with stuck clock port to stuck GND10 Warning: Circuit may not operate. Detected 1 non-operational path(s)clocked by clock "class[1]" with clock skew larger than data delay. See Compilation Report for details.11 Warning: Circuit may not operate. Detected 1 non-operational path(s) clocked by clock "sign" with clock skew larger than data delay. See Compilation Report for details.12 Error: VHDL error at counter_clk.vhd(90): actual port "class" of mode "in"cannot be associated with formal port "class" of mode "out"------两者不能连接起来13 Warning: Ignored node in vector source file. Can't find corresponding node name "class_sig[2]" in design.------没有编写testbench文件，或者没有编辑输入变量的值 testbench里是元件申明和映射14 Error: VHDL Binding Indication error at freqdetect_top.vhd(19): port "class"in design entity does not have std_logic_vector type that is specified for thesame generic in the associated component---在相关的元件里没有当前文件所定义的类型15 Error: VHDL error at tongbu.vhd(16): can't infer register for signal "gate"because signal does not hold its outside clock edge16 Warning: Found clock high time violation at 1000.0 ns on register "|fcounter|lpm_counter:temp_rtl_0|dffs[4]"17 Warning: Compiler packed, optimized or synthesized away node "temp[19]".Ignored vector source file node.---"temp[19]"被优化掉了18 Warning: Reduced register "gate~reg0" with stuck data_in port to stuck GND19 Warning: Design contains 2 input pin(s) that do not drive logic Warning: No output dependent on input pin "clk"Warning: No output dependent on input pin "sign"------输出信号与输入信号无关，20 Warning: Found clock high time violation at 16625.0 ns on register"|impulcomp|gate1"21 Error: VHDL error at impulcomp.vhd(19): can't implement clock enable condition specified using binary operator "or"22 Error: VHDL Association List error at period_counter.vhd(38): actual parameter assigned to formal parameter "alarm", but formal parameter is not declared-------连接表错误，形参"alarm"赋值给实参，形参没定义，可能是形参与实参的位置颠倒了，规定形参在实参之前。

QuartusII7使用安装剖析

Quartus II 7.2 使用图解一．Quartus II 7.2 启动◆方法一、直接双击桌面上的图标，可以打开Quartus II 软件；◆方法二、执行：〖开始〗→〖程序〗→〖Altera〗→〖Quartus II 7.2〗→〖Quartus II 7.2 TalkBackInstall〗菜单命令，可以打开软件。

◆启动软件后，若你的电脑没有连接到Internet互联网，会出现如下图所示的提示，提示你没有连接到Altera的官方网站，将无法获得更新的资源。

点击〖确定〗继续，因为这不影响软件的正常使用。

◆若你的电脑已经正常连接到Internet互联网，则在打开软件时就不会出现以上的提示，并且可以通过软件界面右下方的两个图标：，直接连接到Altera公司的官方网站，以便获取更多的信息和资源。

二．Quartus II 7.2软件界面Quartus II 7.2软件的默认启动界面如下图所示，由标题栏、菜单栏、常用工具栏、资源管理窗口、程序编译或仿真运行状态的显示窗口、程序编译或仿真的结果显示窗口和工程编辑工作区组成。

三．Quartus II 7.2软件使用1. 新建项目工程使用QuartusII7.2设计一个数字逻辑电路，并用时序波形图对电路的功能进行仿真，同时还可以将设计正确的电路下载到可编程的逻辑器件（CPLD、FPGA）中。

因软件在完成整个设计、编译、仿真和下载等这些工作过程中，会有很多相关的文件产生，为了很好的管理这些设计文件，我们在设计电路之前，先要建立一个项目工程，并设置好这个工程能正常工作的相关条件和环境。

建立工程的方法和步骤如下：的文件夹，文件夹的命名及其保存的路径不能有中文字符。

（2）如右图点击：File菜单，选择下拉列表中的New Project Wizard...命令，打开建立项目工程的对话框。

如下图，出现第一个对话框，让你选择项目工程保存位置、定义项目名称以及设计文件顶层实体名称。

Quartus常见错误分析报告

Quartus常见错误分析2011-06-15 10:031.Found clock-sensitive change during active clock edge at time <time> on register "<name>"原因：vector source file中时钟敏感信号〔如：数据，允许端，清零，同步加载等〕在时钟的边缘同时变化。

而时钟敏感信号是不能在时钟边沿变化的。

其后果为导致结果不正确。

措施：编辑vector source file2.Verilog HDL assignment warning at <location>: truncated with size <number> to match size of target (<number> 原因:在HDL设计中对目标的位数进展了设定,如:reg[4:0] a;而默认为32位,将位数裁定到适宜的大小措施:如果结果正确,无须加以修正,如果不想看到这个警告,可以改变设定的位数3.All reachable assignments to data_out(10) assign '0', register removed by optimization原因:经过综合器优化后，输出端口已经不起作用了4.Following 9 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results原因:第9脚，空或接地或接上了电源措施:有时候定义了输出端口，但输出端直接赋‘0’，便会被接地，赋‘1’接电源。

如果你的设计中这些端口就是这样用的，那便可以不理会这些warning5.Found pins ing as undefined clocks and/or memory enables原因:是你作为时钟的PIN没有约束信息。

Quartus常见错误说明

quartus的功能仿真出错怎么办Error: Run Generate Functional Simulation Netlist (quartus_map and_gate --generate_functional_sim_netlist) to generate functional simulation netlist for top level entity "and_gate" before running the Simulator (quartus_sim）一般如果出现这些错误信息，可以作如下处理功能仿真出错你要运行下processing->Generate Functional Simulation Netlist 下再功能仿真就没有问题一、Quartus 中仿真时出现no simulation input file assignment specify 解决方法翻译成中文就是仿真文件没有被指定，要仿真的话先要建一个仿真文件: file -> new -> 选择Other file 选项卡-> Vector Waveform File 然后把输入输出端口加进去，再设置输入的信号，保存，就可以仿真了。

如果你之前已经建立过了，就打开assignments->settings->simulator settings 看里面的有个文本框simulation input 里面是否为空，为空的话就要找到你所建立的Vector Waveform File 文件，是以*.VWF 结尾的，如果没找到，你又以为你建立了Vector Waveform File ,很可能粗心的你还没保存Vector Waveform File ,保存了才会在project 里面找到。

找到之后进行仿真，如果是functional simulation，要做processing>generate functional simulation netlist..不然会出现:Error: Run Generate Functional Simulation Netlist (quartus_map bmg_control --generate_functional_sim_netlist) to generate functional simulation netlist for top level entity bmg_control before running the Simulator (quartus_sim)之类的错误。

quartus的IP仿真错误分析

quartus的IP仿真错误分析
大家都知道quartus 的IP 可以直接拿来用的，大大节省了开发时间，而且
其代码是绝对优化的；所有的前奏都操作成功，设置没什么问题，开始对生成
的fft.vhd 文件进行编译，点击Start Compilation，第一感觉：慢！编译很慢，
应该是文件太庞大了吧，需要生成很多信息，在Status 里观察进度，Full Compilation 进行至80%，报错！无奈，但没能通过EDA Netlist Writer，查找
错误信息，简单六行：
主要错误：
Error：Can’’t generate netlist outout files because the fileC：/altera/72/ip/fft/lib/auk_dspip_math_pkg_fft_72.vhd is an OpenCore Plus time-limited file.
生成网表输出文件出错。

OpenCore Plus time-limited ，在之前进行的一系列
设置里（settings）ENA Netlist Writer options 里选择的是第三方仿真软件modelsim，缘故就出在此。

在没有授权时opencore 是不允许生成Netlist 的，更
改设置：settings 里EDA Tool Settings Simulation 选择none，重新编译，通过。

接下来，理清管脚关系，进行仿真。

tips:感谢大家的阅读，本文由我司收集整编。

仅供参阅！。

QUARTUS 7常见错误剖析

QUARTUS II常见错误剖析made by lingfeng1，Error (10053): Verilog HDL error at ADDBCD.v(13): can't index object "out" with zero packed or unpacked array dimensions这个错误是由于OUT是个寄存器变量，在程序的开始忘记定义reg out 或者out寄存器变量的宽度定义错误。

2，编写好程序并进行编译后，把文件作为顶层文件然后进行波形仿真，出现对应引脚与程序中的引脚不符。

这个错误是因为把文件作为顶层文件后还要再编译一次，顶层文件才能够进行波形仿真。

否则仿真对应的文件永远是上一个顶层文件。

3，在给寄存器赋初值时，应该通过在进程中设置一个复位的单元来给寄存器变量赋初值。

4，项目导航窗口被关闭了，怎样重新打开？点击主菜单的VIEW->utility windows->project navigator(工程文件) and status(编译状态)5，Error: Can't elaborate top-level user hierarchy解决办法：看看Always中的敏感表达式是否与之后的程序相矛盾。

6，Error: Can't compile duplicate declarations of entity "class_design" into library "work"解决办法：把文件名修改成和别的文件不重复的名字。

7，Error (10219): Verilog HDL Continuous Assignment error at adder.v(9): object "cout" on left-hand side of assignment must have a net type错误原因：变量的定义类型错误。

quartus仿真出现的问题

quartus仿真出现的问题在QuartusII下进行编译和仿真的时候,会出现一堆warning,有的可以忽略,有的却需要注意,虽然按F1可以了解关于该警告的帮助,但有时候帮助解释的仍然不清楚,大家群策群力,把自己知道和了解的一些关于警告的问题都说出来讨论一下,免得后来的人走弯路.下面是我收集整理的一些,有些是自己的经验,有些是网友的,希望能给大家一点帮助,如有不对的地方,请指正,如果觉得好,请版主给点威望吧,谢谢1.Found clock-sensitive change during active clock edge at time on register ""原因：vector source file中时钟敏感信号（如：数据，允许端，清零，同步加载等）在时钟的边缘同时变化。

而时钟敏感信号是不能在时钟边沿变化的。

其后果为导致结果不正确。

措施：编辑vector source file2.Verilog HDL assignment warning at : truncated value with size to match size of target (原因:在HDL设计中对目标的位数进行了设定,如:reg[4:0] a;而默认为32位,将位数裁定到合适的大小措施:如果结果正确,无须加以修正,如果不想看到这个警告,可以改变设定的位数3.All reachable assignments to data_out(10) assign '0', register removed by optimization原因:经过综合器优化后，输出端口已经不起作用了4.Following 9 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results 原因:第9脚，空或接地或接上了电源措施:有时候定义了输出端口，但输出端直接赋‘0’，便会被接地，赋‘1’接电源。

Quartus常见问题

Quartus常见问题Quartus常见错误1.Error (10028): Can't resolve multiple constant drivers for net ……解析：不能在两个以上always内对同一变量赋值，这个细节一般看书看资料会看到，但是编程时，就是没想到。

2.Error (10158): Verilog HDL Module Declaration error at clkseg.v(1): port\解析：大意了，端口类型还没定义啊！3.Error (10110): variable \Assignments -- must be all blocking or all nonblocking assignments解析:en在程序中有时用非阻塞赋值，有时用阻塞赋值，这是禁止的。

在初学的时候，可能分得不是很清楚，所以在检查时，一定要一步步观察慢慢来。

4.Error (10161): Verilog HDL error at clkseg.v(36): object \is notdeclared解析：这个错误应该很明显啦，只要能读得懂。

5．Error (10170): Verilog HDL syntax error at clkseg.v(37) near text \expecting \解析：意思应该也很简单，就是检查的时候要细心点。

6.Error (10171): Verilog HDL syntax error at ir_ctrl.v(149) near end offile ;expecting an identifier, or \解析：最后上了endmodule。

一般编程的程序长了，到最后也就容易忘记。

7.Error (10278): Verilog HDL Port Declaration error at ir_ctrl.v(11):input port\解析：在Altra官网中就有该解释/support/kdb/solutions/rd03102021_162.html 官网上有很多东西值得我们发现学习。

Quartus常见错误

Quartus常见错误1：看看警告：it conflicts with Quartus II primitive name，实体名和QUARTUS 的保留字冲突，楼主把实体名改一下就行了。

有很多这种名字都不能乱起的比如or2 and2 啥的。

为什么还提示“Error: Top-level design entity "and2" is undefined”library ieee;use ieee.std_logic_1164.all;entity and2 isport(a,b:in std_logic;y ut std_logic);end and2;architecture and2_1 of and2 isbeginy<=a nand b;end and2_1;在设置里已经设定top-level entity为and2了怎么还是报错啊！标题：关于quartus中模块的引用2009-05-27 17:10:35quartus中一个工程中可包含一个顶层模块，多个子模块，通过顶层模块引用子模块。

1：顶层模块的实体名必须与建立工程时的实体名一致，否则编译时会出错，如下Error: Top-level design entity "AND" is undefined2，多个实体文件建立后在quartus界面左边的工程文件夹中找到要作为顶层文件的文件点击右键设置为顶层文件3.所有文件设置好后再进行编译，单独编译某个文件的话肯定错误很多。

/Detail/DefaultView.aspx?BookId=ISBN7-115-13204-6里面有一个调用模块的例子，书中间的子模块命名为NAND编译时不能通过，后来改个名字NAND11就通过了，难道NAND是关键词不可用来命名？错误为：Top-level design entity "rojectName" is undefined我已经把项目名称和顶层设计的名称设为一样的而且有时候出现这样的情况，有时候又不出现这样的情况例如下面这个例子//与非门行为描述module NAND(in1,in2,out);input in1,in2;output out;//连续赋值语句assign out=~(in1&in2);endmodule我建工程后就会提示Top-level design entity "NAND" is undefined这个例子是从电子书上直接拷贝过来的，我很好奇的是有的例子可以运行，有的例子不可以。