VCS教程

SAN JOSE STATE UNIVERSITY

College of Engineering

DEPARTMENT OF ELECTRICAL ENGINEERING

EE271

Tutorial on Using Synopsys Verilog Compiler Simulator This tutorial basically describes how to use the Synopsys Verilog Compiler Simulator (vcs) to simulate a Verilog description of a design and how to display graphical waveforms.

Apply for An Account

If you already have an account on Cadence lab then use it. There is no need for having multiple accounts. If you’re an engineering student or are taking an engineering class, you already have one UNIX account. You can (re)set your password by following the instruction at

Once you have already had an account, you can login to your account from workstations in room ENGR289 and room ENGR291. You can remote login to your account from you PC by using SSH remote Secure Shell together with the X-Server for Window software, the Exceed Hummingbird.

The Synopsys VCS Simulator

VCS (Verilog Compiler Simulator) is a tool suite from Synopsys. It includes VirSim, a graphical user interface to VCS for debugging and viewing waveforms.

The methodology of debugging your project design involves three steps:

1) Compiling your verilog source code,

2) Running the simulation, and

3) Viewing the generated waveforms.

The VCS tools will allow you to combine these steps to debug your design interactively. VCS works by compiling your Verilog source code into object files, or translating them into C source files. VCS invokes a C compiler (cc, gcc, or egcs) to create an executable file that will simulate your design. This simulator can be executed on the command line, and can create a waveform file. Alternately, the design can be simulated interactively using VirSim, and the waveforms can be viewed as you step through the simulation.

The rest of this document will give a brief overview of the tools and show you how to compile and simulate a down-counter example.

Initial Setup

The VCS package is installed at /apps/synopsys/X-2005.06-SP2/bin/vcs. For convenience, set the following environment variables to your .cshrc file. Remember that anytime you changed/modified .cshrc file, you must source it (by command “source .cshrc”) or by logging-out and then logging back in.

setenv MYPATH $PATH

setenv SYNOPSYS /apps/synopsys

setenv SNPSLMD $SYNOPSYS/Y-2006.06-SP1

setenv VCS_ARCH_OVERRIDE redhat30

setenv SYNOPSYS_SIM $SYNOPSYS/X-2005.06-SP2

setenv CLS_CSD_COMPATIBILITY_LOCKING NO

setenv SKIP_CDS_DIALOG

setenv VCS_HOME $SYNOPSYS_SIM

set path=($path $SNPSLMD/linux/bin )

set path=($path $SYNOPSYS )

set path=($path $SYNOPSYS/Y-2006.06-SP1/linux/syn/bin )

source $SYNOPSYS_SIM/bin/environ.csh

Create a directory where you want to do the tutorial and create the following three text files named count.v, test_count.v, and main_count.f in that directory. Listings of count.v and test_count.v are at the end of this tutorial. The main_count.f file has only 1 line as shown below:

test_count.v count.v

Compiling and Simulating in post-processing mode

1. Change to tutorial directory that contains count.v, test_count.v, and

main_count.f (in this tutorial it is tutorial)

2. Compile the verilog source code by typing the following at the machine prompt

/export/home/staff/thuyle/tutorial> vcs -f main_count.f option means that the file specified (

-f main_count.f

The ) contains a list of command line options for vcs. In this case, the command-line options are just a list of file names and note that the testbench is listed first. The following command line would have the same effect:

/export/home/staff/thuyle/tutorial> vcs test_count.v count.v

/export/home/staff/thuyle/tutorial> vcs -f main_count.f

Chronologic VCS (TM)

Version X-2005.06-SP2 -- Wed Oct 11 20:20:03 2006

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ALL RIGHTS RESERVED