数电课件第10次课
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CHAPTER 7
Sec.7.4 Flip-Flop Applications
Counting
Example 7-11 Determine the output waveforms.
CHAPTER 7
Sec.7.4 Flip-Flop Applications
Counting
CHAPTER 7
Chapter 8 Counters
Review
• Latch • Flip-Flop
Sec.7.3 Flip-Flop Operating Characteristics
Propagation Delay Times
A propagation delay time is the interval of time required after an input signal has been applied for the resulting output change to occur.
CHAPTER 7
Sec.7.3 Flip-Flop Operating Characteristics
Maximum Clock Frequency
The maximum clock frequency is the highest rate at which a flipflop can be reliably triggered.
CHAPTER 7
Sec.7.3 Flip-Flop Operating Characteristics
Propagation Delay Times
CHAPTER 7
Sec.7.3 Flip-Flop Operating Characteristics
Set-up Time
The set-up time is the minimum interval required for the logic levels to be maintained constantly on the inputs prior to the triggering edge of the clock pulse in order for the levels to be reliably clocked into the flipflop.
CHAPTER 7
Sec.7.3 Flip-Flop Operating Characteristics
Hold Time
The hold time is the minimum interval required for the logic levels to remain on the inputs after the triggering edge of the clock pulse in order for the levels to be reliably clocked into the flip-flop.
The power dissipation is very important in most applications in which the capacity of the dc supply is concern.
CHBaidu NhomakorabeaPTER 7
Sec.7.4 Flip-Flop Applications
CHAPTER 7
Sec.7.4 Flip-Flop Applications
Frequency Division
Dividing (reducing) the frequency of a periodic waveform
CHAPTER 7
Sec.7.4 Flip-Flop Applications
Frequency Division
CHAPTER 7
Sec.7.4 Flip-Flop Applications
Frequency Division
CHAPTER 7
Sec.7.4 Flip-Flop Applications
Counting
Figure 7–41 Flip-flops used to generate a binary count sequence. Two repetitions (00, 01, 10, 11) are shown.
…
Z1 output Zj signal
Flip-flop Output signal
Q1
D1
Flip-flop
Flip-flop
…
…
circuit
Input signal
Qm
Dm
CP
Sec.8.1 Asynchronous Counter Operation
The term asynchronous refers to events that do not have a fixed time relationship with each other and, generally, do not occur at the same time.
Parallel Data Storage
A common requirement in digital systems is to store several bits of data from parallel lines simultaneously in a group of flipflops.
Main Contents
• Synchronous Counter Operation • Asynchronous Counter Operation • Cascaded Counters • Counter Decoding
input X1 signal Xi
…
Combinational circuit
Sec.7.3 Flip-Flop Operating Characteristics
Power Dissipation
The power dissipation of any digital circuit is the total power consumption of the device.
Pulse Widths
The minimum pulse widths for reliably operation are usually specified by the manufacturer for the clock, preset, and clear inputs.
CHAPTER 7
Sec.7.4 Flip-Flop Applications
Counting
Example 7-11 Determine the output waveforms.
CHAPTER 7
Sec.7.4 Flip-Flop Applications
Counting
CHAPTER 7
Chapter 8 Counters
Review
• Latch • Flip-Flop
Sec.7.3 Flip-Flop Operating Characteristics
Propagation Delay Times
A propagation delay time is the interval of time required after an input signal has been applied for the resulting output change to occur.
CHAPTER 7
Sec.7.3 Flip-Flop Operating Characteristics
Maximum Clock Frequency
The maximum clock frequency is the highest rate at which a flipflop can be reliably triggered.
CHAPTER 7
Sec.7.3 Flip-Flop Operating Characteristics
Propagation Delay Times
CHAPTER 7
Sec.7.3 Flip-Flop Operating Characteristics
Set-up Time
The set-up time is the minimum interval required for the logic levels to be maintained constantly on the inputs prior to the triggering edge of the clock pulse in order for the levels to be reliably clocked into the flipflop.
CHAPTER 7
Sec.7.3 Flip-Flop Operating Characteristics
Hold Time
The hold time is the minimum interval required for the logic levels to remain on the inputs after the triggering edge of the clock pulse in order for the levels to be reliably clocked into the flip-flop.
The power dissipation is very important in most applications in which the capacity of the dc supply is concern.
CHBaidu NhomakorabeaPTER 7
Sec.7.4 Flip-Flop Applications
CHAPTER 7
Sec.7.4 Flip-Flop Applications
Frequency Division
Dividing (reducing) the frequency of a periodic waveform
CHAPTER 7
Sec.7.4 Flip-Flop Applications
Frequency Division
CHAPTER 7
Sec.7.4 Flip-Flop Applications
Frequency Division
CHAPTER 7
Sec.7.4 Flip-Flop Applications
Counting
Figure 7–41 Flip-flops used to generate a binary count sequence. Two repetitions (00, 01, 10, 11) are shown.
…
Z1 output Zj signal
Flip-flop Output signal
Q1
D1
Flip-flop
Flip-flop
…
…
circuit
Input signal
Qm
Dm
CP
Sec.8.1 Asynchronous Counter Operation
The term asynchronous refers to events that do not have a fixed time relationship with each other and, generally, do not occur at the same time.
Parallel Data Storage
A common requirement in digital systems is to store several bits of data from parallel lines simultaneously in a group of flipflops.
Main Contents
• Synchronous Counter Operation • Asynchronous Counter Operation • Cascaded Counters • Counter Decoding
input X1 signal Xi
…
Combinational circuit
Sec.7.3 Flip-Flop Operating Characteristics
Power Dissipation
The power dissipation of any digital circuit is the total power consumption of the device.
Pulse Widths
The minimum pulse widths for reliably operation are usually specified by the manufacturer for the clock, preset, and clear inputs.
CHAPTER 7