MV_verification

Software& System Exploration
Verification VCS with MVSIM MVRC CustomSim Low Power Methodology
• Automated LP assertions and coverage
• Multi-voltage static checks from RTL to transistor-level • Optimized power-state checking (relative always-on validation)
Routed PG netlist UPF”
3
Eclypse Seminar 2010
Power Intent Consistency Checks
Pipe-cleaning power intent
Power Intent - IEEE 1801 (UPF)
Power State Table Isolation Policy Level Shifter Policy Retention Policy
Missing, redundant, incorrect
PD 1 0.7V
LS
PD 2
ON/OFF
Missing Interchanged Illegal routing
ISO
strategy and/or implementation clk Placement, polarity, type, ISO LS ISO enable, etc PD 3 Support for state tables, 0.9V transitions, sequences Proper power / ground connectivity in PG netlist report_protection –intent [–file intent.rpt]
Debugging Failures from MVRC Report Crossprobe selected error
Missing Isolation Cell
Missing Isolation Cell
11
Eclypse Seminar 2010
New MVRC Wizard
Simplifies Setup
Reports
14
Eclypse Seminar 2010
MVRC: Under the Hood
RTL UPF Liberty (.db) • Compiles the RTL files and UPF • Checks and reports syntax and • semantic Reads theerrors initial compiled database • Elaborates design • Creates a multidatabase • voltage Performs structural and power architecture checks on design • Generates reports
Eclypse Seminar 2010
Multi-Voltage Rule Checking & Simulation
May 2010
Eclypse Seminar 2010
1
Eclypse Low Power Solution
Power-aware Verification
• Voltage-level aware simulation
Services Comprehensive verification of advanced LP techniques
2
Eclypse Seminar 2010
C RTL IEEE 1801
● ●
Power-aware Implementation
Power-aware Signoff
MVRC Low Power Static Rule Checker
apdb
MVCMP (Parsing the design) MVDBGEN (Multi-Voltage Elaboration)
MVRC (Static Checks)
Reports
15
Eclypse Seminar 2010
RTL Checks: Suggested commands
# Read the MV Database read_db
4
Eclypse Seminar 2010
Library Consistency Checks
Design (RTL,GL, or PG Netlist) Operating Corner in UPF Operating Corner in Library
MVRC
Mismatch Report
• Operating point in UPF should be subset of that in Library
• Used at netlist stage
Most report_* commands have “-file” option, to send output to a file
9
Eclypse Seminar 2010
Modeling Multi-Voltage Connectivity
1.2V 1.0V 0.9V
• Includes connectivity tracing
6
Eclypse Seminar 2010
Architectural Checks
• Critical functional signals and UPF control signals automatically checked
– – – – – – – – – Clock Clock Enable Reset Scan Enable Isolation Enable Power Enable Power OK Retention Save Retention Restore
Domain 4 1.2V 1.2V 1.2V
1.2V Off Off
Mode2
Memory
Mode3
IO Control Real Time Clock (Battery) ISO_EN
Power Management Unit
Check on ISO_EN signal shows island ordering (i.e., relative alwayson) error: PMU is OFF in Mode 3
MVRC
Mismatch Report
report_protection -critique -no_design_checks
Examples… • Isolation needed but not specified • Isolation specified but not needed • Multiple rails transitioning during power state transitions
INACTIVE POWER DOMAIN
CRITICAL SIGNAL
ACTIVE POWER DOMAIN
report_architecture –island_order
• Users can also add their own signals
report_architecture –island_order -signal <signal_root_pin>
– Voltage_map attribute in Liberty referenced
• Checks on all cell types
– Isolation cells, level shifters, power switches, retention cells, always-on cells, standard cells
Cell level pins must be associated with chip level supply voltages connect_supply_net (UPF) set_related_supply_net (UPF extension)
V2_VDD V1_VDD V3_VDD
12
Eclypse Seminar 2010
Partial Schematic Display
Simplifies Debug
Full Schematic Partial Schematic
Partial Schematic Displays Only Relevant Cross-Over Information
– No testbench or sim cycles needed
UPF’
IC Compiler Architectural, Structural, Functional, PG, & Transistor Checks
MVRC can be used for any design phase
8
Eclypse Seminar 2010
Structural Checks
Checks ISO/LS requirements,
based on PST and UPF strategies, against power management (PM) elements implemented in the design
Implementation
RTL UPF
MVRC
UPF & Library Consistency Checks, and Architectural Checks