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VHDL各种计数器程序

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vhdl加法计数器

vhdl加法计数器

6、编写一个4位加法计数器VHDL源程序，要求：复位信号reset低电平清零，变高后在clk上升沿开始工作，输入时钟信号为clk，输出为q。

(以十二进制为例)LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY counter ISPORT(clk,reset:IN STD_LOGIC;q:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));END ENTITY priorityencoderARCHITECTURE rtl OF counter ISSIGNAL count: STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINq<=cout;PROCESS(clk,reset)ISBEGINIF(reset=’0’)THENcout<="0000";ELSIF(clk’EVENT AND clk=’1’)THENIF(cout="1011")THENcout<="0000"ELSEcout<=cout+’1’;END IF;END IF;END PROCESS;END ARCHITECTURE rtl;4位二进制并行加法器的源程序ADDER4B.VHDLIBRARY IEEE；USE IEEE.STD_LOGIC_1164.ALL；USE IEEE.STD_LOGIC_UNSIGNED.ALL；ENTITY ADDER4B IS --4位二进制并行加法器PORT(CIN：IN STD_LOGIC；--低位进位A：IN STD_LOGIC_VECTOR(3 DOWNTO 0)；--4位加数B：IN STD_LOGIC_VECTOR(3 DOWNTO 0)；--4位被加数S：OUT STD_LOGIC_VECTOR(3 DOWNTO 0)；--4位和CONT：OUT STD_LOGIC)；END ADDER4B；ARCHITECTURE ART OF ADDER4B ISSIGNAL SINT：STD_LOGIC_VECTOR(4 DOWNTO 0)；SIGNAL AA，BB：STD_LOGIC_VECTOR(4 DOWNTO 0)；BEGINAA<='0'& A；--将4位加数矢量扩为5位，为进位提供空间BB<='0'& B；--将4位被加数矢量扩为5位，为进位提供空间SINT<=AA+BB+CIN ；S<=SINT(3 DOWNTO 0)；CONT<=SINT(4)；END ART；8位二进制加法器的源程序ADDER8B.VHDLIBRARY IEEE；USE IEEE_STD.LOGIC_1164.ALL；USE IEEE_STD.LOGIC_UNSIGNED.ALL：ENTITY ADDER8B IS--由4位二进制并行加法器级联而成的8位二进制加法器PORT(CIN：IN STD_LOGIC；A：IN STD_LOGIC_VECTOR(7 DOWNTO 0)；B：IN STD_LOGIC_VECTOR(7 DOWNTO 0)；S：OUT STD_LOGIC_VECTOR(7 DOWNTO 0)；COUT：OUT STD_LOGIC)；END ADDER8B；ARCHICTURE ART OF ADDER8B ISCOMPONENET ADDER4B--对要调用的元件ADDER4B的界面端口进行定义PORT(CIN：IN STD_LOGIC；A：IN STD_LOGIC_VECTOR(3 DOWNTO 0)；B：IN STD_LOGIC_VECTOR(3 DOWNTO 0)；S：OUT STD_LOGIC_VECTOR(3 DOWNTO 0)；CONT：OUT STD_LOGIC)；END COMPONENT ；SIGNAL CARRY_OUT：STD_LOGIC；--4位加法器的进位标志BEGINU1：ADDER4B --例化(安装)一个4位二进制加法器U1PORT MAP(CIN=>CIN，A=>A(3 DOWNTO 0)，B=>B(3DOWNTO0)，S=>S(3 DOWNTO 0)，COUT=>CARRY_OUT)；U2：ADDER4B --例化(安装)一个4位二进制加法器U2PORT MAP(CIN=>CARRY_OUT，A=>A(7 DOWNTO 4)，B=>B(7 DOWNTO 4)，S=>S (7 DOWNTO 4)；CONT=>CONT)；END ART；六进制计数器的源程序CNT6.VHD(十进制计数器的源程序CNT10.VHD与此类似)LIBRARY IEEE；USE IEEE.STD_LOGIC_1164.ALL；USE IEEE.STD_LOGIC_UNSIGNED.ALL；ENTITY CNT6 ISPORT (CLK：IN STD_LOGIC；CLR：IN STD_LOGIC；ENA：IN STD_LOGIC；CQ：OUT STD_LOGIC_VECTOR(3 DOWNTO 0)；CARRY_OUT：OUT STD_LOGIC )；END CNT6；ARCHITECTURE ART OF CNT6 ISSIGNAL CQI：STD_LOGIC_VECTOR(3 DOWNTO 0)；BEGINPROCESS(CLK，CLR，ENA)BEGINIF CLR='1' THEN CQI<="0000"；ELSIF CLK'EVENT AND CLK='1' THENIF ENA='1' THENIF CQI=“0101” THEN CQI<=“0000”；ELSE CQI<=CQI+'1'；END IF；END IF；END IF；END PROCESS；PROCESS(CQI)BEGINIF CQI=“0000” THEN CARRY_OUT<='1'；ELSE CARRY_OUT<='0'；END IF；END PROCESS；CQ<=CQI；END ART；十进制计数器LIBRARY ieee;USE ieee.std_logic_1164.ALL;USE ieee.std_logic_unsigned.ALL;ENTITY count10 ISPORT(clk: IN STD_LOGIC;seg: OUT STD_LOGIC_VECTOR(6 DOWNTO 0)); END count10;ARCHITECTURE a1 OF count10 ISsignal sec: STD_LOGIC; signal q : STD_LOGIC_VECTOR(21 DOWNTO 0);signal num: STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINprocess(clk) ----get 1 hz clock pulsebeginif clk'event and clk='1' then q<=q+1; end if;sec<=q(21); --get 1 hz clock pulseend process;timing: process(sec) beginif sec'event and sec='1' thenif num<9 then num<=num+1; else num<="0000"; end if;end if;end process;B1: block --bcd-7segsBegin --gfedcbaseg<= "0111111" when num=0 else"0000110" when num=1 else"1011011" when num=2 else"1001111" when num=3 else"1100110" when num=4 else"1101101" when num=5 else"1111101" when num=6 else"0000111" when num=7 else"1111111" when num=8 else"1101111" when num=9 else"0000000";end block;END a1;四位全加器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity add isport(a,b:in std_logic_vector(3 downto 0);cin:in std_logic;s:out std_logic_vector(3 downto 0);cout:out std_logic);end add;architecture beh of add isbeginprocess(a,b,cin)ariable x:std_logic_vector(3 downto 0);variable m,n,l:integer;beginm:=conv_integer(a);n:=conv_integer(b);l:=m+n+conv_integer(cin);x:=conv_std_logic_vector(l,4);s<=x(3 downto 0);cout<=x(3);end process;end beh;10位计数器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CNT10 ISPORT ( CLK ,clr : IN STD_LOGIC ;CQ : OUT STD_LOGIC_VECTOR ( 3 DOWNTO 0 ));END ENTITY CNT10;ARCHITECTURE ONE OF CNT10 ISBEGINPROCESS ( CLK , clr )V ARIABLE LCQ : STD_LOGIC_VECTOR ( 3 DOWNTO 0 ); BEGINIF RST = …1‟ THEN LCQ := “0000”;ELSIF CLK‟EVENT AND CLK = …1‟ THENIF LCQ < 9 THEN LCQ := LCQ + 1;ELSE LCQ := “0000” ;END IF; END IF;CQ <= LCQ ;END PROCESS;END ARCHITECTURE ONE;八位串行二进制全加器use ieee.std_logic_1164.all;entity product_adder_subtracter isport(a,b:in std_logic_vector(7 downto 0);s:out std_logic_vector(8 downto 0));end;architecture behavioral of product_adder_subtracter isbeginbehavior:process(a,b) isvariable carry_in:std_logic;variable carry_out:std_logic;variable op2:std_logic_vector(b'range);beginop2:=b;end if;for index in 0 to 7 loopcarry_in:=carry_out;s(index)<=a(index) xor op2(index)xor carry_in ;carry_out:=(a(index)and op2(index))or(carry_in and (a(index) xor op2(index)));end loop;s(8)<=a(7) xor op2(7) xor carry_out;end process;end;8、根据已给出全加器VHDL程序，试写出一个四位逐位进位加法器的VHDL源程序。

2位2进制计数器vhdl代码

2位2进制计数器vhdl代码

2位2进制计数器VHDL代码1. 介绍2位2进制计数器是一种广泛用于数字电路设计和嵌入式系统开发中的基本电路。

它可以在数字系统中实现对二进制计数的功能，常用于控制信号发生器、时序逻辑和状态机等应用场景。

本文将深入探讨2位2进制计数器的VHDL代码实现，并对其进行全面评估和分析。

2. 基本概念在开始编写VHDL代码之前，我们首先需要了解2位2进制计数器的基本概念。

2位2进制计数器可以实现对二进制数00、01、10、11的循环计数，并在每次计数完成后进行自动重置。

其基本结构包括两个触发器和逻辑门，通过时钟信号和控制信号进行计数和重置操作。

在VHDL代码中，我们需要定义计数器的输入、输出和内部逻辑，并编写时序逻辑实现循环计数和自动重置功能。

3. VHDL代码实现在VHDL代码中，我们首先需要定义2位2进制计数器的输入信号（时钟）和输出信号（计数值），并声明内部变量和逻辑控制信号。

接下来，我们使用时序逻辑描述计数器的计数过程，并在适当的时机对计数值进行重置。

具体的VHDL代码如下：```vhdllibrary IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity binary_counter isPort ( clk : in STD_LOGIC;reset : in STD_LOGIC;count : out STD_LOGIC_VECTOR (1 downto 0)); end binary_counter;architecture Behavioral of binary_counter issignal temp_count : STD_LOGIC_VECTOR (1 downto 0); beginprocess(clk, reset)beginif reset = '1' thentemp_count <= "00";elsif rising_edge(clk) thentemp_count <= temp_count + 1;end if;end process;count <= temp_count;end Behavioral;```在以上的VHDL代码中，我们定义了一个名为binary_counter的实体，包括时钟信号（clk）、复位信号（reset）和计数信号（count）。

VHDL各种计数器程序全新

VHDL各种计数器程序全新

1. 具有CLK，Q端口的简单加法计数器，要程序和最后的RTL图；LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CNT4 ISPORT ( CLK : IN STD_LOGIC;Q : OUT INTEGER RANGE 15 DOWNTO 0);END;ARCHITECTURE behav OF CNT4 ISSIGNAL D,Q1 : INTEGER RANGE 15 DOWNTO 0;BEGINPROCESS (CLK)BEGINIF CLK'EVENT AND CLK='1'THEN Q1<=D;END IF;END PROCESS;D<=Q1+1;Q<=Q1;END behav;2. 具有异步清零aclr，CLK，Q端口的加法计数器，要程序和最后的RTL图；LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL ;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CNT4 ISPORT ( CLK,ACLR : IN STD_LOGIC;Q : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)); END ;ARCHITECTURE behav OF CNT4 ISSIGNAL Q1 : STD_LOGIC_VECTOR(15 DOWNTO 0);BEGINPROCESS (CLK,ACLR)BEGINIF ACLR='0' THENQ1<=(OTHERS=>'0');ELSIF CLK'EVENT AND CLK='1' THENQ1<=Q1+1;END IF;END PROCESS;Q<=Q1;END behav;3. 具有同步清零sclr，CLK，Q端口的加法计数器，要程序和最后的RTL图；LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL ;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CNT4 ISPORT ( CLK,SCLR : IN STD_LOGIC;Q : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)); END ;ARCHITECTURE behav OF CNT4 ISSIGNAL Q1 : STD_LOGIC_VECTOR(15 DOWNTO 0);BEGINPROCESS (CLK,SCLR)BEGINIF CLK'EVENT AND CLK='1' THENIF SCLR='1' THENQ1<=(OTHERS=>'0');ELSEQ1<=Q1+1;END IF;END IF;END PROCESS;Q<=Q1;END behav;4. 具有异步置位apre，CLK，Q端口的加法计数器，要程序和最后的RTL图；LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CNT4 ISPORT(CLK :IN STD_LOGIC;APRE:IN STD_LOGIC;Q :OUT STD_LOGIC_VECTOR(3 DOWNTO 0));END;ARCHITECTURE behav OF CNT4 ISSIGNAL Q1 :STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINPROCESS(CLK,APRE)BEGINIF APRE='1' THENQ1<="0001";ELSIF CLK'EVENT AND CLK='1' THENQ1<=Q1+1;END IF;END PROCESS;Q<=Q1;END behav;5. 具有同步置位spre，CLK，Q端口的加法计数器，要程序和最后的RTL图；LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CNT4 ISPORT(CLK :IN STD_LOGIC;SPRE:IN STD_LOGIC;Q :OUT STD_LOGIC_VECTOR(3 DOWNTO 0));END;ARCHITECTURE behav OF CNT4 ISSIGNAL Q1 :STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINPROCESS(CLK,SPRE)BEGINIF CLK'EVENT AND CLK='1' THENIF SPRE='1' THENQ1<="0001";ELSEQ1<=Q1+1;END IF;END IF;Q<=Q1;END behav;6. 具有异步清零aclr，异步置位apre，CLK，Q端口的加法计数器，要程序和最后的RTL 图；LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CNT4 ISPORT(CLK :IN STD_LOGIC;ACLR:IN STD_LOGIC;APRE:IN STD_LOGIC;Q :OUT STD_LOGIC_VECTOR(3 DOWNTO 0));END;ARCHITECTURE behav OF CNT4 ISSIGNAL Q1 :STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINPROCESS(CLK,APRE,ACLR)BEGINIF ACLR='1' THENQ1<="0000";ELSEIF APRE='1' THENQ1<="0001";ELSIF CLK'EVENT AND CLK='1' THENQ1<=Q1+1;END IF;END PROCESS;Q<=Q1;END behav;7. 具有同步使能ENB，CLK，Q端口的加法计数器，要程序和最后的RTL图；LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CNT4 ISPORT(CLK :IN STD_LOGIC;ENB :IN STD_LOGIC;Q :OUT STD_LOGIC_VECTOR(3 DOWNTO 0));END;ARCHITECTURE behav OF CNT4 ISSIGNAL Q1 :STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINPROCESS(CLK,ENB)BEGINIF CLK'EVENT AND CLK='1' THENIF ENB='1' THENQ1<=Q1+1;END IF;END IF;END PROCESS;Q<=Q1;END behav;8. 具有异步清零aclr，异步置位apre，同步使能ENB，CLK，Q端口的加法计数器，要程序和最后的RTL图；LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CNT4 ISPORT(CLK :IN STD_LOGIC;ACLR:IN STD_LOGIC;ENB :IN STD_LOGIC;APRE:IN STD_LOGIC;Q :OUT STD_LOGIC_VECTOR(3 DOWNTO 0));END;ARCHITECTURE behav OF CNT4 ISSIGNAL Q1 :STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINPROCESS(CLK,APRE,ACLR,ENB)BEGINIF ACLR='1' THENQ1<="0000";ELSEIF APRE='1' THENQ1<="0001";ELSIF CLK'EVENT AND CLK='1' THENIF ENB='1' THENQ1<=Q1+1;END IF;END IF;END IF;END PROCESS;Q<=Q1;END behav;1.生活如意，事业高升。

vhdl语言100例程序

vhdl语言100例程序

vhdl语言100例程序以下是100个关于VHDL语言的程序示例：1. 用VHDL编写一个计数器模块2. 用VHDL编写一个SR-Latch模块3. 用VHDL编写一个JK-Flip Flop模块4. 用VHDL编写一个D-Flip Flop模块5. 用VHDL编写一个T-Flip Flop模块6. 用VHDL编写一个复位计数器模块7. 用VHDL编写一个移位寄存器模块8. 用VHDL编写一个状态机模块9. 用VHDL编写一个MUX模块10. 用VHDL编写一个DeMUX模块11. 用VHDL编写一个加法器模块12. 用VHDL编写一个减法器模块13. 用VHDL编写一个乘法器模块14. 用VHDL编写一个除法器模块15. 用VHDL编写一个比较器模块16. 用VHDL编写一个位逻辑模块17. 用VHDL编写一个字逻辑模块18. 用VHDL编写一个数据选择器模块19. 用VHDL编写一个FIFO队列模块20. 用VHDL编写一个LIFO栈模块21. 用VHDL编写一个流水线模块22. 用VHDL编写一个中断控制器模块23. 用VHDL编写一个时钟分频器模块24. 用VHDL编写一个IO控制器模块25. 用VHDL编写一个SPI通信控制器模块26. 用VHDL编写一个I2C通信控制器模块27. 用VHDL编写一个UART通信控制器模块28. 用VHDL编写一个哈希函数模块29. 用VHDL编写一个随机数产生器模块30. 用VHDL编写一个CRC校验器模块31. 用VHDL编写一个AES加密算法模块32. 用VHDL编写一个DES加密算法模块33. 用VHDL编写一个SHA加密算法模块34. 用VHDL编写一个MD5加密算法模块35. 用VHDL编写一个RSA加密算法模块36. 用VHDL编写一个卷积滤波器模块37. 用VHDL编写一个峰值检测器模块38. 用VHDL编写一个平滑滤波器模块39. 用VHDL编写一个中值滤波器模块40. 用VHDL编写一个微处理器模块41. 用VHDL编写一个信号发生器模块42. 用VHDL编写一个信号采集器模块43. 用VHDL编写一个频率计算器模块44. 用VHDL编写一个相位计算器模块45. 用VHDL编写一个时序分析器模块46. 用VHDL编写一个正弦波产生器模块47. 用VHDL编写一个余弦波产生器模块48. 用VHDL编写一个数字滤波器模块49. 用VHDL编写一个数字信号处理器模块50. 用VHDL编写一个数字识别模块51. 用VHDL编写一个自动售货机模块52. 用VHDL编写一个二进制加法器模块53. 用VHDL编写一个二进制减法器模块54. 用VHDL编写一个二进制乘法器模块55. 用VHDL编写一个二进制除法器模块56. 用VHDL编写一个自然对数模块57. 用VHDL编写一个指数函数模块58. 用VHDL编写一个三角函数模块59. 用VHDL编写一个高斯滤波器模块60. 用VHDL编写一个激光传感器模块61. 用VHDL编写一个超声波传感器模块62. 用VHDL编写一个光电传感器模块63. 用VHDL编写一个温度传感器模块64. 用VHDL编写一个气压传感器模块65. 用VHDL编写一个陀螺仪模块67. 用VHDL编写一个电流传感器模块68. 用VHDL编写一个电容传感器模块69. 用VHDL编写一个磁场传感器模块70. 用VHDL编写一个通信电缆模块71. 用VHDL编写一个电源控制器模块72. 用VHDL编写一个电机控制器模块73. 用VHDL编写一个汽车控制器模块74. 用VHDL编写一个飞机控制器模块75. 用VHDL编写一个摄像头模块76. 用VHDL编写一个音频控制器模块77. 用VHDL编写一个扬声器控制器模块78. 用VHDL编写一个拨号器模块79. 用VHDL编写一个振动控制器模块80. 用VHDL编写一个压力控制器模块81. 用VHDL编写一个过滤器模块82. 用VHDL编写一个微波发射模块84. 用VHDL编写一个智能电表模块85. 用VHDL编写一个闹钟模块86. 用VHDL编写一个计时器模块87. 用VHDL编写一个时间戳模块88. 用VHDL编写一个脉冲宽度模块89. 用VHDL编写一个电路仿真模块90. 用VHDL编写一个电路控制模块91. 用VHDL编写一个电路测试模块92. 用VHDL编写一个电路优化模块93. 用VHDL编写一个电路布局模块94. 用VHDL编写一个电路验证模块95. 用VHDL编写一个数字信号发生器模块96. 用VHDL编写一个数字信号反演器模块97. 用VHDL编写一个数字信号滤波器模块98. 用VHDL编写一个数字信号加速器模块99. 用VHDL编写一个数字信号降噪器模块100. 用VHDL编写一个数字信号解调器模块VHDL语言是一种硬件描述语言，它用于描述数字电路和系统。

VHDL各种计数器程序

VHDL各种计数器程序

V H D L各种计数器程序------------------------------------------作者xxxx------------------------------------------日期xxxx1. 具有CLK，Q端口的简单加法计数器，要程序和最后的RTL图；LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CNT4 ISPORT ( CLK : IN STD_LOGIC;Q : OUT INTEGER RANGE 15 DOWNTO 0);END;ARCHITECTURE behav OF CNT4 ISSIGNAL D,Q1 : INTEGER RANGE 15 DOWNTO 0;BEGINPROCESS (CLK)BEGINIF CLK'EVENT AND CLK='1'THEN Q1<=D;END IF;END PROCESS;D<=Q1+1;Q<=Q1;END behav;2. 具有异步清零aclr，CLK，Q端口的加法计数器，要程序和最后的RTL图；LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL ;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CNT4 ISPORT ( CLK,ACLR : IN STD_LOGIC;Q : OUT STD_LOGIC_VECTOR(15 DOWNTO 0));END ;ARCHITECTURE behav OF CNT4 ISSIGNAL Q1 : STD_LOGIC_VECTOR(15 DOWNTO 0);BEGINPROCESS (CLK,ACLR)BEGINIF ACLR='0' THENQ1<=(OTHERS=>'0');ELSIF CLK'EVENT AND CLK='1' THENQ1<=Q1+1;END IF;END PROCESS;Q<=Q1;END behav;3. 具有同步清零sclr，CLK，Q端口的加法计数器，要程序和最后的RTL图；LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL ;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CNT4 ISPORT ( CLK,SCLR : IN STD_LOGIC;Q : OUT STD_LOGIC_VECTOR(15 DOWNTO 0));END ;ARCHITECTURE behav OF CNT4 ISSIGNAL Q1 : STD_LOGIC_VECTOR(15 DOWNTO 0);BEGINPROCESS (CLK,SCLR)BEGINIF CLK'EVENT AND CLK='1' THENIF SCLR='1' THENQ1<=(OTHERS=>'0');ELSEQ1<=Q1+1;END IF;END IF;END PROCESS;Q<=Q1;END behav;4. 具有异步置位apre，CLK，Q端口的加法计数器，要程序和最后的RTL图；LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CNT4 ISPORT(CLK :IN STD_LOGIC;APRE:IN STD_LOGIC;Q :OUT STD_LOGIC_VECTOR(3 DOWNTO 0));END;ARCHITECTURE behav OF CNT4 ISSIGNAL Q1 :STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINPROCESS(CLK,APRE)BEGINIF APRE='1' THENQ1<="0001";ELSIF CLK'EVENT AND CLK='1' THENQ1<=Q1+1;END IF;END PROCESS;Q<=Q1;END behav;5. 具有同步置位spre，CLK，Q端口的加法计数器，要程序和最后的RTL图；LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CNT4 ISPORT(CLK :IN STD_LOGIC;SPRE:IN STD_LOGIC;Q :OUT STD_LOGIC_VECTOR(3 DOWNTO 0));END;ARCHITECTURE behav OF CNT4 ISSIGNAL Q1 :STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINPROCESS(CLK,SPRE)BEGINIF CLK'EVENT AND CLK='1' THENIF SPRE='1' THENQ1<="0001";ELSEQ1<=Q1+1;END IF;END IF;END PROCESS;Q<=Q1;END behav;6. 具有异步清零aclr，异步置位apre，CLK，Q端口的加法计数器，要程序和最后的RTL图；LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CNT4 ISPORT(CLK :IN STD_LOGIC;ACLR:IN STD_LOGIC;APRE:IN STD_LOGIC;Q :OUT STD_LOGIC_VECTOR(3 DOWNTO 0));END;ARCHITECTURE behav OF CNT4 ISSIGNAL Q1 :STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINPROCESS(CLK,APRE,ACLR)BEGINIF ACLR='1' THENQ1<="0000";ELSEIF APRE='1' THENQ1<="0001";ELSIF CLK'EVENT AND CLK='1' THENQ1<=Q1+1;END IF;END IF;END PROCESS;Q<=Q1;END behav;7. 具有同步使能ENB，CLK，Q端口的加法计数器，要程序和最后的RTL图；LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CNT4 ISPORT(CLK :IN STD_LOGIC;ENB :IN STD_LOGIC;Q :OUT STD_LOGIC_VECTOR(3 DOWNTO 0));END;ARCHITECTURE behav OF CNT4 ISSIGNAL Q1 :STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINPROCESS(CLK,ENB)BEGINIF CLK'EVENT AND CLK='1' THENIF ENB='1' THENQ1<=Q1+1;END IF;END IF;END PROCESS;Q<=Q1;END behav;8. 具有异步清零aclr，异步置位apre，同步使能ENB，CLK，Q端口的加法计数器，要程序和最后的RTL图；LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CNT4 ISPORT(CLK :IN STD_LOGIC;ACLR:IN STD_LOGIC;ENB :IN STD_LOGIC;APRE:IN STD_LOGIC;Q :OUT STD_LOGIC_VECTOR(3 DOWNTO 0));END;ARCHITECTURE behav OF CNT4 ISSIGNAL Q1 :STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINPROCESS(CLK,APRE,ACLR,ENB)BEGINIF ACLR='1' THENQ1<="0000";ELSEIF APRE='1' THENQ1<="0001";ELSIF CLK'EVENT AND CLK='1' THENIF ENB='1' THENQ1<=Q1+1;END IF;END IF;END IF; END PROCESS;Q<=Q1; END behav;。

vhdl 计数器的使用

vhdl 计数器的使用

实验四计数器的使用一、实验目的熟悉步长可变的加减计数器的工作原理、设计过程和实现方法。

二、实验内容与要求学习用VHDL设计步长可变的加减计数器电路，完成编译、综合、适配、仿真和实验箱上的硬件测试，通过LED数码管显示输入输出各部分数据。

三、实验原理通过输入一组4BIT二进制数据，控制计数方式，即步长，决定每个脉冲到来时计数器增加的数值，同时还有一个单BIT的控制位，选择加计数或者减计数，并通过电路显示各部分数据（输入及输出）。

拨码开关置为MODEL_SEL5-8，全部置为ON，通过USB下载；全部置为OFF，则通过LAB_JTAG_PS_AS接口下载。

DISP_SEL8，处于“ON”状态，这样可以使用静态共阳数码管DISP_SEL1，DISP_SEL2处于“OFF”状态，通过F1，F2的十六进制的输入，在静态共阳数码管DP1B，DP2B上显示输出。

F1，F2预置数据，通过计数器，总的计数值控制电平宽度，其中一组控制高电平，一组控制低电平。

在DP1B上显示的是0-F的步长可变的加减计数器。

四、实验平台（1）硬件：计算机、GX-SOC/SOPC-DEV-LABCycloneII EP2C35F672C8核心板（2）软件：Quartus II软件五、六、仿真截图七、硬件实现八、程序代码1--10 位计数SCAN TOP_LEVEL程序：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;use ieee.std_logic_unsigned.all;ENTITY ACOUNT100 ISPORT(clk,clr,en,en6:IN STD_LOGIC ;count1 : out std_logic ;ledseg : out std_logic_vector(6 downto 0);ledcom :out std_logic_vector(5 downto 0)); END;ARCHITECTURE ONE OF ACOUNT100 IS COMPONENT clkgen ISPORT(clkin:IN STD_LOGIC ;clkout: OUT STD_LOGIC);END COMPONENT;COMPONENT COUNT10a ISPORT(clk,clr,en:IN STD_LOGIC ;q:OUT STD_LOGIC_vector(3 downto 0);count1:OUT STD_LOGIC);end COMPONENT;COMPONENT bcd_7seg isport(bcd_led :in std_logic_vector(3 downto 0);--input bcdledseg : out std_logic_vector(6 downto 0));--output to 7 segmentend COMPONENT;COMPONENT mx isport(s:in std_logic;a,b:in std_logic_vector(3 downto 0);q:out std_logic_vector(3 downto 0));end COMPONENT;COMPONENT comcoun isport(clk : in std_logic;--synchronouse clockenable : in std_logic;--scan clockcomclk : out std_logic_vector(2 downto 0));--output countend COMPONENT;COMPONENT com_encode isport(s :in std_logic;--input countledcom :out std_logic_vector(5 downto 0));--output encodeend COMPONENT ;signal clk1,c10: std_logic;signal q1,q2,bcd: std_logic_vector(3 downto 0);BEGINU1:clkgen PORT MAP(CLKIN=>CLK,CLKOUT=>CLK1);U2:COUNT10a PORT MAP(clk=>CLK1,clr=>clr,en=>en,q=>q1,count1=>c10);U3:COUNT10a PORT MAP(clk=>CLK1,clr=>clr,en=>c10,q=>q2,count1=>count1); U4:MX PORT MAP(S=>CLK1,A=>q1,b=>q2,q=>bcd);U5:bcd_7seg PORT MAP(bcd_led=>bcd,ledseg=>ledseg);U6:com_encode PORT MAP(s=>clk1,ledcom=>ledcom );end;2---clkgen.vhdLIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;use ieee.std_logic_unsigned.all;ENTITY clkgen ISPORT(clkin:IN STD_LOGIC ;clkout: OUT STD_LOGIC);END;ARCHITECTURE even OF clkgen ISconstant N:Integer:=50000000;--constant N:Integer:=10;SIGNAL coun:integer range 0 to N;SIGNAL clk1:STD_LOGIC;BEGINPROCESS(clkin)BEGINIF(clkin'EVENT AND clkin='1')THENIF(coun=N)THENcoun<=0;clk1<=Not clk1;elsecoun<=coun+1;END IF;END IF;END PROCESS;clkout<=clk1;END even;3--10 位计数器程序：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY COUNT10a ISPORT(clk,clr,en:IN STD_LOGIC;count1:OUT STD_LOGIC;q:OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); END COUNT10a ;ARCHITECTURE rtl OF COUNT10a ISSIGNAL qs:STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL ca:STD_LOGIC;BEGINPROCESS(clk)BEGINIF(clk'EVENT AND clk='1')THENIF(clr='1')THENqs<="0000";ELSIF(en='1')THENIF(qs="1001")THENqs<="0000";ca<='0';ELSIF(qs="1000")THEN --在计数到8时,即让进位赋值1,--由于信号会产生一个滞后,使得实际ca在9时出现qs<=qs+1;ca<='1';ELSEqs<=qs+1;ca<='0';END IF;END IF;END IF;END PROCESS;PROCESS(ca,en)BEGINq<=qs;count1<=ca AND en;END PROCESS;END rtl;4library ieee;use ieee.std_logic_1164.all;entity mx isport(s:in std_logic;a,b:in std_logic_vector(3 downto 0);q:out std_logic_vector(3 downto 0));end mx;architecture rtl of mx isbeginq<= a WHEN s = '0' ELSE b ;end rtl;5--七段显示扫描电路--comcoun.vhd 7 segment com scan counterlibrary ieee ;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity comcoun isport(clk : in std_logic;--synchronouse clockenable : in std_logic;--scan clockcomclk : out std_logic_vector(2 downto 0));--output countend comcoun;architecture behavior of comcoun issignal q : std_logic_vector(2 downto 0);--internal counted signal beginfscan:process(clk)beginif (clk'event and clk='1') thenif (enable='1') thenif q>=1 thenq<="000";--initial counterelseq<=q+1;--countingend if;end if;end if;end process fscan;comclk<=q; --output internal countend behavior;6library ieee ;use ieee.std_logic_1164.all;entity bcd_7seg isport(bcd_led :in std_logic_vector(3 downto 0);--input bcdledseg : out std_logic_vector(6 downto 0));--output to 7 segment end bcd_7seg;architecture behavior of bcd_7seg isbeginwith bcd_led selectledseg<="0111111" when "0000",--0,3f"0000110" when "0001",--1,06"1011011" when "0010",--2,5b"1001111" when "0011",--3,4f"1100110" when "0100",--4,66"1101101" when "0101",--5,6d"1111101" when "0110",--6,7d"0100111" when "0111",--7,27"1111111" when "1000",--8,7f"1101111" when "1001",--9,6f"1110111" when "1010",--A"1111100"when "1011", --b"0111001"when "1100",--c"1011110" when "1101",--d"1111001"when "1110",--E"1110001" when "1111",--F"0000000" when others;end behavior;7--计数译码电路-- 6 共阴--com_encode.vhd 7 segment com encoderlibrary ieee ;use ieee.std_logic_1164.all;entity com_encode isport(s :in std_logic;--input countledcom :out std_logic_vector(5 downto 0));--output encode end com_encode;architecture behavior of com_encode isbeginledcom<="000001" when s='0' else"000010" ;end behavior;九、实验总结。

三位的十进制加法计数器的VHDL语言

三位的十进制加法计数器的VHDL语言

三位的十进制加法计数器的VHDL语言--VHDL程序如下：LIBRARY ieee;UsE ieee。

std_logic_1164。

all;ENTITY cnt1000 IsPORT（clk ： IN STD_LOGIC；clr ： IN STD_LOGIC；en ： IN STD_LOGIC；count ： OUT I NTEGER RANGE 0 TO 999； co ：OUT STD_LOGIC);END cnt1000；ARCHITECTURE a OF cnt1000 IsSIGNAL s ： INTEGER RANGE 0 TO 999;BEGINPROCESS (clk, clr)BEGINIF clr = '0’ THENs 〈= 0；ELSIF (clk'EVENT AND clk = '1’） THENIF en = '1' THENIF s<999 THENs <= s + 1;ELSE s<=0；END IF；ELSEs <= s；END IF;IF s = 999 THEN co 〈='1’;ELSE co <=’0'；END IF;END IF；END PROCESS；count 〈= s;END a;摘要：根据教学实践, 介绍了VHDL 硬件描述语言进行工程设计的优点。

他既是一种与实际技术相独立的语言, 不束缚于某一特定的模拟程序或数字装置上，也不把设计方法强加于设计者，他允许设计者在其使用范围内选择工艺和方法，描述能力极强, 覆盖了逻辑设计的诸多领域和层次，并支持众多的硬件模型；也是一种在数字电路教学中全新的理论联系实际的教学方法和全新的培养学生实际动手能力的有效工具。

同时简要地说明VHDL 硬件描述语言的支撑软件M ax+ Plus.并结合实例详细阐明VHDL 语言在M ax+ Plus 软件的环境下对数字电路的设计、应用方法及使用时需注意的几个方面事项。

用VHDL编写的各种功能的计数器代码

用VHDL编写的各种功能的计数器代码

Library IEEE ;use IEEE.std_logic_1164.all ;use IEEE.std_logic_arith.all ;ENTITY counters ISPORT(d : IN INTEGER RANGE 0 TO 255;clk : IN BIT;clear : IN BIT;ld : IN BIT;enable : IN BIT;up_down : IN BIT;qa : OUT INTEGER RANGE 0 TO 255;qb : OUT INTEGER RANGE 0 TO 255;qc : OUT INTEGER RANGE 0 TO 255;qd : OUT INTEGER RANGE 0 TO 255;qe : OUT INTEGER RANGE 0 TO 255;qf : OUT INTEGER RANGE 0 TO 255;qg : OUT INTEGER RANGE 0 TO 255;qh : OUT INTEGER RANGE 0 TO 255;qi : OUT INTEGER RANGE 0 TO 255;qj : OUT INTEGER RANGE 0 TO 255;qk : OUT INTEGER RANGE 0 TO 255;ql : OUT INTEGER RANGE 0 TO 255;qm : OUT INTEGER RANGE 0 TO 255;qn : OUT INTEGER RANGE 0 TO 255 );END counters;ARCHITECTURE a OF counters ISBEGIN-- An enable counterPROCESS (clk)V ARIABLE cnt : INTEGER RANGE 0 TO 255;BEGINIF (clk'EVENT AND clk = '1') THENIF enable = '1' THENcnt := cnt + 1;END IF;END IF;qa <= cnt;END PROCESS;-- A synchronous load counterPROCESS (clk)V ARIABLE cnt : INTEGER RANGE 0 TO 255; BEGINIF (clk'EVENT AND clk = '1') THENIF ld = '0' THENcnt := d;ELSEcnt := cnt + 1;END IF;END IF;qb <= cnt;END PROCESS;-- A synchronous clear counterPROCESS (clk)V ARIABLE cnt : INTEGER RANGE 0 TO 255; BEGINIF (clk'EVENT AND clk = '1') THENIF clear = '0' THENcnt := 0;ELSEcnt := cnt + 1;END IF;END IF;qc <= cnt;END PROCESS;-- An up/down counterPROCESS (clk)V ARIABLE cnt : INTEGER RANGE 0 TO 255;V ARIABLE direction : INTEGER;BEGINIF (up_down = '1') THENdirection := 1;ELSEdirection := -1;END IF;IF (clk'EVENT AND clk = '1') THENcnt := cnt + direction;END IF;qd <= cnt;END PROCESS;-- A synchronous load enable counterPROCESS (clk)V ARIABLE cnt : INTEGER RANGE 0 TO 255; BEGINIF (clk'EVENT AND clk = '1') THENIF ld = '0' THENcnt := d;ELSEIF enable = '1' THENcnt := cnt + 1;END IF;END IF;END IF;qe <= cnt;END PROCESS;-- An enable up/down counterPROCESS (clk)V ARIABLE cnt : INTEGER RANGE 0 TO 255;V ARIABLE direction : INTEGER;BEGINIF (up_down = '1') THENdirection := 1;ELSEdirection := -1;END IF;IF (clk'EVENT AND clk = '1') THENIF enable = '1' THENcnt := cnt + direction;END IF;END IF;qf <= cnt;END PROCESS;-- A synchronous clear enable counterPROCESS (clk)V ARIABLE cnt : INTEGER RANGE 0 TO 255; BEGINIF (clk'EVENT AND clk = '1') THENIF clear = '0' THENcnt := 0;ELSEIF enable = '1' THENcnt := cnt + 1;END IF;END IF;END IF;qg <= cnt;END PROCESS;-- A synchronous load clear counterPROCESS (clk)V ARIABLE cnt : INTEGER RANGE 0 TO 255; BEGINIF (clk'EVENT AND clk = '1') THENIF clear = '0' THENcnt := 0;ELSEIF ld = '0' THENcnt := d;ELSEcnt := cnt + 1;END IF;END IF;END IF;qh <= cnt;END PROCESS;-- A synchronous load up/down counterPROCESS (clk)V ARIABLE cnt : INTEGER RANGE 0 TO 255;V ARIABLE direction : INTEGER;BEGINIF (up_down = '1') THENdirection := 1;ELSEdirection := -1;END IF;IF (clk'EVENT AND clk = '1') THENIF ld = '0' THENcnt := d;ELSEcnt := cnt + direction;END IF;END IF;qi <= cnt;END PROCESS;-- A synchronous load enable up/down counterPROCESS (clk)V ARIABLE cnt : INTEGER RANGE 0 TO 255;V ARIABLE direction : INTEGER;BEGINIF (up_down = '1') THENdirection := 1;ELSEdirection := -1;END IF;IF (clk'EVENT AND clk = '1') THENIF ld = '0' THENcnt := d;ELSEIF enable = '1' THENcnt := cnt + direction;END IF;END IF;END IF;qj <= cnt;END PROCESS;-- A synchronous clear load enable counterPROCESS (clk)V ARIABLE cnt : INTEGER RANGE 0 TO 255; BEGINIF (clk'EVENT AND clk = '1') THENIF clear = '0' THENcnt := 0;ELSEIF ld = '0' THENcnt := d;ELSEIF enable = '1' THENcnt := cnt + 1;END IF;END IF;END IF;END IF;qk <= cnt;END PROCESS;-- A synchronous clear up/down counterPROCESS (clk)V ARIABLE cnt : INTEGER RANGE 0 TO 255;V ARIABLE direction : INTEGER;BEGINIF (up_down = '1') THENdirection := 1;ELSEdirection := -1;END IF;IF (clk'EVENT AND clk = '1') THENIF clear = '0' THENcnt := 0;ELSEcnt := cnt + direction;END IF;END IF;ql <= cnt;END PROCESS;-- A synchronous clear enable up/down counterPROCESS (clk)V ARIABLE cnt : INTEGER RANGE 0 TO 255;V ARIABLE direction : INTEGER;BEGINIF (up_down = '1') THENdirection := 1;ELSEdirection := -1;END IF;IF (clk'EVENT AND clk = '1') THENIF clear = '0' THENcnt := 0;ELSEIF enable = '1' THENcnt := cnt + direction;END IF;END IF;END IF;qm <= cnt;END PROCESS;-- A modulus 200 up counterPROCESS (clk)V ARIABLE cnt : INTEGER RANGE 0 TO 255;CONSTANT modulus : INTEGER := 200;BEGINIF (clk'EVENT AND clk = '1') THENIF cnt = modulus THENcnt := 0;ELSEcnt := cnt + 1;END IF;END IF;qn <= cnt;END PROCESS; END a;。

vhdl课程设计设计模为 4、8、12、16的可变计数器实验报告总结

vhdl课程设计设计模为 4、8、12、16的可变计数器实验报告总结

VHDL课程设计 - 可变计数器实验报告总结
一、设计概述
本课程设计的主要目标是设计并实现一个可变计数器，其模（Modulo）值可以在4、8、12、16之间进行选择。

计数器采用VHDL编程语言进行描述，并在FPGA开发板上进行测试验证。

二、设计实现
1. 硬件平台：我们选择了Xilinx的FPGA开发板作为硬件平台，它具有丰富的I/O资源和足够的逻辑单元，可以满足我们的设计需求。

2. VHDL编程：我们采用VHDL语言进行编程，实现了模4、模8、模12和模16的可变计数器。

通过选择不同的计数模式，计数器的模值可以在4、8、12、16之间进行切换。

3. 测试与验证：为了验证计数器的功能，我们编写了测试平台，并通过仿真和实际硬件测试对计数器进行了全面的测试。

三、实验结果与分析
1. 实验结果：通过仿真和实际硬件测试，我们验证了计数器的
功能正确性。

在不同的模值下，计数器都能正确地进行计数操作，并且在达到模值后能正确地回绕到0。

2. 结果分析：实验结果表明，我们的VHDL编程和FPGA开发技能得到了很好的应用和提升。

同时，通过这次课程设计，我们更深入地理解了可变计数器的设计和实现原理，提高了我们的硬件设计能力。

四、总结与展望
本次课程设计让我们深入了解了VHDL编程语言和FPGA开发技术，提高了我们的硬件设计能力。

通过实际的设计和测试，我们成功地实现了一个可变模值的计数器，达到了课程设计的要求。

在未来的学习和工作中，我们将继续深入学习FPGA设计和VHDL编程，不断提高自己的硬件设计能力。

同时，我们也期待将这种技术应用于更多的实际项目中，为工程实践做出贡献。

VHDL-计数器程序

VHDL-计数器程序

VHDL-计数器程序十五计数器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY fiveteencout ISPORT(clk,reset,enable : IN std_logic; count : OUT std_logic _vector(3 downto 0));END fiveteencout;ARCHITECTURE counter OF fiveteencout ISSIGNAL count_int:std_logic_vector(0 to 3);BEGINPROCESS(clk,reset)BEGINWAIT UNTIL rising_edge(clk);IF reset = '1' THENcount_int <= (OTHERS => '0');ELSIF enable = '1' THENIF(count_int="1110") THENcount_int<="0000";ELSEcount_int <= count_int 1;-- NULL ;--IF (count_int="1001") THEN--count_int<="0000";END IF;END IF;END PROCESS;count <= count_int;-- IF (reset='0') then--q<="0000";---ELSIF(clk'event and clk='1') THEN--q<=q 1;--IF (q<="1001") then--q<="0000";---END IF;--IF (reset<='1')THEN--q<="00";--ELSIF--wait until (clk'event and clk='1');--WAIT UNTIL (clk'EVENT AND clk = '1');--WAIT UNTIL (clock'EVENT AND clock = '1'); -- q<=q '1';--count<=q;-- WAIT UNTIL clock = '1';--if (clock'event and clock='1')then--WAIT UNTIL rising_edge(clock);--clock'event and clock='1';--count <= 0;--WAIT UNTIL (clock'EVENT AND clock = '1'); --WAIT riseedge clock = '1';--if (clock'event and clock='1') then--WAIT UNTIL rising_edge(clock);--count <= 1;--WAIT UNTIL (clock'EVENT AND clock = '1'); --WAIT UNTIL clock = '1';--if (clock'event and clock='1')then--WAIT UNTIL rising_edge(clock);--count <= 2;--end if;--end if;--end if;-- END PROCESS;END counter;十四计数器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY fourteencout ISPORT(clk,reset,enable : IN std_logic; count : OUT std_logic _vector(3 downto 0));END fourteencout;ARCHITECTURE counter OF fourteencout ISSIGNAL count_int:std_logic_vector(0 to 3);BEGINPROCESS(clk,reset)BEGINWAIT UNTIL rising_edge(clk);IF reset = '1' THENcount_int <= (OTHERS => '0');ELSIF enable = '1' THENIF(count_int="1101") THENcount_int<="0000";ELSEcount_int <= count_int 1;-- NULL ;--IF (count_int="1001") THEN--count_int<="0000";END IF;END IF;END PROCESS;count <= count_int;-- IF (reset='0') then--q<="0000";---ELSIF(clk'event and clk='1') THEN--q<=q 1;--IF (q<="1001") then--q<="0000";---END IF;--IF (reset<='1')THEN--q<="00";--ELSIF--wait until (clk'event and clk='1');--WAIT UNTIL (clk'EVENT AND clk = '1');--WAIT UNTIL (clock'EVENT AND clock = '1'); -- q<=q '1';--count<=q;-- WAIT UNTIL clock = '1';--if (clock'event and clock='1')then--WAIT UNTIL rising_edge(clock);--clock'event and clock='1';--count <= 0;--WAIT UNTIL (clock'EVENT AND clock = '1'); --WAIT riseedge clock = '1';--if (clock'event and clock='1') then--WAIT UNTIL rising_edge(clock);--count <= 1;--WAIT UNTIL (clock'EVENT AND clock = '1'); --WAIT UNTIL clock = '1';--if (clock'event and clock='1')then--WAIT UNTIL rising_edge(clock);--count <= 2;--end if;--end if;--end if;-- END PROCESS;END counter;十三计数器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY thireteencout ISPORT(clk,reset,enable : IN std_logic; count : OUT std_logic _vector(3 downto 0));END thireteencout;ARCHITECTURE counter OF thireteencout ISSIGNAL count_int:std_logic_vector(0 to 3);BEGINPROCESS(clk,reset)BEGINWAIT UNTIL rising_edge(clk);IF reset = '1' THENcount_int <= (OTHERS => '0');ELSIF enable = '1' THENIF(count_int="1100") THENcount_int<="0000";ELSEcount_int <= count_int 1;-- NULL ;--IF (count_int="1001") THEN--count_int<="0000";END IF;END IF;END PROCESS;count <= count_int;-- IF (reset='0') then--q<="0000";---ELSIF(clk'event and clk='1') THEN--q<=q 1;--IF (q<="1001") then--q<="0000";---END IF;--IF (reset<='1')THEN--q<="00";--ELSIF--wait until (clk'event and clk='1');--WAIT UNTIL (clk'EVENT AND clk = '1');--WAIT UNTIL (clock'EVENT AND clock = '1'); -- q<=q '1';--count<=q;-- WAIT UNTIL clock = '1';--if (clock'event and clock='1')then--WAIT UNTIL rising_edge(clock);--clock'event and clock='1';--count <= 0;--WAIT UNTIL (clock'EVENT AND clock = '1'); --WAIT riseedge clock = '1';--if (clock'event and clock='1') then--WAIT UNTIL rising_edge(clock);--count <= 1;--WAIT UNTIL (clock'EVENT AND clock = '1'); --WAIT UNTIL clock = '1';--if (clock'event and clock='1')then--WAIT UNTIL rising_edge(clock);--count <= 2;--end if;--end if;--end if;-- END PROCESS;END counter;十二计数器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY twelvecout ISPORT(clk,reset,enable : IN std_logic; count : OUT std_logic _vector(3 downto 0));END twelvecout;ARCHITECTURE counter OF twelvecout ISSIGNAL count_int:std_logic_vector(0 to 3);BEGINPROCESS(clk,reset)BEGINWAIT UNTIL rising_edge(clk);IF reset = '1' THENcount_int <= (OTHERS => '0');ELSIF enable = '1' THENIF(count_int="1011") THENcount_int<="0000";ELSEcount_int <= count_int 1;-- NULL ;--IF (count_int="1001") THEN--count_int<="0000";END IF;END IF;END PROCESS;count <= count_int;-- IF (reset='0') then--q<="0000";---ELSIF(clk'event and clk='1') THEN--q<=q 1;--IF (q<="1001") then--q<="0000";---END IF;--IF (reset<='1')THEN--q<="00";--ELSIF--wait until (clk'event and clk='1');--WAIT UNTIL (clk'EVENT AND clk = '1');--WAIT UNTIL (clock'EVENT AND clock = '1'); -- q<=q '1';--count<=q;-- WAIT UNTIL clock = '1';--if (clock'event and clock='1')then--WAIT UNTIL rising_edge(clock);--clock'event and clock='1';--count <= 0;--WAIT UNTIL (clock'EVENT AND clock = '1'); --WAIT riseedge clock = '1';--if (clock'event and clock='1') then--WAIT UNTIL rising_edge(clock);--count <= 1;--WAIT UNTIL (clock'EVENT AND clock = '1'); --WAIT UNTIL clock = '1';--if (clock'event and clock='1')then--WAIT UNTIL rising_edge(clock);--count <= 2;--end if;--end if;--end if;-- END PROCESS;END counter;十一计数器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY elevencout ISPORT(clk,reset,enable : IN std_logic; count : OUT std_logic _vector(3 downto 0));END elevencout;ARCHITECTURE counter OF elevencout ISSIGNAL count_int:std_logic_vector(0 to 3);BEGINPROCESS(clk,reset)BEGINWAIT UNTIL rising_edge(clk);IF reset = '1' THENcount_int <= (OTHERS => '0');ELSIF enable = '1' THENIF(count_int="1010") THENcount_int<="0000";ELSEcount_int <= count_int 1;-- NULL ;--IF (count_int="1001") THEN--count_int<="0000";END IF;END IF;END PROCESS;count <= count_int;-- IF (reset='0') then--q<="0000";---ELSIF(clk'event and clk='1') THEN--q<=q 1;--IF (q<="1001") then--q<="0000";---END IF;--IF (reset<='1')THEN--q<="00";--ELSIF--wait until (clk'event and clk='1');--WAIT UNTIL (clk'EVENT AND clk = '1');--WAIT UNTIL (clock'EVENT AND clock = '1'); -- q<=q '1';--count<=q;-- WAIT UNTIL clock = '1';--if (clock'event and clock='1')then--WAIT UNTIL rising_edge(clock);--clock'event and clock='1';--count <= 0;--WAIT UNTIL (clock'EVENT AND clock = '1'); --WAIT riseedge clock = '1';--if (clock'event and clock='1') then--WAIT UNTIL rising_edge(clock);--count <= 1;--WAIT UNTIL (clock'EVENT AND clock = '1'); --WAIT UNTIL clock = '1';--if (clock'event and clock='1')then--WAIT UNTIL rising_edge(clock);--count <= 2;--end if;--end if;--end if;-- END PROCESS;END counter;十计数器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY count ISPORT(clk,reset,enable : IN std_logic; count : OUT std_logic_vector(3 downto 0));END count;ARCHITECTURE counter OF count IS SIGNAL count_int:std_logic_vector(0 to 3); BEGINPROCESS(clk,reset)BEGINWAIT UNTIL rising_edge(clk);IF reset = '1' THENcount_int <= (OTHERS => '0');ELSIF enable = '1' THENIF(count_int="1001") THENcount_int<="0000";ELSEcount_int <= count_int 1;--ELSE-- NULL ;--IF (count_int="1001") THEN--count_int<="0000";END IF;END IF;END PROCESS;count <= count_int;-- IF (reset='0') then--q<="0000";---ELSIF(clk'event and clk='1') THEN--q<=q 1;--IF (q<="1001") then--q<="0000";---END IF;--IF (reset<='1')THEN--q<="00";--ELSIF--wait until (clk'event and clk='1');--WAIT UNTIL (clk'EVENT AND clk = '1');--WAIT UNTIL (clock'EVENT AND clock = '1'); -- q<=q '1';--end if;--count<=q;-- WAIT UNTIL clock = '1';--if (clock'event and clock='1')then--WAIT UNTIL rising_edge(clock);--clock'event and clock='1';--count <= 0;--WAIT UNTIL (clock'EVENT AND clock = '1'); --WAIT riseedge clock = '1';--if (clock'event and clock='1') then--WAIT UNTIL rising_edge(clock);--count <= 1;--WAIT UNTIL (clock'EVENT AND clock = '1'); --WAIT UNTIL clock = '1';--if (clock'event and clock='1')then--WAIT UNTIL rising_edge(clock);--count <= 2;--end if;--end if;--end if;-- END PROCESS;END counter;九计数器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY ninecout ISPORT(clk,reset,enable : IN std_logic; count : OUT std_logic _vector(3 downto 0));END ninecout;ARCHITECTURE counter OF ninecout ISSIGNAL count_int:std_logic_vector(0 to 3);BEGINPROCESS(clk,reset)BEGINWAIT UNTIL rising_edge(clk);IF reset = '1' THENcount_int <= (OTHERS => '0');ELSIF enable = '1' THENIF(count_int="1000") THENcount_int<="0000";ELSEcount_int <= count_int 1;--ELSE-- NULL ;--IF (count_int="1001") THEN--count_int<="0000";END IF;END IF;END PROCESS;count <= count_int;-- IF (reset='0') then--q<="0000";---ELSIF(clk'event and clk='1') THEN--q<=q 1;--IF (q<="1001") then--q<="0000";---END IF;--IF (reset<='1')THEN--q<="00";--ELSIF--wait until (clk'event and clk='1');--WAIT UNTIL (clk'EVENT AND clk = '1');--WAIT UNTIL (clock'EVENT AND clock = '1'); -- q<=q '1';--end if;--count<=q;-- WAIT UNTIL clock = '1';--if (clock'event and clock='1')then--WAIT UNTIL rising_edge(clock);--clock'event and clock='1';--count <= 0;--WAIT UNTIL (clock'EVENT AND clock = '1'); --WAIT riseedge clock = '1';--if (clock'event and clock='1') then--WAIT UNTIL rising_edge(clock);--count <= 1;--WAIT UNTIL (clock'EVENT AND clock = '1'); --WAIT UNTIL clock = '1';--if (clock'event and clock='1')then--WAIT UNTIL rising_edge(clock);--count <= 2;--end if;--end if;--end if;-- END PROCESS;END counter;八计数器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY eightcout ISPORT(clk,reset,enable : IN std_logic; count : OUT std_logic _vector(2 downto 0));END eightcout;ARCHITECTURE counter OF eightcout ISSIGNAL count_int:std_logic_vector(0 to 2);BEGINPROCESS(clk,reset)BEGINWAIT UNTIL rising_edge(clk);IF reset = '1' THENcount_int <= (OTHERS => '0');ELSIF enable = '1' THENIF(count_int="111") THENcount_int<="000";ELSEcount_int <= count_int 1;--ELSE-- NULL ;--IF (count_int="1001") THEN--count_int<="0000";END IF;END IF;END PROCESS;count <= count_int;-- IF (reset='0') then--q<="0000";---ELSIF(clk'event and clk='1') THEN--q<=q 1;--IF (q<="1001") then--q<="0000";---END IF;--IF (reset<='1')THEN--q<="00";--ELSIF--wait until (clk'event and clk='1');--WAIT UNTIL (clk'EVENT AND clk = '1');--WAIT UNTIL (clock'EVENT AND clock = '1'); -- q<=q '1';--end if;--count<=q;-- WAIT UNTIL clock = '1';--if (clock'event and clock='1')then--WAIT UNTIL rising_edge(clock);--clock'event and clock='1';--count <= 0;--WAIT UNTIL (clock'EVENT AND clock = '1'); --WAIT riseedge clock = '1';--if (clock'event and clock='1') then--WAIT UNTIL rising_edge(clock);--count <= 1;--WAIT UNTIL (clock'EVENT AND clock = '1'); --WAIT UNTIL clock = '1';--if (clock'event and clock='1')then--WAIT UNTIL rising_edge(clock);--count <= 2;--end if;--end if;--end if;-- END PROCESS;END counter;六计数器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY sixcout ISPORT(clk,reset,enable : IN std_logic; count : OUT std_logic _vector(2 downto 0));END sixcout;ARCHITECTURE counter OF sixcout ISSIGNAL count_int:std_logic_vector(0 to 2);BEGINPROCESS(clk,reset)BEGINWAIT UNTIL rising_edge(clk);IF reset = '1' THENcount_int <= (OTHERS => '0');ELSIF enable = '1' THENIF(count_int="101") THENcount_int<="000";ELSEcount_int <= count_int 1;--ELSE-- NULL ;--IF (count_int="1001") THEN--count_int<="0000";END IF;END IF;END PROCESS;count <= count_int;-- IF (reset='0') then--q<="0000";---ELSIF(clk'event and clk='1') THEN --q<=q 1;--IF (q<="1001") then--q<="0000";---END IF;--IF (reset<='1')THEN--q<="00";--ELSIF--wait until (clk'event and clk='1');--WAIT UNTIL (clk'EVENT AND clk = '1');--WAIT UNTIL (clock'EVENT AND clock = '1'); -- q<=q '1';--end if;--count<=q;-- WAIT UNTIL clock = '1';--if (clock'event and clock='1')then--WAIT UNTIL rising_edge(clock);--clock'event and clock='1';--count <= 0;--WAIT UNTIL (clock'EVENT AND clock = '1'); --WAIT riseedge clock = '1';--if (clock'event and clock='1') then--WAIT UNTIL rising_edge(clock);--count <= 1;--WAIT UNTIL (clock'EVENT AND clock = '1'); --WAIT UNTIL clock = '1';--if (clock'event and clock='1')then--WAIT UNTIL rising_edge(clock);--count <= 2;--end if;--end if;--end if;-- END PROCESS;END counter;四计数器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY fourcout ISPORT(clk,reset,enable : IN std_logic; count : OUT std_logic _vector(1 downto 0));END fourcout;ARCHITECTURE counter OF fourcout ISSIGNAL count_int:std_logic_vector(0 to 1);BEGINPROCESS(clk,reset)BEGINWAIT UNTIL rising_edge(clk);IF reset = '1' THENcount_int <= (OTHERS => '0');ELSIF enable = '1' THENIF(count_int="11") THENcount_int<="00";ELSEcount_int <= count_int 1;--ELSE-- NULL ;--IF (count_int="1001") THEN--count_int<="0000";END IF;END IF;END PROCESS;count <= count_int;-- IF (reset='0') then--q<="0000";---ELSIF(clk'event and clk='1') THEN --q<=q 1;--IF (q<="1001") then--q<="0000";---END IF;--IF (reset<='1')THEN--q<="00";--wait until (clk'event and clk='1');--WAIT UNTIL (clk'EVENT AND clk = '1');--WAIT UNTIL (clock'EVENT AND clock = '1'); -- q<=q '1';--end if;--count<=q;-- WAIT UNTIL clock = '1';--if (clock'event and clock='1')then--WAIT UNTIL rising_edge(clock);--clock'event and clock='1';--count <= 0;--WAIT UNTIL (clock'EVENT AND clock = '1'); --WAIT riseedge clock = '1';--if (clock'event and clock='1') then--WAIT UNTIL rising_edge(clock);--count <= 1;--WAIT UNTIL (clock'EVENT AND clock = '1'); --WAIT UNTIL clock = '1';--if (clock'event and clock='1')then--WAIT UNTIL rising_edge(clock);--count <= 2;--end if;--end if;-- END PROCESS; END counter;。

vhdl七段数码管显示0到9计数器显示电路设计

vhdl七段数码管显示0到9计数器显示电路设计

vhdl七段数码管显示0到9计数器显示电路设计在 VHDL 中，可以使用进程`PROCESS`和状态机来实现七段数码管显示 0 到 9 的计数器显示电路设计。

以下是一个示例代码：```vhdl-- 七段数码管显示 0 到 9 的计数器显示电路设计-- 定义七段数码管的显示编码CONSTANT seven_seg : STD_LOGIC_VECTOR(6 DOWNTO 0) := "1111110";CONSTANT seg_map : STD_LOGIC_VECTOR(6 DOWNTO 0) := "0000011";-- 定义计数器的位数和初始值CONSTANT count_width : NATURAL := 4;CONSTANT count_init : NATURAL := 0;-- 声明计数器和七段数码管显示的信号Signal count : STD_LOGIC_VECTOR(count_width - 1 DOWNTO 0);Signal seg : STD_LOGIC_VECTOR(6 DOWNTO 0);-- 计数器的进程Process (clk)BeginIf clk'event and clk = '1' ThenIf count = count_init - 1 Thencount <= count_init;Elsecount <= count + 1;End If;End If;End Process;-- 七段数码管显示的进程Process (count)BeginCase count IsWhen count_init - 1 => seg <= seven_seg;When count_init => seg <= seg_map;When count_init + 1 => seg <= seven_seg;When count_init + 2 => seg <= seg_map;When count_init + 3 => seg <= seven_seg;When count_init + 4 => seg <= seg_map;When count_init + 5 => seg <= seven_seg;When count_init + 6 => seg <= seg_map;When count_init + 7 => seg <= seven_seg;When count_init + 8 => seg <= seg_map;When count_init + 9 => seg <= seven_seg;When Others => seg <= seven_seg;End Case;End Process;-- 连接计数器和七段数码管显示的信号Output seg;```上述代码中，使用了两个进程`PROCESS`来实现计数器和七段数码管的显示。

时序逻辑VHDL设计——计数器

时序逻辑VHDL设计——计数器

实验名称：实验6 时序逻辑VHDL设计——计数器班级： 09电气2Z 学号：姓名：钱雷一、结合74160芯片的逻辑功能，对（1）中所设计的程序进行改进，用VHDL设计一个带有高电平使能信号，低电平清零信号，低电平置数信号的十进制计数器。

1.实体框图2.程序设计①编译前的程序library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity CNT10 isport(CLK,RST,LD,EP,ET:in std_logic;D:in std_logic_vector(3 downto 0);Q:out std_logic_vector(3 downto 0);CO:out std_logic);end CNT10;architecture behav of CNT10 isbeginprocess(CLK,RST,LD,EP,ET)variable QI:std_logic_vector(3 downto 0);beginif RST='0' then QI:=(others=>'0');elsif CLK'EVENT and CLK='1' thenif LD='0' then QI:=D;elsif EP='1' and ET='1' thenif QI<9 then QI:=QI+1;else QI:=(others=>'0');end if;end if;if QI=9 then CO<='1';else CO<='0';end if;Q<=QI;end process;end behav;②程序编译错误情况③正确的程序library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity CNT10 isport(CLK,RST,LD,EP,ET:in std_logic;D:in std_logic_vector(3 downto 0); Q:out std_logic_vector(3 downto 0); CO:out std_logic);end CNT10;architecture behav of CNT10 isbeginprocess(CLK,RST,LD,EP,ET)variable QI:std_logic_vector(3 downto 0);beginif RST='0' then QI:=(others=>'0');elsif CLK'EVENT and CLK='1' thenif LD='0' then QI:=D;elsif EP='1' and ET='1' thenif QI<9 then QI:=QI+1;else QI:=(others=>'0');end if;end if;end if;if QI=9 then CO<='1';else CO<='0';end if;Q<=QI;end process;end behav;3.仿真波形图4.仿真波形分析输入端D0—D3是输入置数端，EP，ET是使能端，并且高电平有效，LD是置数控制端口，低电平有效，RST是清零端，低电平有效。

用vhdl语言设计计数器资料讲解

用vhdl语言设计计数器资料讲解

用v h d l语言设计计数器76进制计数器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CDU_76 ISPORT (CLK:IN STD_LOGIC; Q:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); END CDU_76;ARCHITECTURE AA OF CDU_76 ISSIGNAL COUT2,COUT1:STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINPROCESS(CLK)BEGINIF (CLK'EVENT AND CLK='1') THENIF(COUT2=7 AND COUT1=5) THEN COUT2<="0000";COUT1<="0000"; ELSE IF (COUT1=9) THEN COUT2<=COUT2+1;COUT1<="0000";ELSE COUT2<=COUT2;COUT1<=COUT1+1;END IF;END IF;END IF;END PROCESS;Q<=COUT2&COUT1;END AA;24进制计数器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CDU_24 ISPORT (CLK:IN STD_LOGIC;Q:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));END CDU_24;ARCHITECTURE AA OF CDU_24 ISSIGNAL COUT2,COUT1:STD_LOGIC_VECTOR(3 DOWNTO 0); BEGINPROCESS(CLK)BEGINIF (CLK'EVENT AND CLK='1') THENIF(COUT2=2 AND COUT1=3) THEN COUT2<="0000";COUT1<="0000"; ELSE IF (COUT1=9) THEN COUT2<=COUT2+1;COUT1<="0000";ELSE COUT2<=COUT2;COUT1<=COUT1+1;END IF;END IF;END IF;END PROCESS;Q<=COUT2&COUT1;END AA;用VHDL 设计一个带高电平使能信号、低电平清零信号、低电平置数信号的十进制计数器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CNT10 ISPORT(CLK,SET,CLR,EN:IN STD_LOGIC;CQ:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);COUT:OUT STD_LOGIC);END CNT10;ARCHITECTURE behav OF CNT10 ISBEGINPROCESS(CLK,SET,CLR,EN)VARIABLE CQI:STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINIF CLR='0' THEN CQI:=(OTHERS=>'0');ELSIF CLK'EVENT AND CLK='1' THENIF SET='0' THEN CQI:=(OTHERS=>'1');ELSIF EN='1' THENIF CQI<9 THEN CQI:=CQI+1;ELSE CQI:=(OTHERS=>'0');END IF;END IF;END IF;IF CQI=9 THEN COUT<='1'; ELSE COUT<='0';END IF;CQ<=CQI;END PROCESS;END behav;。

VHDL计数器程序

VHDL计数器程序

VHDL-计数器程序十五计数器ELSEcount_int <= count_int 1;--ELSE-- NULL ;--IF (count_int="1001") THEN--count_int<="0000";END IF;END IF;END PROCESS;count <= count_int;-- IF (reset='0') then--q<="0000";---ELSIF(clk'event and clk='1') THEN --q<=q 1;--IF (q<="1001") then--q<="0000";---END IF;--IF (reset<='1')THEN--q<="00";--wait until (clk'event and clk='1');--WAIT UNTIL (clk'EVENT AND clk = '1');--WAIT UNTIL (clock'EVENT AND clock = '1'); -- q<=q '1';--end if;--count<=q;-- WAIT UNTIL clock = '1';--if (clock'event and clock='1')then--WAIT UNTIL rising_edge(clock);--clock'event and clock='1';--count <= 0;--WAIT UNTIL (clock'EVENT AND clock = '1'); --WAIT riseedge clock = '1';--if (clock'event and clock='1') then--WAIT UNTIL rising_edge(clock);--count <= 1;--WAIT UNTIL (clock'EVENT AND clock = '1'); --WAIT UNTIL clock = '1';--if (clock'event and clock='1')then--WAIT UNTIL rising_edge(clock);--count <= 2;--end if;--end if;-- END PROCESS;END counter;十四计数器ELSEcount_int <= count_int 1;--ELSE-- NULL ;--IF (count_int="1001") THEN--count_int<="0000";END IF;END IF;END PROCESS;count <= count_int;-- IF (reset='0') then--q<="0000";---ELSIF(clk'event and clk='1') THEN --q<=q 1;--IF (q<="1001") then--q<="0000";---END IF;--IF (reset<='1')THEN--q<="00";--ELSIF--wait until (clk'event and clk='1');--WAIT UNTIL (clk'EVENT AND clk = '1');--WAIT UNTIL (clock'EVENT AND clock = '1'); -- q<=q '1';--end if;--count<=q;-- WAIT UNTIL clock = '1';--if (clock'event and clock='1')then--WAIT UNTIL rising_edge(clock);--clock'event and clock='1';--count <= 0;--WAIT UNTIL (clock'EVENT AND clock = '1'); --WAIT riseedge clock = '1';--if (clock'event and clock='1') then--WAIT UNTIL rising_edge(clock);--count <= 1;--WAIT UNTIL (clock'EVENT AND clock = '1'); --WAIT UNTIL clock = '1';--if (clock'event and clock='1')then--WAIT UNTIL rising_edge(clock);--count <= 2;--end if;--end if;--end if;-- END PROCESS;END counter;十三计数器ELSEcount_int <= count_int 1;--ELSE-- NULL ;--IF (count_int="1001") THEN--count_int<="0000";END IF;END IF;END PROCESS;count <= count_int;-- IF (reset='0') then--q<="0000";---ELSIF(clk'event and clk='1') THEN--q<=q 1;--IF (q<="1001") then--q<="0000";---END IF;--IF (reset<='1')THEN--q<="00";--ELSIF--wait until (clk'event and clk='1');--WAIT UNTIL (clk'EVENT AND clk = '1');--WAIT UNTIL (clock'EVENT AND clock = '1'); -- q<=q '1';--end if;--count<=q;-- WAIT UNTIL clock = '1';--if (clock'event and clock='1')then--WAIT UNTIL rising_edge(clock);--clock'event and clock='1';--count <= 0;--WAIT UNTIL (clock'EVENT AND clock = '1'); --WAIT riseedge clock = '1';--if (clock'event and clock='1') then--WAIT UNTIL rising_edge(clock);--count <= 1;--WAIT UNTIL (clock'EVENT AND clock = '1'); --WAIT UNTIL clock = '1';--if (clock'event and clock='1')then--WAIT UNTIL rising_edge(clock);--count <= 2;--end if;--end if;--end if;-- END PROCESS;END counter;十二计数器ELSEcount_int <= count_int 1;--ELSE-- NULL ;--IF (count_int="1001") THEN--count_int<="0000";END IF;END IF;END PROCESS;count <= count_int;-- IF (reset='0') then--q<="0000";---ELSIF(clk'event and clk='1') THEN--q<=q 1;--IF (q<="1001") then--q<="0000";---END IF;--IF (reset<='1')THEN--q<="00";--ELSIF--wait until (clk'event and clk='1');--WAIT UNTIL (clk'EVENT AND clk = '1');--WAIT UNTIL (clock'EVENT AND clock = '1'); -- q<=q '1';--end if;--count<=q;-- WAIT UNTIL clock = '1';--if (clock'event and clock='1')then--WAIT UNTIL rising_edge(clock);--clock'event and clock='1';--count <= 0;--WAIT UNTIL (clock'EVENT AND clock = '1'); --WAIT riseedge clock = '1';--if (clock'event and clock='1') then--WAIT UNTIL rising_edge(clock);--count <= 1;--WAIT UNTIL (clock'EVENT AND clock = '1'); --WAIT UNTIL clock = '1';--if (clock'event and clock='1')then--WAIT UNTIL rising_edge(clock);--count <= 2;--end if;--end if;--end if;-- END PROCESS;END counter;十一计数器ELSEcount_int <= count_int 1;--ELSE-- NULL ;--IF (count_int="1001") THEN--count_int<="0000";END IF;END IF;END PROCESS;count <= count_int;-- IF (reset='0') then--q<="0000";---ELSIF(clk'event and clk='1') THEN --q<=q 1;--IF (q<="1001") then--q<="0000";---END IF;--IF (reset<='1')THEN--q<="00";--ELSIF--wait until (clk'event and clk='1');--WAIT UNTIL (clk'EVENT AND clk = '1');--WAIT UNTIL (clock'EVENT AND clock = '1'); -- q<=q '1';--end if;--count<=q;-- WAIT UNTIL clock = '1';--if (clock'event and clock='1')then--WAIT UNTIL rising_edge(clock);--clock'event and clock='1';--count <= 0;--WAIT UNTIL (clock'EVENT AND clock = '1'); --WAIT riseedge clock = '1';--if (clock'event and clock='1') then--WAIT UNTIL rising_edge(clock);--count <= 1;--WAIT UNTIL (clock'EVENT AND clock = '1'); --WAIT UNTIL clock = '1';--if (clock'event and clock='1')then--WAIT UNTIL rising_edge(clock);--count <= 2;--end if;--end if;--end if;-- END PROCESS;END counter;十计数器OUT std_logic_vector(3 downto 0));END count;ARCHITECTURE counter OF count IS SIGNAL count_int:std_logic_vector(0 to 3); BEGINPROCESS(clk,reset)BEGINWAIT UNTIL rising_edge(clk);IF reset = '1' THENcount_int <= (OTHERS => '0');ELSIF enable = '1' THENIF(count_int="1001") THENcount_int<="0000";ELSEcount_int <= count_int 1;--ELSE-- NULL ;--IF (count_int="1001") THEN--count_int<="0000";END IF;END IF;END PROCESS;count <= count_int;-- IF (reset='0') then--q<="0000";---ELSIF(clk'event and clk='1') THEN--q<=q 1;--IF (q<="1001") then--q<="0000";---END IF;--IF (reset<='1')THEN--q<="00";--ELSIF--wait until (clk'event and clk='1');--WAIT UNTIL (clk'EVENT AND clk = '1');--WAIT UNTIL (clock'EVENT AND clock = '1'); -- q<=q '1';--end if;--count<=q;-- WAIT UNTIL clock = '1';--if (clock'event and clock='1')then--WAIT UNTIL rising_edge(clock);--clock'event and clock='1';--count <= 0;--WAIT UNTIL (clock'EVENT AND clock = '1'); --WAIT riseedge clock = '1';--if (clock'event and clock='1') then--WAIT UNTIL rising_edge(clock);--count <= 1;--WAIT UNTIL (clock'EVENT AND clock = '1'); --WAIT UNTIL clock = '1';--if (clock'event and clock='1')then--WAIT UNTIL rising_edge(clock);--count <= 2;--end if;--end if;--end if;-- END PROCESS;END counter;九计数器ELSEcount_int <= count_int 1;--ELSE-- NULL ;--IF (count_int="1001") THEN--count_int<="0000";END IF;END IF;END PROCESS;count <= count_int;-- IF (reset='0') then--q<="0000";---ELSIF(clk'event and clk='1') THEN --q<=q 1;--IF (q<="1001") then--q<="0000";---END IF;--IF (reset<='1')THEN--q<="00";--ELSIF--wait until (clk'event and clk='1');--WAIT UNTIL (clk'EVENT AND clk = '1');--WAIT UNTIL (clock'EVENT AND clock = '1'); -- q<=q '1';--end if;--count<=q;-- WAIT UNTIL clock = '1';--if (clock'event and clock='1')then--WAIT UNTIL rising_edge(clock);--clock'event and clock='1';--count <= 0;--WAIT UNTIL (clock'EVENT AND clock = '1'); --WAIT riseedge clock = '1';--if (clock'event and clock='1') then--WAIT UNTIL rising_edge(clock);--count <= 1;--WAIT UNTIL (clock'EVENT AND clock = '1'); --WAIT UNTIL clock = '1';--if (clock'event and clock='1')then--WAIT UNTIL rising_edge(clock); --count <= 2;--end if;--end if;--end if;-- END PROCESS;END counter;八计数器ELSEcount_int <= count_int 1;--ELSE-- NULL ;--IF (count_int="1001") THEN--count_int<="0000";END IF;END IF;END PROCESS;count <= count_int;-- IF (reset='0') then--q<="0000";---ELSIF(clk'event and clk='1') THEN--q<=q 1;--IF (q<="1001") then--q<="0000";---END IF;--IF (reset<='1')THEN--q<="00";--ELSIF--wait until (clk'event and clk='1');--WAIT UNTIL (clk'EVENT AND clk = '1');--WAIT UNTIL (clock'EVENT AND clock = '1'); -- q<=q '1';--end if;--count<=q;-- WAIT UNTIL clock = '1';--if (clock'event and clock='1')then--WAIT UNTIL rising_edge(clock);--clock'event and clock='1';--count <= 0;--WAIT UNTIL (clock'EVENT AND clock = '1'); --WAIT riseedge clock = '1';--if (clock'event and clock='1') then--WAIT UNTIL rising_edge(clock);--count <= 1;--WAIT UNTIL (clock'EVENT AND clock = '1'); --WAIT UNTIL clock = '1';--if (clock'event and clock='1')then--WAIT UNTIL rising_edge(clock);--count <= 2;--end if;--end if;--end if;-- END PROCESS;END counter;六计数器ELSEcount_int <= count_int 1;--ELSE-- NULL ;--IF (count_int="1001") THEN--count_int<="0000";END IF;END IF;END PROCESS;count <= count_int;-- IF (reset='0') then--q<="0000";---ELSIF(clk'event and clk='1') THEN--q<=q 1;--IF (q<="1001") then--q<="0000";---END IF;--IF (reset<='1')THEN--q<="00";--ELSIF--wait until (clk'event and clk='1');--WAIT UNTIL (clk'EVENT AND clk = '1');--WAIT UNTIL (clock'EVENT AND clock = '1'); -- q<=q '1';--end if;--count<=q;-- WAIT UNTIL clock = '1';--if (clock'event and clock='1')then--WAIT UNTIL rising_edge(clock);--clock'event and clock='1';--count <= 0;--WAIT UNTIL (clock'EVENT AND clock = '1'); --WAIT riseedge clock = '1';--if (clock'event and clock='1') then--WAIT UNTIL rising_edge(clock);--count <= 1;--WAIT UNTIL (clock'EVENT AND clock = '1'); --WAIT UNTIL clock = '1';--if (clock'event and clock='1')then--WAIT UNTIL rising_edge(clock);--count <= 2;--end if;--end if;--end if;-- END PROCESS;END counter;四计数器--WAIT UNTIL (clock'EVENT AND clock = '1'); -- q<=q '1';--end if;--count<=q;-- WAIT UNTIL clock = '1';--if (clock'event and clock='1')then--WAIT UNTIL rising_edge(clock);--clock'event and clock='1';--count <= 0;--WAIT UNTIL (clock'EVENT AND clock = '1'); --WAIT riseedge clock = '1';--if (clock'event and clock='1') then--WAIT UNTIL rising_edge(clock);--count <= 1;--WAIT UNTIL (clock'EVENT AND clock = '1'); --WAIT UNTIL clock = '1';--if (clock'event and clock='1')then--WAIT UNTIL rising_edge(clock);--count <= 2;--end if;--end if;--end if;-- END PROCESS; END counter;。

第5章 计数器VHDL描述

第5章 计数器VHDL描述

调整进制
PROCESS (clr，clk) BEGIN IF(clr=‗1‘) THEN Count_B<=―00000000‖; q <= ‗0‘; ELSIF (clk'EVENT AND clk = ‗1‘ ) THEN IF (Count_B = ―00001111‖) THEN Count_B<=―00000000‖; else Count_B<=count_B + 1;
END IF; END IF; END PROCESS;
一、基本计数器的设计
计数器是数字系统的一种基本部件，是典 型的时序电路。计数器的应用十分广泛， 常用于数/模转换、 计时、频率测量等。
加法计数器VHDL源程序：
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY countbasic IS PORT(clk:IN STD_LOGIC; q:BUFFER STD_LOGIC_VECTOR(7 DOWNTO 0)); END countbasic; ARCHITECTURE a OF counbasict IS BEGIN
同步复位
PROCESS (clock) BEGIN if clock =‗1‘ and clock‘EVENT then if reset = ‗1‘ then sout <= ‗0‘; tmp <= ‗0‘; else sin sout <= sin; tmp tmp <= not tmp; clock reset end if; END IF; END PROCESS;
简单时序电路的VHDL描述

基于VHDL的16进制计数器的程序设计

基于VHDL的16进制计数器的程序设计

实事求是实验课程名称通信系统集成电路设计实验项目名称 Quartus II实验操作实验一：Quartus II操作及16进制加法器1.实验目的a)熟悉熟悉EDA工具QuartusII及modelsim软件的使用方法。

掌握用quartus ii或其他EDA软件对VHDL源程序进行编译、调试、修改、波形仿真。

b)学习VHDL程序的软件及硬件的编写及仿真方法并熟练掌握VHDL程序的编写方法和注意事项。

c)编写、调试出16进制计数器的程序，仿真出波形。

d)在上面的基础上做出PCM9程序，并仿真出波形数据。

2.实验器材a)电脑中要有Quartus II 软件b)电脑中要有Modelsim软件3.实验内容a)熟悉Quartus II和modelsim软件，并将两个软件进行配置，使软件可以用于为后面的软件进行调试。

b)尽量自己编写VHDL程序，做16进制的计数器实验，包括计数器程序和测试平台。

c)了解模块设计方法和思想，并设计并搭建测试平台。

实事求是实事求是4. 实验要求a) 熟悉两个软件并配置好相关环境。

熟悉两个软件并配置好相关环境。

b) 编写实验用的VHDL 程序。

程序。

c) 使用Quartus II 编译，查找错误并修改到正确无误。

编译，查找错误并修改到正确无误。

d) 使用Quartus II 仿真，生成波形文件。

仿真，生成波形文件。

e) 保存相关文件，并书写实验报告。

保存相关文件，并书写实验报告。

5. 实验步骤及结果a) 建立工程并加入16进制模块和测试平台。

进制模块和测试平台。

1. 建立工程。

建立工程。

在菜单栏里有在菜单栏里有 file àNew Project Wizard ，点击Next 到这个界面。

到这个界面。

输入项输入项目名称。

后点击Finish ，完成项目的创建。

，完成项目的创建。

2. 建立文件。

建立文件。

在菜单栏里有在菜单栏里有 file àNew ，跳转到下面这个界面。

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1. 具有CLK，Q端口的简单加法计数器，要程序和最后的RTL图；LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CNT4 ISPORT ( CLK : IN STD_LOGIC;Q : OUT INTEGER RANGE 15 DOWNTO 0);END;ARCHITECTURE behav OF CNT4 ISSIGNAL D,Q1 : INTEGER RANGE 15 DOWNTO 0;BEGINPROCESS (CLK)BEGINIF CLK'EVENT AND CLK='1'THEN Q1<=D;END IF;END PROCESS;D<=Q1+1;Q<=Q1;END behav;2. 具有异步清零aclr，CLK，Q端口的加法计数器，要程序和最后的RTL图；LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL ;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CNT4 ISPORT ( CLK,ACLR : IN STD_LOGIC;Q : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)); END ;ARCHITECTURE behav OF CNT4 ISSIGNAL Q1 : STD_LOGIC_VECTOR(15 DOWNTO 0);BEGINPROCESS (CLK,ACLR)BEGINIF ACLR='0' THENQ1<=(OTHERS=>'0');ELSIF CLK'EVENT AND CLK='1' THENQ1<=Q1+1;END IF;END PROCESS;Q<=Q1;END behav;3. 具有同步清零sclr，CLK，Q端口的加法计数器，要程序和最后的RTL图；LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL ;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CNT4 ISPORT ( CLK,SCLR : IN STD_LOGIC;Q : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)); END ;ARCHITECTURE behav OF CNT4 ISSIGNAL Q1 : STD_LOGIC_VECTOR(15 DOWNTO 0);BEGINPROCESS (CLK,SCLR)BEGINIF CLK'EVENT AND CLK='1' THENIF SCLR='1' THENQ1<=(OTHERS=>'0');ELSEQ1<=Q1+1;END IF;END IF;END PROCESS;Q<=Q1;END behav;4. 具有异步置位apre，CLK，Q端口的加法计数器，要程序和最后的RTL图；LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CNT4 ISPORT(CLK :IN STD_LOGIC;APRE:IN STD_LOGIC;Q :OUT STD_LOGIC_VECTOR(3 DOWNTO 0));END;ARCHITECTURE behav OF CNT4 ISSIGNAL Q1 :STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINPROCESS(CLK,APRE)BEGINIF APRE='1' THENQ1<="0001";ELSIF CLK'EVENT AND CLK='1' THENQ1<=Q1+1;END IF;END PROCESS;Q<=Q1;END behav;5. 具有同步置位spre，CLK，Q端口的加法计数器，要程序和最后的RTL图；LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CNT4 ISPORT(CLK :IN STD_LOGIC;SPRE:IN STD_LOGIC;Q :OUT STD_LOGIC_VECTOR(3 DOWNTO 0));END;ARCHITECTURE behav OF CNT4 ISSIGNAL Q1 :STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINPROCESS(CLK,SPRE)BEGINIF CLK'EVENT AND CLK='1' THENIF SPRE='1' THENQ1<="0001";ELSEQ1<=Q1+1;END IF;END IF;END PROCESS;Q<=Q1;END behav;6. 具有异步清零aclr，异步置位apre，CLK，Q端口的加法计数器，要程序和最后的RTL 图；LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CNT4 ISPORT(CLK :IN STD_LOGIC;ACLR:IN STD_LOGIC;APRE:IN STD_LOGIC;Q :OUT STD_LOGIC_VECTOR(3 DOWNTO 0));END;ARCHITECTURE behav OF CNT4 ISSIGNAL Q1 :STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINPROCESS(CLK,APRE,ACLR)BEGINIF ACLR='1' THENQ1<="0000";ELSEIF APRE='1' THENQ1<="0001";ELSIF CLK'EVENT AND CLK='1' THENQ1<=Q1+1;END IF;END IF;END PROCESS;Q<=Q1;END behav;7. 具有同步使能ENB，CLK，Q端口的加法计数器，要程序和最后的RTL图；LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CNT4 ISPORT(CLK :IN STD_LOGIC;ENB :IN STD_LOGIC;Q :OUT STD_LOGIC_VECTOR(3 DOWNTO 0));END;ARCHITECTURE behav OF CNT4 ISSIGNAL Q1 :STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINPROCESS(CLK,ENB)BEGINIF CLK'EVENT AND CLK='1' THENIF ENB='1' THENQ1<=Q1+1;END IF;END IF;END PROCESS;Q<=Q1;END behav;8. 具有异步清零aclr，异步置位apre，同步使能ENB，CLK，Q端口的加法计数器，要程序和最后的RTL图；LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CNT4 ISPORT(CLK :IN STD_LOGIC;ACLR:IN STD_LOGIC;ENB :IN STD_LOGIC;APRE:IN STD_LOGIC;Q :OUT STD_LOGIC_VECTOR(3 DOWNTO 0));END;ARCHITECTURE behav OF CNT4 ISSIGNAL Q1 :STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINPROCESS(CLK,APRE,ACLR,ENB)BEGINIF ACLR='1' THENQ1<="0000";ELSEIF APRE='1' THENQ1<="0001";ELSIF CLK'EVENT AND CLK='1' THENIF ENB='1' THENQ1<=Q1+1;END IF;END IF;END IF;END PROCESS;Q<=Q1; END behav;。

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