东南大学 数电实验报告 FPGA时序逻辑电路
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10 10 10 10 10 10 10 10 10 10 10 10 10 10
0100 0101 0101 0110 0110 0111 1000 1000 1001 1010 1011 1100 1101 111X
X 0 1 0 1 X 0 1 X X X X X X
001 010 011 010 011 001 010 011 100 110 111 000 000 000
4
FPGA
1 2 3 4
FPGA Xilinx ISE Schematic VHDL
C I 2C I 2C
I 2C
(SDA) SDA 0 (Z) SCL SCL IC
2
(SCL) I2C SCL 1 SDA SCL SDA START STOP I 2C
SDA SDA SDA
IC
2
I 2C 8
7 (MSB) -> -> -> STOP -> -> ACK-> ACK-> -> ->
3
SCL
SDA
4
I 2C H 1 (Z) 1 1
clkin sclclk sdaclk modctl1 ~ modctl0 scl sda resp led_ok num7 ~ num0 ct rst SCL SDA SCL SDA
XXXX 0000 0001 0001 0010 0010 0011 01XX 1XXX 0000 0001 0001 0010 0011 0100 0101 011X 1XXX 0000 0001 0001 0010 0010 0011 0011
X X 0 1 0 1 X X X X 0 1 X X X X X X X 0 1 0 1 0 1
EQ
SDA X X X
ROM
RIN(6:5) MODCTL(1:0) RIN(4:1) STATECNT(3:0) RIN(0) SEND_C OMPLETE ROUT(11:9) STATEOUT(2:0) ROUT(8) SCNTEN ROUT(7:0) DATAOUT(7:0)
00 01 01 01 01 01 01 01 01 11 11 11 11 11 11 11 11 11 10 10 10 10 10 10 10
CE 0 0 1 0 0 0 0 0
CLR 1 1 0 1 1 1 1 1
CE 0 0 0 0 1 0 0 0
CLR 1 1 1 1 0 1 1 1
EQ 0
SCL Z Z SCLCLK SCLCLK
SDA Z ↓ W_D Z Z 0 Z ↑
LED_OK 0
SDA-O X X X SDA
D_V
SCLCLK SCLCLK SCLCLK Z
000 001 010 011 010 011 111 000 000 001 010 011 100 110 111 000 000 000 001 010 011 010 011 010 011
0 1 0 0 0 0 1 0 0 1 0 0 0 1 1 0 0 0 1 0 0 0 0 0 0
00000000 00000000 11010000 00000000 10101010 00000000 00000000 00000000 00000000 00000000 11010001 00000000 00110011 00000000 00000000 00000000 00000000 00000000 00000000 11010000 00000000 00000011 00000000 00110011 00000000
1 0 0 0 0 1 0 0 0 1 1 0 0 0
00000000 11010000 00000000 00000101 00000000 00000000 11010001 00000000 01010101 00000000 00000000 00000000 00000000 00000000
11010000 ACK
00000101 ACK Repeated start
110100来自百度文库1 ACK
01010101 NACK
01010101
55
5 I 2C SCL SDA ROM SCL SDA
FPGA Schematic VHDL FPGA
Xilinx ISE
1 2 3 I/O
ACK-> -> NACK->
1 ROM ROM ROM
HOLD START WRITE WACK READ ACK NACK STOP
SEND_COMPLETE_ACK READ_COMPLETE READ_COMPLETE_ACK WRITE_DATA REG_RECV(7:0) ROM_VERIFY_DATA(7:0) DATA_VERIFIED
D0h
AAh
11010000 ACK
10101010 ACK
D0h
33h
11010001 ACK
00110011 NACK
00110011
33
IC 33h 05h 55h
2
D0h
03h
11010000 ACK
00000011 ACK
00110011 ACK Repeated start
ROM ROUT(11:0) ROUT(i) 11 10 9 8 7 6 5 4 3 2 1 0 STATEOUT(2) STATEOUT(1) STATEOUT(0) SCNTEN DATAOUT(7) DATAOUT(6) DATAOUT(5) DATAOUT(4) DATAOUT(3) DATAOUT(2) DATAOUT(1) DATAOUT(0) 8
STATEOUT(2:0) 0 1 2 3 4 5 6 7 000 001 010 011 100 101 110 111 HOLD START WRITE WACK READ ACK NACK STOP
CE HOLD START WRITE WACK READ ACK NACK STOP 1 1 0 0 0 1 1 1
S_C_A R_C R_C_A W_D R_R R_V_D D_V ROM ACK
2
ROM RIN(6:0) RIN(i) 6 5 4 3 2 1 0 MODCTL(1) MODCTL(0) STATECNT(3) STATECNT(2) STATECNT(1) STATECNT(0) SEND_COMPLETE