数字时钟c语言代码
- 1、下载文档前请自行甄别文档内容的完整性，平台不提供额外的编辑、内容补充、找答案等附加服务。
- 2、"仅部分预览"的文档,不可在线预览部分如存在完整性等问题,可反馈申请退款(可完整预览的文档不适用该条件!)。
- 3、如文档侵犯您的权益，请联系客服反馈,我们会尽快为您处理(人工客服工作时间：9:00-18:30)。
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY SECOND1 IS
PORT(CLKS,CLR:IN STD_LOGIC;
SECS,SESG:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
COUT1:OUT STD_LOGIC);
END SECOND1;
ARCHITECTURE S OF SECOND1 IS
BEGIN
PROCESS(CLKS,CLR)
V ARIABLE SS,SG:STD_LOGIC_VECTOR(3 DOWNTO 0);
V ARIABLE CO:STD_LOGIC;
BEGIN
IF CLR='1' THEN SS:="0000";SG:="0000";
ELSIF CLKS'EVENT AND CLKS='1' THEN
IF (SS="0101") AND (SG="1001") THEN
SS:="0000";SG:="0000";CO:='1';
ELSIF SG<"1001" THEN
SG:=SG+1;CO:='0';
ELSIF SG="1001" THEN
SG:="0000";SS:=SS+1;CO:='0';
END IF;
END IF;COUT1<=CO;
SECS<=SS;
SESG<=SG;
END PROCESS;
END S;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY MIN1 IS
PORT(CLKM,CLR:IN STD_LOGIC;
MINS,MING:BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0);
ENMIN,ALARM:OUT STD_LOGIC);
END MIN1;
ARCHITECTURE M OF MIN1 IS
BEGIN
PROCESS(CLKM,CLR)
V ARIABLE MS,MG:STD_LOGIC_VECTOR(3 DOWNTO 0);
V ARIABLE SO,ALM:STD_LOGIC;
BEGIN
IF CLR='1' THEN MS:="0000";MG:="0000";
ELSIF CLKM'EVENT AND CLKM='1' THEN
IF (MS="0101") AND (MG="1001") THEN
MS:="0000";MG:="0000";SO:='1';ALM:='1';
ELSIF MG<"1001" THEN
MG:=MG+1;SO:='0';ALM:='0';
ELSIF MG="1001" THEN
MG:="0000";MS:=MS+1;SO:='0';ALM:='0';
END IF;
END IF;
ALARM<=ALM;
ENMIN<=SO;
MINS<=MS;
MING<=MG;
END PROCESS;
END M;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY HOUR1 IS
PORT(CLKH,CLR:IN STD_LOGIC;
HOURS,HOURG:OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); END HOUR1;
ARCHITECTURE H OF HOUR1 IS
BEGIN
PROCESS(CLKH,CLR)
V ARIABLE HS,HG:STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
IF CLR='1' THEN HS:="0000";HG:="0000";
ELSIF CLKH'EVENT AND CLKH='1' THEN
IF (HS="0010") AND (HG="0011") THEN
HS:="0000";HG:="0000";
ELSIF HG<"1001" THEN
HG:=HG+1;
ELSIF HG="1001" THEN
HG:="0000";HS:=HS+1;
END IF;
END IF;
HOURS<=HS;
HOURG<=HG;
END PROCESS;
END H;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY JIAOFEN IS
PORT(EN,CLK,SECIN,M1:IN STD_LOGIC;
MINSET:OUT STD_LOGIC);
END JIAOFEN;
ARCHITECTURE F OF JIAOFEN IS
BEGIN
PROCESS(EN,M1)
BEGIN
IF EN='1' THEN
IF M1='1' THEN
MINSET<=CLK;
ELSE MINSET<=SECIN;
END IF;
ELSE MINSET<=SECIN;
END IF;
END PROCESS;
END F;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY JIAOSHI IS
PORT(EN,CLK,MININ,H1:IN STD_LOGIC;
HOURSET:OUT STD_LOGIC);
END JIAOSHI;
ARCHITECTURE J OF JIAOSHI IS
BEGIN
PROCESS(EN,H1)
BEGIN
IF EN='1' THEN
IF H1='1' THEN
HOURSET<=CLK;
ELSE HOURSET<=MININ;
END IF;HOURSET<=MININ;
END IF;
END PROCESS;
END J;