郭天祥51单片机开发板原理图

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0 A 0 A 0 A 0 A @1 " @1 " @1 " @1 " ?3 ?3 ?3 ?3 4 "A 4 "A 4 "A 4 "A 5 @ C ? 5 @ ? 5 @ ? 5 @ ? C C C 501 ? @ @ 502 ? @ @ 503 ? @ @ 504 ? @ @ C - C - C - C - ". @ ". @ ". @ ". @ A A A A 0 0 0 0 / 061 / 062 / 063 / 064
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91 61 69 3 69
1
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VCC WE1 b c e d WE3 b c e d WE5 b c e d VCC R3 1 2 3 4 5 1 2 3 4 5 1 2 3 4 5 LED1 LED2 LED3 PDIUSBD12 D0 D1 D2 D3 g 10 h 9 a 8 f 7 WE26 g 10 h 9 a 8 f 7 WE46 g 10 h 9 a 8 f 7 WE66 D4 D5 D6 D7 ALE CSUSB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 DATA0 A0 DATA1 VOUT3.3 DATA2 D+ DATA3 DGND VCC DATA4 XTAL2 DATA5 XTAL1 DATA6 GL_N DATA7 RESET_N ALE EOT_N CS_N DMACK_N SUSPEND DMREQ CLKOUT WR_N INT_N RD_N D12 28 27 26 25 24 23 22 21 20 19 18 17 16 15 C1 104 R4 R5 VCC UXT1 UXT2 R6 1K R7 R8 R9 WR RD R10 1M D9 10K 10K 10K C2 UXT1 20P Y2 6M C3 UXT2 VCC 40 P1 89S52 P10/T P11/T P12 P13 P14 P15 P16 P17 INT1 INT0 P00 P01 P02 P03 P04 P05 P06 P07 P20 P21 P22 P23 P24 P25 P26 P27 39 38 37 36 35 34 33 32 21 22 23 24 25 26 27 28 VCC D0 D1 D2 D3 D4 D5 D6 D7 1 2 3 4 5 6 7 8 9 10K 1 DULA11 D0 D1 D2 D3 D4 D5 D6 D7 2 3 4 5 6 7 8 9 U1 E VCC L GND D0 D1 D2 D3 D4 D5 D6 D7 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 20 10 19 18 17 16 15 14 13 12 a b c d e f g h VCC 1 WELA 11 D0 D1 D2 D3 D4 D5 D6 D7 2 3 4 5 6 7 8 9 U2 E VCC L GND D0 D1 D2 D3 D4 D5 D6 D7 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 20 10 19 18 17 16 15 14 13 12 VCC WE1 WE2 WE3 WE4 WE5 WE6 CSAD VCC DB7 DB6 DB5 RST FM FM 1K RXD TXD ALE/P PSEN 10 11 30 29 P3.0 P3.1 ALE R18 Q1 PNP P3 1 2 3 4 5 6
VREF RFB IOUT1 IOUT2
8 9 11 12
U6 R22 R23 10K 10K 1 2 3 5 6 7 A0 A1 A2
VCC
10 R21
SDA SCL
1 2 3 RS 4 5 LCDEN 6 D0 7 D1 8 D2 9 D3 10 D4 11 D5 12 D6 13 D7 14 P3.0 15 P3.1 16 VCC 17 VEE 18 VCC 19 20 TR1402
VCC S1 R2 R1 1M 1M
总开关
+
10K
R11 1K CJ1 10UF
+
A CJ2 10UF
USB 18 18 D1 D2 + USB接口 VCC
D10
74HC573 10K VCC 1 R15 10k B Re2 C11 2 1 ADIN 104 10K R12 1K VCC R13 R14 1K 2 CSAD 1 RD 2 WR 3 4 5 6 7 8 9 10 U5 VCC 20 19 18 17 16 15 14 13 12 11 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 2 1 INT1 INT1 3 TAP A
2 03 1 1 1 5 1 4 1 3 1 2 1 1 1 0 1 0 . 0 0 0 5 0 4
877
877 1 0 0 0 6 6 0 0 0 3 0 0 6 6. 877 03 03 . 03 71 1% 0 60 61 9 2 80 2 8
VCC I/O GND DS18B20
3 2 1
18B20
SDA SCL 18B20 FM CSUSB DIOLA DULA WELA
RST D11
R19 1K
74HC573 VCC
74HC573
DS18B20
VCC R20 10K
20
89S52 P4 10k Re1 VCC 1 2 3 RS 4 5 LCDEN 6 D0 7 D1 8 D2 9 D3 10 D4 11 D5 12 D6 13 D7 14 15 16 HEADER 16
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VEE
3 2K
W1 2
VCC 1
LCD1
C6 104
VCC
C
U7 CSDA WR VCC D0 D1 D2 D3 D4 D5 D6 D7 D 1 2 18 19 17 7 6 5 4 16 15 14 13 3 10 CS WR1 WR2 ILE XFER DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 GND GND DAC0832 VDD
1 2 3 4
4 VSS
VDD
8
SDA SCL WP 24C00
D13 P3.0
R24 1K
VCC
J1 DB9
5 9 4 8 3 7 2 6 1
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Title Size A Date: File: 1 2 3 4 5 2006-5-2 D:\pcb\..\TX2型开发板.SCHDOC Sheet of Drawn By: 6 Number Revision
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下载口
U3 A P2 1 2 3 4 5 6 7 8 9 1K VCC D1 D2 D3 D4 D5 D6 D7 D8 VCC 20 10 19 18 17 16 15 14 13 12 VCC E GND L Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 D0 D1 D2 D3 D4 D5 D6 D7 1 11 DIOLA 2 3 4 5 6 7 8 9 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8
C7 104
U4 1 2 3 4 5 6 7 8 C1+ VCC V+ GND C1- T1OUT C2+ R1IN C2- R1OUT VT1IN T2OUTT2IN R2IN R2OUT MAX232 C9 104 16 15 14 13 12 11 10 9
C10 104 P3.0 P3.1
C8 104
92 62 6 4 ,6 877 5 69
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95 65 ,/1 6 . 69
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1 7 8 0 7 669731 2 0 1 0 % 1 2 06 0 7/3)2
VCC 20 P5
DA输出接口 VCC D0 D1 D2 D3 D4 D5 D6 D7 D12 P6 1 2 3 4 5 6 7 8 9 10 P0口 VCC DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 P7 1 2 3 4 5 6 7 8 9 10 P1口 VCC SDA SCL 18B20 FM CSUSB DIOLA DULA WELA P8 1 2 3 4 5 6 7 8 9 10 P2口 VCC P3.0 P3.1 CSDA INT1 LCDEN RS WR RD P9 1 2 3 4 5 6 7 8 9 10 P3口 VCC
30P C4 30P C5 Y1 12MHZ X1 X2
20P B S22 VCC CJ3
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B
VCC
AD0804
P3.0 S6 P3.1 S10 CSDA S14 INT1 S18 LCDEN C RS WR RD S19 S20 S21 S15 S16 S17 S5 S11 S12 S13 S7 S8 S9 S2
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%' 2 %' 20 7 69 4
LCDEN
DB1 1 DB2 2 DB3 3 DB4 4 DB5 5 DB6 6 DB7 7 DB8 8 INT1 13 CSDA 12
1K R16 10K R17 RST
10UF
RS S3 WR S4 RD VCC
RS 15 T1 14 LCDEN T0 31 X1 19 X2 18 RST 9 GND RD 17 WR16 EA/VP X1 X2 RESET RD WR