iphone6电路图

8
7
6 5 4 3
2
1
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.
Thu Apr 17 17:11:44 2014
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
N61 CARRIER BUILD
D
PDF PAGE CONTENTS
2 2 SOC:MAIN N56_MLB 08/29/2013
3
3
SOC:I/OS
N56_MLB
08/29/2013
PART#
QTY
DESCRIPTION
REFERENCE DESIGNATOR(S)
CRITICAL
BOM OPTION
4
4
SOC:VDDCA,VDD1/2,VDD,VDD_CPU,VDD_GPU N56_MLB
08/29/2013
335S0998
1 NAND,19NM,16GX8,MLC,PPN1.5
U0604
CRITICAL
NAND_16G
5
5
SOC:GND,VDDIO18,VDDIOD,VDD_VAR_SOC N56_MLB
08/29/2013
335S0993
1
NAND,19NM,32GX8,MLC,PPN1.5
U0604
CRITICAL
NAND_32G
6
6
SOC:NAND
N56_MLB
08/29/2013
335S0994
1 NAND,19NM,64GX8,MLC,PPN1.5
U0604
CRITICAL
NAND_64G
SOC:CAM,LCD,LPDP,PCIE
N56_MLB
08/29/2013 335S00010
1
NAND,19NM,128GX8,TLC,PPN1.5
U0604
CRITICAL
NAND_128G
8
8
IO:BUTTON FLEX CONN
N61_MLB 08/26/2013
138S0867 1 C0610,C0611,C0614,C0634
CRITICAL
NAND_16G
9
9
AUDIO:L67 CODEC (1/2) N61_MLB
08/26/2013
CAP,X5R,10UF,20%,6.3V,0.65MM,HRTZ,0402
10
10
AUDIO:L67 CODEC (2/2)
N61_MLB 08/26/2013
138S0867
1 CAP,X5R,10UF,20%,6.3V,0.65MM,HRTZ,0402
CRITICAL
NAND_32G & NAND_64G
11
11
CAMERA:FRONT FLEX CONN N61_MLB
08/26/2013
138S00003
1
CAP,X5R,15UF,20%,6.3V,0.65MM,HRTZ,0402
CRITICAL
NAND_128G
12 12 POWER:ADI(1/2) N56_MLB 08/29/2013
13
13
POWER:ADI(2/2)
N56_MLB 08/29/2013
14
14
POWER:TIGRISR,VIBE DRIVER
N61_MLB
08/21/2013
ALTERNATE NAND BOM OPTIONS
15
15
DISPLAY:CHESTNUT,BACKLIGHT DRIVER
N61_MLB 08/26/2013
16
16
AUDIO:SPKR AMP,STROBE
N61_MLB
08/26/2013
PART NUMBER
ALTERNATE FOR BOM OPTION
REF DES
COMMENTS:
PART NUMBER
17
17
IO:TRISTAR2
N61_MLB 08/26/2013
335S0992
335S0998
ALTERNATE
U0604
18
18
IO:DOCK FLEX CONN N61_MLB
08/26/2013
TOSHIBA,NAND,16GB
19
19
SENSORS:COMPASS
N61_MLB 08/26/2013
335S1038
335S0998
ALTERNATE
U0604
HYNIX,NAND,16GB
20
20
DISPLAY:FLEX CONN
N61_MLB
08/26/2013
335S1040
335S0994
ALTERNATE U0604
HYNIX,NAND,64GB
21
21
SENSORS:MESA FLEX CONN
N61_MLB
08/26/2013
335S00014
335S0994
ALTERNATE
U0604
TOSHIBA,NAND,64GB
C
SENSORS:OSCAR,CARBON,PHOS,MAGNESIUM
N61_MLB
08/26/2013 335S00015 335S00010
ALTERNATE U0604
TOSHIBA,NAND128GB 23
23
CAMERA:REAR FLEX CONN
N61_MLB
08/26/2013
335S00009 335S0994
ALTERNATE
U0604
24
24
TOUCH:CUMULUS,MESON
N/A
N/A
SANDISK,NAND,64GB,TLC
25
25
POWER:BATT CONN,TPS,PD FEATURES
N61_MLB 08/26/2013
26 26
SYSTEM:VOLTAGE PROPERTIES N56_MLB
09/10/2013
27 27
SYSTEM:N61 SPECIFIC
N56_MLB 09/10/2013
28
28
BLANK
N56_MLB
09/10/2013
SHIELD BOM OPTIONS
CELL:ALIASES
30
31
AP INTERFACE & DEBUG CONNECTORS
N61_RADIO_MLB 03/24/2014
604-00241 1 SH2501
CRITICAL
COMMON
31
32
BASEBAND PMU (1 0F 2) N61_RADIO_MLB
03/24/2014
SUBASSY, SHIELD, UPPER FRONT, N61
32
33
BASEBAND PMU (2 OF 2)
N61_RADIO_MLB
03/24/2014
604-00242
1 SUBASSY, SHIELD, LOWER FRONT, N61
SH2502
CRITICAL
COMMON
33 34 BASEBAND (1 OF 2) N61_RADIO_MLB 03/24/2014
604-00243 1 SUBASSY, SHIELD, LOWER BACK, N61
SH2504 CRITICAL
COMMON
34
35
BASEBAND (1 OF 2)
N61_RADIO_MLB 03/24/2014
604-00244
1
SUBASSY, SA SHIELD, N61
SH2506
CRITICAL
COMMON
MOBILE DATA MODEM (2 OF 2) N61_RADIO_MLB
03/24/2014
36
37
RF TRANSCEIVER (1 0F 3)
N61_RADIO_MLB 03/24/2014
37
38
RF TRANSCEIVER (2 OF 3) N61_RADIO_MLB
03/24/2014
38
39
RF TRANSCEIVER (3 OF 3)
N61_RADIO_MLB 03/24/2014
39
40
QFE DCDC N61_RADIO_MLB
03/24/2014
40
41
2G PA
N61_RADIO_MLB 03/24/2014
41
42
VERY LOW BAND PAD N61_RADIO_MLB
03/24/2014
42 43
LOW BAND PAD
N61_RADIO_MLB 03/24/2014
43 44
MID BAND PAD N61_RADIO_MLB
03/24/2014
B
44
45
HIGH BAND PAD
N61_RADIO_MLB 03/24/2014
45
46
ANTENNA SWITCH N61_RADIO_MLB
03/24/2014
46
47
HIGH BAND SWITCH
N61_RADIO_MLB 03/24/2014
47
48
RX DIVERSITY N61_RADIO_MLB
03/24/2014
48
49
GPS
N61_RADIO_MLB 03/24/2014
49
50
GPS
N61_RADIO_MLB
03/24/2014
50
51
ANTENNA FEEDS
N61_RADIO_MLB 03/24/2014
51
52
WIFI/BT: MODULE AND FRONT END
N61_RADIO_MLB
03/24/2014
52
53
N61_RADIO_MLB 03/24/2014
53
54
JUMPER
N61_RADIO_MLB
03/24/2014
54 55 JUMPER N61_RADIO_MLB 03/24/2014
SCH 051-9903
BRD 820-3486
A
MCO 056-6825
BOM 639-4237 (16GB,BETTER)
BOM 639-00208 (16GB,BETTER,DTD)
BOM 639-5838 (32GB,BEST) BOM 639-00209 (32GB,BEST,DTD) BOM 639-5839 (64GB,ULTRA)
BOM 639-00210 (64GB,ULTRA,DTD)
BOM 639-00025(128GB,SUPREME,TLC) BOM 639-00212(128GB,SUPREME,TLC,DTD)
CK
REV
ECN
DESCRIPTION OF REVISION
APPD
DATE
7 0002727241 ENGINEERING RELEASED
2014-04-18
PART#
QTY DESCRIPTION
REFERENCE DESIGNATOR(S)
CRITICAL
BOM OPTION
051-9903
1
SCH, MLB, N61
SCH
CRITICAL
?
820-3486
1
PCBF, MLB, N61
PCB
CRITICAL ?
825-6838
1
EEEE FOR 639-4237 16GB
EEEE_G16T CRITICAL
EEEE_16G
825-6838
1
EEEE FOR 639-5838 32GB
EEEE_G16R
CRITICAL EEEE_32G
825-6838
1
EEEE FOR 639-5839 64GB
EEEE_G16Q CRITICAL
EEEE_64G
825-6838
1
EEEE FOR 639-00025 128GB
EEEE_G16N
CRITICAL EEEE_128G
825-6838
1
EEEE FOR 639-00208 16GB
EEEE_F98F CRITICAL
EEEE_16G_TDDLTE
825-6838
1
EEEE FOR 639-00209 32GB
EEEE_FQK0
CRITICAL EEEE_32G_TDDLTE
825-6838
1
EEEE FOR 639-00210 64GB
EEEE_FQJY CRITICAL
EEEE_64G_TDDLTE
825-6838
1
EEEE FOR 639-00212 128GB
EEEE_FY9W
CRITICAL
EEEE_128G_TLC_TDDLTE
ALTERNATE BOM OPTIONS
PART NUMBER ALTERNATE FOR
BOM OPTION
REF DES COMMENTS:
PART NUMBER
152S1844
152S1836
ALTERNATE
L1604
TY ALT INDUCTOR 152S1842
152S1849
ALTERNATE
L1519
TY ALT INDUCTOR
197S0392
197S0369 ALTERNATE
Y1200
ESPON ALT XTAL 197S0399
197S0369
ALTERNATE
Y1200
NDK ALT XTAL
338S1285
338S1202 ALTERNATE
U1601
L21 SPKAMP
152S2034 152S2033
ALTERNATE
1.2MM 1.0UH, CYNTEC 152S00004
152S2049 ALTERNATE
1.2MM 0.47UH, CYNTEC
339S00005
339S0246
ALTERNATE
U0201
FIJI, B0, SAMSUNG
339S0247
339S0246 ALTERNATE
U0201
FIJI, B0, HYNIX
339S00006
339S0246
ALTERNATE
U0201
FIJI, B1, E
339S00007
339S0246 ALTERNATE
U0201
FIJI, B1, H
339S00008
339S0246
ALTERNATE
U0201
FIJI, B1, S 155S0773
155S0453 ALTERNATE
TY 120OHM FERRITE
118S0764
118S0717
ALTERNATE
R1309
3.92KOHM, 01005 343S0688
343S0638 ALTERNATE
U2401
CUMULUS C1, FAB4
138S00005
138S00003
ALTERNATE
C1290
15UF,0402,HRTZL CAP
155S00011
155S00008 ALTERNATE
L1135
CMC,90OHM,MURATA
377S0168
377S0140
ALTERNATE
DZ1113
155S0885
155S0610 ALTERNATE
FL1802,FL1803 138S0648
138S0652
ALTERNATE
C1018
138S0657
138S0702 ALTERNATE
C1106
338S00028
338S00017
ALTERNATE
U2203
CARBON, BOSCH, BMI162BC
338S00029
338S00017 ALTERNATE
U2203
CARBON, ST, AP6DS2AA
335S00013 335S0894
ALTERNATE
U0301
ST 8K EEPROM
DRAWING TITLE
SCHEM,MLB,N61
DRAWING NUMBER SIZE
Apple Inc.
051-9903
D
7.0.0
NOTICE OF PROPRIETARY PROPERTY:
BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 1 OF 55
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
1 OF 54 IV ALL RIGHTS RESERVED
D C B A
8
7 6 5 4 3
D
C
B
A
8 7 6 5 4 3 2 1
FIJI: JTAG,USB,HSIC,XTAL
ROOM=SOC
D
FL0201 1KOHM-25%-0.2A
PP1V8_XTAL
1
2
PP1V8 ROOM=SOC
0201
PP1V2 R0201
1
2 PP1V2_PLL
C0203
C0204
0.1UF
2.2UF
0.00
01005
01 C0206
1 C0213 1 C0207 1 C0208
4V
6.3V
X5R
X5R
0.1UF
0.1UF
0.01UF
0.01UF
000000
4V
4V
6.3V
6.3V
01005
01005
01005 01005
ROOM=SOC
VOLTAGE=0V
1 C0212
PP3V3_USB
0.1UF
C0202
1
01005
0.22UF
0.1UF
2
0%
D 7
A N 4
M 16
V 19
V 17
G 7
E 14
J 7
E 2
E 1 D
16
N 5
ROOM=SOC
X5R-CERM
1 C0211
0.1UF
2 4V P2MM-NSM PLACE NEAR SOC.
01005
3.3V _
_
C
PP SM
PP0203
P2MM-NSM
0.95V
1.2V
PP SM
PP0204
U0201
PP0201
NC
C1
UH1_HSIC0_DATA
POP-FIJI-1GB-DDR-B0
C2 BGA P4MM
NC
UH1_HSIC0_STB
SYM 1 OF 13
REMOVE PP IF
50_AP_BI_BB_HSIC1_DATA AR4 UH2_HSIC1_DATA
PP0202
ROOM=SOC
D1 5
SPACE IS NEEDED BASEBAND 29 50_AP_BI_BB_HSIC1_STB
AP4 NC F5 90_AP_BI_TRISTAR_USB0_P
PP
USB_DP
K4 E5 90_AP_BI_TRISTAR_USB0_N
JTAG_SEL USB_DM
NC
L4
JTAG_TRTCK
USBHS ON/OFF TOLERANCE 5V/1.98V
J5
PP1V8
NC
JTAG_TRST*
L3 NO_XNET_CONNECTION=TRUE
NC
JTAG_TDO K5 D3 USB_VBUS_DETECT
1R0206
NC
JTAG_TDI
USB_VBUS
100K
SERIAL MODE NAMES
K2
D2
5%
TRISTAR_TO_AP_JTAG_SWCLK
JTAG_TCK
USB_ID
NC
1/32W
MF
2 01005
AH32 RESET*
RESET_1V8_L
USB_REXT D1 USB_REXT
AJ33
1R0203
ROOM=SOC W4
CFSB1
NOTE: NEW USB_REXT
1 C0201 AH33
HOLD_RESET
A16
1%
AH31 A15
6.3V
TST_CLKOUT
XO0
B
01005
AG29
FAST_SCAN_CLK
AH29 TESTMODE C0209
12PF
2
I2C ADDRESS MAP
1
Y0201
3
5
%
1.00M 1.60X1.20MM-SM 01005 PCB: PLACE THIS XW
45_XTAL_24M_O
R0207
2
C0210
XW0204
1
DEVICE
BINARY
7-BIT HEX 8-BIT HEX
12PF
SHORT-10L-0.1MM-SM
45_XTAL_24M_O_R
2
45_XTAL_24M_O_GND
1 2
ADI PMU: 1110100X
0X74
0XE8 1
2
1
%
MF ROOM=SOC
LM3534 BL DRIVER:
1100011X
0X63
0XC6
1/32W 01005 5%
TRISTAR:
0011010X
0X1A
0X34 16V
CERM
CHESTNUT: 0100111X
0X27
0X4E
I2C1
TIGRIS CHARGER:
1110101X 0X75 0XEA
LINEAR VIBE: 1011010X 0X5A 0XB4
CS35L19B AMP:
1000000X 0X40 0X80
MESA EEPROM (MEMORY): 1010110X 0X56 0XAC
MESA EEPROM (ID): 1011110X 0X5E 0XBC
I2C2
CT814 ALS:
0101001X 0X29 0X52
DISPLAY EEPROM:
1010001X
0X51
0XA2
RCAM I2C
A
OPEL STROBE DRIVER:
1100011X
0X63
0XC6
SYNC_MASTER=N56_MLB
SYNC_DATE=08/29/2013
REAR FACING CAM:
0010000X
0X10
0X20
PAGE TITLE
SOC:MAIN
8
7 6 5 4 3 2 1
D C
B
A
FIJI: DIGITAL I/O,BOOTSTRAPPING
PP1V8 2
ROOM=SOC
ROOM=SOC ROOM=SOC ROOM=SOC
ROOM=SOC ROOM=SOC
R03021 R03031 R03041 R03051
R0306 1R0308 1
P2MM-NSM
D
2.2K
2.2K 2.2K
2.2K 1.33K
1.33K
1 PP SM PP0301
1/32W
1/32W
1/32W
1/32W
1/32W
1%
P2MM-NSM
1 PP SM
PP0302 01005 2 01005 2 01005 2 01005 2 01005 2 01005 2
ROOM=SOC
R0301
33.2
45_AP_TO_CODEC_I2S0_MCLK_R D26 I2S0_MCK I2C0_SCL AM32
AP_TO_I2C0_SCL 13 15 17
45_AP_TO_CODEC_I2S0_MCLK 1
2
U0201
PP1V8_SDRAM
AP_TO_HEADSET_HS3_CTRL
AC1 GPIO0
1%
45_AP_TO_CODEC_ASP_I2S0_BCLK
U30 I2S0_BCLK
I2C0_SDA AM31
AP_BI_I2C0_SDA 13
U0201
AP_TO_CODEC_ASP_I2S0_LRCLK
U31 POP-FIJI-1GB-DDR-B0 18 AP_TO_HEADSET_HS4_CTRL MF
AC2 GPIO1
01005
U32 I2S0_LRCK BGA
G R P 3
Y31
8
BUTTON_TO_AP_VOL_UP_L
AC3 GPIO2
POP-FIJI-1GB-DDR-B0
CODEC ASP
10 CODEC_TO_AP_ASP_I2S0_DIN
I2S0_DIN SYM 3 OF 13
I2C1_SCL
AP_TO_I2C1_SCL 14 16 21
8 BUTTON_TO_AP_VOL_DOWN_L
AC4 GPIO3 BGA
AP_TO_CODEC_ASP_I2S0_DOUT
U33 I2S0_DOUT
I2C1_SDA Y30
AP_BI_I2C1_SDA 14
SYM 2 OF 13
5
PP1V8_ALWAYS
16 SPKAMP_TO_AP_INT_L
AD1 GPIO4
NC R30 AH1 AP_TO_I2C2_SCL 11 20
16 AP_TO_SPKAMP_BEE_GEES
AD2 GPIO5
TMR32_PWM0 AM3 OSCAR_BI_AP_TIME_SYNC_HOST_INT
I2S1_MCK
I2C2_SCL
220K
ROOM=SOC AP_TO_BB_RST_L
AD3 GPIO8
TMR32_PWM1 AM4 AP_TO_VIBE_TRIG 14
29 45_AP_TO_BT_I2S1_BCLK P30 I2S1_BCLK
G R P
4
G R P 2
I2C2_SDA AH2
AP_BI_I2C2_SDA 11
R0314
R0313
AP_TO_BT_WAKE AD4 GPIO7 TMR32_PWM2 AN 3NC
BLUETOOTH
AP_TO_BT_I2S1_LRCLK
T30 I2S1_LRCK
I2C3_SCL AN 1
NC
392K
BT_TO_AP_I2S1_DIN R31
I2C3_SDA
5%
1/32W
AP_TO_WLAN_JTAG_SWCLK AG31 GPIO9
UART0_RXD AL2
TRISTAR_TO_AP_DEBUG_UART0_RXD 17
ROOM=SOC
AP_TO_BT_I2S1_DOUT
T31
I2S1_DOUT
NC 1/32W
MF R0311 AL29 45_AP_TO_PMU_AND_BL_DWI_CLK
13
P2MM-NSM
MF
2
01005 2
AP_TO_WLAN_JTAG_SWDIO
AG32 GPIO10
UART0_TXD AL1
AP_TO_TRISTAR_DEBUG_UART0_TXD 17
DWI_CLK
16 45_AP_TO_SPKAMP_I2S2_MCLK
45_AP_TO_SPKAMP_I2S2_MCLK_R D25 PP0305
BUTTON_TO_AP_MENU_KEY_L
Y3 GPIO11 1 2
I2S2_MCK
BUTTON_TO_AP_HOLD_KEY_L Y4 GPIO12
UART1_CTSN H30
BT_TO_AP_UART1_CTS_L
1%
45_AP_TO_CODEC_XSP_I2S2_BCLK
N30 I2S2_BCLK
DWI_DO AL30 45_AP_TO_PMU_AND_BL_DWI_DO
P2MM-NSM
1/32W
AP_TO_CODEC_XSP_I2S2_LRCLK
N31
PP SM
PP0304
13 PMU_TO_AP_IRQ_L
AK31 GPIO13 UART1_RTSN H31
AP_TO_BT_UART1_RTS_L 29
01005
10 CODEC_TO_AP_XSP_I2S2_DIN P32 I2S2_DIN
29 BB_TO_AP_IPC_GPIO1 AE1 GPIO14 UART1_RXD H32 BT_TO_AP_UART1_RXD 29 BLUETOOTH
29 AP_TO_BB_WAKE_MODEM
AF30 GPIO15 UART1_TXD H33 AP_TO_BT_UART1_TXD 29 CODEC XSP & SPKR AMP
AP_TO_CODEC_XSP_I2S2_DOUT
P33 I2S2_DOUT BOARD_ID3
NC AE2 GPIO16
PP0303
ALS_TO_AP_INT_L
AA2
AP_TO_STOCKHOLM_SIM_SEL AE3 GPIO17
UART2_CTSN AL31
BB_TO_AP_UART2_CTS_L
P2MM-NSM
I2S3_MCK AA4
BOOT_CONFIG0 AE4 GPIO18
UART2_RTSN AM33
AP_TO_BB_UART2_RTS_L 29 1 45_AP_TO_BB_I2S3_BCLK
I2S3_BCLK
13 AP_TO_PMU_KEEPACT
AK32 GPIO19 UART2_RXD AL32 BB_TO_AP_UART2_RXD 17 29 BASEBAND ROOM=SOC
AP_TO_BB_I2S3_LRCLK AA3 I2S3_LRCK
NC
GPIO20 UART2_TXD
AP_TO_BB_UART2_TXD 17 29
BASEBAND
AP_TO_BB_I2S3_DOUT
Y2
29 BB_TO_AP_DEVICE_RDY
AF4 I2S3_DOUT
GPIO21 G R P 2
29 BB_TO_AP_GPS_SYNC
AH4 GPIO22 UART3_CTSN
F30
STOCKHOLM_TO_AP_UART3_CTS_L 29 13 TRISTAR_TO_AP_INT
AB32 I2S4_MCK
BOOT_CONFIG1 29 AP_TO_BB_HOST_RDY
AJ1 GPIO23
UART3_RTSN G30
AP_TO_STOCKHOLM_UART3_RTS_L 29
STOCKHOLM
CODEC VSP
29 BB_TO_AP_RESET_DET_L
AD29 GPIO24
UART3_RXD G31
STOCKHOLM_TO_AP_UART3_RXD 29 0
45_AP_TO_CODEC_VSP_I2S4_BCLK
AB33 I2S4_BCLK 25 FORCE_DFU
AK33 GPIO26
10 CODEC_TO_AP_VSP_I2S4_DIN
AA32 I2S4_DIN SEP_I2C_SCL AR31 AP_TO_EEPROM_I2C_SCL 3
DFU STATUS
AJ30 GPIO27 UART4_CTSN AE31 WLAN_TO_AP_UART4_CTS_L 29
AP_TO_CODEC_VSP_I2S4_DOUT AA33 I2S4_DOUT
SEP_I2C_SDA AP31
AP_BI_EEPROM_I2C_SDA 3
NC
AJ3 GPIO28 UART4_RTSN AF31
AP_TO_WLAN_UART4_RTS_L 29
SEP_SPI_SCLK
AN 30
BOARD_ID4
NC BOOT_CONFIG2 NC
WIFI UART
AN 31
10 CODEC_TO_AP_INT_L AD30 GPIO30
UART4_TXD AE33
AP_TO_WLAN_UART4_TXD 29
SEP_SPI_MISO AN 33
NC
29 AP_TO_RADIO_ON_L
AC30 GPIO31
BOARD_ID2
BOARD_ID2
AG1
SPI0_MISO SEP_SPI_MOSI AN 32
AB29
AG4
BOARD_ID1
27 BOARD_ID1
AG2 SPI0_MOSI
G R P
2
SEP_GPIO0 AM 30
GPIO32 UART5_RTXD AP_TO_TIGRIS_SWI
GAS GAUGE
NC PP1V8
NC
BOARD_REV2
BOARD_REV2 NC AK2 GPIO33
ISP_UART0_RXD C32 OSCAR_TO_AP_ISP_UART_RXD
R03101
NC AH3 SPI0_SSIN BOARD_REV3
BOARD_REV3
AK1 GPIO34
C33
BOARD_REV1
NC AK3 GPIO36
10 CODEC_TO_AP_SPI_MISO J3 SPI1_MISO
10K
J2
BOARD_REV0
BOARD_REV0
AK4 GPIO37
UART6_RXD AM2 TRISTAR_TO_AP_ACC_UART6_RXD 17 10 AP_TO_CODEC_SPI_MOSI
SPI1_MOSI
G R P
1
1/32W
R0315
CODEC
AP_TO_BB_COREDUMP AM29 AM1
AP_TO_TRISTAR_ACC_UART6_TXD 17 SPI1_SCLK GPIO38 UART6_TXD
J4 SOCHOT0 AJ31
PMU_TO_AP_PRE_UVLO_L_R
0.00
PMU_TO_AP_PRE_UVLO_L 13
BB_TO_AP_IPC_GPIO
AB31 GPIO41 UART7_TXD A30
AP_TO_WLAN_DEVICE_WAKE 29
10 AP_TO_CODEC_SPI_CS_L SPI1_SSIN
G R P 3
ROOM=SOC 1
2
AP_TO_PMU_SOCHOT1_L_R
BUTTON_TO_AP_RINGER_A AB30 GPIO40
UART7_RXD B30NC
SOCHOT1
AJ32
% MF
1/32W 01005
AP_TO_VIBE_EN
AL3 AF2
OSCAR_TO_AP_UART_RXD 22 24 AP_TO_TOUCH_SPI_MOSI
F32 SPI2_MOSI
G R P 4
DISP_VSYNC
NC
GPIO42
UART8_RXD
GRAPE
24 AP_TO_TOUCH_SPI_CLK E32
UART8_TXD AF1
AP_TO_OSCAR_UART_TXD 22
SPI2_SCLK
AB1 45_AP_TO_TOUCH_CLK32K_RESET_L
24
PP1V8_SDRAM
24 AP_TO_TOUCH_SPI_CS_L
E31 SPI2_SSIN
CLK32K_OUT
CPU_SLEEP_STATUS AH30
NOSTUFF
B
MESA_TO_AP_SPI_MISO AD33 SPI3_MISO NC NO CONNECTED ON MLB
1R0307
AP_TO_MESA_SPI_CLK
ROOM=SOC
21 AP_TO_MESA_SPI_MOSI
AD32 SPI3_MOSI
G R P 3
10K
R0340
5%
01005
21 MESA_TO_AP_INT
AE30 SPI3_SSIN NAND_SYS_CLK
AB4
NC
USED FOR PCIE NAND
MF
20
.00
R0312 ROOM=SOC
0.00
AP_TO_PMU_SOCHOT1_L 13
1
2
%
MF 1/32W
01005
ROOM=SOC
ANTI-ROLLBACK EEPROM
ONSEMI EEPROM APN:335S0894
PP1V8REMOVED HOLD + MENU KEY
BUFFERS SINCE NOT NEEDED FOR FIJI
A 1
1 C0301
1
1 1.0UF
R0317
R0316 20% 2.2K
2.2K
VCC
6.3V
5%
5%
2 01005
CAT24C08C4A
2 ROOM=E
01005
_SE
ROOM=E_SE
WLCSP
3 AP_TO_EEPROM_I2C_SCL
B1 SCL
B2
AP_BI_EEPROM_I2C_SDA 3
SDA
A
SYNC_MASTER=N56_MLB
SYNC_DATE=08/29/2013
PAGE TITLE
SOC:I/OS
VSS
A 2
DRAWING NUMBER
SIZE
Apple Inc. 051-9903 D
REVISION
7.0.0
NOTICE OF PROPRIETARY PROPERTY:
BRANCH
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
PAGE 3 OF 55
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
3 OF 5
4 IV ALL RIGHTS RESERVED
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1 FIJI: VDDCA,VDD1/2,VDDQ,VDD,VDD_FIXED,VDD_CPU,VDD_GPU
VDDCA, VDD1/2, VDDQ
VDD
VDD_CPU, VDD_GPU
2
RESET_1V8_L D17 DDR0_CKEIN
R11 7
26 PP0V95_FIXED_SOC
PP_GPU
NOTE: CKEIN CONFIRMED 1.8V TOLERANT
N4 DDR1_CKEIN
R13
ROOM=SOC
ROOM=SOC
ROOM=SOC
ROOM=SOC
ROOM=SOC
ROOM=SOC
R15 1 C0442
ROOM=SOC ROOM=SOC
C0445
C0448
C0418
C0419
C0420
C0475
R17
1
C0435
C0438 C0439
AA16
L12
10UF
4.3UF
4.3UF
1UF
1UF
0.47UF
4.3UF
D
D
R19
10UF
4.3UF
4.3UF
AA18
L14
6.3V 20% 20%
20% 20% 20% 20%
45_DDR0_ZQ_CA A17 DDR0_ZQ_CA R2 20% 20% 20% U0201
CERM-X5R 4V 4V 4V 4V 6.3V 4V 2 6.3V
4V 4V AA22 L16 0402-9 CERM CERM CERM CERM CERM CERM 45_DDR1_ZQ_CA M1 DDR1_ZQ_CA R21 CERM-X5R
CERM
CERM
POP-FIJI-1GB-DDR-B0
1
0402
1
0402
0402
3
0402
0402
1
0402
0402-9 0402 0402
AA6
L26
3
3
1
1 3
1 3
3
45_DDR0_ZQ_DQ AR13 DDR0_ZQ_DQ R23 ROOM=SOC
1
3
1
3 BGA
AB10 L8 1 C0466
45_DDR1_ZQ_DQ
L33 DDR1_ZQ_DQ R25 SYM 10 OF 13
2 4
2 4 2 4 2 4 2 4
2 4
2 4 2 4
AB23 M11
4 45_DDR0_VREF_CA A18 DDR0_VREF_CA
R27
10UF AB25 M13
20%
4 45_DDR1_VREF_CA
P1 DDR1_VREF_CA R29 2 6.3V
AC14
M15
CERM-X5R
1
1 AR15 DDR0_VREF_DQ
R3
04
02-9
R0401R0402R0411 R0412 AC16 M17 240
240
240
240 4 45_DDR1_VREF_DQ
N33 DDR1_VREF_DQ R32
AC18
M9
R4 1/32W 1/32W 1/32W 1/32W
AC27 N10
MF
MF
MF
MF
A20 R5 26 12 PP_CPU AA10 AA17 2 01005 2 01005
AC7
N12
ROOM=SOC
ROOM=SOC
ROOM=SOC
ROOM=SOC
B17
U0201
R6
ROOM=SOC
ROOM=SOC ROOM=SOC
AA14
U0201
AA19
ROOM=SOC
AD13 N14 C0443
C0446
C0444
C14
R7 ROOM=SOC AA8 AA21
C0405
AD19 N16 0.47UF
0.47UF
1UF
POP-FIJI-1GB-DDR-B0
BGA
C0404
AB11
AA23
H1
R9
1UF
20%
20% 20% BGA
(DDR IMPEDANCE CONTROL)
SYM 7 OF 13
1UF 20%
AD21
N26
6.3V
6.3V
4V
AB13
SYM 13 OF 13
AA25
N1 VDDCA T10
CERM
CERM CERM
0AD25 N8
U1
T12 4V CERM
0402 0402
0402
AB15
AB16
CERM
0402
AD6 P11 1
3
1
3
1
3
V1
T14
0402
1
3
AB9
AB18 1
3
AE10 P13 T16
2 4
2 4 2 4
AC10
AB20 AE11 P15 T18 2
4
AC12 AB22 2 4
23 12 4 2 PP1V2_SDRAM
AE16 P17 AC8 AB24
AA1 T2
AE22 P9 AF33
T20
ROOM=SOC
ROOM=SOC ROOM=SOC
AD11
AB26
AP25
T22
AF13 R10 C0409
C0411
C0414
AD15
AC17
AF17 R12 ROOM=SOC
ROOM=SOC
4.3UF
4.3UF
4.3UF
AD9
AC19 AP6
T24
C0476
C0406
AF23
R14
20%
20%
20%
AE12
AC21
AR17 T26 4.3UF
0.47UF
AF25 R16 CERM
CERM CERM
B15
T28 20%
20% 0402
0402 0402 AE14 AC23
VDD2
4V
6.3V
AF27 R18
1 3
1 3 1 3
VDD_CPU
B19 T29 CERM
CERM
AE8
AC25
1.2V
0402 0402
AF7 R26
AF11
0.775V - 1.0V
AD16
ROOM=SOC ROOM=SOC ROOM=SOC
ROOM=SOC
B7
T3
1
3
1
3
C
C VSS 2
4
2
4
2 4
TBD: 7.6A? @ 105C
C0402
C0422
C0401
C0429
AG14
R8 AF15
AD18 E33
T4
AG16 T11 1UF
1UF
1UF
4.3UF
G1 T7 2 4 2 4 AF9
AD20
20%
20%
20%
20%
AG18 T13 4V
4V
4V
4V
K33
T8
AG10
AD22
CERM
CERM
CERM
CERM
AG6 T15
0402
0402 0402 0402 R1 U11 C0408
C0410
C0413
AG12
AD24 1
3
1
3
1
3
1
3
AH10
T17 AG8 AD26 T32 U13 VDD_FIXED
4.3UF
4.3UF
1UF
AH20 VDD_FIXED
0.95V
T19
20% 20% 20% AH11 AE17 2 4
2 4
2 4
2 4
Y32
U15
4V 4V 4V AH7
TBD: 3.3A? @ 105C
T9
CERM
CERM
CERM
AH13 AE19 U17 0402
0402
0402 AJ14 U10
U19
1
3
1 3 1 3
AH15 AE21
AJ16 U12
U2
AH9 AE23
AJ24 U14 2
4
2
4
2 4
U21
AJ10
AE25 AJ27 U16 U23
AJ12
AF18
1 C0478 AJ6 U18 U25
AJ7
VDD_GPU
AF20
AJ9
U26
U27 10UF
AJ8
0.8V - 0.95V
AF22
2
%
AK12 U8
U29
6.3V
1 C0447
TBD: 3.45A? @ 105C AF24
AK18 V11 10 3
PP1V8_SDRAM
A19
U3 0402-9
10UF
AF26
AK20
V13
AG33 U4 012 45_BUCK0_FB
AA12 VDD_CPU_SENSE
AG17
ROOM=SOC
ROOM=SOC ROOM=SOC
2 6.3V
AK22 V15
CERM-X5R 1 C0450 1 C0451
1 C0452
AR16 U5 AG19
AK25 V9 0402-9
2.2UF
2.2UF
2.2UF
AR25 U6 ROOM=SOC
PP0401
AG21
20%
20%
20%
F26 W10
AG23 6.3V
2
6.3V
6.3V
AR7
U7
P2MM-NSM
VDD1
F7 W12 AG25
0201-1
0201-1 0201-1 B16
U9
ROOM=SOC
ROOM=SOC
1.8V G10 W14 C0415
C0465
ROOM=SOC
B8
AH16
G12 W16
D33 2
0% 20% AH18 G14 W18
4V
4V
K1
CERM CERM
AH22
G16
W21
0402
0402
AH24
T1 1
3
1 3
1
C0449 G18
W8
T33
AH26 10UF
G20 Y11 2 4
2 4
AJ17 W1 20%
B
G22 Y13
6.3V
AJ19
B
G8
Y15
0402-9
AJ21
ROOM=SOC
PP1V2
AC33
H11 Y19 AJ23
H13 Y23
AJ25
ROOM=SOC
ROOM=SOC
AR11
C0431
ROOM=SOC C0427
C0432
AR14
H15
Y25
ROOM=SOC
ROOM=SOC
W17
1 C0472
4.3UF
1 C0467 1
1UF
AR19
H9
Y27
C0471 1
C0468
Y16
20% 1.0UF
1.0UF
20% J10 Y7 2.2UF
2.2UF
4V 20% 20% 4V AR22
20% 10UF Y18
PP0403
20%
CERM 2 6.3V
2CERM J12 Y9
2 6.3V 20% Y20
0402
X5R X5R 0402 AR24
X5R X5R
2
2
6.3V
1 3
00 1
3 J1
4 0201-1
AR6
VDD_FIXED_SENSE V7 45_BUCK5_FB
0402-9
Y22
ROOM=SOC
1
VDDQ
J26 ROOM=SOC
Y24
2 4
2
4
AR8 ROOM=SOC
J8 Y26
G33 K11
J33
K13 AG27 45_BUCK1_FB
M33 VDD_GPU_SENSE K15
R33
K9
1 C0426
ROOM=SOC
ROOM=SOC
V33
C0425
C0430
L10 PP0402
Y33
15PF
0.47UF
0.47UF
P2MM-NSM
20%
20%
2 16V 1
NP0-C0G-CERM
6.3V
6.3V
PP
01005
ROOM=SOC
0402 0402
ROOM=SOC 1 3 1 3
2
4
2 4
2 PP1V2
A 26 23 12 4 2 PP1V2_SDRAM
1R0409
A
1
C0423
1
1 C0433 1
1 C0436 1
1 C0440
SYNC_MASTER=N56_MLB
SYNC_DATE=08/29/2013
R0403
R0405
R0407 0.01UF
4.7K
0.01UF
10K 0.01UF
10K
0.01UF
4.7K
1
%
PAGE TITLE
10%
1%
1%
1%
1/32W
SOC:VDDCA,VDD1/2,VDD,VDD_CPU,VDD_GPU
10%
10%
6.3V
2 6.3V
1/32W 1/32W 1/32W 2
MF X5R
MF
2 X5R
MF
2 X5R
MF
01005
01005
DRAWING NUMBER
SIZE
000 2
01005 2
01005
2
ROOM=SOC
ROOM=SOC
ROOM=SOC
ROOM=SOC
ROOM=SOC
051-9903
D
ROOM=SOC
ROOM=SOC
Apple Inc.
45_DDR1_VREF_CA 4
45_DDR1_VREF_DQ 4
45_DDR0_VREF_CA 4
45_DDR0_VREF_DQ 4
REVISION
1 C0424
1
C0434
1
C0441 1R0410
7.0.0
1
C0437
1
1
0.01UF
R0404
R0406
NOTE: SOME VENDORS HAVE
1
R0408
4.7K
NOTICE OF PROPRIETARY PROPERTY:
BRANCH
00.01UF
2 6.3V
1% 10% 1% INTERNAL DIVIDER CIRCUITS
1%
10% 1/32W
THE INFORMATION CONTAINED HEREIN IS THE
1/32W 2 6.3V
1/32W 10% 2 6.3V
MF
X5R
MF
6.3V
X5R
01005 2 MF
01005
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
0100
5 01005 2
01005 X5R
01005
ROOM=SOC
ROOM=SOC
ROOM=SOC
01005
ROOM=SOC
ROOM=SOC
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
4 OF 55
ROOM=SOC ROOM=SOC
II NOT TO REPRODUCE OR COPY IT
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
4 OF 54 IV ALL RIGHTS RESERVED
8 7 6 5 4 3 2 1
8
7 6
5
4
3 2
1 FIJI: VDDIOD,VDDIO18,VDD_VAR_SOC
JUST A FEW GNDS
VDD_SRAM, VDD_SOC
A1
AJ15 C22
J29
V10
A2
U0201
AJ18 C23
U0201
J30
U0201
V12
A32 AJ20 C24 J31
V14
POP-FIJI-1GB-DDR-B0
C25 POP-FIJI-1GB-DDR-B0
J32
POP-FIJI-1GB-DDR-B0
V16
D
D
A33 AJ22 BGA
BGA
BGA C26 J9 V18 AA11
SYM 11 OF 13
AJ26 SYM 12 OF 13
SYM 8 OF 13
AA15
AJ28 C27 K10
V2
AA20
AJ5 C28 K12
PP_VAR_SOC
G24
V20
AA24 AK10 C3 K14 V22
G26
C4
K17
ROOM=SOC
ROOM=SOC
ROOM=SOC
ROOM=SOC
V24
AA26 AK14
1
C0508
C0503 C0507 C0509 C0510 H16
C5 K18 V26
AA27
AK16
H19
C6 K20 10UF
4.3UF
1UF
1UF
0.47UF
V28
AA28
AK24
20%
20%
20%
20%
20%
H21
C9 K22 2 6.3V
4V
4V
4V
6.3V
V29 AA31
AK27
CERM-X5R CERM CERM CERM CERM
H23
AA5
AK28 D10 K24
0402-9
0402
0402
0402
0402
V3
ROOM=SOC
1
3
1
3
1
3
1
3
H25
D12 K26 V30 AA7
AK29 J15
D13 K28 V31 AA9
AK6 2
4
2
4
2 4
2 4
J17
D18 K29 V32 AB12
AK8 J18
D19 K30 V4
AB14
AL11
J20
D20 K31 V5 AB17
AL13 J22
D21 K32 V6 AB19
AL15 J24
D22 K6 V8
AB21
AL17
K16
D23 K8 W11 AB27
AL19 K19
D24 L1 W13 AB28
AL21 K21
D27 L11 W15
AB6
AL23
K23
D4 L13 W19 AB7
AL25 VDDIOD, VDDIO18
K25
D5 L15 W2 AB8
AL27 L18 AC11
AL6 D6 L17 W23 L20 D8 L19 W25
AC13 AL7 L22 VDD_VAR_SOC VSS D9 L2 W27
AC15
AL9 L24 0.90V - 0.95V E11
L21 CAPS FOR VDDIOD ARE SHARED WITH VDDQ
W29 AC20 AM10 M19
1.8A @ 105C
E15
L23
W3
AC22
AM11 PP1V2
E16 VDDIOD_DDRCA VDDIO18_GRP1 J6
PP1V8M21
C
C
AC24 AM12 E17 L25 W30 E18 VDDIOD_DDRCA ROOM=SOC
M23 E19 L27 W31
AC26 AM13
F15 VDDIOD_DDRCA
C0502
M25
AC28 AM14
E21 L29 W32
F17 VDDIOD_DDRCA
ROOM=SOC
1UF
N18
E23 L30 C0501
20% W33
AC32
AM15
K7 VDDIOD_DDRCA
2.2UF
4V
N20
AC5 AM16
E24 L31 VDDIO18_GRP2 AB5 CERM
W6
L6 VDDIOD_DDRCA
20% 0402
N22
AC6 AM17 E25 L32 VDDIO18_GRP2 AE5 1
3 W7
M7 VDDIOD_DDRCA
X5R
N24
AC9 VSS
E26 L5 VDDIO18_GRP2 AH5 0201-1 W9
VSS
AM18
N6 VDDIOD_DDRCA
2
4
P19
AD10
AM19 E27 L7
U0201
VDDIO18_GRP2 T6
Y10
P7 VDDIOD_DDRCA
P21 AD12 AM20 E28 L9 VDDIO18_GRP2 W5
Y12
POP-FIJI-1GB-DDR-B0
P23
E6 M10 BGA
Y14
AD17
AM21
VDDIO18_GRP3 AA29
P25
SYM 9 OF 13
AD23
AM22 E7 M12 Y17
AK11 VDDIOD_DDR0DQ VDDIO18_GRP3 AC29 R20 AD27 AM23 E9 M14
ROOM=SOC
Y21
AF29 AK19 VDDIOD_DDR0DQ 1.8V
VDDIO18_GRP3 ROOM=SOC
C0506
R22 F10 M18
Y28
AD28
AM24
F12 VSS VSS
AK21 VDDIOD_DDR0DQ
VDDIO18_GRP3 AJ29
C0511 1
0.47UF
R24
Y29
AD5
AM26
M2
AK23 VDDIOD_DDR0DQ
1.0UF
20%
T21
AD7 AM28 F14 M20 VDDIO18_GRP4 F25 20%
6.3V Y5
AK7 VDDIOD_DDR0DQ
6.3V
CERM
T23
AD8 AM5 F16 M22 VDDIO18_GRP4 F28 0402
Y6
AK9 VDDIOD_DDR0DQ
0201-1
1
3
T25
AE13
AM6 F18
M24
VDDIO18_GRP4 H28
Y8
AL10 VDDIOD_DDR0DQ 1.2V
U20
AE18
AM7 F20 M26 2
4
AL12 U22 AA13
VDDIOD_DDR0DQ VSS_SENSE AE20
AM8 F22 M28 AL18 VDDIOD_DDR0DQ U24 AE24
AM9 F24 M29 AL20 VDDIOD_DDR0DQ V21 AE26
AN25 F27 M3 AL22 VDDIOD_DDR0DQ V23 AE27
AN26 F29 M30 AL8 VDDIOD_DDR0DQ
V25 GRP7 POWERS GPIO11,12 (BUTTONS)
AE28 AN27 F31 M31
W20
T5
F6 M32 K27 VDDIOD_DDR1DQ VDDIO18_GRP7 PP1V8_ALWAYS 3
AE29
AN28
W22
F8 M4 L28 VDDIOD_DDR1DQ
AE6
AN29 VDDIO18_PPN AK13
1 C0520
W24
AE7
AN5
G11
M5
M27 VDDIOD_DDR1DQ
B
G13
M6
N28 VDDIOD_DDR1DQ
VDDIO18_PPN AK15
0.1UF
45_BUCK2_FB
W26 VDD_VAR_SOC_SENSE
B
AE9
AN6
VDDIO18_PPN AK17 20%
G15 M8 P27 4V AF10
AP1
VDDIOD_DDR1DQ
VDDIO18_PPN AL14
2
AF12 AP10
G17 N11 R28 VDDIOD_DDR1DQ
VDDIO18_PPN AL16 ROOM=SOC
G19 N13 T27 VDDIOD_DDR1DQ AF14
AP12
AF16
AP14 G21 N15 U28 VDDIOD_DDR1DQ
AF19
AP17 G23 N17 V27 VDDIOD_DDR1DQ
PP0501
AF21
AP19 G25 N19 W28 VDDIOD_DDR1DQ
AF28
AP2 G27
N2
P2MM-NSM
G28
N21
SM CPU_VSS_SENSE
AF32
AP21
PP
AF5
AP24 G6 N23
ROOM=SOC
AF6
AP3 G9 N25
AF8
AP32 H10 N27
AG11
AP33 H12 N29
AG13
AP5 H14 N3
AG15
AP7 H17 N32
AG20
AR1 H18 N7
AG22
AR2 H2 N9
AG24
AR3 H20 P10
AG26
AR32 H22 P12
AG28
AR33 H24 P14
AG5
AR5 H26 P16
AG7
B1 H27 P18
AG9
B18 H29 P2
AH12
B2 H5 P20
AH14
B20 H6 P22
AH17
B32 H7 P24
A
A
AH19
B33 H8 P26
SYNC_MASTER=N56_MLB
SYNC_DATE=08/29/2013
AH21
C10 J11 P28
AH23
C11 J13 P29
PAGE TITLE
SOC:GND,VDDIO18,VDDIOD,VDD_VAR_SOC
AH25
C15 J16
P3
AH27
C16 J19
P31
DRAWING NUMBER SIZE
051-9903
D
AH28
C17 J21
P4
Apple Inc.
J23 P5 REVISION
AH6 C18
J25 P6
7.0.0
AH8
C19
NOTICE OF PROPRIETARY PROPERTY:
AJ11
C20
J27
P8
BRANCH
AJ13
J28
C21
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
5 OF 55
II NOT TO REPRODUCE OR COPY IT SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART 5 OF 54 IV ALL RIGHTS RESERVED
8
7 6
5
4
3 2
1。