verilog语言基本程序

1.设计一个产生010*******的序列信号发生器。

module generator(out,clk,state);output [3:0]state;output out;input clk;reg [3:0]state;reg out;always@(posedge clk)beginif(state==9)state<=0;elsestate<=state+1;case(state)4'b0000:out<=0;4'b0001:out<=1;4'b0010:out<=0;4'b0011:out<=0;4'b0100:out<=1;4'b0101:out<=0;4'b0110:out<=0;4'b0111:out<=1;4'b1000:out<=1;4'b1001:out<=1;default:out<=0;endcaseendendmodule2.设计一个8位的加减计数器。

时钟信号为clk，同步清零信号为rst。

Clk上升沿时刻，当inc=1计数器加二，其他情况计数器保持不变。

module counter(rst,clk,q,inc,dec);input rst,clk,inc,dec;output [7:0]q;reg [7:0]q;always@(posedge clk)if(rst)q<=0;elsecase({inc,dec})2'b10:begin if(q==254) q<=0;else q<=q+2;end//2'b01:begin if(q==0) q<=254;else q<=q-2;end//default:q<=q;endcaseendmodule3．序列检测器（移位寄存器法）11111010000序列检测器module shift(q,s,d,clk);input clk,d;output [10:0]q;output s;reg[10:0]q;reg s;always@(posedge clk)beginq<=q<<1;q[0]<=d;endalways@(posedge clk)if(q==11'b11111010000)s<=1;else s<=0;endmodule11111010000序列检测器（状态机）module shift1 (x,z,rst,clk,state);input x,rst,clk;output z;output[3:0]state;wire z;reg[3:0] state;parameters0=4'b0000,s1=4'b0001,s2=4'b0010,s3=4'b0011,s4=4'b0100,s5=4'b 0101,s6=4'b0110,s7=4'b0111,s8=4'b1000,s9=4'b1001,s10=4'b1010; assign z=(state==s10 && x==0)?1:0;always@(posedge clk or negedge rst)if(!rst)state<=s0;elsecase(state)s0: if(x==1) state<=s1;else state<=s0;s1: if(x==1) state<=s2;else state<=s0;s2: if(x==1) state<=s3;else state<=s0;s3: if(x==1) state<=s4; else state<=s0;s4: if(x==1) state<=s5; else state<=s0;s5: if(x==0) state<=s6; else state<=s5;s6: if(x==1) state<=s7; else state<=s0;s7: if(x==0) state<=s8; else state<=s2;s8: if(x==0) state<=s9; else state<=s1;s9: if(x==0) state<=s10; else state<=s1;s10: if(x==0) state<=s0; else state<=s1; default: state<=s0; endcase endmoduleVerilog设计一个为16*4的RAMmodule mymem (data, addr, read, write);inout [3:0] data;input [3:0] addr;input read, write;reg [3:0] memory [0:15]; // 16*4// 读assign data = read ? memory[addr] : 4'bz; // 写always @( posedge write)memory[addr] = data; endmodule1KB的RAMmodule ram1kB (data, addr, read, write); inout [7:0] data;input [9:0] addr;input read, write;reg [7:0] memory [0:1023]; // 16*4// 读assign data = read ? memory[addr] : 8'bz;// 写always @( posedge write)memory[addr]<=data;endmoduleROM在下面的例子中，给出如何定义一个字长和地址均参数化的只读存储器件module scalable_ROM (mem_word, address);parameter addr_bits = 8; // 地址总线宽度parameter wordsize = 8; // 字宽parameter words = (1 << addr_bits); // mem容量output [wordsize:1] mem_word; // 存储器字input [addr_bits:1] address; // 地址总线reg [wordsize:1] mem [0 : words-1]; // mem声明// 输出存储器的一个字wire [wordsize:1] mem_word = mem[address];endmodule例中存储器字范围从0而不是1开始，因为存储器直接用地址线确定地址。

也可以用下面的方式声明存储器并寻址。

reg [wordsize:1] mem [1:words]; // 从地址1开始的存储器// 存储器寻址时地址必须加1wire [wordsize:1] mem_word = mem[ address + 1];∙小时光∙消息(1)∙∙∙新闻∙网页∙贴吧∙知道∙音乐∙图片∙视频∙地图∙百科∙文库∙经验首页问题分类∙经济金融∙企业管理∙法律法规∙社会民生∙科学教育∙健康生活∙体育运动∙文化艺术∙电子数码∙电脑网络∙娱乐休闲∙地区∙心理分析∙医疗卫生∙资源共享知道栏目∙知道日报∙真相问答机∙知道大数据知道用户∙芝麻∙芝麻团∙芝麻将∙财富商城∙知道之星∙知道活动咨询专家∙高质量问答∙知道行家∙问医生∙作业帮∙宝宝知道经验∙开放平台∙手机知道∙个人中心急求一个verilog编写的异步串行通信的程序，最好有校验位，459785950@。

答的好可以再加分提问者采纳moduleasyn(clk,rst,wr,wr_bit,addr,bit_in,data_in,t1_ow,rxd,txd,intr,data_out,pcon,sco n,rx_sbuf);input clk;input rst;input wr;input wr_bit;input [7:0] addr;input bit_in;input [7:0] data_in;input t1_ow;input rxd;output txd;output intr;output [7:0] data_out;output [7:0] scon;output [7:0] pcon;output [7:0] rx_sbuf;reg txd;reg [7:0] scon;reg [7:0] pcon;assign intr=scon[1]|scon[0];//wire t1_ow_final;reg div2_flag;reg t1_ow_buf;reg t1_ow_final_buf;// signals with transmit partreg [7:0] tx_sbuf;reg send_n; //active low,indicate that it is transmiting dataswire wr_sbuf_en;assign wr_sbuf_en=(wr==1'b1&&addr==8'h99);reg wr_sbuf_en_mem;wire shift_en;reg [3:0] tx_next_state;reg [3:0] tx_current_state;parameterIDLE=11,START=0,D0=1,D1=2,D2=3,D3=4,D4=5,D5=6,D6=7,D7=8,TB8_BIT =9,STOP_BIT=10; //states definereg [3:0] osc_cnt;reg [3:0] tx_sample_cnt;reg tx_clk;//signals with receive partreg [3:0] rx_next_state;reg [3:0] rx_current_state;reg [3:0] rx_sample_cnt;wire one_bit;reg rxd_buf;reg [10:0] sbuf_rxd_tmp;reg [7:0] rx_sbuf;reg sample_7,sample_8,sample_9;reg receive;//signals with both transmiting and receiving parts//always @(*)//begin//SM0=scon[7];//SM1=scon[6];//SM2=scon[5];//REN=scon[4];//TB8=scon[3];//RB8=scon[2];//TI=scon[1];//RI=scon[0];//endalways @(posedge clk or posedge rst) //register scon beginif (rst)scon <=8'b0100_0000;else if ((wr) & !(wr_bit) & (addr==8'h98))scon <=data_in;else if ((wr) & (wr_bit) & (addr[7:3]==5'b10011))scon[addr[2:0]]<=bit_in;else if (tx_next_state==STOP_BIT)scon[1] <=1'b1;elsecase(rx_next_state)START:scon[0]<=1'b0;IDLE:if(rx_current_state==STOP_BIT)begincase (scon[7:6])2'b00: scon[0] <= 1'b1;2'b01: if(scon[5])if(one_bit)scon[0] <= 1'b1;elsescon[0] <= 1'b0;elsescon[0] <= 1'b1;2'b10,2'b11: if(scon[5])scon[0]<=sbuf_rxd_tmp[9];elsescon[0]=1'b1;endcaseendendcaseend////power control register//wire smod;assign smod = pcon[7];always @(posedge clk or posedge rst)beginif (rst)pcon <= 8'b0000_0000;else if ((addr==8'h87) & (wr) & !(wr_bit))pcon <= data_in;endalways @(posedge clk or posedge rst) //osc_cntif(rst)osc_cnt<=4'b0000;else if(osc_cnt==4'b1011)osc_cnt<=4'b0000;elseosc_cnt<=osc_cnt+1'b1;always @(posedge clk or posedge rst) //t1_ow_buf if(rst)t1_ow_buf<=1'b0;else if(t1_ow)t1_ow_buf<=~t1_ow;always @(posedge clk or posedge rst) //div2_flagif(rst)div2_flag<=1'b0;else if(~t1_ow_buf&t1_ow)div2_flag<=~div2_flag;assign t1_ow_final=(pcon[7]==1'b1)?t1_ow:t1_ow&div2_flag;//transmit partalways @(posedge clk or posedge rst) //t1_ow_final_bufif(rst) t1_ow_final_buf<=1'b0;else t1_ow_final_buf<=t1_ow_final;always @(posedge clk or posedge rst) //tx_sample_cntif(rst)begintx_sample_cnt<=4'b0000;endelse if(t1_ow_final_buf==1'b0&&t1_ow_final==1'b1)tx_sample_cnt<=tx_sample_cnt+1'b1;always @(posedge clk or posedge rst)if(rst)wr_sbuf_en_mem<=1'b0;else if (wr_sbuf_en&&wr_sbuf_en_mem<=1'b0)wr_sbuf_en_mem<=1'b1; //represent that the tx_sbuf has been loadedelse if(tx_current_state==STOP_BIT)wr_sbuf_en_mem<=1'b0;assignshift_en=wr_sbuf_en_mem==1'b1&&tx_sample_cnt==4'b1111&&osc_cnt==4' b1011&&t1_ow_final_buf==1'b0&&t1_ow_final==1'b1;always @(posedge clk or posedge rst)if(rst)tx_sbuf<=8'b0000_0000;else if (wr_sbuf_en&&wr_sbuf_en_mem<=1'b0)tx_sbuf<=data_in;else if(send_n==1'b0&&shift_en)tx_sbuf<=tx_sbuf>>1'b1;//the three always phrase below is the 3 parts discription of state machinealways @(*)//(tx_current_state or wr_sbuf_en_mem or tx_sample_cnt or osc_cnt or TH1 or TL1 or shift_en)begincase(tx_current_state)IDLE: if(shift_en) //tx_next_state=START;elsetx_next_state= IDLE;START:if(shift_en)tx_next_state=D0;elsetx_next_state=START;D0: if(shift_en)tx_next_state=D1;elsetx_next_state=D0;D1: if(shift_en)tx_next_state=D2;elsetx_next_state=D1;D2: if(shift_en)tx_next_state=D3;elsetx_next_state=D2;D3: if(shift_en)tx_next_state=D4;elsetx_next_state=D3;D4: if(shift_en)tx_next_state=D5;elsetx_next_state=D4;D5: if(shift_en)tx_next_state=D6;elsetx_next_state=D5;D6: if(shift_en)tx_next_state=D7;elsetx_next_state=D6;D7: if(shift_en)if(scon[7:6]==2'b00||scon[7:6]==2'b01)tx_next_state=STOP_BIT;elsetx_next_state=TB8_BIT;elsetx_next_state=D7;TB8_BIT: tx_next_state=STOP_BIT;STOP_BIT:if(tx_sample_cnt==4'b1111&&osc_cnt==4'b1011&&t1_ow_final==1'b1) tx_next_state=IDLE;elsetx_next_state=STOP_BIT;default:tx_next_state=IDLE;endcaseendalways @(posedge clk or posedge rst) if(rst)tx_current_state<=IDLE;elsetx_current_state<=tx_next_state;always @(posedge clk or posedge rst) if(rst)begintxd<=1'b1;send_n<=1'b1;endelsecase(tx_next_state)IDLE:beginsend_n<=1'b1;txd<=1'b1;endSTART:beginsend_n<=1'b0;txd<=1'b0;endD0: txd<=tx_sbuf[0];D1: txd<=tx_sbuf[0];D2: txd<=tx_sbuf[0];D3: txd<=tx_sbuf[0];D4: txd<=tx_sbuf[0];D5: txd<=tx_sbuf[0];D6: txd<=tx_sbuf[0];D7: txd<=tx_sbuf[0];TB8_BIT: txd<=scon[3];STOP_BIT:begintxd<=1'b1;endendcase//receiving partassignrx_shift_en=rx_sample_cnt==4'b1111&&t1_ow_final_buf==1'b0&&t1_ow_final ==1'b1;always @(posedge clk or posedge rst) //describe the rxd_bufif(rst)rxd_buf<=1'b0;elserxd_buf<=rxd;always @(posedge clk or posedge rst) //describe therx_sample_cntif(rst)rx_sample_cnt<=4'b0000;else if(rxd_buf==1'b1&&rxd==1'b0) //此条件启动接收过程rx_sample_cnt<=4'b0000;else if(t1_ow_final)rx_sample_cnt<=rx_sample_cnt+1'b1;always @(posedge clk)if(rx_sample_cnt==4'b0110&&t1_ow_final)sample_7<=rxd;always @(posedge clk)if(rx_sample_cnt==4'b0111&&t1_ow_final)sample_8<=rxd;always @(posedge clk)if(rx_sample_cnt==4'b1000&&t1_ow_final)sample_9<=rxd;assignone_bit=sample_7&&sample_8||sample_7&&sample_9||sample_8&&sample_ 9;//the three always phrase below is the 3 parts discription of state machinealways @(*)begincase(rx_current_state)IDLE: if(rxd_buf==1'b1&&rxd==1'b0&&scon[4]==1'b1) //检测到了rxd从1到0的跳变rx_next_state=START;elserx_next_state= IDLE;START: if(rx_shift_en)if(~one_bit)rx_next_state=D0;elserx_next_state=IDLE;elserx_next_state=START;D0: if(rx_shift_en)rx_next_state=D1;elserx_next_state=D0;D1: if(rx_shift_en)rx_next_state=D2;elserx_next_state=D1;D2: if(rx_shift_en)rx_next_state=D3;elserx_next_state=D2;D3: if(rx_shift_en)rx_next_state=D4;elserx_next_state=D3;D4: if(rx_shift_en)rx_next_state=D5;elserx_next_state=D4;D5: if(rx_shift_en)rx_next_state=D6;elserx_next_state=D5;D6: if(rx_shift_en)rx_next_state=D7;elserx_next_state=D6;D7: if(rx_shift_en)if(scon[7:6]==2'b00||scon[7:6]==2'b01)rx_next_state=STOP_BIT;elserx_next_state=TB8_BIT;else rx_next_state=D7;TB8_BIT: if(rx_shift_en)rx_next_state=STOP_BIT;elserx_next_state=TB8_BIT;STOP_BIT: if(rx_shift_en)rx_next_state=IDLE;elserx_next_state=STOP_BIT;endcaseendalways @(posedge clk or posedge rst)if(rst)rx_current_state<=IDLE;elserx_current_state<=rx_next_state;always @(posedge clk or posedge rst)if(rst)receive<=1'b0;elsecase(rx_next_state)IDLE:receive<=1'b0;START:beginreceive<=1'b1;sbuf_rxd_tmp<=10'b11_1111_1111;endD0,D1,D2,D3,D4,D5,D6,D7: if(rx_shift_en) sbuf_rxd_tmp<={sbuf_rxd_tmp[10:0],one_bit}; STOP_BIT:receive<=1'b1; // end of receiving endcase////serial port buffer (receive)//always @(posedge clk or posedge rst)beginif (rst)rx_sbuf<=8'h00;else if (rx_next_state==STOP_BIT)case (scon[7:6])2'b00,2'b01:rx_sbuf<=sbuf_rxd_tmp[7:0];2'b10,2'b11:rx_sbuf<=sbuf_rxd_tmp[8:1];endcaseendendmodulemodule sin(reset,clock,d_out);input reset,clock;output [7:0]d_out;reg [7:0]d_out;reg clk;reg cnt;reg [3:0]state0;always@(posedge clock)if(cnt==0)begin clk<=1;cnt<=cnt+1;endelsebegin clk<=0;cnt<=cnt+1;endalways@(posedge clk)if(reset)begin state0<=0;d_out<=128;endelsecase(state0)0:begin d_out<=128;state0<=state0+1;end1:begin d_out<=128+38;state0<=state0+1;end 2:begin d_out<=128+71;state0<=state0+1;end 3:begin d_out<=128+92;state0<=state0+1;end 4:begin d_out<=128+100;state0<=state0+1;end 5:begin d_out<=128+92;state0<=state0+1;end 6:begin d_out<=128+71;state0<=state0+1;end 7:begin d_out<=128+38;state0<=state0+1;end 8:begin d_out<=128;state0<=state0+1;end9:begin d_out<=128-38;state0<=state0+1;end 10:begin d_out<=128-71;state0<=state0+1;end 11:begin d_out<=128-92;state0<=state0+1;end 12:begin d_out<=128-100;state0<=state0+1;end 13:begin d_out<=128-92;state0<=state0+1;end 14:begin d_out<=128-71;state0<=state0+1;end 15:begin d_out<=128-38;state0<=state0+1;end default:begin d_out<=128;state0<=0;endendcaseendmodulemodule txout(clk,din,reset,wr,ce,dbf,txd,d8);input clk,reset,wr,ce;input [7:0]din;output txd,dbf;output d8;reg[7:0]data;reg[10:0]shift;reg[4:0]count,t;reg[3:0]state;reg[1:0]state0;reg dbf,tbr;wire txd;wire d8;reg dd;assignd8=~(din[0]+din[1]+din[2]+din[3]+din[4]+din[5]+din[6]+din[7]); assign txd=shift[0];always@(posedge clk)if(reset==0)state0<=0;elsecase(state0)0:beginif(wr==1&&ce==1)begin state0<=1;data<=din;dd<=d8;end if(tbr==1)state0<=2;end1:if(wr==0||ce==0)begin dbf<=1;state0<=0;end2:begin dbf<=0;state0<=0;end endcasealways@(posedge clk)if(reset==0)begin state<=0;shift[0]<=1;endelsecase(state)4'b0000:if(t==11&&dbf==1)begintbr<=1;state<=1;t<=0;shift[10]<=1;shift[9:1]<={dd,data[7:0]};shift[0]<=0;endelseif(t<11) t<=t+1;//4'b0001:if(t==11)begin shift<=shift>>1;shift[10]<=1;state<=2;t<=0;tbr<=0;end else t<=t+1;4'b0010:if(t==11)begin shift<=shift>>1;shift[10]<=1;state<=3;t<=0;endelse t<=t+1;4'b0011:if(t==11)begin shift<=shift>>1;shift[10]<=1;state<=4;t<=0;endelse t<=t+1;4'b0100:if(t==11)begin shift<=shift>>1;shift[10]<=1;state<=5;t<=0;endelse t<=t+1;4'b0101:if(t==11)begin shift<=shift>>1;shift[10]<=1;state<=6;t<=0;end else t<=t+1;4'b0110:if(t==11)begin shift<=shift>>1;shift[10]<=1;state<=7;t<=0;end else t<=t+1;4'b0111:if(t==11)begin shift<=shift>>1;shift[10]<=1;state<=8;t<=0;end else t<=t+1;4'b1000:if(t==11)begin shift<=shift>>1;shift[10]<=1;state<=9;t<=0;end else t<=t+1;4'b1001:if(t==11)begin shift<=shift>>1;shift[10]<=1;state<=10;t<=0;end else t<=t+1;4'b1010:if(t==11)begin shift<=shift>>1;shift[10]<=1;state<=0;t<=0;end else t<=t+1;default:begin t<=0;state<=0;endendcaseendmodule。