SystemVerilog快速入门PPT课件

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SystemVerilog 是Verilog-2001扩展后的超集
------------------------- SystemVerilog -------------------------------
interfaces dynamic processes nested hierarchy 2-state modeling byte unrestricted ports packed arrays implicit port connections array assignments enhanced literals enhanced event control time values & units unique/priority case/if logic-specific processes root name space
-------- from C / C++--------
multi dimensional arrays signed types Automatic ** (power operator)
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SystemVerilog 是Verilog-2001扩展后的超集
------------------------- Verilog -1995 -------------------------------
-------- from C / C++--------
int
globals
break
shortint enum continue
longint typedef return
Byte structures do-while
Shortreal unions ++ --
+= -= *= /=
ຫໍສະໝຸດ Baidu
void
casting >> =
SystemVerilog 讲座
第一讲: SystemVerilog 基本知识
2008
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Verilog HDL的发展历史
1984: Gateway Design Automation 推出 Verilog 初版 1989: Gateway 被Cadence Design Systems 公司收购 1990: Cadence 向业界公开 Verilog HDL 标准 1993: OVI 提升 the Verilog 标准，但没有被普遍接受 1995: IEEE 推出 Verilog HDL (IEEE 1364-1995)标准 2001: IEEE 推出 Verilog IEEE Std1364-2001 标准 2002: IEEE 推出 Verilog IEEE Std1364.1-2002 标准 2002: Accellera 对 SystemVerilog 3.0 进行标准化
<<=
>>>= <<<=
alias
const &= |=
^= %=
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SystemVerilog 是Verilog-2001扩展后的超集
---------------------------------- Verilog -2001 -------------------------------
ANSI C style ports standard (* attributes *) generate $value$plusargs configurations localparam `ifndef `elsif `line memory part selects constant functions @* variable part select
– Accellera 是OVI & VHDL International (VI)合并后的 国际标准化组织 2003: Accellera 标准化后的SystemVerilog 3.1 2006: IEEE 推出带SystemVerilog 扩展的Verilog新标准
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为什么称 SystemVerilog 3.x?
modules $finish $fopen $fclose initial wire reg parameters $display $write disable integer real function/task $monitor events time always @ `define `ifdef `else wait # @ packed arrays assign `include `timescale fork–join 2D memory
constrained random values
process control direct C function calls
------ from C / C++ --------
classes dynamic arrays inheritance associative arrays strings references
SystemVerilog 是 对Verilog 革命性的扩展 Verilog 1.0
- IEEE 1364-1995 “Verilog-1995” 标准 – 第一代 IEEE Verilog 标准 Verilog 2.0 - IEEE 1364-2001 “Verilog-2001” 标准 – 第二代 IEEE Verilog 标准 – 显著提升了 Verilog-1995 标准的性能 SystemVerilog 3.x - 国际标准化组织对Verilog-2001的扩展 – 第三代 Verilog 标准 – DAC-2002 - SystemVerilog 3.0 – DAC-2003 - SystemVerilog 3.1
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SystemVerilog 是Verilog-2001扩展后的超集
----------------------- SystemVerilog ------------------------------
assertions mailboxes test program blocks semaphores clocking domains