电气专业毕业设计外文翻译--电源管理技术及计算

附录3 英文资料
Power Management Techniques and Calculation
Relevant Devices
This application note applies to the following devices: C8051F000, C8051F001, C8051F002, C8051F005, C8051F006, C8051F010, C8051F011, C8051F012, C8051F012, C8051F015, C8051F016, and C8051F017.
Introduction
This application note discusses power management techniques and methods of calculating power in a Cygnet C8051F00x and C8051F01x Sock. Many applications will have strict power requirements, and there are several methods of lowering the rate of power consumption without sacrificing performance. Calculating the predicted power use is important to characterize the system‟s power supply requirements.
Key Points
• Supply volt age and system clock frequency strongly affect power consumption.
• Cygnet‟s Sock‟s feature power management modes: IDLE and STOP.
• Power use can be calculated as a function of system clock frequency, supply voltage, and enabled peripherals.
Power Saving Methods
CMOS digital logic device power consumption is affected by supply voltage and system clock (SYSCLK) frequency. These parameters can be adjusted to realize power savings, and are readily controlled by the designer. This section discusses these parameters and how they affect power usage.
Reducing System Clock Frequency
In CMOS digital logic devices, power consumption is directly proportional to system clock (SYSCLK) frequency: power=CV2ƒ, where C is CMOS load capacitance, V is supply voltage, and ƒ is SYSCLK frequency.
Equation 1.CMOS Power Equation
The system clock on the C8051Fxxx family of devices can be derived from an internal oscillator or an external source. External sources may be a CMOS clock, RC circuit, capacitor, or crystal oscillator. For information on configuring oscillators, see applic ation note: “AN02 - Configuring the Internal and External Oscillators.” The internal oscillator can provide four SYSCLK frequencies: 2, 4, 8, and16 MHz. Many
different frequencies can be achieved using the external oscillator.
To conserve power, a designer must decide what the fastest needed SYSCLK frequency and required accuracy is for a given application. A design may require a constant SYSCLK frequency during all device opera tions. In this case, the designer will choose the lowest possible frequency required, and use the oscillator configuration that consumes the least power. Typical applications include serial communications, and periodic sampling with an ADC that must be performed.
Some operations may require high speed operation, but only in short, intermittent intervals. This is sometimes referred to as “burst” operation. In the C8051Fxxx, the SYSCLK frequency can be changed at anytime. Thus, the device can operate at low frequency until a condition occurs that requires high frequency operation.
Two examples of alternating between SYSCLK sources are (1) an internal oscillator/external crystal configuration, and (2) an external crystal/RC oscillator configuration. If the device is used for occasional high speed data conversion, and a real-time clock is used for time-stamping the data, a combination internal oscillator and external crystal would be ideal. During sampling operations, the high speed internal oscillator would be used. When sampling is complete, the device could then use an external 32 kHz crystal to maintain the real-time clock. Once high speed operations are required again, the device switches to the internal oscillator as necessary (see Figure 1below). An example of this procedure is illustrated in application note “AN008 Implementing a Rea l-Time Clock”.
The crystal oscillator and internal oscillator may be operated simultaneously and each selected as the SYSCLK source in software as desired. To reduce supply current, the crystal may also be shutdown when using the internal oscillator. In this case, when switching from the internal to external oscillator the designer must consider the start-up delay when switching the SYSCLK source. The C8051F0xx devices have a flag that is set when the external clock signal is valid (XTLVLD bit in the OSCXCN register) to indicate the oscillator is running and stable. This flag is polled before switching to the external oscillator. Note that other operations can continue using the internal oscillator during the crystal start-up time.
Some applications require intermittent high speed and accuracy (e.g., ADC sampling and data processing), but have lower frequency and accuracy requirements at other times (e.g., waiting for sampling interval), a combination of an external oscillator and RC circuit can be useful. In this case, the external RC oscillator is used
to derive the lower frequency SYSCLK source, and the crystal is used for high frequency operations. The RC circuit requires a connection to VDD (voltage source) to operate.
Because this connection could load the crystal oscillator circuit while the crystal is in operation, we connect the RC circuit to a general purpose port pin (see Figure 2 below). When the RC circuit is in use, the port pin connection is driven high (to VDD) by selectin g its output mode to “push-pull” and writing a …1‟ to the port latch. When the crystal oscillator is being used, the port pin is placed in a …hi- Z‟ condition by configuring the output mode of the port to “open-drain” and writing a …1‟ to the port latch. Note the RC circuit may take advantage of the existing capacitors used for the crystal oscillator.
The start-up of the RC-circuit oscillator is nearly instantaneous. However, there is a notable start-up time for the crystal. Therefore, switching from the RC oscillator to the external crystal oscillator using the following procedure:
1. Switch to the internal oscillator.
2. Configure the port pin used for the RC circuit voltage supply as open-drain and write a …1‟ to the port pin (Hi-Z condition).
3. Start the crystal (Set the XFCN bits).
4. Wait for 1 ms.
5. Poll for the External Crystal Valid Bit (XTLVLD --> …1‟).
6. Switch to the external oscillator.
Switch from the external crystal oscillator to the RC oscillator as follows:
1. Switch to the internal oscillator.
2. Shutdown the crystal (clear the XFCN bits).
3. Drive the voltage supply port pin high (to VDD) by putting the port pin in
“push pull” mode and writing a …1‟ to its port latch.
4. Switch back to the external oscillator.
Supply Voltage
The amount of current used in CMOS logic is directly proportional to the voltage of the power supply. The power consumed by CMOS logic is proportional the power supply voltage squared (See Equation 1). Thus, power consumption may be reduced by lowering the supply voltage to the device. The C8051Fxxx families of devices require a supply voltage of 2.7-3.6 Volts. Thus, to save power, it is recommended to use a 3.0 volt regulator instead of a 3.3 volt regulator for power savings.
CIP-51 Processor Power Management Mode s
The C8051 processor has two modes which can be used for power management. These modes are IDLE and STOP.
IDLE Mode
In IDLE Mode, the CPU and FLASH memory are taken off-line. All peripherals external to the CPU remain active, including the internal clocks. The CPU exits IDLE Mode when an enabled interrupt or reset occurs. The CPU is placed in IDLE Mode by setting the Idle Mode Select Bit (PCON.0) to …1‟.
When the IDLE Mode Select Bit is set to …1‟, the CPU enters IDLE Mode once the instruction that sets the bit has executed. An asserted interrupt will clear the IDLE Mode Select Bit and the CPU will vector to service the interrupt. After a return from interrupt (RETI), the CPU will return to the next instruction following the one that had set the IDLE Mode Select Bit. If a reset occurs while in IDLE Mode, the normal reset sequence will occur and the CPU will begin executing code at memory location 0x0000.
As an example, the CPU can be placed in IDLE while waiting for a Timer 2 overflow to
Initiate a sample/conversion in the ADC. Once the conversion and sample processing is complete, the ADC end-of-conversion interrupt wakes the CPU from IDLE Mode and processes the sample. After the sample processing is complete, the CPU is placed back into IDLE Mode to save power while waiting for the next interrupt.
As another example, the CPU may wait in IDLE Mode to save power until an external
Interrupt signal is used to “wake up” the CPU as needed. Upon receivin g an external interrupt, the CPU will exit IDLE Mode and vector to the corresponding interrupt vector (e.g., / INT0 or /INT1).
STOP Mode
The C8051 STOP Mode is used to shut down the CPU and oscillators. This will effectively shut down all digital peripherals as well. All analog peripherals must be shutdown by software prior to entering STOP Mode. The processor exits STOP Mode only by an internal or external reset. Thus, STOP Mode saves power by reducing the SYSCLK frequency to zero.
Note that the Missing Clock Detector will cause an internal reset (if enabled) that will terminate STOP Mode. Thus, the Missing Clock Detector should be disabled prior to entering STOP Mode if the CPU is to be in STOP Mode longer than the Missing Clock Detector timeout (100 μs).
The C8051 processor is placed in STOP Mode by setting the STOP Mode Select Bit (PCON.1) to …1‟. Upon reset, the CPU performs the normal reset sequence and begins executing code at 0x0000. Any valid RESET source will exit STOP Mode. Sources of reset to exit STOP Mode are External Reset (/RST), Missing Clock Detector, Comparator 0, and the External ADC Convert Start (/CNVSTR).
As an example, the CPU may be placed in STOP Mode for a period to save power when no device operation is required. When the device is needed, Comparator 0 reset could be used to “wake up” the device.
Generally, a power conscious design will use the lowest voltage supply, lowest SYSCLK frequency, and will use Power Management Modes when possible to maximize power savings. Most of these can be implemented or controlled in software.
Calculating Power Consumption
There are two components of power consumption in Cygnet‟s C8051F00x and C8051F01x family of devices: analog and digital. The analog component of power consumption is nearly constant for all SYSCLK frequencies. The digital component of power consumption changes considerably with SYSCLK frequency. The digital and analog components are added to determine the total power consumption.
The current use calculations presented in this application note apply to the C8051F00x and C8051F01x (…F000, 01, 02, 03, 05, 06, 10, 11, 12, 15, and 16) family of Cygnet devices.
The data sheet section, “Global DC Electrical Characteristics” contains various supply current values for different device conditions. The current values are separated into digital (at three example frequencies) and analog components. The analog numbers presented are values with all analog peripherals active. Supply current values for each analog peripheral can be found in the data sheet section for the peripheral.
For convenience, the Global DC Electrical Characteristics for the C8051F00x and C8051F01x family of devices are presented in the table below.
Internal vs. External Oscillator
Besides using lower SYSCLK frequencies, the designer can realize power savings by making smart SYSCLK source choices. The internal oscillator will typically consume 200μA of current supplied from the digital power supply. The current used to drive an external oscillator can vary. The drive current (supplied from the analog power supply) for an external source, such as a crystal, is set in software by configuring the XFCN bits in the External Oscillator Control Register (OSCXCN). Thus, at higher drive currents the user may save power by using the internal oscillator. However, at the lowest XFCN setting the external oscillator will use less than 1μA which is less current than used by the internal oscillator. Some typical measured current values are listed below. These measurements may vary from device to device. This drive level is kept as low as possible
To minimize power consumption, but must be high enough to start the external oscillator. The following table lists the current vs. External Oscillator Frequency Control Bit settings.
Digital Peripherals
For rough calculations, a good rule of thumb is to assume a 1mA/MHz of operating current (digital) + 1mA if the analog components (ADC, comparators, DAC, VREF, etc.) are enabled. This rule of thumb assumes a 3.6 V supply voltage. A lower
supply voltage will reduce power consumption. At 2.7 V, the rule of thumb is 0.5mA/MHz (in NORMAL mode). The rules of thumb for rough calculations are presented in the table below:
Analog Peripherals
The individual supply current values for each analog peripheral are posted in the data sheet section for that component (typically near the end of the section). It is recommended to disable all peripherals not in use to save power. For convenience, the C8051F00x and C8051F10x analog peripherals supply current values are listed below:
Calculating Total Current
When the required SYSCLK frequency, supply voltage, and peripherals have been determined, the total supply current can be estimated. To calculate the total supply current, the analog peripheral current use (found by adding the currents of each of the enabled analog peripherals) is added to the digital current use (calculated for a given frequency, power mode, and supply voltage). If all of the analog peripherals are enabled, analog current use is about 1mA.
Example Calculations
The following are examples of supply current calculations. Each application may use different power modes, SYSCLK frequencies, and peripherals at different times. Thus, power management specifications may require several different supply current calculations. The digital component and analog components of current use are found separately, and then added together for the total.
Example 1
The C8051F000 device is being used in a system with VDD=3.6 V. An ADC is sampling parameters and processing the sample for an output to one DAC. Because of the sampling and processing requirements of the application, SYSCLK frequency is 16 MHz using the internal oscillator.
Analog Components
Peripheral Supply Current (μ A)
ADC 450
VREF (internal) 50
Internal Oscan. 200
One DAC 110
VDD monitor 15
Total Analog 825
Digital Component
In NORMAL Mode @ 16 MHz;
1mA/M Hz * 16 MHz = 16mA
Total
825μA (analog) + 16mA (digital)= 16.8mA
Example 2
Assume we are still estimating the supply current in the same application in Example 1. If the sample processing is a burst operation (i.e., intermittent need for sampling and conversions), we may choose to place the CIP-51 in IDLE Mode to allow a Timer to wake-up the CIP-51 after a specified interval. In this case, the average supply current can be calculated in order to estimate power requirements. The device will switch between NORMAL Mode (for sampling and data conversion) and IDLE Mode (between sample processing operations). The switch between IDLE and NORMAL Modes (and supply current values) will happen in a cycle with a period equal to the sampling rate. (See Figure 3 below). This will allow us to calculate average supply current, after we calculate the supply current in IDLE Mode.
Analog Component
Analog peripherals are disabled during the IDLE Mode period between sample processing and output. Thus, analog current consumption is just:
VDD monitor = 15μA.
Digital Component
In IDLE Mode @ 16 MHz;
0.65mA/MHz * 16 MHz = 10.4mA
Total
The analog component would be considered negligible in most applications, thus, the total is just the digital component:
50μA (analog) + 10.4mA (digital) = 10.4mA
Now that we have calculated IDLE Mode supply current and NORMAL Mode supply current (in Example 1), we must calculate the time we spend in each mode to find the average current the device will use.
Assuming the ADC is in low-power tracking mode and at the maximum SAR conversion
Clock of 2 MHz (ADC set for SAR clock = SYSCLK/8), and we desire a 10 kHz
sampling rate. The period of the power cycle in Figure 3 is 1/10,000 (sample rate) = 100μs.
The time in NORMAL Mode will be the ADC tracking/conversion time, and the time to store the value in memory. In low-power tracking mode, it will take 3 SAR clocks for tracking, and 16 SAR clocks for conversion. 19 SAR clocks at 2 MHz will take 9.5μs. To store the number will take to system clock cycles, or 0.125μs. To enter NORMAL Mode, a move instruction is executed, taking 3 SYSCLK cycles which takes 0.188μs. Thus, the total time in NORMAL Mode is 9.5 μs+0.125 μs+0.188μs = 9.8μs.
Because the ADC sample period is 100μs, the time we may be in IDLE Mode during the power cycle is 100μs - 9.8μs (time in NORMAL Mode) = 90.2μs. By integrating the area under the curve in Figure 3 for one period (100μs), and dividing that number by the period, the average supply current is 11mA.
Example 3
If the oscillator frequency were lowered while in IDLE Mode (in Example 2) to 32 kHz using an external crystal for additional power savings, the current use would be:
The external oscillator contr ol bits will be set to XFCN = 000. This uses 0.6μA of analog current. (0.65mA *.032 MHz) + 0.6μA = 21μA
This is a dramatic difference from Example 2‟s IDLE Mode at 16 MHz, by simply reducing oscillator frequency.
Continuing with the average supply current calculation in Example 2 (with 6 extra SYSCLK cycles in NORMAL Mode to lower the frequency), the average supply current would be 1.7mA!
Example 4
In this application, the C8051F000 is being used to sample a parameter using the ADC and store samples in memory, with high accuracy timing of samples required. For more accurate timing, the SYSCLK is derived from an external 18.432 MHz crystal oscillator. To save power, the designer has decided to use a supply voltage of 3.0 V. Timer 2 is used to time the ADC sampling intervals.
Digital Component
In NORMAL Mode @ 18.432 MHz;
0.8mA/MHz * 18.432 MHz = 14.7mA
Total Current Use
3.4mA (analog)+1
4.7mA (digital)= 18.1mA
Example 4 in IDLE Mode
Placing the application in IDLE Mode with the ADC disabled during intervals that sampling is not required (no CIP-51 operations are needed; digital peripherals continue to operate) will save power if the sampling operation is a burst operation. In IDLE Mode, the digital current consumption is only 0.6mA/MHz, with no ADC, thus the current consumption at 18.432 MHz =11.1 miscalculating the average supply current for one sample period (similarly to Example 2, assuming a 10 kHz sampling rate and low-power tracking mode), the average current is estimated to be 11.9mA
附录4 英文资料翻译
电源管理技术及计算
本设计应用于下列器件
C8051F000、C8051F001、C8051F002、C8051F005、C8051F006、C8051F010、C8051F011、C8051F012、C8051F015、C8051F016、C8051F017
1 引言
本应用笔记讨论电源管理技术及计算C8051F00x和C8051F01x Sock中的功率消耗的方法。

很多应用系统对功耗有严格的要求，也存在几种不以牺牲性能为代价的降低功耗的方法，计算预计功耗对于说明系统的供电要求是很重要的。

2 关键点
供电电压和系统时钟频率对功率消耗有很大影响。

Cygnet的Sock有两种电源管理方式等待和停止。

功率消耗可以作为系统时钟电源电压和被允许的外设的函数来计算。

3 降低功耗的方法
CMOS数字逻辑器件的功耗受供电电压和系统时钟（SYSCLK）频率的影响。

可以通过调整这些参数来降低功耗，设计者也很容易控制这些参数。

本节讨论这些参数及它们对功率消耗的影响。

4 降低系统时钟频率
在CMOS数字逻辑器件中，功耗与系统时钟（SYSCLK）频率成正比：
功耗 = CV2f
其中C是CMOS的负载电容，V是电源电压，f是SYSCLK的频率。

C8051Fxxx系列器件的系统时钟可以来自内部振荡器或一个外部时钟源。

外部源可以是一个CMOS时钟、RC电路、电容或晶体振荡器。

有关振荡器配置方面的信息见应用笔记–“配置内部和外部振荡器”。

内部振荡器可提供四个时钟频率2、4、8 和16 MHz。

很多不同的频率可以通过使用外部振荡器得到，为了节省功耗设计者必须知道给定应用所需要的最高SYSCLK频率和精度。

一个设计可能需要一个在器件全部工作时间内保持不变的SYSCLK频率。

在这种情况下，设计者将选择满足要求的最低频率，采用消耗最低功率的振荡器配置。

典型的应用包括串行通信和必须用ADC完成的周期性采样。

某些操作可能要求高速度，但只是在很短的、断续的时间间隔内。

这种情况
在某些时候被称为“猝发”操作。

在C8051Fxxx中，SYSCLK频率可在任何时刻改变，因此器件平时可工作在较低的频率，直到某个需要高速操作的条件发生。

切换系统时钟源的两个例子是（1）内部振荡器/外部晶体配置，（2）外部晶体/RC振荡器配置。

如果器件偶尔进行高速数据转换，并使用一个实时时钟为数据提供时间戳，则一个内部振荡器和外部晶体的组合将是最理想的。

在采样操作期间应使用高速内部振荡器。

采样结束后，使用一个外部32kHz晶体以维持实时时钟。

一旦重新需要高速操作，器件将切换到内部振荡器（见图1）。

在应用笔记“实现一个实时时钟”中给出了这种操作过程的一个例子。

图1. 内部振荡器和外部晶体源配置
晶体振荡器和内部振荡器可以同时工作，每一个都可以根据需要被选为系统时钟源。

为了减小电源电流，在使用内部振荡器时可停止晶体振荡器。

在这种情况下，当从内部切换到外部振荡器时，设计者必须考虑切换系统时钟源时的起动延迟。

C8051F0xx器件有一个指示外部时钟信号有效的标志位（OSCXCN寄存器中的XTLVLD位），该标志在外部振荡器稳定运行时置位。

在切换到外部振荡器之前应查询该标志。

注意：在外部晶体起动期间，其它操作可继续使用内部振荡器。

某些应用需要间歇的高速度和高精度（例如ADC采样和数据处理），但在其它时间可允许低速度和低精度（例如等待采样时），这时可以用到外部振荡器和RC电路的组合。

在这种情况下，外部RC振荡器用于产生低频SYSCLK源，而晶体用于高频率操作。

RC电路需要接到VDD（电压源）才能工作。

由于在晶体处于工作状态时，这种连接可能加载晶体振荡器电路，我们将RC电路接到一个通用端口引脚（见图2），当使用RC电路时，与之连接的端口引脚被驱动到高电平（到VDD），这可以通过选择端口为“推挽”输出方式并向端口锁存器写“1”来实现。

当使用晶体振荡器时，端口引脚被置于“高阻”状态，这是通过设置端口为“漏极开路”输出方式，并向端口锁存器写“1”来实现的。

注意：RC电路可以利用晶体振荡器电路中已有的电容。

RC电路振荡器的起动几乎是瞬间完成的，然而晶体振荡器的起动时间是比较
可观的。

因此从RC振荡器切换到外部晶体振荡器时要经过下列过程：
a.切换到内部振荡器。

b. 将作为RC电路电源的端口引脚设置为漏极开路并向该端口引脚写“1”（高阻状态）。

c.起动晶体（设置XFCN位）。

d.等待1ms 。

e.查询外部晶体有效位（XTLVLD --> ‘1’）。

f.切换到外部振荡器。

从外部晶体振荡器切换到RC振荡器的步骤如下
a.切换到内部振荡器。

b.关闭晶体振荡器（清除XFCN位）。

c.驱动电源端口引脚到高电平（到VDD），通过选择端口为“推挽”输出方式并向端口锁存器写“1”来实现。

d.切换到外部振荡器。

图2. 外部RC和晶体振荡器配置
5 电源电压
CMOS逻辑电路中的电流与电源电压成正比。

CMOS逻辑电路的功耗与电源电压的平方成正比（见方程1）。

因此降低器件的供电电压可以减小功耗，C8051Fxxx 系列器件所要求的电源电压为2.7-3.6V。

为了减小功耗，建议使用3.0V的稳压器而不采用3.3V的稳压器。

CIP51处理器电源管理方式
C8051处理器有两种电源管理方式。

这两种方式为等待方式和停机方式。

6 等待方式
在等待方式下，CPU和FLASH存储器停止工作。

所有外设都处于工作状态，包
括内部时钟。

在有中断（被允许的中断）产生或发生系统复位时CPU退出等待方式。

可通过将等待方式选择位（PCON.0）设置为‘1’使CPU进入等待状态。

当等待方式选择位被置‘1’时，一旦设置该位的那条指令执行完，CPU立即进入等待状态。

有中断发生后，等待方式选择位将被清除，CPU将转入中断服务程序。

从中断返回后（RETI），CPU将进入设置等待方式选择位那条指令的下一条指令。

如果在等待方式下有复位条件产生，将产生正常的复位过程，CPU将从存储器地址0x0000开始执行程序。

例如，CPU被置于等待方式，等待定时器2溢出后启动一次A/D转换。

一旦转换过程结束，ADC转换结束中断将CPU从等待状态唤醒，开始处理采样值。

在样本处理过程结束后，CPU又重新被置于等待方式以节省功耗，同时等待下一次中断。

另一个例子，CPU平时处于等待方式以节省功耗，在需要时用一个外部中断信号将其“唤醒”。

在收到外部中断时，CPU将退出等待方式并转到相应的中断服务向量（例如/INT0或/INT1）。

7 停机方式
C8051的停机方式用于停止CPU和振荡器。

这将使所有数字外设都停止工作。

在进入停机方式前必须用软件将所有的模拟外设关闭，只有内部或外部复位可以使处理器退出停机方式。

实际上停机方式节省功耗是靠将SYSCLK频率降低到0 。

注意：时钟丢失检测器会产生一个内部复位（如果被允许），这个内部复位将结束停机方式。

因此如果要使CPU处于停机状态的时间大于时钟丢失检测器的超时时间（100 μs），则在进入停机方式之前应禁止时钟丢失检测器。

通过将停机方式选择位置‘1’使C8051处理器处于停机方式。

在复位时，CPU 完成正常的复位过程并从0x0000地址开始执行程序，任何有效的复位源都可以使CPU退出停机方式。

能使CPU退出停机方式的复位源是：外部复位（/RST）、时钟丢失检测器、比较器0、外部ADC转换启动信号（/CNVSTR）。

例如，CPU在不需要工作的一段时间内可以被置于停机方式以节省功耗，在需要工作时用用比较器0复位信号将其“唤醒”。

一般来说，一个低功耗的设计应采用最低的电源电压、最低的SYSCLK频率，并尽可能地使用电源管理方式，以最大限度地节省功耗。

这些条件中的大多数都可以用软件实现或控制。

8 功耗计算
在Cygnet 的C8051F00x和C8051F01x系列器件中消耗功率的两大部件是：模拟部件和数字部件。

模拟部件的功耗对于所有的SYSCLK频率来说几乎是不变的；数字部件的功耗随着SYSCLK频率的不同而有较大的变化。

模拟部件和数字部件的
功耗加在一起构成器件的总功耗。

本应用笔记中所介绍的器件消耗电流的计算方法适用于C8051F00x和C8051F01x（F000、01、02、05、06、10、11、12、15和16系列器件）。

数据手册中“总体直流电气特性”一节中给出了不同条件下器件的供电电流值。

电流值被分为数字部件（在三种示例频率下）和模拟部件两部分。

所给出的模拟电流值是所有模拟外设都工作时的数值。

每个模拟外设的供电电流可以在数据手册中与外设相关的章节中查到。

9 内部和外部振荡器比较
除了使用较低的SYSCLK频率之外，设计者还可以通过合理地选择时钟源达到减小功耗的目的。

内部振荡器消耗数字电源电流的典型值为200 μA，用于驱动外部振荡器的电流是变化的。

对于一个外部振荡源（例如一个晶体），驱动电流（由模拟电源提供）用软件通过配置外部振荡器控制寄存器（OSCXCN）的XFCN 位来设置。

在驱动电流较大时，用户可以使用内部振荡器以节省功耗，但是在最低的XFCN设置下，外部振荡器使用不到1μA的电流，小于内部振荡器所使用的电流。

下面列出了几个典型测量电流值。

这些测量值对于不同的器件可能不一样。

驱动电平应保持最低以节省功耗，但又应足够高以使外部振荡器能够起振。

下表列出了电流与外部振荡器频率控制位设置的关系。

10 数字外设
对于粗略的计算，一个经验公式是假设1mA/MHz的工作电流+1mA，如果模拟部件（ADC、比较器、DAC、VREF等被允许）。

这个经验公式假定使用3.6V的电源电压。

较低的电源电压将使功耗降低。

在2.7V经验公式为 0.5mA/MHz（在正常方式）。

下表列出了用于估算电源电流的经验数据。

注意：数字电源电流与使用多少个数字外设无关，电源电流与SYSCLK的频率及电源电压成正比。

11 模拟外设
每个模拟外设的供电电流值都在数据表中关于这个外设的部分给出（通常在该部分的最后）。

建议禁止所有不用的外设部件以降低功耗。

为方便起见，将C8051F00x和C8051F01x模拟外设的供电电流值列于下表：
C8051F0xx模拟外设供电电流
注意：模拟功耗与SYSCLK频率相对无关。

12 总电流计算
当所需要的SYSCLK频率、电源电压及外设部件都已经确定后，可以估算总的电源电流。

所使用的模拟外设电流（将每个被允许的模拟外设的电流加在一起）加上所使用的数字电流（在给定频率、电源方式和电源电压下计算）就得到总的电源电流。

如果所有的模拟外设都被允许，则所用模拟电流大约为1mA 。

13 计算举例
下面是电源电流计算的几个例子。

每个应用在不同的时间，可以使用不同的电源方式、SYSCLK频率和外设部件。

因此，功率管理指标需要几种不同的电源电流计算。

数字部件和模拟部件所使用的电流分别计算然后加到一起得到总电流。

例1
在一个VDD=3.6V的系统中使用C8051F000器件。

ADC对一个参数采样，将样本处理后经DAC输出。

由于在该应用中需要进行采样和处理，选择内部振荡器提供16MHz的SYSCLK频率。

模拟部件：
数字部件：在正常方式工作频率为16 MHz；1mA/MHz * 16 MHz = 16mA
总电流:825μA（模拟）+ 16mA（数字）= 16.8mA 例2
假设我们仍然估算例1中同一个应用的电源电流。

如果采样处理是一个猝发操作（即间歇性地需要采样和转换），我们可以选择平时将CIP-51置于等待方式，经过一个规定的时间间隔后，再用一个定时器将其“唤醒”。

在这种情况下，可以通过计算平均电流来估算功率需求。

器件将在正常方式（用于采样和数据转换）和等待方式（在两个采样处理操作之间）之间切换。

在正常方式和等待方式之间切换的周期等于采样速率。

这就允许我们在计算了等待方式的电源电流之后计算平均电源电流。

模拟部件：
在两次采样处理和输出之间，器件处于等待方式，模拟外设被禁止。

这种情况下模拟电流消耗为：
VDD监视器 = 15μA
数字部件：
在等待方式，工作频率为16 MHz
0.65mA/MHz * 16 MHz = 10.4mA
总电流
在大多数应用中，模拟部件的功耗可以被忽略，这样一来总电流就是数字部件的电流：
50 μA（模拟）+ 10.4mA（数字）= 10.4mA
注意，我们已经计算了等待方式下的电源电流和正常方式下的电源电流（在例1中）。

我们还必须计算在每种方式下所消耗的时间，以计算所用器件的平均电流。

假设ADC工作在低功耗跟踪方式，使用最大的2MHz SAR转换时钟（ADC设置为：SAR时钟 = SYSCLK/8），我们需要10kHz的采样速率。

图3中的电源周期为1/10,000（采样速率）= 100 μs 。

处在正常方式下的时间是ADC跟踪/转换时间和将样本保存到存储器的时间。

在低功耗跟踪方式，需要3个SAR时钟用于跟踪和16个SAR时钟用于转换。

这19个SAR时钟在频率为2MHz时需要9.5 μs。

存储采样值需要两个系统时钟周期即0.125 μs。

为了进入正常方式，要执行一条mov指令，需三个SYSCLK周期，即0.188
μs。

这样在正常方式下的总时间为 9.5 μs + 0.125 μs+ 0.188 μs = 9.8 μ
s 。

因为ADC的采样周期是100 μs，所以在电源周期中等待方式所占的时间为100 μs – 9.8 μs（正常方式下的时间）= 90.2 μs。

对图3曲线下方的区域在一个周期（100 μs）内积分，然后除以周期值，得到平均电源电流为11 mA 。

16.8mA\10.4mA等待方式采样周期时间数据采样和转换正常方式电流。

例3
如果在器件处于等待方式（在例2中）时使用一个外部振荡器，使振荡器的频率降低到32kHz，可以进一步降低功耗。

这时所用的电流是：
将外部振荡器控制位设置为XFCN = 000。

这样将使用0.6 μA的模拟电流。

(0.65mA * 0.032MHz) + 0.6 μA = 21 μA
这与例2中16MHz下的等待方式有惊人的差别，只是通过简单地降低振荡器频率。

继续进行列2中（在正常方式有6个附加的SYSCLK周期用于降低振荡器频率）的平均电流计算得到的平均电流为1.7mA 。

例4
在这个应用中，用C8051F000的ADC对一个参数采样并将采样值保存到存储器中，需要对采样精确定时。

为了满足更精确的定时要求，SYSCLK由一个外部18.432 MHz晶体振荡器提供。

为了节省功耗，设计者决定使用3.0V的电源电压。

定时器2用于对ADC采样间隔定时。

模拟部件：
数字部件：
在正常方式，工作频率为18.432MHz；0.8mA/MHz * 18.432 MHz = 14.7mA
总电流：3.4mA模拟+ 14.7mA数字= 18.1mA
例4 在等待方式时的电流
如果采样操作是猝发式的在不需要采样的时间段内将器件置于等待方式并禁止ADC不需CIP-51操作数字外设继续工作将节省功耗在等待方式所消耗的数字电流仅为0.6mA/MHz如果没有ADC转换在18.432 MHz下电流消耗= 11.1mA。