Xilinx FPGA XC5VLX30T 特殊资源分布示意图

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FPGA硬件实战设计经验

TR_Con_ZD板卡设计经验总结针对TR板卡的PCB布线一根线未动想到的TR板卡bank分配方法介绍与原来在华为工作的师兄（他做的TR板卡的PCB）聊了一下，他说TR板卡的FPGA线序一根都没改。

Bank分配是我来做的，原则是方便PCB走线。

分配时候是参考下面的资料来分配的。

TR板卡结构图XC6VSX315T-FF1759的bank管脚分布图考虑到板卡上IO资源大户是AD/DA，FPGA的bank分配集中在右侧，而AD/DA在板卡的上方，因此将FPGA逆时针转90°，如下图所示，这样PCB布线就比较方便了。

分配bank的时候没有考虑Bank在FPGA内部的分布图，如下图所示：想到的硬件设计流程的东西师兄说：“动一根线的话，都需要FPGA程序重新跑一遍，这需要浪费很多时间。

”FPGA 程序？TR板卡的程序还没有呢！的确值得思考了，到底这个设计应该是按照怎样的一个流程。

在华为，是按照这样的流程进行的。

1.硬件设计人员将IO需求，板卡供电等情况反馈给逻辑设计人员2.逻辑人员对所需的FPGA资源做评估，最终确定FPGA型号（硬件设计人员也可以参与一起选型）3.逻辑设计人员对FPGA进行bank分配，需要以下资源：a)硬件设计人员提供硬件设计框图b)最好对所用的IO先画一个自己根据原理图框图分配的bank的原理图草图，导入PCB后进行一下预布局，这样信号流程就清晰了。

逻辑人员根据上述资源进行bank的分配，因为他们对FPGA内部的资源最清楚。

逻辑人员要兼顾PCB布局布线的方便，有时候不可能照顾都到布局布线的方便。

这时候，就需要在硬件设计人员和FPGA设计人员之间来回折腾，最终兼顾双方，得到一个bank 分配方案。

4.FPGA人员根据bank分配，写一个测试评估的程序，如果能够跑通，时序满足设计需求，说明现在的bank分配可以使用，如果出现严重的时序错误，那么就需要考虑重新分配bank，通过不断地调整，最终确定板卡的bank分配。

FPGA可编程逻辑器件芯片XC5VLX330-2FFG1760I中文规格书

Table 1-2:DSP48E Port List and Definitions (Cont’d)Name Direction Bit Width DescriptionBCIN(1)In18Cascaded data input from BCOUT of previous DSP48E slice(muxed with B).PCIN(1)In48Cascaded data input from PCOUT of previous DSP48E slice toadder.CARRYCASCIN(1)In1Cascaded carry input from CARRYCASCOUT of previousDSP48E slice.MULTSIGNIN(1)In1Sign of the multiplied result from the previous DSP48E slice forMACC extension.ACOUT(1)Out30Cascaded data output to ACIN of next DSP48E slice.BCOUT(1)Out18Cascaded data output to BCIN of next DSP48E slice. CARRYCASCOUT(1)Out1Cascaded carry output to CARRYCASCIN of next DSP48E slice.This signal is internally fed back into the CARRYINSELmultiplexer input of the same DSP48E slice. MULTSIGNOUT(1)Out1Sign of the multiplied result cascaded to the next DSP48E slicefor MACC extension.P Out48Data output from second stage adder/subtracter or logicfunction.PATTERNBDETECT Out1Output indicating a match between P[47:0] and pattern bar. PATTERNDETECT Out1Output indicating a match between P[47:0] and pattern. OVERFLOW Out1Output indicating overflow when used with appropriatesetting of the pattern detector.UNDERFLOW Out1Output indicating underflow when used with appropriatesetting of the pattern detector.CARRYOUT Out44-bit CARRYOUT from each 12-bit section of logic unit/adder.Useful for SIMD.CARRYOUT[3] is the carryout of the 48-bit adder (invalidduring multiplies).PCOUT(1)Out48Cascaded data output to PCIN of next DSP48E slice.Notes:1.These signals are dedicated routing paths internal to the DSP48E column. They are not accessible via fabric routing resources.2.All signals are active High.Simplified DSP48E Slice OperationThe math portion of the DSP48E slice consists of a 25-bit by 18-bit, two's complementmultiplier followed by three 48-bit datapath multiplexers (with outputs X, Y, and Z). Thisis followed by a three-input adder/subtracter or two-input logic unit (see Figure1-5).When using two-input logic unit, the multiplier cannot be used.The data and control inputs to the DSP48E slice feed the arithmetic and logic stages. The Aand B data inputs can optionally be registered one or two times to assist the construction ofPipeline RegistersNotesAREG, BREG ACASCREG,BCASCREG(Refer to Figure1-7)Current DSP To Cascade DSP00Direct and cascade paths have no registers.11Direct and cascade paths have one register.21, 2When direct path has two registers, cascade path canhave one or two registers.X, Y, and Z MultiplexerThe OPMODE (Operating Mode) control input contains fields for X, Y, and Z multiplexerselects.The OPMODE input provides a way for the user to dynamically change DSP48Efunctionality from clock cycle to clock cycle (e.g., when altering the internal datapathconfiguration of the DSP48E slice relative to a given calculation sequence).The OPMODE bits can be optionally registered using the OPMODEREG attribute (asnoted in Table1-3).Table1-6, Table1-7, and Table1-8 list the possible values of OPMODE and the resultingfunction at the outputs of the three multiplexers (X, Y, and Z multiplexers). Themultiplexer outputs supply three operands to the following adder/subtracter. Not allpossible combinations for the multiplexer select bits are allowed. Some are marked in thetables as “illegal selection” and give undefined results. If the multiplier output is selected,then both the X and Y multiplexers are used to supply the multiplier partial products to theadder/subtracter.If AREG/BREG = 0 and USE_MULT = MULT_S (this requires MREG=1), the A:B pathshould not be selected via the opmode multiplexer. Since the opmode can be dynamic,switching between the registered multiplier with MREG=1 and the combinatorial A:B pathis not supported. If the multiplier is not being used, USE_MULT should be set to NONE. Table 1-6:OPMODE Control Bits Select X Multiplexer OutputsZ OPMODE [6:4]YOPMODE [3:2]XOPMODE [1:0]XMultiplexerOutputNotesxxx xx000Defaultxxx0101M Must select withOPMODE[3:2]=01 xxx xx10Pxxx xx11A:B 48 bits wide Table 1-7:OPMODE Control Bits Select Y Multiplexer OutputsZ OPMODE[6:4]YOPMODE[3:2]XOPMODE[1:0]YMultiplexerOutputNotesxxx00xx0Defaultxxx0101M Must select withOPMODE[1:0]=01xxx10xx48'ffffffffffff Used mainly for logicunit bitwise operations onX and Z multiplexersxxx11xx CChapter 1:DSP48E Description and SpecificsZ OPMODE[6:4]YOPMODE[3:2]XOPMODE[1:0]ZMultiplexerOutputNotes000xx xx0Default001xx xx PCIN010xx xx P011xx xx C1001000P Use for MACC extendonly101xx xx17-bitShift(PCIN)110xx xx17-bitShift(P)111xx xx xx Illegal selectionSimplified DSP48E Slice OperationAdder/Subtracter or Logic UnitThe adder/subtracter or logic unit output is a function of control and data inputs (see Figure1-15). The data inputs to the adder/subtracter are selected by the OPMODE and the CarryInSel signals. The ALUMODE signals choose the function implemented in theadder/subtracter. Thus, the OPMODE, ALUMODE, and CARRYINSEL signals together determine the functionality of the embedded adder/subtracter/logic unit. When using the logic unit, the multiplier must not be used. The values of OPMODEREG andCARRYINSELREG must be identical.As with the input multiplexers, the OPMODE bits specify a portion of this function. The symbol ± in the table means either add or subtract and is specified by the state of theALUMODE control signal (ALUMODE = 0011 is defined as “subtraction,” used forretargeting designs from Virtex-4 devices). The symbol “:” in the table meansconcatenation. The outputs of the X and Y multiplexer and CIN are always added together.Refer to “ALUMODE Inputs,” page 32.。

FPGA可编程逻辑器件芯片XC5VLX30-1FFG324I中文规格书

XTP481 (v3.3) November 18, 2019 FAQ: Implications of XCN18002 SummaryThe purpose of this notification is to communicate FAQs related to substrate material change for Virtex®, Virtex®-II, Virtex®-II Pro, Virtex®-4 and Virtex®-5 FPGA packages.The manufacturer of the current substrate material is discontinuing production of the substrate material. Therefore, Xilinx qualified new substrate material set to continue supply and shipment of Virtex, Virtex-II, Virtex II-Pro, Virtex-4 and Virtex-5 FPGA packages. This enables Xilinx to better support long-term customer demand. There is no change in the fit, form or function with this change. The new substrate core and build up material have been qualified and shipping in many 7 series, ROHS Lead Free and UltraScale™ packages.Xilinx will revise the corresponding material declaration data sheet (MDDS) to reflect the new material change . FAQsQ: What is the change?Substrate material will change.Q: Why is Xilinx making this change?The manufacturer of the current substrate material is discontinuing production of the substrate material. Therefore, Xilinx qualified new substrate material set to continue supply and shipment of Virtex, Virtex-II, Virtex II-Pro, Virtex-4 and Virtex-5 FPGA packages as mentioned in XCN18002. This enables Xilinx to better support long-term customer demand.Q: When will this change take effect?Xilinx will start shipping commercial / industrial “XC” devices 90 days after the PCN release. Estimated cut-over dates for Defense-grade “XQ” devices are listed below. No delay or exceptions will be allowed once the PCN is released.Q: Can customer continue with current core/build up material?No. Substrate material supplier is ending production of current material. There will be no material to continue with current BOM.Q:Is there any change in shelf life?No change.Q: Is there any change in package dimension?No change.FAQ: Substrate Material Change for Virtex, Virtex-II, Virtex-II Pro, Virtex-4 & Virtex-5 FBGA PackagesFAQ: Substrate Material Change for Virtex, Virtex-II, Virtex-II Pro, Virtex-4 & Virtex-5 FBGA Packages Table 1: Virtex-II Pro Devices-PackagesDevice Package-PinEstimatedcrossshippingDevice Package-PinEstimatedcrossshippingXC2VP2 FF(G)672 May 2020 XC2VP50 FF(G)1517 Jul 2018 XC2VP4 FF(G)672 May 2020 XC2VP70 FF(G)1517 Oct 2019 XC2VP7 FF(G)672 Jan 2019 XC2VP100 FF(G)1696 Jul 2018 XC2VP20 FF(G)896 May 2020 XC2VP100 FF(G)1704 Mar 2019 XC2VP30 FF(G)896 Jun 2019 XC2VP70 FF(G)1704 Jun 2019 XC2VP7 FF(G)896 Dec 2019Table 3: Virtex-5 Devices-PackagesDevice Package-PinEstimatedcrossshippingDevice Package-PinEstimatedcrossshippingXC5VTX150T FF(G)1156 Jul 2018 XC5VFX100T FF1738 May 2020 XC5VFX130T FF(G)1738 Jul 2019 XC5VLX110T FF1738 May 2020 XC5VFX200T FF(G)1738 Jan 2019 XC5VLX155T FF1738 Jun 2019 XC5VLX220T FF(G)1738 Nov 2018 XC5VLX110 FF1760 Nov 2019 XC5VLX330T FF(G)1738 Dec 2018 XC5VLX155 FF1760 Jul 2018 XC5VSX240T FF(G)1738 Jun 2019 XC5VLX20T FF323 Jul 2019 XC5VTX150T FF(G)1759 Feb 2019 XC5VLX30T FF323 Feb 2019 XC5VTX240T FF(G)1759 Feb 2019 XC5VLX30 FF324 Jan 2019 XC5VFX100T FF1136 May 2020 XC5VLX50 FF324 Mar 2019 XC5VFX70T FF1136 May 2020 XC5VFX30T FF665 Oct 2019 XC5VLX110T FF1136 Dec 2019 XC5VFX70T FF665 May 2020 XC5VLX155T FF1136 May 2020 XC5VLX30T FF665 Dec 2019 XC5VLX50T FF1136 May 2020 XC5VLX50T FF665 Dec 2019 XC5VLX85T FF1136 Sep 2019 XC5VSX35T FF665 May 2020 XC5VSX50T FF1136 May 2020 XC5VSX50T FF665 Jan 2019 XC5VSX95T FF1136 Apr 2019 XC5VLX110 FF676 Mar 2020 XC5VLX110 FF1153 Jan 2020 XC5VLX30 FF676 Jan 2019 XC5VLX155 FF1153 Feb 2019 XC5VLX50 FF676 Aug 2018 XC5VLX50 FF1153 Aug 2019 XC5VLX85 FF676 Nov 2018 XC5VLX85 FF1153 Feb 2019 XC5VLX220 FF(G)1760 Nov 2019XC5VLX330 FF(G)1760 Nov 2018 Table 4: Virtex-4 EasyPath Devices-PackagesDevice Package-PinEstimatedcrossshippingXCE04L6 FF1148 Nov 2018 XCE04S2 FFG668 Apr 2019 XCE04L10 FF(G)1513 May 2020 XCE04L4 FF(G)1148 Oct 2018 XCE04L8 FFG1148 Oct 2018 XCE04F10 FF(G)1152 Feb 2019Table 8: Virtex-4Q Defense-grade Devices-PackagesDevice Package-PinEstimatedcut-overdate codeDevice Package-PinEstimatedcut-overdate codeXQ4VLX60 EF668 1837 XQL4VFX100 FF1152 1837 XQ4VLX25 FF668 1918 XQL4VFX60 FF1152 2017 XQ4VLX40 FF668 1837 XQ4VFX100 FF(G)1152 2030 XQ4VLX60 FF668 1837 XQ4VFX60 FF(G)1152 1841 XQL4VLX60 FF668 1837 XQL4VLX200 FF(G)1513 1901 XQ4VSX35 FF(G)668 2019 XQ4VFX140 FF1517 2020 XQ4VFX60 EF672 1837 XQL4VFX140 FF(G)1517 1901 XQL4VFX40 FF672 1901 XQ4VLX25 SF363 1837 XQL4VFX60 FF672 1837。

RF_FPGASX50T芯片详细设计(版本号V2.13)

SP5203RF_FPGASX50T芯片详细设计文件编号xxxx修订 2.13版本记录：目录目录....................................................................................................................................... - 3 -1RF_FPGASX50T芯片简介............................................................................................. - 11 -1.1RF_FPGASX50T芯片的一级模块划分. (11)1.2RF_FPGASX50T芯片的内部功能模块结构图 (12)2时钟/复位控制模块..................................................................................................... - 13 -2.1功能描述 . (13)2.2接口说明 (13)2.3实现说明 (13)2.3.1rst_sync模块：..................................................................................................... - 14 -2.4表项/寄存器设置 (15)2.5重要资源使用情况说明 (15)3LBUS控制模块 ............................................................................................................ - 16 -3.1功能描述 . (16)3.2接口说明 (16)3.3实现说明 (16)3.3.1LBUS译码模块：.................................................................................................. - 17 -3.3.2小数分频模块................................................................................................... - 19 -3.3.3温度监控模块................................................................................................... - 22 -3.3.4ADC检波控制模块 ............................................................................................... - 23 -3.3.5FLASH接口模块.................................................................................................... - 25 -3.3.6SP5162时钟板I2C控制模块 ............................................................................... - 27 -3.3.7SP5162时钟板本振控制模块 .............................................................................. - 28 -3.3.8AD9779A控制模块............................................................................................... - 33 -3.3.9ADS62C15控制模块 ............................................................................................. - 34 -3.3.10SP5161通路板控制接口模块.......................................................................... - 34 -3.3.11发射功率自动校准模块................................................................................... - 35 -3.3.12发射本振自动控制模块................................................................................... - 38 -3.3.13接收参考电平自动校准模块........................................................................... - 38 -3.3.14发射BRAM数据源控制模块........................................................................... - 41 -3.3.15DDR2访问仲裁控制模块................................................................................. - 42 -3.3.16发射链路自动开关模块................................................................................... - 43 -3.4表项/寄存器说明 (44)4GTP收发模块 .............................................................................................................. - 45 -4.1功能描述 . (45)4.2接口说明 (45)4.3实现说明 (46)4.3.1时钟的设计....................................................................................................... - 46 -4.3.2Virtex-5 FPGA Rocket IO复位设计 ....................................................................... - 47 -4.3.3GTP用户接口设计 ............................................................................................... - 47 -4.3.1GTP链路检测 ....................................................................................................... - 50 -4.4重要资源使用情况说明 . (50)5发射链路信号处理模块............................................................................................... - 51 -5.1功能描述 . (51)5.2接口说明 (51)5.3实现说明 (51)5.3.1发射FIR滤波器组：........................................................................................ - 51 -5.3.2数据源选择：................................................................................................... - 60 -5.3.3数字上变频：................................................................................................... - 61 -5.3.4数字域增益调整：........................................................................................... - 62 -5.3.5发射功率补偿：............................................................................................... - 62 -5.3.6IQ平衡补偿： ...................................................................................................... - 64 -5.3.7LO直流补偿：...................................................................................................... - 64 -5.4重要资源使用情况说明 . (65)6接收链路信号处理模块............................................................................................... - 66 -6.2接口说明 (66)6.3实现说明 (66)6.3.1DC OFFSET校准： ................................................................................................ - 67 -6.3.2模拟补偿滤波：............................................................................................... - 67 -6.3.3接收功率补偿：............................................................................................... - 68 -6.3.4数字下变频：................................................................................................... - 68 -6.3.5接收FIR滤波器组：........................................................................................ - 68 -6.3.6接收BRAM缓存：........................................................................................... - 70 -6.3.7192X数据采样：.................................................................................................. - 71 -6.3.8DFT功率计算：.................................................................................................... - 71 -6.4重要资源使用情况说明 . (71)7DDR2接口模块............................................................................................................ - 72 -7.1功能描述 . (72)7.2接口说明 (72)7.3实现说明 (73)7.3.1MIG简要配置....................................................................................................... - 73 -7.3.2ddr2各模块功能介绍 .......................................................................................... - 74 -7.3.3用户接口时序说明........................................................................................... - 75 -7.4重要资源使用情况说明 . (76)8参考资料 ..................................................................................................................... - 77 -9附录一：FLASH表项介绍 ........................................................................................... - 78 -9.1发射功率校准表 . (80)9.2发射LO直流补偿表 (82)9.3发射IQ平衡补偿表 (82)9.4接收功率补偿表 (82)9.5板卡信息表 (83)10附录二：内部寄存器地址分配说明........................................................................ - 85 -10.1.1版本寄存器....................................................................................................... - 92 -10.1.2版本补充寄存器............................................................................................... - 92 -10.2板卡控制寄存器 . (92)10.2.1板卡控制寄存器............................................................................................... - 92 -10.3SP5161通路板控制寄存器 .. (92)10.3.1SP5161通路板控制寄存器.............................................................................. - 92 -10.3.2SP5161控制接口读数据寄存器 ...................................................................... - 93 -10.4发射功率补偿寄存器 .. (93)10.4.1功率模式寄存器............................................................................................... - 93 -10.4.2输出功率寄存器............................................................................................... - 93 -10.4.3功率补偿状态寄存器....................................................................................... - 94 -10.4.4反馈补偿校准控制寄存器............................................................................... - 94 -10.4.5发射功率补偿控制寄存器............................................................................... - 94 -10.4.6发射功率补偿寄存器值I/Q ............................................................................. - 94 -10.4.7发射功率自动控制基准功率........................................................................... - 95 -10.4.8发射功率补偿反馈值....................................................................................... - 95 -10.4.9发射功率自动设置补偿值d ............................................................................ - 95 -10.4.10发射功率自动设置补偿值0 ........................................................................... - 95 -10.4.11发射功率自动设置补偿值1 ........................................................................... - 95 -10.4.12发射功率自动设置补偿值2 ........................................................................... - 96 -10.4.13发射功率自动设置补偿值3 ........................................................................... - 96 -10.4.14发射功率自动设置补偿值4 ........................................................................... - 96 -10.4.15OUT口和IO口的固定差损值 ......................................................................... - 96 -10.4.16发射功率自动设置ATT1初始值 .................................................................... - 96 -10.4.17发射功率自动设置多级ATT补偿值 .............................................................. - 96 -10.4.18发射功率自动设置DDS默认值...................................................................... - 97 -10.4.19发射功率50M带内补偿值............................................................................. - 97 -10.5接收功率补偿寄存器 .. (97)10.5.1输入功率寄存器............................................................................................... - 97 -10.5.3接收功率0dbfs基准值.................................................................................... - 98 -10.5.4接收功率补偿寄存器值I/Q ............................................................................. - 98 -10.5.5接收参考电平自动设置ATT参考值............................................................... - 98 -10.5.6接收功率补偿反馈值....................................................................................... - 98 -10.5.7接收功率自动设置补偿值d ............................................................................ - 99 -10.5.8接收功率自动设置补偿值............................................................................... - 99 -10.5.9接收功率自动设置补偿值0 ............................................................................ - 99 -10.5.10接收功率自动设置补偿值1 ........................................................................... - 99 -10.5.11接收功率自动设置补偿值2 ........................................................................... - 99 -10.5.12接收功率计算值 ............................................................................................ - 100 -10.5.13接收功率自动设置DDS默认值.................................................................... - 100 -10.5.14接收功率自动设置DDC默认值 ................................................................... - 100 -10.5.15接收功率50M带内补偿值........................................................................... - 100 -10.6射频本振控制寄存器 (101)10.6.1射频频率控制寄存器..................................................................................... - 101 -10.6.2射频发射频率寄存器..................................................................................... - 101 -10.6.3射频接收频率寄存器..................................................................................... - 101 -10.6.4射频VCO寄存器............................................................................................ - 101 -10.6.5锁定计数器..................................................................................................... - 102 -10.7FLASH控制寄存器 .. (102)10.7.1FLASH地址寄存器.......................................................................................... - 102 -10.7.2FLASH写数据寄存器...................................................................................... - 103 -10.7.3FLASH读数据寄存器...................................................................................... - 103 -10.7.4FLASH操作控制寄存器.................................................................................. - 103 -10.8温度控制模块寄存器 (104)10.8.1温度控制寄存器............................................................................................. - 104 -10.8.2温度门限寄存器............................................................................................. - 104 -10.8.3温度状态寄存器............................................................................................. - 104 -10.9IIC数字电位计控制 (104)10.9.2IIC使能启动寄存器........................................................................................ - 105 -10.9.3IIC状态寄存器................................................................................................ - 105 -10.10D/A转换模块寄存器 (105)10.10.1AD9779A SPI数据寄存器............................................................................... - 105 -10.10.2AD9779A SPI使能启动寄存器 ....................................................................... - 105 -10.10.3AD9779A SPI状态寄存器............................................................................... - 105 -10.11直流补偿寄存器. (106)10.11.1LO直流补偿控制寄存器................................................................................ - 106 -10.11.2LO直流补偿寄存器值.................................................................................... - 106 -10.11.3LO直流补偿固化值 ....................................................................................... - 106 -10.12数字域增益控制寄存器 . (106)10.12.1发射增益调整控制寄存器 ............................................................................ - 106 -10.12.2发射增益调整寄存器值 ................................................................................ - 107 -10.12.3LO直流补偿固化值 ....................................................................................... - 107 -10.13IQ平衡控制寄存器 .. (107)10.13.1IQ平衡控制寄存器 ........................................................................................ - 107 -10.13.2IQ平衡寄存器值 ............................................................................................ - 107 -10.13.3IQ平衡固化值 ................................................................................................ - 108 -10.14VCO小数分频寄存器.. (108)10.14.1VCO小数分频控制寄存器............................................................................. - 108 -10.14.2VCO小数分频参数N ..................................................................................... - 108 -10.14.3VCO小数分频参数P ...................................................................................... - 108 -10.14.4VCO小数分频参数Q ..................................................................................... - 108 -10.15AD7680控制模块寄存器 .. (109)10.15.1AD7680控制寄存器....................................................................................... - 109 -10.15.2AD7680数据寄存器....................................................................................... - 109 -10.16A/D转换模块寄存器 (109)10.16.1ADS62C15 SPI数据寄存器 ............................................................................. - 109 -10.16.2ADS62C15 SPI使能启动寄存器 ..................................................................... - 109 -10.17SP5162时钟板控制寄存器 (110)10.17.1SP5162时钟板控制寄存器............................................................................ - 110 -10.18发射链路BRAM控制.. (110)10.18.1发射Bram控制寄存器 ................................................................................. - 110 -10.18.2发射Bram数据 ............................................................................................. - 110 -10.18.3发射Bram截止地址 ..................................................................................... - 111 -10.19接收链路BRAM控制.. (111)10.19.1接收Bram控制寄存器 ................................................................................. - 111 -10.19.2接收Bram数据 ............................................................................................. - 111 -10.20内部DDS控制寄存器 . (112)10.20.1发射内部DDS控制寄存器 ........................................................................... - 112 -10.20.2发射内部DDS控制数据 ............................................................................... - 112 -10.21DUC DDS控制寄存器 .. (112)10.21.1DUC DDS控制寄存器 ..................................................................................... - 112 -10.21.2DUC DDS控制数据 ......................................................................................... - 112 -10.22DDC DDS控制寄存器 .. (113)10.22.1DDC DDS控制寄存器 ..................................................................................... - 113 -10.22.2DDC DDS控制数据 ......................................................................................... - 113 -10.23功率自动控制模块 (113)10.23.1功率自动控制开关 ........................................................................................ - 113 -10.24芯片状态寄存器. (113)10.24.1芯片状态寄存器 ............................................................................................ - 113 -10.25模拟补偿滤波器模块 .. (114)10.25.1模拟补偿滤波器控制寄存器 ........................................................................ - 114 -10.25.2模拟补偿滤波器系数 .................................................................................... - 114 -10.26DDR2控制模块寄存器 (114)10.26.1DDR2控制寄存器........................................................................................... - 114 -10.26.2DDR2接收地址寄存器................................................................................... - 115 -10.26.3DDR2发射地址寄存器................................................................................... - 115 -10.27.1ADF4001状态寄存器 ..................................................................................... - 116 -10.28滤波器模式控制寄存器 . (116)10.28.1滤波器模式控制寄存器 ................................................................................ - 116 -10.29GTP链路检测寄存器表 . (116)10.29.1GTP链路检测寄存器表 ................................................................................. - 116 -1 RF_FPGASX50T芯片简介RF_FPGASX50T芯片是北京星河亮点通信软件有限责任公司研发的芯片，使用美国XILINX公司的XC5VSX50T-1FFG665C实现，应用于自主研发的射频模块。

FPGA可编程逻辑器件芯片XC5VFX130T-1FF1738C中文规格书

Application Note: Virtex-5 FPGAsSummary Virtex®-5 FPGAs and ISE® software support configuration from and programming of industry-standard, parallel NOR flash memory (BPI PROMs). Industry standard BPI PROMs are analternate solution for Virtex-5 FPGA designs whose requirements are not met by the PlatformFlash XL configuration and storage device (see [Ref1] for more information on Platform FlashXL). The iMPACT software, included in the ISE® development software tools, provides indirectprogramming for select BPI PROMs during prototyping. This application note demonstrateshow to program a Numonyx StrataFlash P30 BPI PROM indirectly using iMPACT 11.4 and aXilinx cable. In this solution, the Virtex-5 FPGA serves as a bridge between the IEEE Std1149.1 (JTAG) bus interface and the BPI bus interface. The required hardware setup, BPI-UPPROM file generation flow, and BPI indirect programming flow are shown. The Virtex-5 FPGABPI-UP configuration sequence is also described.Note:Parallel NOR flash memory is referred to by the term BPI PROM throughout this document.PROM (connected to the FPGA's BPI bus interface). This extra logic must be downloaded into the FPGA by iMPACT before indirect programming is possible.This application note is divided into three main sections. The first section discusses the hardware connections required for the indirect in-system programming of BPI PROMs for prototype designs. The second section shows the Xilinx software tool flows for generating a PROM file formatted for 16-bit BPI-UP mode and then for programming the select BPI PROMs. The third section provides a basic configuration flow overview for the FPGA after the BPI PROM is programmed and describes expectations when using this indirect setup.iMPACT Indirect In-System Programming with aVirtex-5 FPGA The basic hardware setup required for the iMPACT indirect BPI PROM programming method is shown in Figure1.Minimum Requirements•Virtex-5FPGA•BPI PROM (refer to Table1)•Xilinx Cable and Connector (refer to T able4, page7)•ISE iMPACT Software 11.4Note:Indirect BPI PROM programming was introduced with limited device support in iMP ACT 9.2i.This application note demonstrates the software flow and lists the device support in iMP ACT 11.4.Figure 1:iMPACT Indirect BPI PROM Programming with a Virtex-5 FPGASelecting BPI PROMsSeveral factors are considered when selecting a BPI PROM (including BPI PROM family, density, package, and the data bus width). When using iMPACT for programming, the BPI PROM family must be selected from the supported list in T able 1. After the BPI PROM family is selected, consider the BPI PROM density. All of the Virtex-5 FPGAs can be configured from a single BPI PROM (typical configuration density requirements for Virtex-5 FPGAs are provided in Table 2). A larger BPI PROM can be used for daisy-chained applications, storing multiple FPGA configuration bitstreams, or for applications storingadditional user data, such as code for embedded MicroBlaze™ core or embedded PowerPC™ processors.Table 1: BPI PROM Programming Capability with iMPACTBPI PROM Vendor (1)Family (2)Density NumonyxStrataFlash Embedded P30 (28FxxxP30)(3)64Mb–1Gb Embedded J3 v. D or F (28FxxxJ3)32Mb–256MbNotes:1.Refer to Software Flows for BPI File Preparation and Programming, page 9 for more information.2.Numonyx StrataFlash Embedded P30 monolithic die and top-boot options are supported by the iMP ACT indirect BPI programming solution. Numonyx stacked die, bottom, or uniform boot options are not supported.Table 2: Typical Virtex-5 FPGA Configuration Bit RequirementsXilinx FPGA Configuration Bits (Per Device)Smallest BPI PROMRequiredXC5VLX308,374,0168Mb XC5VLX5012,556,67216Mb XC5VLX8521,845,632 32Mb XC5VLX11029,124,60832Mb XC5VLX15541,048,06464Mb XC5VLX22053,139,45664Mb XC5VLX33079,704,832128Mb XC5VLX20T 6,251,2008Mb XC5VLX30T 9,371,13616Mb XC5VLX50T 14,052,35216Mb XC5VLX85T 23,341,31232Mb XC5VLX110T 31,118,84832Mb XC5VLX155T 43,042,30464Mb XC5VLX220T 55,133,69664Mb XC5VLX330T 82,696,192128Mb XC5VSX35T 13,349,12016Mb XC5VSX50T 20,019,32832Mb XC5VSX95T 35,716,09664Mb XC5VSX240T 79,610,368128Mb XC5VTX150T 43,278,46464 Mb XC5VTX240T65,755,64864MbXC5VFX30T13,517,05616Mb XC5VFX70T 27,025,40832Mb XC5VFX100T 39,389,696 64Mb XC5VFX130T 49,234,94464Mb XC5VFX200T70,856,704128MbTable 2: Typical Virtex-5 FPGA Configuration Bit Requirements (Cont’d)Notes:1.VCC_CONFIG (VCCO_0) is the configuration output supply voltage and supplies the dedicated configuration pins: TMS, TCK, TDO, TDI,M[2:0], HSWAPEN, PROGRAM_B, DONE, INIT_B, CCLK, D_IN.2.VCCO_1 supplies A[19:0].3.VCCO_2 supplies FCS_B, FOE_B, FWE_B, A[25:20], and D[0:7].4.VCCO_4 supplies D[8:15].5.It is recommended to have the option for both JT AG (M[2:0]=101) and BPI_UP (M[2:0]=010) configuration modes.6.HSWAPEN can be driven Low to enable pull-ups on I/O.7.RS[1:0] and CSO_B signals are used for advanced daisy-chain and revisioned applications. These signals are not connected for this setup.Refer to [Ref4] for detailed information.8.With iMP ACT versions 11.3 and later, pin IO_L9P_CC_GC_4 is pulled High when the P30 flash family is targeted. Before iMP ACT 11.3, it wasrecommended that the IO_L9P_CC_GC_4 pin be reserved and not connected in a design using the iMP ACT indirect programming core. If this signal is used, the target application must consider that the iMP ACT indirect programming core will drive this signal Low.Caution!The iMP ACT indirect programming solution drives all FPGA address lines (A[25:0]) during ISP operations on the BPI PROM.Figure 2:BPI Configuration Mode Setup (Master Virtex-5 FPGA and Slave BPI PROM)。

FPGA可编程逻辑器件芯片XQ5VFX100T中文规格书

TDO_0
PROGRAM_B
CCLK_0
TCK_0
TMS
The RocketIO™ GTP transceiver I/O channels for the devices listed in Table 1-3 or the GTX transceiver I/O channels for the devices listed in Table 1-4.
Table 1-1: Flip-Chip Packages
Package
Packages
Specifications FF323 FF324 FF665 FF676 FF1136 FF1153 FF1156
Pitch (mm) 1.00 1.00 1.00 1.00 1.00 1.00
1.00
Size (mm) 19 x 19 19 x 19 27 x 27 27 x 27 35 x 35 35 x 35 35 x 35
H13
24 IO_L7P_24
H10
24 IO_L7N_24
J10
24 IO_L8P_CC_24
H14
24 IO_L8N_CC_24(2 )
H15
24 IO_L9P_CC_24
K10
Virtex-5 FPGA Packaging and Pinout Specification
Maximum I/Os
172
220
360
440
640
800
360
FF1738 1.00 42.5 x 42.5
960
FF1759 1.00 42.5 x 42.5
680
FF1760 1.00 42.5 x 42.5

FPGA可编程逻辑器件芯片XQ5VFX130T-1F1738C中文规格书

48
96 48 1,728 6 不适用不适用不适用不适用不适用 17 560
XC5VLX85
120 x 54 12,960
840
48
192 96 3,456 6 不适用不适用不适用不适用不适用 17 560
XC5VLX110 XC5VLX155
160 x 54 17,280 160 x 76 24,320
XC5VLX330 240 x 108 51,840 3,420
192 576 288 10,368 6 不适用不适用不适用不适用不适用 33 1,200
XC5VLX20T 60 x 26 3,120
210
24
52 26 936 1 不适用
1
2
4 不适用 7 172
XC5VLX30T 80 x 30 4,800
DS100 (v5.0) 2009 年 2 月 6 日产品规范
Virtex-5 系列概述
数控阻抗 (DCI) 有源 I/O 终端 • 可选串行或并行终端 • 温度和电压补偿 • 显著简化电路板布局
- 减少电阻器 - 在理想的位置设置终端，比如信号源或信号终点
65nm 铜 CMOS 工艺
• 1.0V 内核电压 • 12 层金属提供最强的布线功能，并可容纳硬 IP 植入 • 三栅极氧化层技术，确实可降低静态功耗
1,120 1,640
64
256 128 4,608 6 不适用不适用不适用不适用不适用 23 800
128 384 192 6,912 6 不适用不适用不适用不适用不适用 23 800
XC5VLX220 160 x 108 34,560 2,280

FPGA可编程逻辑器件芯片XQ5VFX130T-1F1738I中文规格书

General DescriptionThe Defense-grade Virtex®-5Q family provides the newest, most capable features in the aerospace and defense industry from the reprogrammable FPGA market leader. The Virtex-5Q family delivers on Size, Weight, and Power - Cost (SWAP-C) reduction requirements while increasing performance and density for higher integration. Based on the proven commercial Virtex-5 FPGAs, the Virtex-5Q family offers greater operational temperature ranges off the shelf to fit the needs of the aerospace and defense customer base as well as ruggedized packaging for protection against tin-whiskering and harsh manufacturing processes. Mask-set control and long-term product availability are also standard. Using the second generation Advanced Silicon Modular Block (ASMBL™) column-based architecture, the Virtex-5Q family contains four distinct sub-families, the most offered by any FPGA vendor. Each sub-family contains a different ratio of features to address the needs of a wide variety of advanced designs. In addition to the most advanced, high-performance logic fabric, Virtex-5Q FPGAs contain many dedicated system-level blocks, including powerful 36Kbit block RAM/FIFOs, second generation 25x18 DSP slices, SelectIO™ technology with built-in digitally-controlled impedance, ChipSync™ technology source-synchronous interface blocks, system monitor functionality, enhanced clock management tiles (CMTs) with integrated digital clock managers (DCM) and phase-locked-loop (PLL) clock generators, and advanced configuration options. Additional device-dependent features include power-optimized, high-speed serial transceiver blocks for enhanced serial connectivity, PCI Express® compliant integrated Endpoint blocks, tri-mode Ethernet Media Access Controllers (Ethernet MACs), and high-performance PowerPC®440 microprocessor embedded blocks. These features allow advanced logic designers to build the highest levels of performance and functionality into their FPGA-based systems. The Virtex-5Q LX, LXT, SXT, and FXT FPGAs also include advanced high-speed serial connectivity and link/transaction layer capability. Virtex-5Q FPGAs offer the best solution for addressing the needs of aerospace and defense logic, DSP, and embedded systems designers for a host of applications including imaging, secure applications, electronic warfare, packet processing, and more. Summary of Virtex-5Q FPGA Features•Four sub-families: LX, LXT, SXT, and FXT•Virtex-5Q LX: High-performance general logic applications •Virtex-5Q LXT: High-performance logic with advanced serial connectivity•Virtex-5Q SXT: High-performance signal processing applications with advanced serial connectivity•Virtex-5Q FXT: High-performance embedded systems with advanced serial connectivity•Cross-family compatibility•LXT, SXT, and FXT devices are footprint compatible in the same package using adjustable voltage regulators •All devices are pin-to-pin compatible with commercial Virtex-5 devices with the same package within sub-familiesfor prototyping.•Most advanced, high-performance, optimal-utilization, FPGA logic•Real 6-input look-up table (LUT) technology•Dual 5-LUT option•Improved reduced-hop routing•64-bit distributed RAM option•SRL32/Dual SRL16 option•Powerful CMT clocking•DCM blocks for zero delay buffering, frequency synthesis, and clock phase shifting•PLL blocks for input jitter filtering, zero delay buffering, frequency synthesis, and phase-matched clock division •36Kbit block RAM/FIFOs•T rue dual-port RAM blocks•Enhanced optional programmable FIFO logic•Programmable-T rue dual-port widths up to x36-Simple dual-port widths up to x72•Built-in optional error-correction circuitry•Optionally program each block as two independent 18Kbit blocks•High-performance parallel SelectIO technology• 1.2 to 3.3V I/O Operation•Source-synchronous interfacing using ChipSync technology •Digitally-controlled impedance (DCI) active termination•Flexible fine-grained I/O banking•High-speed memory interface support •Advanced DSP48E slices•25x18, two’s complement, multiplication•Optional adder, subtracter, and accumulator•Optional pipelining•Optional bitwise logical functionality•Dedicated cascade connections•Flexible configuration options•SPI and Parallel Flash interface•Multi-bitstream support with dedicated fallbackreconfiguration logic•Auto bus width detection capability•System Monitoring capability on all devices•On-chip/Off-chip thermal monitoring•On-chip/Off-chip power supply monitoring•JT AG access to all monitored quantities•Integrated Endpoint blocks for PCI Express designs •LXT, SXT, and FXT FPGAs•Compliant with the PCI Express Base Specification 1.1•x1, x4, or x8 lane support per block•Works in conjunction with RocketIO™ transceivers•Tri-mode 10/100/1000 Mb/s Ethernet MACs•LXT, SXT, and FXT FPGAs•RocketIO transceivers can be used as PHY or connect to external PHY using many soft Media Independent Interface(MII)options•RocketIO GTP transceivers 100Mb/s to 3.75Gb/s •LXT and SXT FPGAs•RocketIO GTX transceivers 150Mb/s to 6.5Gb/s•FXT FPGAs only•PowerPC 440 microprocessors•FXT FPGAs only•RISC architecture•7-stage pipeline•32Kbyte instruction and data caches included•Optimized processor interface structure (crossbar)•65nm copper CMOS process technology• 1.0V core voltage•Rugged EF packaging•Epoxy coated internal chip caps for superior solvent clean resistance (all except FF323 and FF1738 pin packages)•Fully tin/lead packaging including chip-cap finishVirtex-5Q Family OverviewDS174 (v2.0) March 22, 2010Product SpecificationInput/Output Blocks (SelectIO)IOBs are programmable and can be categorized as follows:•Programmable single-ended or differential (LVDS) operation•Input block with an optional single data rate (SDR) or double data rate (DDR) register•Output block with an optional SDR or DDR register •Bidirectional block•Per-bit deskew circuitry•Dedicated I/O and regional clocking resources•Built-in data serializer/deserializerThe IOB registers are either edge-triggered D-type flip-flops or level-sensitive latches.special hardware connections for I/O in the same locality. These regional clock inputs are distributed within a limited region to minimize clock skew between IOBs. Regional I/O clocking supplements the global clocking resources.Data serializer/deserializer capability is added to every I/O to support source-synchronous interfaces. A serial-to-parallel converter with associated clock divider is included in the input path, and a parallel-to-serial converter in the output path.An in-depth guide to the Virtex-5Q FPGA IOB is found in UG194, Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC User Guide.Package FF323FF1738EF676EF665EF1136EF1153EF1738 Size(mm)19x1927x2727x2735x3535x3542.5x42.5 Device GTs I/O GTs I/O GTs I/O GTs I/O GTs I/O GTs I/O XQ5VLX85N/A440XQ5VLX110N/A440N/A800XQ5VLX30T 4 GTPs172XQ5VLX110T16 GTPs640XQ5VLX155T16 GTPs640XQ5VLX220T16 GTPs680 XQ5VLX330T24 GTPs960 XQ5VSX50T8 GTPs360XQ5VSX95T16 GTPs640XQ5VSX240T24 GTPs960XQ5VFX70T8 GTXs36016 GTXs640XQ5VFX100T16 GTXs64016 GTXs680 XQ5VFX130T20 GTXs840 XQ5VFX200T24 GTXs960Virtex-5Q FPGA DocumentationComplete and up-to-date documentation of the Virtex-5Q family of FPGAs is available on the Xilinx website. In addition to the most recent Virtex-5Q Family Overview, the following files are also available for download:Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics (DS714)This data sheet contains the DC and Switching Characteristic specifications for the Virtex-5Q family. Virtex-5 FPGA User Guide (UG190)This guide includes chapters on:•Clocking Resources•Clock Management T echnology (CMT)•Phase-Locked Loops (PLL)•Block RAM•Configurable Logic Blocks (CLBs)•SelectIO Resources•SelectIO Logic Resources•Advanced SelectIO Logic ResourcesVirtex-5 FPGA XtremeDSP Design Considerations (UG193)This guide describes the DSP48E slice and includes reference designs for using DSP48E math functions and various filters.Virtex-5 FPGA Configuration Guide (UG191)This all-encompassing configuration guide includes chapters on configuration interfaces (serial and parallel), multi-bitstream management, bitstream encryption, Boundary-Scan and JT AG configuration, and reconfiguration techniques.Virtex-5 FPGA Packaging and Pinout Specification (UG195)This specification includes the tables for device/package combinations and maximum I/Os, pin definitions, pinout tables, pinout diagrams, mechanical drawings, and thermal specifications.Virtex-5 FPGA PCB Designer’s Guide (UG203)This guide provides information on PCB design forVirtex-5Q devices, with a focus on strategies for making design decisions at the PCB and interface level.Virtex-5 FPGA System Monitor User Guide (UG192) The System Monitor functionality is outlined in this guide.Virtex-5 FPGA RocketIO GTP Transceiver User Guide (UG196)This guide describes the RocketIO GTP transceivers available in the Virtex-5Q LXT and SXT FPGAs.Virtex-5 FPGA RocketIO GTX Transceiver User Guide (UG198)This guide describes the RocketIO GTX transceivers available in the Virtex-5Q FXT FPGAs.Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC User Guide (UG194)This guide describes the dedicated Tri-Mode Ethernet Media Access Controller available in the Virtex-5Q LXT, SXT, and FXT FPGAs.Virtex-5 FPGA Integrated Endpoint Block for PCI Express Designs User Guide (UG197)This guide describes the integrated Endpoint blocks in the Virtex-5Q LXT, SXT, and FXT FPGAs that are PCI Express compliant.Embedded Processor Block in Virtex-5 FPGAs Reference Guide (UG200)This reference guide is a description of the embedded processor block available in the Virtex-5Q FXT FPGAs.。

Xilinx-v5

I/O 组总数
13 17 17 23 23 33 12 15 15 20 20 27 12 15 19
最大用户 I/O 数 (6)
400 560 560 800 800 1,200 360 480 480 680 680 960 360 480 640
Virtex-5 逻辑架构
• 高达 50% 的速度提升
0
R
Virtex-5 系列概述
LX、LXT 和 SXT 平台
DS100 (v3.0) 2007 年 2 月 2 日
0
0
先期产品技术说明
概述
Virtex™-5 系列提供 FPGA 市场中最新最强大的功能。Virtex-5 系列采用第二代 ASMBL™（高级硅片组合模块）列式架构，包含四种截然不同的平台（子系列），比此前任何 FPGA 系列提供的选择范围都大。每种平台都包含不同的功能配比，以满足诸多高级逻辑设计的需求。本概述包含关于 LX、LXT 和 SXT 平台的详细信息。除了最先进的高性能逻辑架构，Virtex-5 FPGA 还包含多种硬 IP 系统级模块，包括强大的 36Kb Block RAM/FIFO、第二代 25 x 18 DSP Slice、带有内置数控阻抗的 SelectIO™ 技术、ChipSync™ 源同步接口模块、系统监视器功能、带有集成 DCM （数字时钟管理器）和锁相环 (PLL) 时钟发生器的增强型时钟管理模块以及高级配置选项。LXT 和 SXT 器件还包含针对增强型串行连接的电源优化高速串行收发器模块、一个符合 PCI Express™ 的集成端点模块和三态以太网 MAC （媒体访问控制器）。这些功能使高级逻辑设计人员能够在其基于 FPGA 的系统中体现最高档次的性能和功能。Virtex-5 FPGA 以最先进的 65nm 铜工艺技术为基础，是定制 ASIC 技术的可编程替代方案。大多数高级系统设计都需要 FPGA 的可编程能力。Virtex-5 FPGA 以前所未有的逻辑、DSP、软 / 硬微处理器和连接功能提供最佳解决方案，以满足高性能逻辑设计人员、高性能 DSP 设计人员和高性能嵌入式系统设计人员的需求。Virtex-5 LXT、SXT 和 FXT 平台具有先进的高速串行连接功能和链路 / 事务层功能。

XilinxFPGA介绍

目前FPGA芯片仍是基于查找表技术的，但其概念和性能已经远远超出查找表技术的限制，并且整合了常用功能的硬核模块（如块RAM、时钟管理和DSP）。

图1-1所示为Xilinx公司FPGA的内部结构示意图（由于不同系列的应用场合不同，所以内部结构会有一定的调整），从中可以看出FPGA芯片主要由 6部分组成：可编程输入输出单元、基本可编程逻辑单元、完整的时钟管理、嵌入块式RAM、丰富的布线资源、内嵌的底层功能单元和内嵌专用硬件模块。

图1-1 FPGA芯片的内部结构每个模块的功能如下：1．可编程输入输出单元（IOB）可编程输入/输出单元简称I/O单元，是芯片与外界电路的接口部分，完成不同电气特性下对输入/输出信号的驱动与匹配要求，提供输入缓冲、输出驱动、接口电平转换、阻抗匹配以及延迟控制等功能，其一般示意结构如图1-2所示。

FPGA内的I/O按组分类，每组都能够独立地支持不同的I/O标准。

通过软件的灵活配置，可适配不同的电气标准与I/O物理特性，可以调整驱动电流的大小，可以改变上、下拉电阻。

目前，I/O口的频率也越来越高，一些高端的FPGA 通过DDR寄存器技术可以支持高达2Gbps的数据速率。

外部输入信号可以通过IOB模块的存储单元输入到FPGA的内部，也可以直接输入FPGA 内部。

当外部输入信号经过IOB模块的存储单元输入到FPGA内部时，其保持时间（Hold Time）的要求可以降低，通常默认为0。

为了便于管理和适应多种电器标准，FPGA的IOB被划分为若干个组（bank），每个bank的接口标准由其接口电压VCCO决定，一个bank只能有一种VCCO，但不同bank的VCCO可以不同。

只有相同电气标准的端口才能连接在一起，VCCO 电压相同是接口标准的基本条件。

2．可配置逻辑块（CLB）CLB是FPGA内的基本逻辑单元。

CLB的实际数量和特性会依器件的不同而不同，但是每个CLB都包含一个可配置开关矩阵，此矩阵由4或6个输入、一些选型电路（多路复用器等）和触发器组成。

FPGA可编程逻辑器件芯片XC5VLX30T-2FFG665C中文规格书

• Advanced DSP48E slices − 25 x 18, two’s complement, multiplication − Optional adder, subtracter, and accumulator − Optional pipelining − Optional bitwise logical functionality − Dedicated cascade connections
• RocketIO GTP transceivers 100 Mb/s to 3.75 Gb/s − LXT and SXT Platforms
• RocketIO GTX transceivers 150 Mb/s to 6.5 Gb/s − TXT and FXT Platforms
• PowerPC 440 Microprocessors − FXT Platform only − RISC architecture − 7-stage pipeline − 32-Kbyte instruction and data caches included − Optimized processor interface structure (crossbar)
• Integrated Endpoint blocks for PCI Express Designs − LXT, SXT, TXT, and FXT Platforms − Compliant with the PCI Express Base Specification 1.1 − x1, x4, or x8 lane support per block − Works in conjunction with RocketIO™ transceivers

FPGA可编程逻辑器件芯片XC5VLX30-1FFG324C中文规格书

Recommended PCB Design Rules for BGA PackagesXilinx provides the diameter of a land pad on the component side. This information is required prior to the start of the board layout so the board pads can be designed to match the component-side land geometry. The typical values of these land pads are described in Figure 5-1 and summarized in Table 5-1. For Xilinx® BGA packages, Non-Solder Mask Defined (NSMD) pads on the board are suggested to allow a clearance between the land metal (diameter L) and the solder mask opening (diameter M) as shown in Figure 5-1. The space between the NSMD pad and the solder mask as well as the actual signal trace widths depend on the capability of the PCB vendor. The cost of the PCB is higher when the line width and spaces are smaller.Figure 5-1:Suggested Board Layout of Soldered Pads for BGA Packages1.3x 3 matrix is shown for illustration purposes only. One land pad is shown with via connection.Power Management Strategy•Heat Sinking Solutions at the System LevelDepending on the system's physical as well as mechanical constraints, the expectation is that the thermal budget is maintained with custom or OEM heat sink solutions,providing the third prong in the thermal management strategy. At this point, Xilinx has left the heat sink solution to the system-level designers who can tailor the design and solution to the constraints of their systems, being fully aware that the part has certain inherent capabilities for delivering the heat to the surface.Heat sink solutions do exist and can be effective on these low θJB flip-chip platforms.Table 6-3 below illustrates a finned heat sink solution matrix in Network environment (1U and 2U) arrangement for 35mm packages and up for power ranging from 15W to 40W. The AAVID standard finned heat sink offerings are used to illustrate the coverage given thermal budgets of ΔT =35°C and ΔT =45°C scenarios. Other heat sink configurations can be explored similarly.The Virtex-5 FPGA packages can be grouped into medium- and high-performancepackages based on their power handling capabilities. All Virtex-5 FPGA packages can use thermal enhancements, ranging from simple airflow to schemes that can include passive as well as active heat sinks. This is particularly true for the bigger flip-chip BGA packages where system designers have the option to further enhance the packages with bigger and more elaborate heat sinks to handle excesses of 25W with arrangements that consider system –physical constraints as illustrated in Table 6-3.Table 6-3:Finned Heat Sink Solution Matrix for Large Flip-chip BGA in Network Package Power(W)35 x 35 mmFF1136/FF1153/FF115642.5 x 42.5 mmFF1738/FF1759/FF1760ΔT=35°CΔT=45°CΔT=35°CΔT=45°C15W1U (5)Note 1Note 12U (6)Note 1Note 125W1U (5)Note 4Note 2Note 4Note 22U (6)Note 2Note 1Note 2Note 135W1U (5)Note 4Note 3Note 4Note 32U (6)Note 4Note 2Note 4Note 240W1U (5)––Note 4Note 32U (6)Note 3Note 2Notes:1.Solution available at 200 LFM, for example, AAVID finned part number 68520, 72390, 72415.2.Solution available at 400 LFM, for example, AAVID finned part number 68520, 69920.3.Solution available at 600 LFM, for example, AAVID finned part number 72390, 69920, 74590.4.No standard. AAVID finned solution below 600 LFM—custom finned might be required.5.For 1U Height—(max heat sink height = 26mm)6.For 2U Height—(max heat sink height = 64mmChapter 6:Thermal SpecificationsSome Thermal Management OptionsSupport for Compact Thermal Models (CTM)•Designs can be implemented to take advantage of the board's ability to spread heat.The effect of the board is dependent on its size and how it conducts heat. Board size,the level of copper traces, and the number of buried copper planes all lower thejunction-to-ambient thermal resistance for a package mounted on the board. The cold ring junction-to-board thermal data for Virtex-5 FPGA packages are given in Table 6-1. Users need to be aware that a direct heat path to the board from a component also exposes the component to the effect of other heat sources on the board, particularly if the board is not cooled effectively. An otherwise cooler component can be heated by other heat contributing components on the board.Table 6-4:Impact of Mounted Board Characteristics on θJA (FF1148)Xilinx 35 x 35 mmFF1148θJA (°C/W) for Different Board Sizes 4 x 4in 10 x 10in20 x 20inLayer Count of Mounted Board49.1(1)8.3–88.0 5.5 4.9127.5 4.7 4.4167.2 4.5 4.224–4.34.0Notes:1.Base JEDEC Mount ConditionsChapter 6:Thermal Specifications。

FPGA可编程逻辑器件芯片XC5VFX200T-2FFG1738I中文规格书

EN057 (v1.3) March 31, 2009IntroductionAlthough Xilinx has made every effort to ensure the highest possible quality, these Virtex®-5 FPGA engineering samples (ES) are subject to the limitations described in the following errata.DevicesThese errata apply to the Virtex-5 devices, as shown in Table 1.Hardware Errata DetailsThis section provides a detailed description of each hardware issue known at the release time of this document.GTX TransceiversClock CorrectionThe Clock Correction feature of the Virtex-5 FPGA GTX transceiver can cause data corruption on the receiver when a clock correction sequence is skipped or added. See UG198, Virtex-5 FPGA RocketIO GTX Transceiver User Guide for more detailed information about the Clock Correction feature.This issue can occur when all of the following conditions are true:•Asynchronous operation: When the local reference clock of the Virtex-5 FPGA GTX transceiver is driven from adifferent oscillator than the far-end transceiver. This introduces a parts per million (PPM) offset in frequency between the operation of the transceivers, requiring clock correction to skip or add clock correction sequences on a periodic basis. This also implies that the RXUSRCLK and RXUSRCLK2 ports of the Virtex-5 FPGA GTX transceiver are derived from the local oscillator and not the RXRECCLK port.•Clock Correction is enabled.-CLK_CORRECT_USE_0/1 attribute is set to TRUE .•The length of the clock correction sequence is 1 or 3 Bytes.-CLK_COR_ADJ_LEN_0/1 attribute is set to 1 or 3.When the conditions described above are met, one of the multiple work-around options described below shall be used to mitigate this issue. XAUI, PCIe®, SRIO, and Infiniband are the most common protocols affected but only when used in asyn-chronous operation.EN057 (v1.3) March 31, 2009Errata NotificationT able 1: Virtex-5 Devices Affected by These ErrataDevices Speed Grades JTAG ID (Revision Code)XC5VFX30T CES-1, -2, -36XC5VFX70T CES-1, -2, -36XC5VFX100T CES-1, -2, -32XC5VFX130T CES-1, -2, -32XC5VFX200T CES-1, -20Packages AllErrata NotificationWork-aroundIf the application permits, implement one of the following work-around options:•Use synchronous clocking•Convert to 2byte or 4byte clock correction sequence•If the application does not permit one of these options, see Answer Record 32164.All versions of UG198, Virtex-5 FPGA RocketIO GTX Transceiver User Guide subsequent to the current version, v2.1, will properly reflect the Clock Correction behavior described herein.PowerPC 440 ProcessorBranch History TableThe Branch History Table (BHT) must be disabled for deterministic execution latency.Auxiliary Processor UnitThere are two errata for the Auxiliary Processor Unit (APU):•After a Translation Look-aside Buffer (TLB) miss caused by an instruction fetch, in a very specific combination of events, the Auxiliary Processor Unit (APU) can lock up or corrupt the data.•When the floating-point execution is disabled in the PowerPC® 440 processor but enabled in the APU controller, and an FPU instruction is executed, the processor can generate a spurious program exception instead of an FPU-unavailable exception.Additional InformationFor more details, including work-arounds for the processor errata, refer to answer record 30529.Operational GuidelinesDesign Software RequirementsCORE Generator™ software must be used to correctly configure the GTX transceivers.The devices listed in Table1, unless otherwise specified, require the following Xilinx development software installations.•Speed specification v1.59 (or later), Xilinx ISE™ Design Suite 10.1 (or later).-For -3 speed grade, the minimum software requirement is Xilinx ISE Design Suite 10.1 with Service Pack 2 (or later).•The stepping should not be set, but if set, it must be set to zero in the user constraint file (UCF): CONFIG STEPPING = “0”;EN057 (v1.3) March 31, 2009EN057 (v1.3) March 31, 2009TraceabilityThe XC5VFX30T CES is marked as shown in Figure 1. The other devices listed inTable 1 are marked similarly.Device T ypeP a ck a geS peed Gr a de D a te Code Lot Code Engineering Sa mpleEN057_01_031808。

FPGA可编程逻辑器件芯片XC5VLX330-2FF1760C中文规格书

IntroductionThank you for participating in the Virtex®-6 Engineering Sample Program. As part of this program, we are pleased to provide to you engineering samples of the devices listed in Table 1. Although Xilinx has made every effort to ensure the highest possible quality, these devices are subject to the limitations described in the following errata.DevicesThese errata apply to the devices shown in Table 1.Hardware Errata DetailsThis section provides a detailed description of each hardware issue known at the release time of this document.MMCMRestriction of Frequency Range for Bandwidth = HIGH or OPTIMIZEDWhen the Phase Frequency Detector (PFD) frequency (FIN/D) is lower than 135MHz and the BANDWIDTH attribute of the MMCM is set to HIGH or OPTIMIZED, a phase error between MMCM output clocks can occur, making the output clock signals invalid. This condition can also cause the fractional output counter to fail.The ISE® software v12.4 and later provides appropriate warnings for possible violations of this restriction.The ISE software v12.4 and later correctly handles designs set to OPTIMIZED bandwidth for all valid PFD frequencies.This issue will not be fixed in the devices listed in Table 1.Work-aroundPFD frequencies lower than 135MHz must use LOW bandwidth mode to ensure correct operation.See Answer Record 38132 for more information.EN101 (v1.9) April 11, 2011Errata Notification Table 1:Devices Affected by These Errata Devices XC6VLX760 CES JTAG ID (Revision Code): 0, 2XC6VLX550T CESJT AG ID (Revision Code): 0XC6VLX365T CESJT AG ID (Revision Code): 0XC6VLX240T CESJT AG ID (Revision Code): 2, 4XC6VLX195T CESJT AG ID (Revision Code): 4XC6VLX130T CESJT AG ID (Revision Code): 2, 4XC6VSX475T CESJT AG ID (Revision Code): 2, 4XC6VSX315T CESJT AG ID (Revision Code): 4PackagesAll Speed Grades -1, -2Restriction of Clock Divider ValuesThe input clock divider (DIVCLK_DIVIDE) cannot have a value of 3 or 4 when the input clock frequency (F IN) of the MMCM is above 315MHz.The ISE software v12.4 and later provides appropriate warnings for possible violations of this restriction.This issue will not be fixed in the devices listed in Table1.Work-aroundIn all designs in which F IN is above 315MHz and DIVCLK_DIVIDE is set to 3 or 4, double the CLKFBOUT_MULT_F and DIVCLK_DIVIDE values. See Answer Record 38133 for more information.Block RAMFIFO - First Read after ResetWhen reading from a FIFO after an asynchronous reset or a reset synchronized to WRCLK, the first word read is sometimes incorrect.Work-aroundSynchronize the reset with the RDCLK of the FIFO. See Answer Record 33224.Synchronous Built-in FIFOWhen using the Built-In FIFO as a Synchronous FIFO (EN_SYN=TRUE) with asynchronous reset, correct behavior of the FIFO flags cannot be guaranteed after the first write.All configurations other than EN_SYN=TRUE are not affected by this issue.Work-aroundsTo work around this issue, synchronize the negative edge of reset to RDCLK/WRCLK.For more information and additional work-arounds see Answer Record 41099.Dual Port Block RAM Address Overlap in READ_FIRST and Simple Dual Port ModeWhen using the block RAM in True Dual Port (TDP) Read_First mode, Simple Dual Port (SDP) mode, or ECC mode with different clocks on ports A and B, the user must ensure certain addresses do not occur simultaneously on both ports when both ports are enabled and one port is being written to. Failure to observe this restriction can result in read and/or memory array corruption.The description is found in the Conflict Avoidance section in v1.3.1 (or later) of UG363, Virtex-6 FPGA Memory Resources User Guide.This description was originally added in UG363 (v1.1), published 9/16/09. This errata is being provided to highlight this change and ensure that all users are aware of this design restriction. The ISE v12.1 software and later provides appropriate warnings for possible violations of these restrictions.This issue will not be fixed in the devices listed in Table1.Work-aroundThe recommended work-around is to configure the block RAM in WRITE_FIRST mode. WRITE_FIRST mode is available in block RAMs configured in TDP mode in all ISE software versions. WRITE_FIRST mode is available in block RAMs configured in SDP mode from ISE v12.2 and later. See Answer Record 34859.ConfigurationPROGRAM_B Pin Behavior During Power-OnHolding the PROGRAM_B input statically Low prior to the completion of the power-on reset does not hold the FPGA in configuration reset. Instead, the FPGA proceeds with its standard power-on configuration sequence.This issue will not be fixed in the devices listed in Table1.Work-aroundFor systems that need to delay the FPGA configuration sequence at power-on, hold the INIT_B pin Low.See Answer Record 38134 for more information.Speed Grade Minimum PLL Frequency(MHz)Maximum PLL Frequency(MHz)AVCC-11,2002,700 1.0V ±50mV-2(1)1,2002,700 1.0V ±50mV 1,2003,250 1.025V ±25mVNotes:1.For -2 devices, if one of the transceivers sharing the same AVCC power plane has a PLL frequency greater than 2,700MHz, the AVCCvoltage must be within the range of 1.0 to 1.05V.TXOUTCLK and RXRECCLK Static Operating BehaviorThe TXOUTCLK and RXRECCLK output ports might operate at reduced frequency in buffer bypass mode if conditions (1) and (2) persist for more than 15,000 cumulative hours at 65°C T j,2,500 cumulative hours at 85°C T j,or800 cumulative hours at 100°C T j:1.Power has been applied to V CCINT.2.The device is in one of the following states:a.The FPGA is not configuredb.The FPGA is configured, but the transceiver is uninstantiatedc.The transceiver is instantiated, but no reference clock is togglingd.The transceiver is instantiated, but is held in reset or power-downWork-aroundTransceivers Uninstantiated in User Design but are Planned to be Used in the FutureFor transceivers that are not instantiated in the user design but are planned to be used in the future, power must be applied to MGTAVCC, and the user design must be implemented using ISE v12.1 (or later) software for automatic insertion of the work-around circuit.Transceivers Uninstantiated in User Design but are Not Planned to be Used in the FutureAutomatic insertion of the work-around circuit can be disabled for uninstantiated transceivers that will not be used.Transceivers Instantiated in User DesignTransceivers instantiated in user design do not require a work-around circuit if the reference clock is toggling and the transceiver is not held in reset or power-down.。

XILINX_VIRTEX-5

© 2006–2007 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. All other trade-marks are the property of their respective owners. PowerPC is a trademark of IBM, Inc. All specifications are subject to change without notice.Virtex-5 Electrical CharacteristicsVirtex™-5 FPGAs are available in -3, -2, -1 speed grades, with -3 having the highest performance.Virtex-5 D C and AC characteristics are specified for both commercial and industrial grades. Except the operating temperature range or unless otherwise noted, all the D C and AC electrical parameters are the same for a particular speed grade (that is, the timing characteristics of a -1 speed grade industrial device are the same as for a -1 speed grade commercial device). However, only selected speed grades and/or devices might be available in the industrial range.All supply voltage and junction temperature specifications are representative of worst-case conditions. The parame-ters included are common to popular designs and typical applications.This Virtex-5 data sheet, part of an overall set of documen-tation on the Virtex-5 family of FPGAs, is available on the Xilinx website:•Virtex-5 Family Overview •Virtex-5 User Guide•Virtex-5 Configuration Guide•Virtex-5 XtremeDSP™ Design Considerations •Virtex-5 Packaging and Pinout Specification•Virtex-5 RocketIO™ GTP Transceiver User Guide •Virtex-5 Tri-mode Ethernet MAC User Guide•Virtex-5 Integrated Endpoint Block User Guide for PCI Express® Designs•Virtex-5 System Monitor User Guide •Virtex-5 PCB Designer’s GuideAll specifications are subject to change without notice.Virtex-5 DC CharacteristicsVirtex-5 Data Sheet:DC and Switching CharacteristicsDS202 (v3.6) November 5, 2007Advance Product SpecificationTable 1: Absolute Maximum RatingsSymbolDescriptionUnitsV CCINT Internal supply voltage relative to GND –0.5 to 1.1V V CCAUX Auxiliary supply voltage relative to GND –0.5 to 3.0V V CCO Output drivers supply voltage relative to GND –0.5 to 3.75V V BATT Key memory battery backup supply –0.5 to 4.05V V REF Input reference voltage–0.5 to 3.75V V IN (3)3.3V I/O input voltage relative to GND (4) (user and dedicated I/Os)–0.75 to4.05V 2.5V or below I/O input voltage relative to GND (user and dedicated I/Os)–0.75 to V CCO + 0.5V V TSVoltage applied to 3-state 3.3V output (4) (user and dedicated I/Os)–0.75 to 4.05V Voltage applied to 3-state 2.5V or below output (user and dedicated I/Os)–0.75 to V CCO + 0.5V T STG Storage temperature (ambient)–65 to 150°C T SOL Maximum soldering temperature (2)+220°C T JMaximum junction temperature (2)+125°CNotes:1.Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only, andfunctional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability.2.For soldering guidelines and thermal considerations, see UG195: Virtex-5 Packaging and Pinout Specification on the Xilinx website.3. 3.3V I/O absolute maximum limit applied to DC and AC signals.4.For 3.3V I/O operation, refer to UG190: Virtex-5 User Guide, Chapter 6, 3.3V I/O Design Guidelines .Table 2: Recommended Operating ConditionsSymbol Description Temperature Range Min Max UnitsV CCINT Internal supply voltage relative to GND, T J = 0°C to +85°C Commercial0.95 1.05V Internal supply voltage relative to GND, T J = –40°C to +100°C Industrial0.95 1.05VV CCAUX(1)Auxiliary supply voltage relative to GND, T J = 0°C to +85°C Commercial 2.375 2.625V Auxiliary supply voltage relative to GND, T J = –40°C to +100°C Industrial 2.375 2.625VV CCO(2,4,5)Supply voltage relative to GND, T J = 0°C to +85°C Commercial 1.14 3.45V Supply voltage relative to GND, T J = –40°C to +100°C Industrial 1.14 3.45VV IN 3.3V supply voltage relative to GND, T J = 0°C to +85°C Commercial GND – 0.20 3.45V 3.3V supply voltage relative to GND, T J = –40°C to +100°C Industrial GND – 0.20 3.45V 2.5V and below supply voltage relative to GND,T J = 0°C to +85°CCommercial GND – 0.20V CCO+ 0.2V2.5V and below supply voltage relative to GND,T J = –40°C to +100°CIndustrial GND – 0.20V CCO+ 0.2VI IN Maximum current through any pin in a powered or unpoweredbank when forward biasing the clamp diode.Commercial10mAIndustrial10mAV BA TT(3)Battery voltage relative to GND, T J = 0°C to +85°C Commercial 1.0 3.6V Battery voltage relative to GND, T J = –40°C to +100°C Industrial 1.0 3.6VNotes:1.Recommended maximum voltage drop for V CCAUX is 10 mV/ms.2.Configuration data is retained even if V CCO drops to 0V.3.V BATT is required only when using bitstream encryption. If battery is not used, connect V BATT to either ground or V CCAUX.4.Includes V CCO of 1.2V, 1.5V, 1.8V, 2.5V, and 3.3V.5.The configuration supply voltage V CC_CONFIG is also known as V CCO_0Table 3: DC Characteristics Over Recommended Operating ConditionsSymbol Description Data Rate Min Typ Max Units V DRINT Data retention V CCINT voltage (below which configuration data might be lost)0.75V V DRI Data retention V CCAUX voltage (below which configuration data might be lost) 2.0VI REF V REF leakage current per pin10µAI L Input or output leakage current per pin (sample-tested)10µAC IN Input capacitance (sample-tested)8pFI RPU(1)Pad pull-up (when selected) @ V IN = 0V, V CCO = 3.3V20150µAPad pull-up (when selected) @ V IN = 0V, V CCO = 2.5V1090µAPad pull-up (when selected) @ V IN = 0V, V CCO = 1.8V545µAPad pull-up (when selected) @ V IN = 0V, V CCO = 1.5V330µAPad pull-up (when selected) @ V IN = 0V, V CCO = 1.2V215µAI RPD(1)Pad pull-down (when selected) @ V IN = 2.5V 5110µA I BATT(2)Battery supply current150nAn Temperature diode ideality factor 1.0002n r Series resistance 5.0ΩNotes:1.Typical values are specified at nominal voltage, 25°C.2.Maximum value specified for worst case process at 25°C.Important NoteTypical values for queiscent supply current are now specified at nominal voltage, 85ºC junction temperatures (T j). Xilinx recommends analyzing static power consumption at T j = 85ºC because the majority of designs operate near the high end of the commercial temperature range. D ata sheets for older products (e.g., Virtex-4 devices) still specify typical quiescent supply current at T j = 25ºC. Queiscent supply current is specified by speed grade for Virtex-5 devices. Use the XPOWER™ Estimator (XPE) spreadsheet tool (download at /power) to calculate static power consumption for conditions other than those specified in Table 4.Table 4: Typical Quiescent Supply CurrentSymbol Description DeviceSpeed and Temperature Grade Units -3 (C)-2 (C & I)-1 (C & I)I CCINTQ Quiescent V CCINT supply current XC5VLX30480480300mAXC5VLX30T507507317mAXC5VLX50651651449mAXC5VLX50T689689475mAXC5VLX8510721072883mAXC5VLX85T11151115866mAXC5VLX110139113911109mAXC5VLX110T144814481154mAXC5VLX220N/A27832278mAXC5VLX220T N/A28442328mAXC5VLX330N/A41933432mAXC5VLX330T N/A42673492mAXC5VSX35T720720554mAXC5VSX50T10921092840mAXC5VSX95T N/A19241475mA I CCOQ Quiescent V CCO supply current XC5VLX30 1.5 1.5 1.5mAXC5VLX30T 1.5 1.5 1.5mAXC5VLX50222mAXC5VLX50T222mAXC5VLX85333mAXC5VLX85T333mAXC5VLX110444mAXC5VLX110T444mAXC5VLX220N/A88mAXC5VLX220T N/A88mAXC5VLX330N/A1212mAXC5VLX330T N/A1212mAXC5VSX35T 1.5 1.5 1.5mAXC5VSX50T222mAXC5VSX95T N/A44mAPower-On Power Supply RequirementsXilinx FPGAs require a certain amount of supply current during power-on to insure proper device initialization. The actual current consumed depends on the power-on ramp rate of the power supply.The power supplies can be can be turned on in any sequence, though the specifications shown in Table 5 are for the recommended power-on sequence of V CCINT , V CCAUX , and V CCO . Xilinx does not specify the current for other power-on sequences.Table 5 shows the minimum current required by Virtex-5devices for proper power-on and configuration.If the current minimums shown in Table 5 are met, the device powers on properly after all three supplies have passed through their power-on reset threshold voltages.The FPGA must be configured after V CCINT is applied.Once initialized and configured, use the XPOWER tools to estimate current drain on these supplies.I CCAUXQQuiescent V CCAUX supply currentXC5VLX30383838mA XC5VLX30T 434343mA XC5VLX50575757mA XC5VLX50T 626262mA XC5VLX85939393mA XC5VLX85T 989898mA XC5VLX110125125125mA XC5VLX110T 130130130mA XC5VLX220N/A 229229mA XC5VLX220T N/A 236236mA XC5VLX330N/A 345345mA XC5VLX330T N/A 353353mA XC5VSX35T 494949mA XC5VSX50T 747474mA XC5VSX95TN/A131131mANotes:1.Typical values are specified at nominal voltage, 85°C junction temperatures (T j ). Industrial(I) grade devices have the same typical values ascommercial (C) grade devices at 85°C, but higher values at 100°C. Use the XPE tool to calculate 100°C values.2.Typical values are for blank configured devices with no output current loads, no active input pull-up resistors, all I/O pins are 3-state and floating.3.If DCI or differential signaling is used, more accurate quiescent current estimates can be obtained by using the XPOWER Estimator (XPE) orXPOWER Analyzer (XPA) tools.Table 4: Typical Quiescent Supply Current (Continued)SymbolDescriptionDeviceSpeed and Temperature GradeUnits-3 (C)-2 (C & I)-1 (C & I)Table 5: Power-On Current for Virtex-5 DevicesDevice I CCINTMINI CCAUXMINI CCOMINUnits Typ (1)MaxTyp (1)MaxTyp (1)MaxXC5VLX302357650mA XC5VLX30T 2468650mA XC5VLX5032011450mA XC5VLX50T 33612450mA XC5VLX85492186100mA XC5VLX85T515196100mASelectIO™ DC Input and Output LevelsValues for V IL and V IH are recommended input voltages. Values for I OL and I OH are guaranteed over the recom-mended operating conditions at the V OL and V OH test points. Only selected standards are tested. These are cho-sen to ensure that all standards meet their specifications. The selected standards are tested at a minimum V CCO with the respective V OL and V OH voltage levels shown. Other standards are sample tested.XC5VLX110623250100mA XC5VLX110T 651260100mA XC5VLX2201023458150mA XC5VLX220T 1056472150mA XC5VLX3301470690150mA XC5VLX330T 1509706150mA XC5VSX35T 3079850mA XC5VSX50T 47214850mA XC5VSX95T804262100mANotes:1.Typical values are specified at nominal voltage, 25°C.Table 5: Power-On Current for Virtex-5 Devices (Continued)Device I CCINTMINI CCAUXMINI CCOMINUnits Typ (1)MaxTyp (1)MaxTyp (1)MaxTable 6: Power Supply Ramp TimeSymbol DescriptionRamp Time Units V CCINT Internal supply voltage relative to GND 0.20 to 50.0ms V CCO Output drivers supply voltage relative to GND 0.20 to 50.0ms V CCAUXAuxiliary supply voltage relative to GND0.20 to 50.0msTable 7: SelectIO DC Input and Output Levels I/O StandardV ILV IHV OLV OH I OL I OH V, MinV, MaxV, MinV, MaxV, MaxV, MinmAmALVTTL –0.30.8 2.0 3.450.4 2.4Note(3)Note(3)LVCMOS33, LVDCI33–0.30.8 2.0 3.450.4V CCO – 0.4Note(3)Note(3)LVCMOS25, LVDCI25–0.30.7 1.7V CCO + 0.30.4V CCO – 0.4Note(3)Note(3)LVCMOS18, LVDCI18–0.335% V CCO 65% V CCO V CCO + 0.30.45V CCO – 0.45Note(4)Note(4)LVCMOS15, LVDCI15–0.335% V CCO 65% V CCO V CCO + 0.325% V CCO 75% V CCO Note(4)Note(4)LVCMOS12–0.335% V CCO 65% V CCO V CCO + 0.325% V CCO 75% V CCO Note(6)Note(6)PCI33_3(5)–0.230% V CCO 50% V CCO V CCO 10% V CCO 90% V CCO Note(5)Note(5)PCI66_3(5)–0.230% V CCO 50% V CCO V CCO 10% V CCO 90% V CCO Note(5)Note(5)PCI-X (5)–0.235% V CCO50% V CCOV CCO10% V CCO90% V CCONote(5)Note(5)GTLP –0.3V REF – 0.1V REF + 0.1–0.6N/A 36N/A GTL –0.3V REF – 0.05V REF + 0.05–0.4N/A 32N/A HSTL I_12–0.3V REF – 0.1V REF + 0.1V CCO + 0.325% V CCO75% V CCO 6.3 6.3HSTL I (2)–0.3V REF – 0.1V REF + 0.1V CCO + 0.30.4V CCO – 0.48–8HSTL II (2)–0.3V REF – 0.1V REF + 0.1V CCO + 0.30.4V CCO – 0.416–16HSTL III (2)–0.3V REF – 0.1V REF + 0.1V CCO + 0.30.4V CCO – 0.424–8HSTL IV (2)–0.3V REF – 0.1V REF + 0.1V CCO + 0.30.4V CCO – 0.448–8DIFF HSTL I (2)–0.350% V CCO – 0.150% V CCO + 0.1V CCO + 0.3––––DIFF HSTL II (2)–0.350% V CCO – 0.150% V CCO + 0.1V CCO + 0.3––––SSTL2 I –0.3V REF – 0.15V REF + 0.15V CCO + 0.3V TT – 0.61V TT + 0.618.1–8.1SSTL2 II –0.3V REF – 0.15V REF + 0.15V CCO + 0.3V TT – 0.81V TT + 0.8116.2–16.2DIFF SSTL2 I –0.350% V CCO – 0.1550% V CCO + 0.15V CCO + 0.3––––DIFF SSTL2 II –0.350% V CCO – 0.1550% V CCO + 0.15V CCO + 0.3––––SSTL18 I –0.3V REF – 0.125V REF + 0.125V CCO + 0.3V TT – 0.47V TT + 0.47 6.7–6.7SSTL18 II –0.3V REF – 0.125V REF + 0.125V CCO + 0.3V TT – 0.60V TT + 0.6013.4–13.4DIFF SSTL18 I –0.350% V CCO – 0.12550% V CCO + 0.125V CCO + 0.3––––DIFF SSTL18 II–0.350% V CCO – 0.12550% V CCO + 0.125V CCO + 0.3––––Notes:1.Tested according to relevant specifications.2.Applies to both 1.5V and 1.8V HSTL.ing drive strengths of 2, 4, 6, 8, 12, 16, or 24 mA.ing drive strengths of 2, 4, 6, 8, 12, or 16 mA.5.For more information on PCI33_3, PCI66_3, and PCI-X, refer to refer to UG190: Virtex-5 User Guide, Chapter 6, 3.3V I/O Design Guidelines .6.Supported drive strengths of 2, 4, 6, or 8 mA.Table 7: SelectIO DC Input and Output Levels (Continued)I/O StandardV ILV IHV OLV OH I OL I OH V, MinV, MaxV, MinV, MaxV, MaxV, MinmAmAHT DC Specifications (HT_25)LVDS DC Specifications (LVDS_25)Extended LVDS DC Specifications (LVDSEXT_25)Table 8: HT DC Specifications Symbol DC ParameterConditionsMin Typ Max Units V CCO Supply Voltage2.38 2.5 2.63V V OD Differential Output Voltage R T = 100 Ω across Q and Q signals495600715mV Δ V OD Change in V OD Magnitude –1515mV V OCM Output Common Mode Voltage R T = 100 Ω across Q and Q signals 495600715mV Δ V OCM Change in V OCM Magnitude –1515mV V ID Input Differential Voltage 2006001000mV Δ V ID Change in V ID Magnitude –1515mV V ICM Input Common Mode Voltage 440600780mV Δ V ICMChange in V ICM Magnitude–1515mVTable 9: LVDS DC Specifications Symbol DC ParameterConditionsMin Typ Max Units V CCO Supply Voltage2.382.52.63V V OH Output High Voltage for Q and Q R T = 100 Ω across Q and Q signals 1.675V V OL Output Low Voltage for Q and QR T = 100 Ω across Q and Q signals0.825V V ODIFF Differential Output Voltage (Q – Q), Q = High (Q – Q), Q = High R T = 100 Ω across Q and Q signals 247350600mV V OCM Output Common-Mode Voltage R T = 100 Ω across Q and Q signals1.125 1.250 1.375V V IDIFF Differential Input Voltage (Q – Q), Q = High (Q – Q), Q = High 100350600mV V ICMInput Common-Mode Voltage0.31.22.2VTa ble 10: Extended LVDS DC Specifications Symbol DC ParameterConditionsMin Typ Max Units V CCO Supply Voltage2.382.5 2.63V V OH Output High Voltage for Q and Q R T = 100 Ω across Q and Q signals – 1.785V V OL Output Low Voltage for Q and QR T = 100 Ω across Q and Q signals0.715––V V ODIFF Differential Output Voltage (Q – Q), Q = High (Q – Q), Q = High R T = 100 Ω across Q and Q signals 350–820mV V OCM Output Common-Mode Voltage R T = 100 Ω across Q and Q signals 1.125 1.250 1.375V V IDIFF Differential Input Voltage (Q – Q), Q = High (Q – Q), Q = High Common-mode input voltage = 1.25V 100–1000mV V ICMInput Common-Mode VoltageDifferential input voltage = ±350 mV0.31.22.2VLVPECL DC Specifications (LVPECL_25)These values are valid when driving a 100Ω differential load only, i.e., a 100Ω resistor between the two receiver pins. The V OH levels are 200 mV below standard LVPECL levels and are compatible with devices tolerant of lower com-mon-mode ranges. Table 11 summarizes the D C output specifications of LVPECL. For more information on using LVPECL, see UG190: Virtex-5 User Guide, Cha pter 6, SelectIO Resources.Ta ble 11: LVPECL DC SpecificationsSymbol DC Parameter Min Typ Max Units V OH Output High Voltage V CC – 1.025 1.545V CC – 0.88V V OL Output Low Voltage V CC – 1.810.795V CC – 1.62V V ICM Input Common-Mode Voltage0.6 2.2V V IDIFF Differential Input Voltage(1,2)0.100 1.5V Notes:1.Recommended input maximum voltage not to exceed V CCAUX + 0.2V.2.Recommended input minimum voltage not to go below –0.5V.RocketIO GTP Transceiver SpecificationsRocketIO GTP Transceiver DC CharacteristicsTa ble 12: Absolute Maximum RatingsSymbol Description Units MGTAVCCPLL Analog supply voltage for the GTP_DUAL shared PLL relative to GND–0.5 to 1.32V MGTAVTTTX Analog supply voltage for the GTP_DUAL transmitters relative to GND–0.5 to 1.32V MGT AVTTRX Analog supply voltage for the GTP_DUAL receivers relative to GND–0.5 to 1.32V MGTAVCC Analog supply voltage for the GTP_DUAL common circuits relative to GND–0.5 to 1.32V–0.5 to 1.32V MGT AVTTRXC Analog supply voltage for the resistor calibration circuit of the GTP_DUALcolumnNotes:1.Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only, andfunctional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability.Ta ble 13: Recommended Operating Conditions(1)(2)Symbol Description Min Max Units MGT AVCCPLL(1)Analog supply voltage for the GTP_DUAL shared PLL relative to GND 1.14 1.26V MGT AVTTTX(1)Analog supply voltage for the GTP_DUAL transmitters relative to GND 1.14 1.26V MGTAVTTRX(1)Analog supply voltage for the GTP_DUAL receivers relative to GND 1.14 1.26V MGT AVCC(1)Analog supply voltage for the GTP_DUAL common circuits relative to GND0.95 1.05V1.14 1.26V MGTAVTTRXC(1)Analog supply voltage for the resistor calibration circuit of the GTP_DUALcolumnNotes:1.Each voltage listed requires the filter circuit described in UG196: Virtex-5 RocketIO GTP T ransceiver User Guide.2.Voltages are specified for the temperature range of T J = –40°C to +100°C.Ta ble 14: DC Characteristics Over Recommended Operating Conditions(2)Symbol Description Min Typ Max UnitsI MGTAVTTTX GTP_DUAL tile transmitter termination supply current(3)7190mAI MGTAVCCPLL GTP_DUAL tile shared PLL supply current3660mAI MGTAVTTRXC GTP_DUAL tile resistor termination calibration supply current0.10.5mAI MGTAVTTRX GTP_DUAL tile receiver termination supply current(3)0.10.5mAI MGTAVCC GTP_DUAL tile internal analog supply current56110mAR REF Precision reference resistor for internal calibration termination49.55050.5ΩNotes:1.Typical values are specified at nominal voltage, 25°C, with a 3.2 Gb/s line rate.2.I CC numbers are given per GTP_DUAL tile with both GTP devices operating with default settings.3.AC coupled TX/RX link.Ta ble 15: Quiescent Supply CurrentSymbol Description Device Typ(1)Max UnitsI CCINTQ Quiescent internal supply current XC5VLX30T mAXC5VLX50T mAXC5VLX85T mAXC5VLX110T mAXC5VLX220T mAXC5VLX330T mAXC5VSX35T mAXC5VSX50T mAXC5VSX95T mAI VTTTXQ Quiescent transmitter supply current XC5VLX30T mAXC5VLX50T mAXC5VLX85T mAXC5VLX110T mAXC5VLX220T mAXC5VLX330T mAXC5VSX35T mAXC5VSX50T mAXC5VSX95T mA I AVCCPLLQ Quiescent GTP_DUAL PLL supply current XC5VLX30T mAXC5VLX50T mAXC5VLX85T mAXC5VLX110T mAXC5VLX220T mAXC5VLX330T mAXC5VSX35T mAXC5VSX50T mAXC5VSX95T mAI VTTRXCQ Quiescent receiver termination switching supply current XC5VLX30T mAXC5VLX50T mAXC5VLX85T mAXC5VLX110T mAXC5VLX220T mAXC5VLX330T mAXC5VSX35T mAXC5VSX50T mAXC5VSX95T mATa ble 15: Quiescent Supply Current (Continued)Symbol Description Device Typ(1)Max UnitsI TTRXQ Quiescent receiver termination supply current XC5VLX30T mAXC5VLX50T mAXC5VLX85T mAXC5VLX110T mAXC5VLX220T mAXC5VLX330T mAXC5VSX35T mAXC5VSX50T mAXC5VSX95T mAI VCCQ Quiescent internal analog supply current XC5VLX30T mAXC5VLX50T mAXC5VLX85T mAXC5VLX110T mAXC5VLX220T mAXC5VLX330T mAXC5VSX35T mAXC5VSX50T mAXC5VSX95T mA Notes:1.Typical values are specified at nominal voltage, 25°C.2.Given for entire die. Powered and unconfigured.3.Unconnected (if channel is driven to voltage).4.More accurate quiescent current estimates can be obtained by using the XPOWER Estimator (XPE) or XPOWER Analyzer (XPA) tools.RocketIO GTP Transceiver DC Input and Output LevelsTable 16 summarizes the D C output specifications of the Virtex-5 RocketIO GTP Transceivers. Figure 1 shows the single-ended output voltage swing. Figure 2 shows the peak-to-peak differential output voltage. Consult UG196: Virtex-5 RocketIO GTP T ransceiver User Guide for further details.Ta ble 16: GTP Transceiver DC SpecificationsSymbolDC ParameterConditionsMinTyp MaxUnitsDV PPIN Differential peak-to-peak inputvoltageExternal AC coupled ≤ 3.2 Gb/s 1502000mV External AC coupled > 3.2 Gb/s 1802000mV V IN Absolute input voltage DC coupledMGT AVTTRX = 1.2V –4001200mV V CMIN Common mode input voltage DC coupledMGT AVTTRX = 1.2V 800mV DV PPOUT Differential peak-to-peak output voltage (1)TXBUFDIFFCTRL = 000, TX_DIFF_BOOST = ON 1400mV V SEOUT Single-ended output voltage swing (1)TXBUFDIFFCTRL = 000, TX_DIFF_BOOST = ON700mV V CMOUT Common mode output voltage Equation basedMGT AVTTTX = 1.2V 1200 – Amplitude/2mVR IN Differential input resistance 90100120ΩR OUT Differential output resistance 90100120ΩT OSKEW T ransmitter output skew15ps C EXTRecommended external AC coupling capacitor (2)75100200nFNotes:1.The output swing and preemphasis levels are programmable using the attributes discussed in UG196:Virtex-5 RocketIO GTP Transceiver UserGuide and can result in values lower than reported in this table.2.Values outside of this range can be used as appropriate to conform to specific protocols and standards.Figure 1: Single-Ended Output Voltage SwingFigure 2: Peak-to-Peak Differential Output VoltageTable 17 summarizes the DC input specifications of the Virtex-5 RocketIO GTP Transceivers. Figure 3 shows the single-ended input voltage swing. Figure 4 shows thepeak-to-peak differential clock input voltage swing. Consult UG196: Virtex-5 RocketIO GTP Transceiver User Guide for further details.Ta ble 17: RocketIO GTP Clock DC Input Level Specification (1)SymbolDC ParameterConditions MinTypMaxUnitsDV PPIN Differential peak-to-peak input voltage2008002000mV V SEIN Single-ended input voltage 1004001000mVR IN Differential input resistance80105130ΩCEXTRequired external AC coupling capacitor75100200nFNotes:1.V MIN = 0V and V MAX = 1200mVFigure 3: Single-Ended Clock Input Voltage Swing Peak-to-PeakFigure 4: Differential Clock Input Voltage Swing Peak-to-PeakRocketIO GTP Switching CharacteristicsConsult UG196:Virtex-5 RocketIO GTP Transceiver User Guide for further information. Ta ble 18: GTP Transceiver PerformanceSymbol DescriptionSpeed GradeUnits -3-2-1F GTPMAX Maximum GTP transceiver data rate 3.75 3.75 3.2Gb/s F GPLLMAX Maximum PLL frequency 2.0 2.0 2.0GHz F GPLLMIN Minimum PLL frequency 1.0 1.0 1.0GHzTa ble 19: CRC Block Switching CharacteristicsSymbol DescriptionSpeed GradeUnits -3-2-1F CRC CRCCLK maximum frequency320320250MHzTa ble 20: GTP Transceiver Reference Clock Switching CharacteristicsAll Speed GradesUnits Symbol Description Conditions Min Typ MaxF GCLK Reference clock frequency range(1)CLK60350MHzT RCLK Reference clock rise time20% – 80%200400ps T FCLK Reference clock fall time80% – 20%200400ps T DCREF Reference clock duty cycle CLK455055% T GJTT Reference clock total jitter, peak-peak(2)CLK40ps T LOCK Clock recovery frequency acquisitiontimeInitial PLL lock1msT PHASE Clock recovery phase acquisition time Lock to data after PLL hasrelocked to the reference clock.Includes lock to reference time.200µsNotes:1.The clock from the GTP_DUAL differential clock pin pair can be used for all serial bit rates. GREFCLK can be used for serial bit rates up to 1 Gb/s.2.Measured at the package pin.Figure 5: Reference Clock Timing ParametersTa ble 21: GTP User Clock Switching Characteristics(1)Speed GradeUnits Symbol Description Conditions-3-2-1F TXOUT TXOUTCLK maximum frequency375375320MHz F RXREC RXRECCLK maximum frequency375375320MHzT RX RXUSRCLK maximum frequency375375320MHzT RX2RXUSRCLK2 maximum frequency RXDA TAWIDTH = 0350350320MHz RXDA TAWIDTH = 1187.5187.5160MHzT TX TXUSRCLK maximum frequency375375320MHzT TX2TXUSRCLK2 maximum frequency TXDA T AWIDTH = 0350350320MHz TXDA T AWIDTH = 1187.5187.5160MHzNotes:1.Clocking must be implemented as described in UG196: Virtex-5 RocketIO GTP T ransceiver User GuideTa ble 22: GTP Transmitter Switching CharacteristicsSymbol Description Min Typ Max UnitsF GTX Serial data rate range0.1F GTPMAX Gb/sT RTX TX Rise time140ps T FTX TX Fall time120ps T LLSKEW TX lane-to-lane skew(1) 2 + 500 ps UI V TXOOBVDPP Electrical idle amplitude20mV T TXOOBTRANS Electrical idle transition time40ns T J3.75T otal Jitter(2) 3.75 Gb/s0.35UID J3.75Deterministic Jitter(2)0.19UIT J3.2T otal Jitter(2) 3.20 Gb/s0.35UID J3.2Deterministic Jitter(2)0.19UIT J2.5T otal Jitter(2) 2.50 Gb/s0.30UID J2.5Deterministic Jitter(2)0.14UIT J2.0T otal Jitter(2) 2.00 Gb/s0.30UID J2.0Deterministic Jitter(2)0.14UIT J1.25T otal Jitter(2) 1.25 Gb/s0.20UID J1.25Deterministic Jitter(2)0.10UIT J1.00T otal Jitter(2) 1.00 Gb/s0.20UID J1.00Deterministic Jitter(2)0.10UIT J500T otal Jitter(2)500 Mb/s0.10UID J500Deterministic Jitter(2)0.04UIT J100T otal Jitter(2)100 Mb/s0.02UID J100Deterministic Jitter(2)0.01UI Notes:ing same REFCLK input with TXENPMAPHASEALIGN enabled for up to four consecutive GTP_DUAL sites.ing PLL_DIVSEL_FB = 2, INTDATAWIDTH = 1.3.All jitter values are based on a Bit-Error Ratio of 1e–12.Ethernet MAC Switching CharacteristicsConsult UG194:Virtex-5 T ri-mode Ethernet Media Access Controller User Guide for further information.Ta ble 23: GTP Receiver Switching CharacteristicsSymbolDescriptionMin Typ Max Units F GRX Serial data rate RX oversampler not enabled 0.5F GTPMAXGb/s RX oversampler enabled0.10.5Gb/s R XOOBVDPP OOB detect threshold peak-to-peakOOBDETECT_THRESHOLD = 10060105165mV R XSST Receiver spread-spectrum tracking (1)Modulated @ 33 KHz–50000ppm R XRL Run length (CID)Internal AC capacitor bypassed 150UI R XPPMTOLData/REFCLK PPM offset toleranceACDR 2nd -order loop enabled–10001000ppmSJ Jitter ToleranceJT_SJ 3.75Sinusoidal Jitter (2) 3.75 Gb/s 0.30UI JT_SJ 3.2Sinusoidal Jitter (2) 3.20 Gb/s 0.40UI JT_SJ 2.50Sinusoidal Jitter (2) 2.50 Gb/s 0.40UI JT_SJ 2.00Sinusoidal Jitter (2) 2.00 Gb/s 0.40UI JT_SJ 1.00Sinusoidal Jitter (2) 1.00 Gb/s 0.30UI JT_SJ 500Sinusoidal Jitter (2)500 Mb/s 0.30UI JT_SJ 500Sinusoidal Jitter (2)500 Mb/s OS 0.30UI JT_SJ 100Sinusoidal Jitter (2)100 Mb/s OS0.30UISJ Jitter Tolerance with Stressed EyeJT_TJSE 3.2T otal Jitter with Stressed Eye (3)3.20 Gb/s 0.87UI JT_SJSE 3.2Sinusoidal Jitter with Stressed Eye (3)3.20 Gb/s0.30UINotes:ing PLL_RX_DIVSEL_OUT = 1.ing 80 MHz sinusoidal jitter only in the absence of deterministic and random jitter.3.Stimulus signal includes 0.4UI of DJ and 0.17UI of RJ. RX equalizer is enabled.4.All jitter values are based on a Bit Error Ratio of 1e –12.Ta ble 24: Maximum Ethernet MAC PerformanceDescriptionSpeed GradeUnits-3-2-1Ethernet MAC Maximum Performance10/100/1000Mb/s。

Xilinx FPGA 内部结构深入分析

Xilinx FPGA 内部结构深入分析作者：fpga001。

论坛：芯片动力（SocVista）。

网页地址：/bbs/viewthread.php?tid=3443&extra=page%3D2&page=7发表时间：2009.12IOB的结构请大家看到手册的第1页，这是IOB的review部分。

IO block 是高手的领地，一般接触FPGA第一年都不会太关心到这个部分。

注意看，IOB有三个数据通道：输入、输出、三态控制。

每个通道都有一对存储器件，他们可以当做寄存器或者锁存起来使用，视乎你的设置。

输入通道有可编程的延迟模块，可以确保hold time为零。

（这是在什么场合使用？请达人补充！）另外可以看到输入输出通道都有完备的DDR支持，这个在后面可以看到。

所有图都请参考PDF原文，这里就不再粘贴了。

可编程输入延迟看到手册第3页，这个像两根鱼骨似的构造就是输入延迟了。

输入延迟一共16节，每节250ps，所以总共的延迟在0~4ns之间。

这个鱼骨的构造非常巧妙，前面8节直接级联，只有一个输出。

这样8节以内的调整就跳过这根长鱼骨；而超过8节的调整就直接利用第一根鱼骨，然后在后面的8节中进行微调。

调整的输出分别供给IOB中的异步和同步单元，异步就是直接穿过IOB，同步则是经由存储单元流出IOB。

异步单元精度较高，可以单节调整，所以精度为250ps；同步单元精度稍低，两个节为单位调整，所以精度只有500ps。

上述内容看图便知可编程输入延迟的设置输入延迟的设置只能在Image配置的时候建立，在设备工作期间无法改变。

我想有两种方法可以改变输入延迟的设置：1. 通过延迟原语在代码中设置；2. 通过FPGA editor在P&R完成后在ngc文件中修改。

存储单元存储单元可以配置为D触发器，就是我们常说的FF，Xilinx称之为FD；也可以配置为锁存器，Xilinx称之为LD。

输出和三态通路各有一对寄存器外加一个MUX。

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