半导体制造技术-第十四章
半导体制造技术第十四章PPT课件
光学增强技术
• 相移掩膜技术 • 光学临近修正 • 离轴照明
对准
• 对准就是确定硅片上图形的位置、方向和图形转 换的过程。
• 对准过程的结果，或者每个连续的图形与先前层 匹配的精度，被称做套准。
• 套准精度是测量对准系统把版图套准到硅片上图 形的能力。套准容差描述要形成的图形层和前层 的最大相对位移。一般套准容差是关键尺寸的三 分之一。
环境条件
• 温度 • 湿度 • 振动 • 大气压力 • 颗粒沾污
对准和曝光的质量测量
• 聚焦-曝光剂量 • 光强 • 掩膜板对准 • 图形分辨率 • 投影掩膜板的质量
写在最后
经常不断地学习,你就什么都知道。你知道得越多,你就越有力量 Study Constantly, And You Will Know Everything. The More
You Know, The More Powerful You Will Be
谢大家
荣幸这一路，与你同行
It'S An Honor To Walk With You All The Way
演讲人：XXXXXX 时 间：XX年XX月XX日
• 可以通过增加镜头半径来增加数值孔径并俘获更 多的衍射光，但是这样的光学系统更加复杂更加 昂贵。
抗反射涂层使用的原因
• 光刻胶的下面是最终要被刻蚀形成图案的底层薄 膜。如果这个底层是反光的，那么光线将从这个 膜层反射并有可能损害临近的光刻胶。这个损害 能够对线宽控制产生不利的影响。
• 两种最主要的光反射问题是反射切口和驻波。
分辨率
• 光刻中，分辨率被定义为清晰分辨出硅片上间隔 很近的特征图形对的能力。分辨率对于任何光学 系统都是一个重要的参数。
半导体制造技术
Semiconductor Manufacturing Technology半导体制造技术Instructor’s ManualMichael QuirkJulian SerdaCopyright Prentice HallTable of Contents目录OverviewI. Chapter1. Semiconductor industry overview2. Semiconductor materials3. Device technologies—IC families4. Silicon and wafer preparation5. Chemicals in the industry6. Contamination control7. Process metrology8. Process gas controls9. IC fabrication overview10. Oxidation11. Deposition12. Metallization13. Photoresist14. Exposure15. Develop16. Etch17. Ion implant18. Polish19. Test20. Assembly and packagingII. Answers to End-of-Chapter Review QuestionsIII. Test Bank (supplied on diskette)IV. Chapter illustrations, tables, bulleted lists and major topics (supplied on CD-ROM)Notes to Instructors:1)The chapter overview provides a concise summary of the main topics in each chapter.2)The correct answer for each test bank question is highlighted in bold. Test bankquestions are based on the end-of-chapter questions. If a student studies the end-of-chapter questions (which are linked to the italicized words in each chapter), then they will be successful on the test bank questions.2Chapter 1Introduction to the Semiconductor Industry Die:管芯 defective:有缺陷的Development of an Industry•The roots of the electronic industry are based on the vacuum tube and early use of silicon for signal transmission prior to World War II. The first electronic computer, the ENIAC, wasdeveloped at the University of Pennsylvania during World War II.•William Shockley, John Bardeen and Walter Brattain invented the solid-state transistor at Bell Telephone Laboratories on December 16, 1947. The semiconductor industry grew rapidly in the 1950s to commercialize the new transistor technology, with many early pioneers working inSilicon Valley in Northern California.Circuit Integration•The first integrated circuit, or IC, was independently co-invented by Jack Kilby at Texas Instruments and Robert Noyce at Fairchild Semiconductor in 1959. An IC integrates multiple electronic components on one substrate of silicon.•Circuit integration eras are: small scale integration (SSI) with 2 - 50 components, medium scale integration (MSI) with 50 – 5k components, large scale integration (LSI) with 5k to 100kcomponents, very large scale integration (VLSI) with 100k to 1M components, and ultra large scale integration (ULSI) with > 1M components.1IC Fabrication•Chips (or die) are fabricated on a thin slice of silicon, known as a wafer (or substrate). Wafers are fabricated in a facility known as a wafer fab, or simply fab.•The five stages of IC fabrication are:Wafer preparation: silicon is purified and prepared into wafers.Wafer fabrication: microchips are fabricated in a wafer fab by either a merchant chip supplier, captive chip producer, fabless company or foundry.Wafer test: Each individual die is probed and electrically tested to sort for good or bad chips.Assembly and packaging: Each individual die is assembled into its electronic package.Final test: Each packaged IC undergoes final electrical test.•Key semiconductor trends are:Increase in chip performance through reduced critical dimensions (CD), more components per chip (Moore’s law, which predicts the doubling of components every 18-24 months) andreduced power consumption.Increase in chip reliability during usage.Reduction in chip price, with an estimated price reduction of 100 million times for the 50 years prior to 1996.The Electronic Era•The 1950s saw the development of many different types of transistor technology, and lead to the development of the silicon age.•The 1960s were an era of process development to begin the integration of ICs, with many new chip-manufacturing companies.•The 1970s were the era of medium-scale integration and saw increased competition in the industry, the development of the microprocessor and the development of equipment technology. •The 1980s introduced automation into the wafer fab and improvements in manufacturing efficiency and product quality.•The 1990s were the ULSI integration era with the volume production of a wide range of ICs with sub-micron geometries.Career paths•There are a wide range of career paths in semiconductor manufacturing, including technician, engineer and management.2Chapter 2 Characteristics of Semiconductor MaterialsAtomic Structure•The atomic model has three types of particles: neutral neutrons（不带电的中子）, positively charged protons（带正电的质子）in the nucleus and negatively charged electrons（带负电的核外电子） that orbit the nucleus. Outermost electrons are in the valence shell, and influence the chemical and physical properties of the atom. Ions form when an atom gains or loses one or more electrons.The Periodic Table•The periodic table lists all known elements. The group number of the periodic table represents the number of valence shell electrons of the element. We are primarily concerned with group numbers IA through VIIIA.•Ionic bonds are formed when valence shell electrons are transferred from the atoms of one element to another. Unstable atoms (e.g., group VIIIA atoms because they lack one electron) easily form ionic bonds.•Covalent bonds have atoms of different elements that share valence shell electrons.3Classifying Materials•There are three difference classes of materials:ConductorsInsulatorsSemiconductors•Conductor materials have low resistance to current flow, such as copper. Insulators have high resistance to current flow. Capacitance is the storage of electrical charge on two conductive plates separated by a dielectric material. The quality of the insulation material between the plates is the dielectric constant. Semiconductor materials can function as either a conductor or insulator.Silicon•Silicon is an elemental semiconductor material because of four valence shell electrons. It occurs in nature as silica and is refined and purified to make wafers.•Pure silicon is intrinsic silicon. The silicon atoms bond together in covalent bonds, which defines many of silicon’s properties. Silicon atoms bond together in set, repeatable patterns, referred to asa crystal.•Germanium was the first semiconductor material used to make chips, but it was soon replaced by silicon. The reasons for this change are:Abundance of siliconHigher melting temperature for wider processing rangeWide temperature range during semiconductor usageNatural growth of silicon dioxide•Silicon dioxide (SiO2) is a high quality, stable electrical insulator material that also serves as a good chemical barrier to protect silicon from external contaminants. The ability to grow stable, thin SiO2 is fundamental to the fabrication of Metal-Oxide-Semiconductor (MOS) devices. •Doping increases silicon conductivity by adding small amounts of other elements. Common dopant elements are from trivalent, p-type Group IIIA (boron) and pentavalent, n-type Group VA (phosphorus, arsenic and antimony).•It is the junction between the n-type and p-type doped regions (referred to as a pn junction) that permit silicon to function as a semiconductor.4Alternative Semiconductor Materials•The alternative semiconductor materials are primarily the compound semiconductors. They are formed from Group IIIA and Group VA (referred to as III-V compounds). An example is gallium arsenide (GaAs).•Some alternative semiconductors come from Group IIA and VIA, referred to as II-VI compounds. •GaAs is the most common III-V compound semiconductor material. GaAs ICs have greater electron mobility, and therefore are faster than ICs made with silicon. GaAs ICs also have higher radiation hardness than silicon, which is better for space and military applications. The primary disadvantage of GaAs is the lack of a natural oxide.5Chapter 3Device TechnologiesCircuit Types•There are two basic types of circuits: analog and digital. Analog circuits have electrical data that varies continuously over a range of voltage, current and power values. Digital circuits have operating signals that vary about two distinct voltage levels – a high and a low.Passive Component Structures•Passive components such as resistors and capacitors conduct electrical current regardless of how the component is connected. IC resistors are a passive component. They can have unwanted resistance known as parasitic resistance. IC capacitor structures can also have unintentional capacitanceActive Component Structures•Active components, such as diodes and transistors can be used to control the direction of current flow. PN junction diodes are formed when there is a region of n-type semiconductor adjacent to a region of p-type semiconductor. A difference in charge at the pn junction creates a depletion region that results in a barrier voltage that must be overcome before a diode can be operated. A bias voltage can be configured to have a reverse bias, with little or no conduction through the diode, or with a forward bias, which permits current flow.•The bipolar junction transistor (BJT) has three electrodes and two pn junctions. A BJT is configured as an npn or pnp transistor and biased for conduction mode. It is a current-amplifying device.6• A schottky diode is formed when metal is brought in contact with a lightly doped n-type semiconductor material. This diode is used in faster and more power efficient BJT circuits.•The field-effect transistor (FET), a voltage-amplifying device, is more compact and power efficient than BJT devices. A thin gate oxide located between the other two electrodes of the transistor insulates the gate on the MOSFET. There are two categories of MOSFETs, nMOS (n-channel) and pMOS (p-channel), each which is defined by its majority current carriers. There is a biasing scheme for operating each type of MOSFET in conduction mode.•For many years, nMOS transistors have been the choice of most IC manufacturers. CMOS, with both nMOS and pMOS transistors in the same IC, has been the most popular device technology since the early 1980s.•BiCMOS technology makes use of the best features of both CMOS and bipolar technology in the same IC device.•Another way to categorize FETs is in terms of enhancement mode and depletion mode. The major different is in the way the channels are doped: enhancement-mode channels are doped opposite in polarity to the source and drain regions, whereas depletion mode channels are doped the same as their respective source and drain regions.Latchup in CMOS Devices•Parasitic transistors can create a latchup condition(???????) in CMOS ICs that causes transistors to unintentionally（无心的） turn on. To control latchup, an epitaxial layer is grown on the wafer surface and an isolation barrier（隔离阻障）is placed between the transistors. An isolation layer can also be buried deep below the transistors.Integrated Circuit Productsz There are a wide range of semiconductor ICs found in electrical and electronic products. This includes the linear IC family, which operates primarily with anal3og circuit applications, and the digital IC family, which includes devices that operate with binary bits of data signals.7Chapter 4Silicon and Wafer Preparation8z Semiconductor-Grade Silicon•The highly refined silicon used for wafer fabrication is termed semiconductor-grade silicon (SGS), and sometimes referred to as electronic-grade silicon. The ultra-high purity of semiconductor-grade silicon is obtained from a multi-step process referred to as the Siemens process.Crystal Structure• A crystal is a solid material with an ordered, 3-dimensional pattern over a long range. This is different from an amorphous material that lacks a repetitive structure.•The unit cell is the most fundamental entity for the long-range order found in crystals. The silicon unit cell is a face-centered cubic diamond structure. Unit cells can be organized in a non-regular arrangement, known as a polycrystal. A monocrystal are neatly arranged unit cells.Crystal Orientation•The orientation of unit cells in a crystal is described by a set of numbers known as Miller indices.The most common crystal planes on a wafer are (100), (110), and (111). Wafers with a (100) crystal plane orientation are most common for MOS devices, whereas (111) is most common for bipolar devices.Monocrystal Silicon Growth•Silicon monocrystal ingots are grown with the Czochralski (CZ) method to achieve the correct crystal orientation and doping. A CZ crystal puller is used to grow the silicon ingots. Chunks of silicon are heated in a crucible in the furnace of the puller, while a perfect silicon crystal seed is used to start the new crystal structure.• A pull process serves to precisely replicate the seed structure. The main parameters during the ingot growth are pull rate and crystal rotation. More homogeneous crystals are achieved with a magnetic field around the silicon melt, known as magnetic CZ.•Dopant material is added to the melt to dope the silicon ingot to the desired electrical resistivity.Impurities are controlled during ingot growth. A float-zone crystal growth method is used toachieve high-purity silicon with lower oxygen content.•Large-diameter ingots are grown today, with a transition underway to produce 300-mm ingot diameters. There are cost benefits for larger diameter wafers, including more die produced on a single wafer.Crystal Defects in Silicon•Crystal defects are interruptions in the repetitive nature of the unit cell. Defect density is the number of defects per square centimeter of wafer surface.•Three general types of crystal defects are: 1) point defects, 2) dislocations, and 3) gross defects.Point defects are vacancies (or voids), interstitial (an atom located in a void) and Frenkel defects, where an atom leaves its lattice site and positions itself in a void. A form of dislocation is astacking fault, which is due to layer stacking errors. Oxygen-induced stacking faults are induced following thermal oxidation. Gross defects are related to the crystal structure (often occurring during crystal growth).Wafer Preparation•The cylindrical, single-crystal ingot undergoes a series of process steps to create wafers, including machining operations, chemical operations, surface polishing and quality checks.•The first wafer preparation steps are the shaping operations: end removal, diameter grinding, and wafer flat or notch. Once these are complete, the ingot undergoes wafer slicing, followed by wafer lapping to remove mechanical damage and an edge contour. Wafer etching is done to chemically remove damage and contamination, followed by polishing. The final steps are cleaning, wafer evaluation and packaging.Quality Measures•Wafer suppliers must produce wafers to stringent quality requirements, including: Physical dimensions: actual dimensions of the wafer (e.g., thickness, etc.).Flatness: linear thickness variation across the wafer.Microroughness: peaks and valleys found on the wafer surface.Oxygen content: excessive oxygen can affect mechanical and electrical properties.Crystal defects: must be minimized for optimum wafer quality.Particles: controlled to minimize yield loss during wafer fabrication.Bulk resistivity(电阻系数): uniform resistivity from doping during crystal growth is critical. Epitaxial Layer•An epitaxial layer (or epi layer) is grown on the wafer surface to achieve the same single crystal structure of the wafer with control over doping type of the epi layer. Epitaxy minimizes latch-up problems as device geometries continue to shrink.Chapter 5Chemicals in Semiconductor FabricationEquipment Service Chase Production BayChemical Supply Room Chemical Distribution Center Holding tank Chemical drumsProcess equipmentControl unit Pump Filter Raised and perforated floorElectronic control cablesSupply air ductDual-wall piping for leak confinement PumpFilterChemical control and leak detection Valve boxes for leak containment Exhaust air ductStates of Matter• Matter in the universe exists in 3 basic states (宇宙万物存在着三种基本形态): solid, liquid andgas. A fourth state is plasma.Properties of Materials• Material properties are the physical and chemical characteristics that describe its unique identity.• Different properties for chemicals in semiconductor manufacturing are: temperature, pressure andvacuum, condensation, vapor pressure, sublimation and deposition, density, surface tension, thermal expansion and stress.Temperature is a measure of how hot or cold a substance is relative to another substance. Pressure is the force exerted per unit area. Vacuum is the removal of gas molecules.Condensation is the process of changing a gas into a liquid. Vaporization is changing a liquidinto a gas.Vapor pressure is the pressure exerted by a vapor in a closed container at equilibrium.Sublimation is the process of changing a solid directly into a gas. Deposition is changing a gas into a solid.Density is the mass of a substance divided by its volume.Surface tension of a liquid is the energy required to increase the surface area of contact.Thermal expansion is the increase in an object’s dimension due to heating.Stress occurs when an object is exposed to a force.Process Chemicals•Semiconductor manufacturing requires extensive chemicals.• A chemical solution is a chemical mixture. The solvent is the component of the solution present in larger amount. The dissolved substances are the solutes.•Acids are solutions that contain hydrogen and dissociate in water to yield hydronium ions. A base is a substance that contains the OH chemical group and dissociates in water to yield the hydroxide ion, OH-.•The pH scale is used to assess the strength of a solution as an acid or base. The pH scale varies from 0 to 14, with 7 being the neutral point. Acids have pH below 7 and bases have pH values above 7.• A solvent is a substance capable of dissolving another substance to form a solution.• A bulk chemical distribution (BCD) system is often used to deliver liquid chemicals to the process tools. Some chemicals are not suitable for BCD and instead use point-of-use (POU) delivery, which means they are stored and used at the process station.•Gases are generally categorized as bulk gases or specialty gases. Bulk gases are the relatively simple gases to manufacture and are traditionally oxygen, nitrogen, hydrogen, helium and argon.The specialty gases, or process gases, are other important gases used in a wafer fab, and usually supplied in low volume.•Specialty gases are usually transported to the fab in metal cylinders.•The local gas distribution system requires a gas purge to flush out undesirable residual gas. Gas delivery systems have special piping and connections systems. A gas stick controls the incoming gas at the process tool.•Specialty gases may be classified as hydrides, fluorinated compounds or acid gases.Chapter 6Contamination Control in Wafer FabsIntroduction•Modern semiconductor manufacturing is performed in a cleanroom, isolated from the outside environment and contaminants.Types of contamination•Cleanroom contamination has five categories: particles, metallic impurities, organic contamination, native oxides and electrostatic discharge. Killer defects are those causes of failure where the chip fails during electrical test.Particles: objects that adhere to a wafer surface and cause yield loss. A particle is a killer defect if it is greater than one-half the minimum device feature size.Metallic impurities: the alkali metals found in common chemicals. Metallic ions are highly mobile and referred to as mobile ionic contaminants (MICs).Organic contamination: contains carbon, such as lubricants and bacteria.Native oxides: thin layer of oxide growth on the wafer surface due to exposure to air.Electrostatic discharge (ESD): uncontrolled transfer of static charge that can damage the microchip.Sources and Control of Contamination•The sources of contamination in a wafer fab are: air, humans, facility, water, process chemicals, process gases and production equipment.Air: class number designates the air quality inside a cleanroom by defining the particle size and density.Humans: a human is a particle generator. Humans wear a cleanroom garment and follow cleanroom protocol to minimize contamination.Facility: the layout is generally done as a ballroom (open space) or bay and chase design.Laminar airflow with air filtering is used to minimize particles. Electrostatic discharge iscontrolled by static-dissipative materials, grounding and air ionization.Ultrapure deiniozed (DI) water: Unacceptable contaminants are removed from DI water through filtration to maintain a resistivity of 18 megohm-cm. The zeta potential represents a charge on fine particles in water, which are trapped by a special filter. UV lamps are used for bacterial sterilization.Process chemicals: filtered to be free of contamination, either by particle filtration, microfiltration (membrane filter), ultrafiltration and reverse osmosis (or hyperfiltration).Process gases: filtered to achieve ultraclean gas.Production equipment: a significant source of particles in a fab.Workstation design: a common layout is bulkhead equipment, where the major equipment is located behind the production bay in the service chase. Wafer handling is done with robotic wafer handlers. A minienvironment is a localized environment where wafers are transferred on a pod and isolated from contamination.Wafer Wet Cleaning•The predominant wafer surface cleaning process is with wet chemistry. The industry standard wet-clean process is the RCA clean, consisting of standard clean 1 (SC-1) and standard clean 2 (SC-2).•SC-1 is a mixture of ammonium hydroxide, hydrogen peroxide and DI water and capable of removing particles and organic materials. For particles, removal is primarily through oxidation of the particle or electric repulsion.•SC-2 is a mixture of hydrochloric acid, hydrogen peroxide and DI water and used to remove metals from the wafer surface.•RCA clean has been modified with diluted cleaning chemistries. The piranha cleaning mixture combines sulfuric acid and hydrogen peroxide to remove organic and metallic impurities. Many cleaning steps include an HF last step to remove native oxide.•Megasonics(兆声清洗) is widely used for wet cleaning. It has ultrasonic energy with frequencies near 1 MHz. Spray cleaning will spray wet-cleaning chemicals onto the wafer. Scrubbing is an effective method for removing particles from the wafer surface.•Wafer rinse is done with overflow rinse, dump rinse and spray rinse. Wafer drying is done with spin dryer or IPA(异丙醇) vapor dry (isopropyl alcohol).•Some alternatives to RCA clean are dry cleaning, such as with plasma-based cleaning, ozone and cryogenic aerosol cleaning.Chapter 7Metrology and Defect InspectionIC Metrology•In a wafer fab, metrology refers to the techniques and procedures for determining physical and electrical properties of the wafer.•In-process data has traditionally been collected on monitor wafers. Measurement equipment is either stand-alone or integrated.•Yield is the percent of good parts produced out of the total group of parts started. It is an indicator of the health of the fabrication process.Quality Measures•Semiconductor quality measures define the requirements for specific aspects of wafer fabrication to ensure acceptable device performance.•Film thickness is generally divided into the measurement of opaque film or transparent film. Sheet resistance measured with a four-point probe is a common method of measuring opaque films (e.g., metal film). A contour map shows sheet resistance deviations across the wafer surface.•Ellipsometry is a nondestructive, noncontact measurement technique for transparent films. It works based on linearly polarized light that reflects off the sample and is elliptically polarized.•Reflectometry is used to measure a film thickness based on how light reflects off the top and bottom surface of the film layer. X-ray and photoacoustic technology are also used to measure film thickness.•Film stress is measured by analyzing changes in the radius of curvature of the wafer. Variations in the refractive index are used to highlight contamination in the film.•Dopant concentration is traditionally measured with a four-point probe. The latest technology is the thermal-wave system, which measures the lattice damage in the implanted wafer after ion implantation. Another method for measuring dopant concentration is spreading resistance probe. •Brightfield detection is the traditional light source for microscope equipment. An optical microscope uses light reflection to detect surface defects. Darkfield detection examines light scattered off defects on the wafer surface. Light scattering uses darkfield detection to detectsurface particles by illuminating the surface with laser light and then using optical imaging.•Critical dimensions (CDs) are measured to achieve precise control over feature size dimensions.The scanning electron microscope is often used to measure CDs.•Conformal step coverage is measured with a surface profiler that has a stylus tip.•Overlay registration measures the ability to accurately print photoresist patterns over a previously etched pattern.•Capacitance-voltage (C-V) test is used to verify acceptable charge conditions and cleanliness at the gate structure in a MOS device.Analytical Equipment•The secondary-ion mass spectrometry (SIMS) is a method of eroding a wafer surface with accelerated ions in a magnetic field to analyze the surface material composition.•The atomic force microscope (AFM) is a surface profiler that scans a small, counterbalanced tip probe over the wafer to create a 3-D surface map.•Auger electron spectroscopy (AES) measures composition on the wafer surface by measuring the energy of the auger electrons. It identifies elements to a depth of about 2 nm. Another instrument used to identify surface chemical species is X-ray photoelectron spectroscopy (XPS).•Transmission electron microscopy (TEM) uses a beam of electrons that is transmitted through a thin slice of the wafer. It is capable of quantifying very small features on a wafer, such as silicon crystal point defects.•Energy-dispersive spectrometer (EDX) is a widely used X-ray detection method for identifying elements. It is often used in conjunction with the SEM.• A focused ion beam (FIB) system is a destructive technique that focuses a beam of ions on the wafer to carve a thin cross section from any wafer area. This permits analysis of the wafermaterial.Chapter 8Gas Control in Process ChambersEtch process chambers••The process chamber is a controlled vacuum environment where intended chemical reactions take place under controlled conditions. Process chambers are often configured as a cluster tool. Vacuum•Vacuum ranges are low (rough) vacuum, medium vacuum, high vacuum and ultrahigh vacuum (UHV). When pressure is lowered in a vacuum, the mean free path(平均自由行程) increases, which is important for how gases flow through the system and for creating a plasma.Vacuum Pumps•Roughing pumps are used to achieve a low to medium vacuum and to exhaust a high vacuum pump. High vacuum pumps achieve a high to ultrahigh vacuum.•Roughing pumps are dry mechanical pumps or a blower pump (also referred to as a booster). Two common high vacuum pumps are a turbomolecular (turbo) pump and cryopump. The turbo pump is a reliable, clean pump that works on the principle of mechanical compression. The cryopump isa capture pump that removes gases from the process chamber by freezing them.。
Michael quirk_半导体制造技术_附录图
Figure A.1
Definitions of Exposure Limits
(Refer to p. 602 for details) • TLV-TWA: Threshold limit values – time weighted average. • TLV-STEL: Threshold limit values – short term exposure limit. • IDLH: Immediately dangerous to life and health.
examplesofhazardsinsemiconductormanufacturing?processchemicals?highlyflammablegases?pyrophoricgases?corrosivegases?toxicorcausticliquids?highvoltages?solvents?mechanicalhazards?hightemperatures?radiationuvlaserxray?freezingtemperatureshazardwarningsignfigurea1332wredwhiteyellowbluehealthhazard0normalnohazard1slighthazard2hazardous3extremelyhazardous4deadlyfirehazard0nonflammable1above200?f2below200?f3below100?f4below73?freactivity0stablenonreactive1unstableifheated2violentlyreactive3maydetonatewithheatorshock4maydetonatespecifichazardoxyoxidizeraciacidalkalkalicorcorrosivewusenowaterradiationhazarddefinitionsofexposurelimitsrefertop
半导体制造技术ppt
半导体制造的环保与安全
05
采用低能耗的设备、优化生产工艺和强化能源管理，以降低能源消耗。
节能设计
利用废水回收系统，回收利用生产过程中产生的废水，减少用水量。
废水回收
采用低排放的设备、实施废气处理技术，以减少废气排放。
废气减排
半导体制造过程中的环保措施
严格执行国家和地方的安全法规
安全培训
安全检查
半导体制造过程的安全规范
将废弃物按照不同的类别进行收集和处理，以便于回收利用。
废弃物处理和回收利用
分类收集和处理
利用回收技术将废弃物进行处理，以回收利用资源。
回收利用
按照国家和地方的规定，将无法回收利用的废弃物进行合法处理，以减少对环境的污染。
废弃物的合法处理
未来半导体制造技术的前景展望
06
新材料
随着人工智能技术的发展，越来越多的半导体制造设备具备了智能化控制和自主学习的能力。
半导体制造设备的最新发展
更高效的生产线
为了提高生产效率和降低成本，各半导体制造厂家正在致力于改进生产线，提高设备的联动性和生产能力。
更先进的材料和工艺
随着科学技术的发展，越来越多的先进材料和工艺被应用于半导体制造中，如石墨烯、碳纳米管等材料以及更为精细的制程工艺。
薄膜沉积
在晶圆表面沉积所需材料，如半导体、绝缘体或导体等。
封装测试
将芯片封装并测试其性能，以确保其满足要求。
半导体制造的基本步骤
原材料准备
晶圆制备
薄膜沉积
刻蚀工艺
离子注入
封装测试
各步骤中的主要技术
制造工艺的优化
通过对制造工艺参数进行调整和完善，提高产品的质量和产量。
制造工艺的改进
半导体制造技术复习总结
半导体制造技术复习总结半导体制造技术复习总结第⼀章半导体产业介绍1、集成电路制造的不同阶段：硅⽚制备、硅⽚制造、硅⽚测试/拣选、装配与封装、终测；2、硅⽚制造：清洗、成膜、光刻、刻蚀、掺杂；3、半导体趋势：提⾼芯⽚性能、提⾼芯⽚可靠性、降低芯⽚价格；4、摩尔定律：⼀个芯⽚上的晶体管数量⼤约每18个⽉翻⼀倍。
5、半导体趋势：①提⾼芯⽚性能：a关键尺⼨（CD）－等⽐例缩⼩（Scale down)b每块芯⽚上的元件数－更多 c 功耗－更⼩②提⾼芯⽚可靠性： a⽆颗粒净化间的使⽤ b控制化学试剂纯度c分析制造⼯艺 d硅⽚检测和微芯⽚测试e芯⽚制造商成⽴联盟以提⾼系统可靠性③降低芯⽚价格：a.50年下降1亿倍 b减少特征尺⼨＋增加硅⽚直径c半导体市场的⼤幅度增长（规模经济）第⼆章半导体材料特性6、最常见、最重要半导体材料－硅：a.硅的丰裕度 b.更⾼的熔化温度允许更宽的⼯艺容限c.更宽的⼯作温度范围d.氧化硅的⾃然⽣成7、GaAs的优点：a.⽐硅更⾼的电⼦迁移率; b.减少寄⽣电容和信号损耗; c.集成电路的速度⽐硅制成的电路更快; d.材料电阻率更⼤，在GaAs衬底上制造的半导体器件之间很容易实现隔离，不会产⽣电学性能的损失；e.⽐硅有更⾼的抗辐射性能。
GaAs的缺点： a.缺乏天然氧化物；b.材料的脆性； c.由于镓的相对匮乏和提纯⼯艺中的能量消耗，GaAs的成本相当于硅的10倍； d.砷的剧毒性需要在设备、⼯艺和废物清除设施中特别控制。
第三章器件技术8、等⽐例缩⼩:所有尺⼨和电压都必须在通过设计模型应⽤时统⼀缩⼩。
第四章硅和硅⽚制备9、⽤来做芯⽚的⾼纯硅称为半导体级硅(semiconductor-grade silicon, SGS)或电⼦级硅西门⼦⼯艺：1.⽤碳加热硅⽯来制备冶⾦级硅SiC(s)+SiO2(s) Si(l)+SIO(g)+CO(g)2.将冶⾦级硅提纯以⽣成三氯硅烷Si(s)+3HCl(g) SiHCl3(g)+H2(g)3.通过三氯硅烷和氢⽓反应来⽣成SGS SiHCl3(g)+H2(g) Si(s)+3HCl(g)10、单晶硅⽣长：把多晶块转变成⼀个⼤单晶，并给予正确的定向和适量的N型或P型掺杂，叫做晶体⽣长。
《电工学》14秦曾煌主编第六版下册电子技术第14章
(14-15)
§14.2 PN 结及其单向导电性
PN 结的形成
在同一片半导体基片上，分别制造P 型 半导体和 N 型半导体，经过载流子的扩散， 在它们的交界面处就形成了PN 结。
(14-16)
内电场越强，漂移运动 就越强，而漂移的结果 使空间电荷区变薄。
漂移运动
P型半导体
内电场E N型半导体
－－－－ － － －－－－ － － －－－－ － － －－－－ － －
结
构
N型硅
图
P型硅 N型硅
C (a)平面型
E 铟球
P B N型锗
P 铟球
C
(b)合金型
常见：硅管主要是平面型，锗管都是合金型
(14-38)
发射结 集电结
发射极
E
N PN
集电极 C
发射区 基区 集电区 B 基极
+4
在其它力的作用下， 空穴可吸引附近的电子 来填补，其结果相当于 空穴的迁移，而空穴的 迁移相当于正电荷的移 动，因此可认为空穴是 载流子。
自由电子：在晶格中运动；空穴：在共价键中运动
(14-10)
本征半导体中电流由两部分组成：
1. 自由电子移动产生的电流。 2. 空穴移动产生的电流。
本征半导体的导电能力取决于载流子的浓度。
心，而相邻四个原子位于四面体的顶点，每个原子与 其相邻的原子之间形成共价键，共用一对价电子。
硅和锗的晶 体结构：
(14-5)
硅和锗的共价键结构
+4表示除 去价电子 后的原子
+4
+4
+4
+4
共价键共 用电子对
(14-6)
+4
半导体工艺及芯片制造技术问题答案(全)
常用術語翻譯active region 有源區2.active component有源器件3.Anneal退火4.atmospheric pressure CVD (APCVD) 常壓化學氣相澱積5.BEOL（生產線）後端工序6.BiCMOS雙極CMOS7.bonding wire 焊線，引線8.BPSG 硼磷矽玻璃9.channel length溝道長度10.chemical vapor deposition (CVD) 化學氣相澱積11.chemical mechanical planarization (CMP)化學機械平坦化12.damascene 大馬士革工藝13.deposition澱積14.diffusion 擴散15.dopant concentration摻雜濃度16.dry oxidation 幹法氧化17.epitaxial layer 外延層18.etch rate 刻蝕速率19.fabrication制造20.gate oxide 柵氧化矽21.IC reliability 集成電路可靠性22.interlayer dielectric 層間介質（ILD）23.ion implanter 離子注入機24.magnetron sputtering 磁控濺射25.metalorganic CVD(MOCVD)金屬有機化學氣相澱積26.pc board 印刷電路板27.plasma enhanced CVD(PECVD) 等離子體增強CVD28.polish 拋光29.RF sputtering 射頻濺射30.silicon on insulator絕緣體上矽（SOI）第一章半導體產業介紹1. 什麼叫集成電路？寫出集成電路發展の五個時代及晶體管の數量？(15分)集成電路：將多個電子元件集成在一塊襯底上，完成一定の電路或系統功能。
集成電路芯片/元件數產業周期無集成 1 1960年前小規模(SSI) 2到50 20世紀60年代前期中規模(MSI) 50到5000 20世紀60年代到70年代前期大規模(LSI) 5000到10萬 20世紀70年代前期到後期超大規模(VLSI) 10萬到100萬 20世紀70年代後期到80年代後期甚大規模(ULSI) 大於100萬 20世紀90年代後期到現在2. 寫出IC 制造の５個步驟？(15分)Wafer preparation(矽片准備)Wafer fabrication (矽片制造)Wafer test/sort (矽片測試和揀選)Assembly and packaging (裝配和封裝)Final test(終測)3. 寫出半導體產業發展方向？什麼是摩爾定律？(15分)發展方向：提高芯片性能——提升速度(關鍵尺寸降低,集成度提高,研發采用新材料)，降低功耗。
半导体工艺标准规范标准及其芯片制造技术问答规范标准答案(全)
常用术语翻译active region 有源区2.active component有源器件3.Anneal退火4.atmospheric pressure CVD (APCVD) 常压化学气相淀积5.BEOL（生产线）后端工序6.BiCMOS双极CMOS7.bonding wire 焊线，引线8.BPSG 硼磷硅玻璃9.channel length沟道长度10.chemical vapor deposition (CVD) 化学气相淀积11.chemical mechanical planarization (CMP)化学机械平坦化12.damascene 大马士革工艺13.deposition淀积14.diffusion 扩散15.dopant concentration掺杂浓度16.dry oxidation 干法氧化17.epitaxial layer 外延层18.etch rate 刻蚀速率19.fabrication制造20.gate oxide 栅氧化硅21.IC reliability 集成电路可靠性22.interlayer dielectric 层间介质（ILD）23.ion implanter 离子注入机24.magnetron sputtering 磁控溅射25.metalorganic CVD(MOCVD)金属有机化学气相淀积26.pc board 印刷电路板27.plasma enhanced CVD(PECVD) 等离子体增强CVD28.polish 抛光29.RF sputtering 射频溅射30.silicon on insulator绝缘体上硅（SOI）第一章半导体产业介绍1. 什么叫集成电路？写出集成电路发展的五个时代及晶体管的数量？(15分)集成电路：将多个电子元件集成在一块衬底上，完成一定的电路或系统功能。
集成电路芯片/元件数产业周期无集成 1 1960年前小规模(SSI) 2到50 20世纪60年代前期中规模(MSI) 50到5000 20世纪60年代到70年代前期大规模(LSI) 5000到10万 20世纪70年代前期到后期超大规模(VLSI) 10万到100万 20世纪70年代后期到80年代后期甚大规模(ULSI) 大于100万 20世纪90年代后期到现在2. 写出IC 制造的５个步骤？(15分)Wafer preparation(硅片准备)Wafer fabrication (硅片制造)Wafer test/sort (硅片测试和拣选)Assembly and packaging (装配和封装)Final test(终测)3. 写出半导体产业发展方向？什么是摩尔定律？(15分)发展方向：提高芯片性能——提升速度(关键尺寸降低,集成度提高,研发采用新材料)，降低功耗。
《半导体制造技术导论》读书笔记PPT模板思维导图下载
3.8 参考文献
3.7 小结
3.9 习题
第4章 晶圆制造
01
4.1 简介
02
4.2 为什 么使用硅 材料
03
4.3 晶体 结构与缺 陷
04
4.4 晶圆 生产技术
06
4.6 衬底 工程
05
4.5 外延 硅生长技 术
4.8 参考文献
4.7 小结
4.9 习题
第5章 加热工艺
01
5.1 简介
02
6.4 光刻技术的 发展趋势
6.5 安全性 6.6 小结
6.7 参考文献 6.8 习题
第7章 等离子体工艺
01
7.1 简介
02
7.2 等离 子体基本 概念
03
7.3 等离 子体中的 碰撞
04
7.4 等离 子体参数
06
7.6 直流 偏压
05
7.5 离子 轰击
7.7 等离子体工 艺优点
7.8 等离子体增 强化学气相沉积
10.9 工艺发展趋 势与故障排除
10.10 化学气相 沉积工艺发展趋 势
10.12 参考文献
10.11 小结
10.13 习题
第11章 金属化工艺
01
11.1 简 介
02
11.2 导 电薄膜
03
11.3 金 属薄膜特 性
04
11.4 金 属化学气 相沉积
06
11.6 铜 金属化工 艺
05
11.5 物 理气相沉 积
5.2 加热 工艺的硬 件设备
03
5.3 氧化 工艺
04
5.4 扩散 工艺
06
5.6 高温 化学气相 沉积
05
半导体制造技术
《半导体制造技术》-(美)Michael Ciuik Julian Serda著韩郑生等译电子工业出版社《微电子制造科学原理与工程技术》(第二版)–(美)StephenA.Camphell著曾莹等译电子工业出版社微电子制造：圆片——生成氧化层光刻：淀积电阻材料——形成电阻材料淀积绝缘层——形成绝缘层淀积绝缘层——形成绝缘层薄膜淀积：溅射和蒸发（物理过程）溅射——Ar+轰击含有淀积材料的靶蒸发——对圆片涂敷在圆片上部生长半导体薄层的过程称之为外延生长。
CMOS工艺流程氧化工艺：清洗液：RCH、SC-1、SC-2清洗体系以及Piranha清洗（硫酸、过氧化氢和水的混合物）干法氧化工艺的工艺菜单危险性：酸和碱（PH小于7为酸性，大于7为碱性）有毒性：磷化氢和砷化氢易燃性：酒精和丙铜自然性：硅烷（在空气55℃（130ºF）温度不能够自燃的物质）HF侵蚀玻璃，只能用塑料容器存放和使用。
不相溶的化学物质集成电路制造工艺：N（P）型SiO2 光刻 B LPVCD（SiO2）光刻（引线孔）蒸发光刻集成电路芯片生产，工艺复杂，工艺步骤高达300余步，同时使用多种化学试剂和特种气体。
但总体来说生产工艺流程是使用硅抛光/外延大园片，在其清洗干净的表面上，通过氧化或CVD的方法形成阻挡或隔离层薄膜，由光刻技术形成掺杂孔或接触孔，然后采用离子注入或扩散的方法掺杂形成器件PN结，最后由溅射镀膜或CVD成膜的方法形成互联引线。
主要生产工序包括：清洗—氧化、扩散—CVD沉积—光刻—去胶—干法刻蚀—CMP抛光—湿法腐蚀—离子注入—溅射—检测—入库。
生产所需主要原材料包括硅片、光掩模、石英制品、大宗气体、烷类特种气体、化学试剂、光刻胶、显影剂等几大类，生产产生的污染物包括酸碱废水、含F-废水、CMP废水、酸碱性废气、有机废气、废液等。
大宗气体包括氮气、氧气、氢气、氩气、氦气等。
●纯水装设容量（m3/h）80电阻率(MΩ·CM、25℃) 18.1TOC(ppb) <2细菌(个/100ml) <1Si (ppb) <0.5Na、K、Ca、Ni、Fe、Zn、Cu、Al <0.01Cl(ppb) <0.05SO4、NO3 (ppm) <0.1PO4 (μm) <0.5水温（℃）冷：23±2水压（MPa）0.3±0.05（使用点）●冷却循环水装设容量（m3/h）340供水压力（MPa）0.80供水温度（℃）16回水温度（℃）21供水水质电导率100μm/cm, PH 6.8~7.5 ●高纯氧气（纯化器出口）纯度（%）99.9995装设容量（m3/h）75CO2含量(ppb) < 1如有你有帮助，请购买下载，谢谢！CO含量(ppb) < 1H2O含量(ppb) < 1N2 (100ppb) < 1THC(100ppb) < 1微粒(pcs/l)＞0.1μm< 1使用压力（Mpa）0.5●高纯氢气（纯化器出口）纯度（%）99.9999装设容量（m3/h）14含O2量(ppb) < 1CO2含量(ppb) < 1CO含量(ppb) < 1H2O含量(ppb) < 1THC(100ppb) < 1N2 (ppb) < 1微粒(pcs/l)＞0.1μm< 1使用压力（Mpa）0.5●高纯氮气纯度（%）99.9999装设容量（m3/h）400含O2量(ppb) < 1CO2含量(ppb) < 1如有你有帮助，请购买下载，谢谢！CO含量(ppb) < 1H2O含量(ppb) < 1THC(100ppb) < 1H2 (ppb) < 1微粒(pcs/l)＞0.1μm< 1使用压力（Mpa）0.6●普通氮气纯度（%）99.999装设容量（含高纯氮）（m3/h）1275含O2量(ppb) < 200CO2含量(ppb) < 100CO含量(ppb) < 100H2O含量(ppb) < 100THC(100ppb) < 100H2 (ppb) < 100微粒(pcs/l)＞0.1μm< 5使用压力（Mpa）0.7●压缩空气露点（%）-70℃装设容量（m3/h）1260微粒(pcs/l)＞0.1μm< 0.35(0.24μm)使用压力（Mpa）0.7工艺生产过程中产生的局部废气包括一般排风、酸性废气、碱性废气与有机废气四类。
《半导体制造技术》课程教学大纲
《半导体制造技术》课程教学大纲课程编号：20821305总学时数：48总学分数：3课程性质：必修适用专业：应用物理学一、课程的任务和基本要求：通过本课程学习，使学生对半导体集成电路制造工艺及原理有一个较为完整和系统的概念，了解集成电路制造相关领域的新技术、新设备、新工艺，使学生具有一定工艺分析和设计以及解决工艺问题和提高产品质量的能力。
主要分两部分内容，第一部分介绍主要的半导体材料，基本性质、在器件制造中的应用、材料的生长和加工等。
第二部分介绍超大规模集成电路制造的工艺流程，包括构成流程的各个基本工艺的原理、技术要点、检测方法和工艺质量评价。
该课程不仅是工艺工程师的入门知识，也是设计工程师应掌握的基本知识。
二、基本内容和要求：第一章硅和硅片的制备1.1 晶体结构1.2 单晶硅的生长1.3 硅中的晶体缺陷1.4 硅片制备通过本章的学习，要求学生掌握晶体生长技术（直拉法、区熔法），硅圆片制备及规格，晶体缺陷，硅中杂质。
第二章集成电路制造工艺简介2.1 CMOS工艺流程2.2 CMOS制作步骤通过本章的学习，要求学生简单了解集成电路制造工艺流程和制作步骤。
第三章氧化3.1 热氧化生长3.2 高温炉设备3.3 氧化工艺3.4 质量检测通过本章的学习，要求学生掌握SiO2结构及性质，硅的热氧化，影响氧化速率的因素，氧化缺陷，掩蔽扩散所需最小SiO2层厚度的估算，SiO2薄膜厚度的测量。
第四章淀积4.1 化学气相淀积4.2 CVD淀积系统4.3 外延4.4 CVD质量检测通过本章的学习，要求学生掌握化学气相淀积的原理和系统，了解外延法的种类。
第五章金属化5.1 金属淀积系统5.2 金属化方案通过本章的学习，要求学生掌握金属化的原理和系统。
第六章光刻6.1 光刻工艺简介6.2 旋转涂胶6.3 前烘6.4 对准和曝光6.5 显影和坚膜通过本章的学习，要求学生掌握光刻工艺流程，光刻缺陷控制及检测，光刻技术分类（光学光刻，非光学光刻），了解最新的光刻工艺技术动态。
半导体制造技术pdf
半导体制造技术pdf
半导体制造技术是制造电子器件或元件所需要的技术，几乎每一个电子器件或元件都需要这种技术。
半导体制造技术可以将纯净的原材料，如锗、硅、锡、铜等，经过复杂的制造过程而进行形成和凝结，形成适合的半导体晶体。
这种技术的重要性不言而喻，可以实现把集成电路上的小尺寸和薄型电子部件进行封装，以形成完整的集成电路。
根据不同的半导体制造技术，制造出来的半导体晶体具有不同的性能特点，如封装密度、功耗、电气特性等都可以由不同的制造技术而有所改变。
另外，由于每一种半导体制造技术自身都有其特定的材料要求，任何在制造过程中含锡、铜等金属元素的技术都需要特殊的条件，以便在不产生尘埃的环境中进行金属元素的过滤和偶合，以便最后形成完整的晶体，这也是一项复杂的技术。
总之，半导体制造技术是电子器件的基础，无论通用的集成电路还是特定的芯片以及其他晶体，都需要依据半导体制造技术进行制造，而它的正确使用及材料的挑选，对电子器件制造性能有着至关重要的影响。
半导体制造技术
电信学院微电子教研室
CMOS 制作中的一般掺杂工艺
工艺步骤
A. p+ 硅衬底 B. p- 外延层 C. 倒掺杂 n 阱 D. 倒掺杂 p 阱 E. p-沟道器件穿通 F. p-沟道阈值电压（VT）调整 G. n-沟道器件穿通 H. n-沟道阈值电压（VT）调整 I. n 沟道器件轻掺杂漏区(LDD) J. n-沟道器件源漏区 (S/D) K. p-沟道器件（ LDD） L. p-沟道器件源漏区（S/D） M.硅 N. 多晶硅 O. SiO2 掺杂
Table 17.5
半导体制造技术
by Michael Quirk and Julian Serda
电信学院 微电子教研室
离子注入在工艺集成中的发展趋势
不同注入工艺的实例
• • • • • • • • • •
半导体制造技术
by Michael Quirk and Julian Serda
深埋层 倒掺杂阱 穿通阻挡层 阈值电压调整 轻掺杂漏区 (LDD) 源漏注入 多晶硅栅 沟槽电容器 超浅结 绝缘体上硅 (SOI)
22
6.1.3 Grove模型
生长动力学
从简单的生长模型出发，用 动力学方法研究化学气相淀 积推导出生长速率的表达式 及其两种极限情况
Cg
气体
薄膜
衬底
Cs
与热氧化生长稍有 不同的是，没有了 在SiO2中的扩散流
F1
F2
U
Grove模型
F1是反应剂分子的粒子流密度 F2代表在衬底表面化学反应消耗的反应剂分子流密度
G
CT N
hg Y
质量输运控制，对温度不敏感
芯片制造-半导体工艺教程
芯片制造-半导体工艺教程芯片制造-半导体工艺教程芯片制造-半导体工艺教程Microchip Fabrication ----A Practical Guide to Semicondutor Processing 目录:第一章:半导体工业第二章:半导体材料和工艺化学品第三章:晶圆制备第四章:芯片制造概述第五章:污染控制第六章:工艺良品率第七章:氧化第八章:基本光刻工艺流程-从表面准备到曝光第九章:基本光刻工艺流程-从曝光到最终检验第十章:高级光刻工艺第十一章:掺杂第十二章:淀积第十三章:金属淀积第十四章:工艺和器件评估第十五章:晶圆加工中的商务因素第十六章:半导体器件和集成电路的形成第十七章:集成电路的类型第十八章:封装附录:术语表1芯片制造-半导体工艺教程#1 第一章半导体工业--1芯片制造-半导体工艺教程点击查看章节目录by r__ 概述本章通过历史简介，在世界经济中的重要性以及纵览重大技术的发展和其成为世界领导工业的发展趋势来介绍半导体工业。
并将按照产品类型介绍主要生产阶段和解释晶体管结构与集成度水平。
目的完成本章后您将能够：1. 描述分立器件和集成电路的区别。
2. 说明术语D固态，‖ D平面工艺‖，DDN‖‖型和DP‖型半导体材料。
3. 列举出四个主要半导体工艺步骤。
4. 解释集成度和不同集成水平电路的工艺的含义。
5. 列举出半导体制造的主要工艺和器件发展趋势。
一个工业的诞生电信号处理工业始于由Lee Deforest 在1906年发现的真空三极管。
1真空三极管使得收音机, 电视和其它消费电子产品成为可能。
它也是世界上第一台电子计算机的大脑，这台被称为电子数字集成器和计算器（ENIAC）的计算机于1947年在宾西法尼亚的摩尔工程学院进行首次演示。
这台电子计算机和现代的计算机大相径庭。
它占据约1500平方英尺，重30吨，工作时产生大量的热，并需要一个小型发电站来供电，花费了1940年时的400, 000美元。
半导体制造工艺技术(PPT 68页)
半导体制造技术 by Michael Quirk and Julian Serda
电信学院微电子教研室
目标
通过本章的学习，将能够：
1. 描述出多层金属化。叙述并解释薄膜生长的三个阶段。 2. 提供对不同薄膜淀积技术的慨况。 3. 列举并描述化学气相淀积（CVD）反应的8个基本步骤，包
Figure 11.10
电信学院微电子教研室
CVD 反应中的压力
如果CVD发生在低压下，反应气体通过边 界层达到表面的扩散作用会显著增加。这会增 加反应物到衬底的输运。在CVD反应中低压的 作用就是使反应物更快地到达衬底表面。在这 种情况下，速度限制将受约于表面反应，即在 较低压下CVD工艺是反应速度限制的。
半导体制造技术 by Michael Quirk and Julian Serda
电信学院微电子教研室
MSI时代nMOS晶体管的各层膜
顶层
垫氧化层
Poly
n+
金属前氧化层 侧墙氧化层
栅氧化层
ILD 场氧化层
n+
p- epi layer
氮化硅
氧化硅
氧化硅 多晶
p+
金属
金属
p+
n-well
p+ silicon substrate
Photo 11.3
电信学院微电子教研室
CVD 化学过程
• 高温分解： 通常在无氧的条件下，通过加热化 合物分解（化学键断裂）；
2. 光分解： 利用辐射使化合物的化学键断裂分解； 3. 还原反应： 反应物分子和氢发生的反应； 4. 氧化反应： 反应物原子或分子和氧发生的反应； • 氧化还原反应： 反应3与4地组合，反应后形成两
半导体技术导论 14.6章内容
半导体技术导论 14.6章内容一、概述在当今信息时代，半导体技术作为信息产业的核心技术，扮演着举足轻重的角色。
半导体技术的发展对于现代电子产品的功能和性能提升起到了至关重要的作用。
本章将介绍半导体技术的发展历程、核心原理和应用前景，帮助读者对该领域有一个清晰的认识。
二、半导体材料1. 硅(Si)材料硅是当前半导体领域应用最为广泛的材料之一，其晶体结构稳定，电子迁移率高，热容量小等优势使其成为集成电路制造的首选材料。
硅材料的加工工艺技术也十分成熟，为半导体工业的迅速发展提供了坚实的基础。
2. 砷化镓(GaAs)材料砷化镓材料因其较大的电子迁移率、较高的饱和漂移速度和较高的饱和电子漂移速度等特点，被广泛应用于高频大功率器件制造。
其在微波通信、雷达系统和光通信领域具有重要的地位。
三、半导体器件1. 晶体管晶体管是半导体技术应用中最为广泛的器件之一，其主要作用是放大电信号和作为开关控制电路。
晶体管的发明代表着电子学史上的一次革命性突破，对于现代电子设备的发展产生了深远的影响。
2. 集成电路集成电路是将大量的电子器件集成在一块半导体晶体片上，可以实现多种功能的电路元件。
其制造工艺和技术含量极高，是半导体技术发展的重要领域。
当前，集成电路已经广泛应用于计算机、通信、消费电子等各个领域，成为信息产业的重要基石。
四、半导体制造工艺1. 光刻工艺光刻工艺是半导体器件制造过程中的一项关键技术，主要用于在半导体晶片上形成微米级甚至纳米级的电路图形。
通过紫外光照射感光胶，再进行显影、腐蚀等步骤，最终获得需要的电路图形。
光刻工艺的精度和稳定性对于半导体器件性能的提升至关重要。
2. 离子注入工艺离子注入工艺是半导体材料电子结构调控的一种关键工艺，通过向半导体材料中注入特定的外来离子，可以改变材料的导电性能和结构特征，从而获得所需的电子器件特性。
五、半导体技术应用前景随着信息技术、通信技术的飞速发展，半导体技术在各个领域都有着广阔的应用前景。
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顶部抗反射涂层
• 顶部抗反射涂层在光刻胶和空气的交界面上减少 反射。顶部抗反射涂层不吸收光，而是作为一个 透明的薄膜干涉层，通过光线间的相干相消来消 除反射。
分辨率
• 光刻中，分辨率被定义为清晰分辨出硅片上间隔 很近的特征图形对的能力。分辨率对于任何光学 系统都是一个重要的参数。
影响分辨率的三个参数
减小驻波效应的方法
• 抗反射涂层 • 染抗反射涂层（吸收光以减少反射） • 无机反射涂层（通过特定波长相移相消起作用） • 选择抗反射涂层的一个因素是在完成光刻工艺后 抗反射涂层能被除去的能力。有些有机抗反射涂 层是水溶的，通过显影步骤很容易去除。无机反 射涂层较难被去除，有时留在硅片上成为器件的 一部分。
抗反射涂层使用的原因
• 光刻胶的下面是最终要被刻蚀形成图案的底层薄 膜。如果这个底层是反光的，那么光线将从这个 膜层反射并有可能损害临近的光刻胶。这个损害 能够对线宽控制产生不利的影响。 • 两种最主要的光反射问题是反射切口和驻波。
驻波引发的问题
驻波表征入射光波和反射光波之间 的干涉，这种干涉引起了随光刻胶厚度 变化的不均匀曝光。 驻波的发生对深紫外光刻胶更加显 著，因为很多硅片表面在较短的深紫外 波长反射更加厉害。 驻波本质上降低了光刻胶成像的分 辨率。
• 波长 • 数值孔径NA • 工艺因子k
焦深
• 焦点周围有个范围，在这个范围内图像连续地保 持清晰，这个范围被称做焦深或DOF。 • 光刻工艺中，焦深应穿越光刻胶层上下表面。
焦深、分辨率和宽容度
• 焦深方程式的含义是如果分辨率提高了焦深就会 减小。然而焦深的减小严重缩减了光学系统的工 艺宽容度。
• 曝光光源的一个重要方面是光的强度，光强定义 为单位面积的功率，并且在光刻胶的表面测量。 光强的另一种解释是单位面积的光亮或亮度。
• 能量是功率和时间的乘积。光强乘上曝光时间就 表示了光刻胶表面获得的曝光能量，或曝光的剂 量。
• 高压汞灯作为紫外光源用于所有常规I线步进光刻 机。为使光刻胶与UV波长相适应，可使用一套滤 波器阻挡不需要的波长和红外波长。
投影掩膜板损伤来源
• • • • 掉铬 表面擦伤 静电放电 灰尘颗粒
光学增强技术
• 相移掩膜技术 • 光学临近修正 • 离轴照明
对准
• 对准就是确定硅片上图形的位置、方向和图形转 换的过程。 • 对准过程的结果，或者每个连续的图形与先前层 匹配的精度，被称做套准。 • 套准精度是测量对准系统把版图套准到硅片上图 形的能力。套准容差描述要形成的图形层和前层 的最大相对位移。一般套准容差是关键尺寸的三 分之一。
扫描投影光刻机
• 1um以上 • 1:1掩膜板
分步重复光刻机
• 0.35um, 0.25um • 只投影一个曝光场 • 具有使用缩小透镜的能力，制造投影掩膜 板更容易 • 对平整度和几何形状变化的补偿更容易
步进扫描光刻机
优点： 1. 增大了曝光场，可以获得较大的芯片尺寸 2. 每次曝光可以曝光多个图形 3. 在整个扫描过程有调节聚焦的能力，使透镜缺 陷和硅片平整度变化能够得到补偿 挑战：增加了机械容许偏差控制的要求
环境条件
• • • • • 温度 湿度 振动 大气压力 颗粒沾污
对准和曝光的质量测量
• • • • • 聚焦-曝光剂量 光强 掩膜板对准 图形分辨率 投影掩膜板的质量
小结
本章学习了： • 对准和曝光的目的 • 光刻曝光光源 • 为什么使用抗反射涂层 • 减小驻波反应的方法 • 用于对准和曝光的五代设备
• CMP对光刻的意义在于，它使减少焦深获得较高 的图形分辨率成为可能。
五代光刻设备
• • • • • 接触式光刻机 接近式光刻机 扫描投影光刻机 分步重复光刻机 步进扫描光刻机
接触式光刻机
• • • • 5um及以上 手动对准 易被沾污 当硅片尺寸增加就有套准精度问题
接近式光刻机
• 2-4um • 紫外光发散，减小了分辨能力
衍射给光刻带来的问题
• 投影掩膜板上有小的清晰图形并且间距很窄。曝 光时，光必须通过这些图形。衍射图样夺走了曝 光能量，并使光发散，导致光刻胶上不需要曝光 的地方被曝光。
• 由衍射引起的干涉图样使小接触孔和小线条很难 被光刻。
数值孔径
• 一个透镜能俘获一些衍射光。透镜收集衍射光的 能力被称做透镜的数值孔径（NA）。 • 可以通过增加镜头半径来增加数值孔径并俘获更 多的衍射光，但是这样的光学系统更加复杂更加 昂贵。
对准和曝光包括两个系统：一个是要把图 形在晶园表面上准确定位（不同的对准机类型 的对准系统各不相同）；另一个是曝光系统 （包括一个曝光光源和一个将辐射光线导向到 晶园表面上的机械装置）。
• 用于硅片制造的光刻在很大程度上以光学光刻为 基础。
曝光光源
• 汞灯（使用于常规I线步进光刻机上） • 准分子激光灯（248nm及以下深紫外波长提 供较大光强）
半导体制造技术
陈弈星
dreamtower@
dreamtower@
第十四章 光刻：对准和曝光
光刻工艺8步骤
3
对准和曝光 对准是把所需图形在晶园表面上定位或对 准。而曝光是通过曝光灯或其他辐射源将图形 转移到光刻胶涂层上。如果说光刻胶是光刻工 艺的“材料”核心，那么对准和曝光则是该工 艺的“设备”核心。图形的准确对准是保证器 件和电路正常工作的决定性因素之一。
步进扫描光刻机的三个目标
• 使硅片表面和石英掩膜板对准并聚焦 • 通过对光刻胶曝光，把高分辨率的投影掩膜板上 得图形复制到硅片上 • 在单位时间内生产出足够多的符合产品质量规格 的硅片
投影掩膜板和掩膜板的比较
投影掩膜板的材料
• 熔融石英 高光学透射 无缺陷 低温度膨胀
投影掩膜板的制造
• 电子束光刻法 清洗 旋转涂胶，软烘 曝光 显影 刻蚀
曝光控制
• 剂量均匀的紫外光对光刻胶的曝光是非常重要的。 对于硅片上任何一次曝光剂量都必须是可重复的。 • 曝光控制通过剂量监控器在硅片表面测量紫外光 强获得。曝光剂量在曝光场的不同位置测量并进 行剂量百分比均匀性的计算。
• 光刻过程需要把投影掩模板的图形投影到光刻胶 上，这个投影必须能做到合适的分辨率、尺寸控 制和对准。其中透镜扮演重要的角色。