HC(LC)1S-POWER(Y6754)常规测试数据

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手机充电器检测标准

1W以下
ACLEAKAGE
CURRENT
恒温
输入GND-
输出GND.B+
MAX0.10mA
部件发热
恒温，大容量电池（BATT）充电
（充电电流750mA基准）
SWITCHINGIC,TRANS,2次DIODE.在输出TR上用热线（TTYPE）或热相分析仪检测
MAX85C（周围温度为25C）
机械
强度
检测
0.1uFceramics蓄电器并联连
接，带域幅社定为20MHz
变换电流(LOAD)检测
max60mVp-p
REVERSE
CURRENT
恒温，
输出4.2V,AC电源OFF
检测从手机流向充电器的电
流
max0.5mA
补偿充电开始电压
恒温，AC220V
充电指示灯保持Green
4.07V土0.05V
充电cutoff电流
充电器正常工作
-40C/48小时(湿度65%RH)
(电源off)
外观无异常
外观无异常
高温保管测试
放在恒温2小时后
充电器正常工作
充电器正常工作
75C/48小时C/(湿度65%RH)
(电源off)
外观无异常
外观无异常
检测项目
检测条件
检测内容
要求
检测结果
分类
详细分类
样
品
样
品
结
果
温度冲击检测
-40C/85C/各2小时/15Cycle
过电流检测
恒温，充电电压2.5V
加电流，
充电电压降到2.5V时的电流
满足450mA+,-50mA(27KQ)

直流电源测试仪(纹波系数)说明书

直流电源纹波系数测试仪
----温州市科星电子有限公司
近年来，随着阀控式铅酸电池的大量采
用，对充电机的性能提出了更高的要求。

原
国家电力部就制定了相关的控制标准，对充
电机稳压精度、稳流精度、纹波系数提出明
确的要求。

但充电机在长期的运行中，随着
运行时间的增加性能会有所改变，其纹波系
数也发生变化。

由于电池的损坏经常是纹波
系数过大造成的，为了控制每组充电机的纹
波系数和纹波含量（交流脉动量），我们特地
开发了本产品，能实时准确地对直流电源纹
波含量和纹波系数做全程监测。

功能特点：
1、采用新型高速采样芯片，高速信号处理。

2、具有预试功能，能全面满足电力系统监测与报警。

3、采样速率达1000kHz，可以全面监测直流纹波含量。

4、满足0-500V的所有直流电源。

5、实时全面监测直流电压值、纹波值、纹波系数等。

6、直流电压超欠压报警、直流系统纹波报警。

7、超压门限、欠压门限、纹波门限可以自行设置。

技术参数：
DCW-IS DCW-III
测量电压范围0-300VDC，测量精度优于1%
纹波电压范围0-9999mV，测量精度优于2%
纹波系数精度0.1%
工作方式采用DSP技术处理、分析采用ARM技术处理、分析供电方式大容量锂电池交直流电源
通讯接口RS485、RS232、USB RS485
显示液晶八段4位4位高亮数码。

74HC00中文资料

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四2输入与非门
简要说明
00 为四组2 输入端与非门（正逻辑），共有54/7400、54/74H00、54/74S00、54/74LS00
四种线路结构形式，其主要电特性的典型值如下：
双列直插封装
极限值
电源电压 (7V)
输入电压
54/7400、54/74H00、54/74S00…………….5.5V
54/74LS00 (7V)
A－B 间电压
除54/74LS00 外………………………………5.5V
工作环境温度
海纳电子资讯网：ｗｗｗ．ｆｐｇａ－ａｒｍ．ｃｏｍ为您提供各种ＩＣ中文资料
54XXX 74XXX
…………………………………. -55~125℃ …………………………………. 0~70℃
存储温度 ………………………………………….-65~150℃ 功能表
[1]: 测试条件中的“最小”和“最大”用推荐工作条件中的相应值。

海纳电子资讯网：ｗｗｗ．ｆｐｇａ－ａｒｍ．ｃｏｍ为您提供各种ＩＣ中文资料
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电源适配器重要参数性能指标和测试方法

电源适配器重要参数性能指标和测试方法现实生活中，被烧坏的电器，电子设备不在少数。

那么电子设备是在什么情况下才会被烧毁呢？电源适配器是电子设备烧毁的主要问题部件之一。

电源适配器质量的好坏，直接影响到电子产品的使用寿命。

而所有电子设备中，最容易被忽略的部件，也往往是电源适配器。

所以，深圳森树强呼吁大家引起对电源适配器的重视。

下面我们就来谈谈电源适配器中几个重要参数的性能指标及测试方法：直流电源的技术指标分为两种：一种是特性指标，包括允许输入电压、输出电压、输出电流及输出电压调节范围等。

一种是质量指标，用来衡量输出直流电压的稳定程度，包括稳压系数(或电压调整率)、输出电阻(或电流调整率)、纹波电压(周围与随机漂移)及温度系数。

稳压电源性能指标测试电路(1) 纹波电压：叠加在输出电压上的交流电压分量。

用示波器观测其峰峰值一般为毫伏量级。

也可用交流毫伏表测量其有效值，但因纹波不是正弦波，所以有一定的误差，一般直流电源的纹波电压VP-P&le10mV。

(2 电源适配器稳压系数：在负载电流、环境温度不变的情况下，输入电压的相对变化引起输出电压的相对变化，即：(3) 电源适配器电压调整率：输入电压相对变化为±10%时的输出电压相对变化量，稳压系数和电压调整率均说明输入电压变化对输出电压的影响，因此只需测试其中之一即可。

(4)电源适配器输出电阻及电流调整率电源适配器输出电阻与放大器的输出电阻相同，其值为当输入电压不变时，输出电压变化量与输出电流变化量之比的绝对值.电流调整率：输出电流从0变到最大值时所产生的输出电压相对变化值。

输出电阻和电流调整率均说明负载电流变化对输出电压的影响。

适合变电站现场使用的断路器安秒特性测试仪

适合变电站现场使用的断路器安秒特性测试仪
断路器安秒特性测试仪功能特点及技术参数：
扬州志力专业生产的断路器安秒特性测试仪适合变电站现场使用的直流断路器安秒测试,可以对直流保护电器的动作特性以及级差配合进行校验，以提高直流系统运行的可靠性，保证电网的安全可靠运行。

断路器安秒特性测试仪功能特点
1、主控部分采用高性能工控机，WindoWS操作系统，实时显示各项参数波形图及数值；
2、线性恒流控制技术，新型功率器件，恒流精度高，测试电流自主设定；
3、测试方式：全点测试或抽点测试；
4、可对直流开关过流和短路速断进行测试；
5、设备具备自保护功能，保证测试过程的安全性和可靠性；
6、管理软件可对断路器的安秒特性曲线、数据、查询、分析和报表输出等功能。

断路器安秒特性测试仪技术指标
1、电源输入：AC220V÷10%,频率50Hz±0.5Hz
2、测试电流范围：0-20OoA（可定制）
3、测试电流纹波系数：小于1%
4、输出电流稳定性：≤±1%
5、时间记录范围：Ims-IOOOs
6、最小时间分辨率:0.1ms
尊敬的客户：感谢您关注我们的产品，本公司除了有此产品介绍以外，还有高压开关机械特性
测试仪,绝缘油介电强度测试仪,高压核相仪,直流高压发生器等等的介绍，您如果对我们的产品有兴趣,欢迎来电咨询。

谢谢！。

HYG2670F 绝缘耐压测试仪使用说明书

-1-HYG2670F绝缘耐压测试仪使用说明书武汉华能阳光电气有限公司-2--3-第一章安全规则本章概要：●安全规定及标志●安全操作规定1．1安全规定及标志●本测试仪的安全要求符合＜GB4706.1＞、＜IEC1010-1＞标准。

●使用测试仪之前，请认真阅读本手册，务必按照手册要求的规定进行操作。

-4-高压测试线时必须握在红色绝缘棒处，绝对不可握在导电位置本章概要：●拆封和检查●输入电压及保险熔丝●安装及开机检查●储存和运输2．1拆封和检查武汉华能阳光电气有限公司产品是包装在一个使用泡沫保护的包装箱内，若用户收到产品时包装箱有破损，应检查仪器外观有无变形或面板损坏等。

如有损坏，请尽快通知武汉华能阳光电气有限公司或其经销商，并请保留包装-5-箱和泡沫材料，以便了解损坏原因。

我们的服务中心将为您提供快捷的维修服务或更换新机。

2．2输入电压及保险熔丝HYG2670系列绝缘耐压测试仪使用220/50Hz 单相电源，保险丝容量见技术参数表格。

更换保险丝前，必须先去掉输入电源线，新更换的保险丝容量需符合要求2.3安装及开机检查及位于测试仪后面板的熔断器是否完好。

确认检查完好后再次开机启动观察。

2．4储存和运输测试仪可在下列条件下储存和运输：温度：-20～60℃湿度＜90％ＲＨ必须避免环境温度的急剧变化，温度的急剧变化可能会使水汽凝结于仪-6-器内部。

第三章概述本章概要：●产品简介●前面板说明●后面板说明●附件3.1产品简介HYG2670系列交/直流耐压、绝缘测试仪，是一种高性能绝缘、耐压测试仪器。

可同时显示绝缘电阻值，耐压电压、击穿电流值等，具有多种测试功能。

该系列测试仪高压输出准确度高（优于5%），漏电流测试精度高（优于5%），绝缘电阻测试速度快，既适用生产线快速化流水检测，又适合实验室多功能高精度要求。

仪器的测量原理符合《GB4706.1》、《GB3883.1》、《GB4943》安全性能检测要求，可对采用基本绝缘、附加绝缘和加强绝缘的器具进行电气强度、绝缘电阻测试。

电解电容测试报告

3、振动现场测试图片（粘贴在此）
第4页，共 8 页
试验项目试验条件及方法峰值加速度：40g 每一方向上碰撞次数：1000 次脉冲宽度：6ms 试验方法：用夹具将样品固定住，从三个相互垂直的方向按照相关的参数设置规定进行测试。
4、碰撞试验结果参数编号
测试标准
GB/T 2693-2001 4.18
循环次数：1000 充电电压：450V×1.10 充电时间：30S 放电时间：5min 30S
OK OK
-4.37 -5.53
4.31 5.52
0.078 0.073
6、浪涌现场测试图片（粘贴在此）
第7页，共 8 页
试验项目
7、压力释放试验条件
测试标准
GB/T 2693-2001 4.28 试验结果参数编号 S6 S7 S10 装置打开，无爆炸和燃烧的危险则判为 pass,否则判为 fail。
OK OK OK OK OK
-6.26 -5.78 -6.58 -5.93 -5.88
6.51 5.22 6.35 6.25 6.33
0.089 0.089 0.087 0.091 0.088
现场测试图片（粘贴在此）
第6页，共 8 页
试验项目
6、浪涌电压试验条件
Hale Waihona Puke 测试标准GB/T 2693-2001 4.27 试验结果参数编号 S8 S9 外观 OK/NG ΔC/C≤ 15% OK/NG 漏电流≤ 0.03CU OK/NG 损耗角正切 OK/NG
施加电压：交流电压的有效值不超过额定直流电压的 0.7 倍。施加电压的频率：50Hz 或 60Hz 串联电阻：为在试验频率下电容器阻抗的 0.5 倍。

ISL6752(6754)EVAL1Z ZVS DC Power Supply with Synchronous Rectifiers User Guide

Application Note 1603Author: Richard GarciaISL6752/54EVAL1Z ZVS DC/DC Power Supply with Synchronous Rectifiers User GuideThe ISL6752/54EVAL1Z is a new design based on the ISL6752EVAL1Z but with several design modifications to improve the efficiency from 90% to 95%. The control circuit has been moved off the main board onto a daughter card. Two different daughter cards are provided: one using the ISL6752 and the other using the ISL6754. Both control cards utilize the Intersil zero voltage switching (ZVS) topology. The ISL6752 daughter card features pulse by pulse current limiting, and the ISL6754 daughter card features a patented method for average current limiting that results in a brick-wall current limit profile.The PCB layout of the ISL6752/54EVAL1Z has also been greatly improved over the ISL6752EVAL1Z. Even though the overall size of the board has been reduced, the copper losses have been reduced.In addition to the ZVS function, this board also incorporates N-Channel FETs as secondary side rectifiers, also known as synchronous rectifiers (SR). Power dissipation of the secondary side rectifiers is reduced because the conduction losses of SRs are significantly less than the conduction losses of PN or Schottky diodes.ScopeThis application note covers implementation of synchronous rectifiers (SRs) and their associated drive circuits as used on the ISL6752/54EVAL1Z board. Implementation of the primary side ZVS controller, based on the ISL6752 daughter card, is described extensively in Intersil Application Note AN1262, “Designing with the ISL6752, ISL6753 ZVS Full-Bridge Controllers.”Also reviewed is the performance of this evaluation board. Oscillographs illustrate the performance of the power supply with load transients on the output. The ZVS switching of the bridge FETs is shown, and efficiency and load regulation are measured.At the end of this application note, the schematics, bill of materials, and printed circuit board layouts are included for reference.TABLE 1.SPECIFICATIONSAbsolute Maximum Input Voltage450VDCOperating Input Voltage 350V to 450VDCMaximum Input Current 2.5ADC Rated Output Current50ADC Current Limit 60A ± 5%Output Voltage12V ± 5%Efficiency at 100% (50A) Load 95%Efficiency at 20% (10A) Load92%FIGURE 1.NEW ISL6752/54EVAL1ZBlock DiagramThe evaluation board is composed of several distinct circuit elements. The three main sections are the ZVS full bridge on the input, the current doubler rectifier on the output, and the controller daughter card. See “Schematics- Main Board,ISL6752/54EVAL1Z” on page23 and “Schematics - Daughter Card” on page25 for complete circuit details.Daughter CardsThe ISL6752 or ISL6754 control ICs are located on their respective daughter cards, as shown in Figures 3 and 4. Both daughter cards have the control ICs on the primary side and the voltage error amplifier on the secondary side. Creepage spacing between the primary and secondary is maintained on the cards. The ISL6752 and the ISL6754 control ICs are located on the primary side, eliminating the need for two AC line isolating gate drive transformers to drive the primary side bridge FETs. Instead, the low side FETs are driven directly by MOSFET drivers (on the main board), and the high side FETs are driven by a gate drive transformer that only requires operational insulation. Primary side control also simplifies design of the current sensing transformers because they also do not have to be AC line isolating.A line isolation rated opto-coupler (D5 on ISL6752DB or D2 on ISL6754DB) passes the analog error signal generated by the error amplifier, U1, from the secondary to the primary. Opto D3 passes a digital signal from primary to secondary to turn off the SRS for diode emulation. The only functional difference between the ISL6752 andISL6754 daughter cards is how current limit is implemented. The ISL6752 uses pulse-by-pulse current limit, and the ISL6754 uses average current limit.Special test points located on the daughter cards aid in probing nodes on the daughter cards for evaluation. Test points PGND and TP_PRI are located on the primary side, and SGND andTP_SEC are located on the secondary. With these test points, the user can employ the spring-like probe accessories included withFIGURE 2.ISL6752/54EVAL1Z BLOCK DIAGRAMFIGURE 3.ISL6752 DAUGHTER CARDmany scope probes. The scope signal pin is inserted in TP_PRI (or TP_SEC), and the short spring ground lead is inserted in PGND (or SGND).To probe any node on the daughter card, solder a 30ga insulated wire between the desired node and the via that is associated with the TP_PRI or TP_SEC test point. This method not only simplifies probing of any node, but also implements the preferredtechnique of measuring small signals in the presence of high amplitude switching magnetic fields.The ISL6752DBEVAL1Z and the ISL6754DBEVAL1Z daughter cards are also available as standalone evaluation kits.ZVS Full BridgeThe low side FETs, Q 3 and Q 4, are driven directly by the ISL89160 MOSFET driver, U1 (Figure 5). The two high-side FETs, Q 1 and Q 2, are indirectly driven by the ISL89160 driver, U2. A level translating gate drive transformer, T 3, with complementary output windings, directly drives the high-side bridge FETs with a symmetrical square wave. The design of T 3 is simplified because it only needs 400V operational insulation, and it is always driven with a square wave, thus eliminating the problems associated with non-symmetrical drive waveforms.Observe that the ISL89160 MOSFET drivers are located as close as possible to their respective bridge FETs to minimize thedetrimental effects of parasitic inductance on the outputs of the drivers. Although the input signal lead lengths between the drivers and the daughter card are relatively long (about 5cm), they are shielded on top and bottom by ground planes, to significantly reduce the noise injected on these lines. Thehysteresis of the ISL89160 inputs also lessens the possibility of noise corrupting the gate signals.High Voltage ProtectionBecause a failure of the bridge can cause catastrophic damage to the primary side control elements, a voltage crowbar, F1 and D 3, and a voltage blocking diode, D 4, are incorporated (Figure 6). D 3 clamps the bias voltage to a safe level. If 400V is applied to the V DD node, F1 opens shortly after D3 conducts current. D 4provides additional protection by blocking high voltage from being applied to the 13V lab supply. Note that a fully debugged power supply does not need these additional components. These parts are included on the evaluation board to minimize damage, should the user accidently introduce a fault while evaluating thecircuits. The designer may want to keep F1 in the final design, toprevent a loud bang if the bridge does fail.FIGURE 4.ISL6754 DAUGHTER CARDFIGURE 5.FULL BRIDGEFIGURE 6.PROTECTION CIRCUITSPrimary Side Current SensingThe primary side bridge has two current sensing transformers, T 2 and T 4, one on each leg on the drains of the low-side bridge FETs (Figure 7). Using two transformers allows each CT to reset during alternate half cycles. Alternate current sensing methods are reviewed in “Current Sensing” on page 8.Synchronous Rectifier Drive CircuitTwo banks of SRs are driven by the ISL89163 MOSFET driver, U4 (Figure 8). An RCD network on the inputs to this driver delay the turn-on of the SRs relative to the turn-off of the primary side bridge FETs.The ISL89367, U108, can optionally be used to drive the SRs instead of the ISL89163. Review “Schematics - Daughter Card” on page 25 to understand how to disconnect the ISL89163 and connect the ISL89367.The pulse transformer, T 6, crosses the isolation boundary to couple the control signals from the ISL6752, ISL6754 to the MOSFET drivers (Figure 9). Note that this transformer alsoprovides the secondary side bias voltage for the MOSFET drivers.Current Doubler OutputThe current doubler output is composed of two banks of SRs, Q 107... Q 109 and Q 111... Q 113; inductors L 102and L 103; and output filter capacitors, C 133... C 136 (Figure 10). The advantage of this topology is that the output current is shared by the two inductors, thus reducing conduction losses. Another advantage isthat the secondary winding of the power transformer does not require a center tap.FIGURE 7.PRIMARY SIDE CURRENT SENSINGFIGURE 8.SRs AND DRIVERSFIGURE 9.PULSE TRANSFORMER AND DRIVERBasic SR PrinciplesReplacing diodes with MOSFETs has two major advantages:•Dramatically reduces conduction losses•The applied duty cycle remains virtually constant from no load to full load. Disadvantages are:•Additional complexity and cost•Higher reverse recovery losses as compared to fast recovery diodes.•When paralleling units for redundancy, provisions must be made to prevent current circulation among the paralleled units.SR Drive Timing RequirementsTo emulate a diode, an SR must be driven ON when a diode would normally be conducting. But unlike a diode, if the SR is ON, the current through the SR can reverse if the voltage on the SR “cathode” becomes positive. The consequence is that if the SR is driven ON when the primary side is sourcing voltage to the secondary, the secondary side will be shorted by the SR. Figure 11 illustrates the timing required to drive the SRs. Notethat the rising edges of the two lower bridge FETs are delayed bythe ISL6752/54 relative to the PWM signal. Likewise, the risingedges of the SRs gate signals are delayed by the ISL89163relative to the falling edge of the PWM signal. These delays arenecessary to prevent the overlap of drive signals that wouldresult with high amplitude short circuit currents.When an SR is turned off while current is flowing from source todrain, the current diverts from the FET channel to the internalbody diode. Because the voltage drop across the body diode ishigher than the channel, it is desirable to minimize dissipation byminimizing the duration of the current flow through the bodydiode.FIGURE 10.CURRENT DOUBLER OUTPUTFIGURE 11.TIMING FOR SRs AND BRIDGE FETsSR Drive and BiasOUTLLN and OUTLRN in Figure 12 are control signals from the ISL6752/54 that are used to drive the SRs. Because theISL6752/54 is located on the primary side, a pulse transformer, T6, is used to cross the isolation boundary. The simplified schematic of Figure 12 illustrates the use of T6 to not only couple OUTLLN and OUTLRN to the secondary, but also to generate the bias for drivers on the secondary.When /OUTLLN or /OUTLRN (outputs of EL7212) transitions to a logic high, it is necessary to turn off the associated SR quickly. For example, when /OUTLRN (blue) transitions high, V1 is high, and C10 is quickly discharged by Q100. U4 then drives R-SR off. In a similar manner, when /OUTLLN is high, U4 drives L-SR off. When /OUTLLN or /OUTLRN transitions to a logic low, it is necessary to turn on the SRs after a time delay, to prevent the SRs from shorting the primary side bridge when it is sourcing current. For example, when /OUTLRN transitions to low, V1 is low and Q100 turns off, allowing C10 to be charged by R27. When the positive threshold of UR is exceeded, the output of U4 drives on R_SR. In a similar manner, the high to low transition of/OUTLLN results in the output of U4 driving on L_SR after a time delay.Note that the cathodes of D9 are connected together to peak charge C123. Because C123 is large in value, after the initial charging, the voltage does not change significantly from cycle to cycle. An important aspect of generating the bias for U4 in this manner is that the thresholds for the logic transitions on the inputs of U4 are proportional to VBIAS, and the voltage to charge C9 and C10 is also VBIAS. Consequently, the delays generated by the RC networks are independent of the absolute value of VBIAS. Current DoublerFigure 13 illustrates the current flow in the two inductors of the current doubler topology. Current flow in the circuit is correlated with the waveforms by color coding. The green waveform represents the sum of red and blue currents through R LOAD. For circuit clarity, paralleled SRs and output capacitors of theISL6752/54EVAL1Z board are not shown.When using diodes (instead of SRs), if the average load current is less than half of the ramp current in the output inductors, the current in the inductors becomes discontinuous, and the duty cycle of the PWM is shortened to maintain the desired output voltage. When using SRs, the inductor currents in L1 and L2 can become negative because current in SRs can flow bidirectionally; consequently, the duty cycle remains virtually unchanged. The benefit is that the load transient performance is the same for any load from zero up to current limit. Another advantage is that, for very light loads, the duty cycle is not reduced to very small duty cycles, pulse skipping does not occur, and the associated voltage jitter does not happen.An important design consideration for the current doubler topology is that the DC resistance of both halves must be equal. PCB layout must be as symmetrical as possible, and the DCRs of the inductors should be reasonably equal. If not, the current between the two sides does not split equally. Because perfect physical PCB symmetry is not always possible, current sharing between inductors must be confirmed.In Figure 14, inductor current waveforms are taken from the ISL6752/54EVAL1Z board. Current balance between the two inductors was achieved after one board revision. The inductor currents maintain the same waveform shape even at no load. Another design consideration when using SRs is how to connect the outputs of multiple power supplies in parallel for redundancy or increased power capacity. A consequence of negative current flow in an SR (when a diode would otherwise be reverse biased and off) is that power can be transferred from the secondary to the primary if one of the paralleled outputs has a higher voltage. The voltage loop of the units with lower set point voltages attempts to pull down the voltage by sinking current from the higher set point units. The primary side bridge capacitor is charged by the secondary side, eventually resulting in excessive voltage damage. This damage can be avoided by using OR-ing diodes (or FETs) on the paralleled outputs. Another solution is to turn off the SRs (diode emulation mode) when the current reverses in the SRs, but this eliminates some of the advantages of using SRs. Paralleling features are not implemented on the ISL6752/54EVAL1Z board.FIGURE 13.CURRENT FLOW IN TWO INDUCTORS OF CURRENT DOUBLER TOPOLOGYFIGURE 14.INDUCTOR CURRENT WAVEFORMS 50A LOAD30A LOAD NO LOADCurrent SensingCurrent flowing from the secondary to the primary can result in an unanticipated malfunction of the current sensing transformer circuit if reverse SR currents are not considered. Figure 15 shows a commonly used primary side current sensing circuit utilizing one current sensing transformer (CT).This circuit works well for peak current mode control if power is always flowing from primary to secondary, as is the case when diodes are used instead of SRs. Figure 16 illustrates the performance of the current sensing output when power always flows from primary to secondary.The voltage across R S is as expected. The vertical dashed lines show when the power cycle is terminated at the required peak of the current.Figure 17 illustrates what happens at no load to the sense voltage across R S.Notice that the negative components of the primary transformer current are rectified, resulting in two peaks of current across R S for each half cycle. Under steady state conditions, the rectified negative component may cause erratic performance because the cycle can terminate on the first peak (the inverted peak, as indicated by the vertical red line) instead of the required second peak. This condition can easily be corrected by having a small load across the output to ensure that the negative peak is always less than the positive.A minimum load, however, does not correct a more serious problem that occurs when there is a large load step from a heavy load to no load. When the load current is interrupted, the output capacitor charges higher than the regulated voltage. As the regulation loop is starting to respond by slewing to a minimum duty cycle, the excessive voltage on the output capacitor starts to discharge back to the primary. This results in a large negative current at the beginning of the duty cycle, which causes the duty cycle to be terminated very early. The imbalance of the applied volt-seconds to the power transformer may saturate the power transformer and damage the power bridge.Another scenario is that the current sensing transformer itself may saturate, which also damages the bridge. The control loop cannot maintain balanced alternate half cycles applied to the power transformer without valid current sense information. There are three solutions to this problem. Figure 18 illustrates the placements of two current sensing transformers, one on each drain leg of the bottom FETs.In this configuration, only positive current flowing into the drains of the bottom FETs are sensed across R S, solving the problem of rectified negative currents being impressed across R S. An advantage of using two CTs is that there is a full half cycle available to reset the cores of the CTs. This is the solution used in the ISL6752/54EVAL1Z board.FIGURE 15.PRIMARY SIDE CURRENT SENSING CIRCUIT UTILIZINGONE CTFIGURE 16.PERFORMANCE OF CURRENT SENSING OUTPUTFIGURE 17.NO LOAD SENSE VOLTAGE ACROSS R SFigure 19 shows a different current sensing implementation that also solves the problem shown in Figure 15. In this example, both drain currents of the bottom FETs are sensed by only one CT. There are some limitations that must be considered, however. The minimum time available to reset the core is the duration of the selected dead time between the two FETs on the same side of the bridge. To accommodate the resetting of the CT, this dead time can be made longer, but the consequences of reducing the maximum duty cycle available for output voltage regulation mustIf the dead time is kept short, then the peak voltage required for resetting the core is relatively large. For example, assume that the selected dead time is 2% of the duty cycle. The resultingworst-case reset voltage is shown approximately in Equation1:In Equation 1, V SMAX is 1V (the current limit voltage of theISL6752); this is the ideal reset voltage. In practice, however, the parasitic capacitance of the output windings suppresses the peak voltage, and consequently, the reset time increases. If a custom current sensing transformer is designed, the effects of the parasitic capacitance can be minimized by increasing the space between turns. If a standard, off-the-shelf transformer is used, however, the output capacitance may be too large to allow long duty cycles. In this case, the two-transformer solution may be necessary.Notice in Figure 19 that the 400V RTN is slightly more negative than signal ground. This configuration is recommended for applications that directly drive the bottom FETs with MOSFET drivers. If the 400V RTN and the MOSFET drivers are grounded, regenerative feedback will be present on the output of the MOSFET drivers because of the CT windings in the gate drive loop.A variation on the current sense circuit in Figure 19 is to place the current sensing transformer in the common drain lead of the two high-side FETs, as shown in Figure 20.The circuits shown in Figures 19 and 20 give exactly the same performance, but the problem associated with the gate drives (as explained in Figure 19) is avoided. The disadvantage of placing the CT at this location is that the CT must be designed with400VDC operational insulation.ConclusionThis application note reviews the use of MOSFETs as synchronous rectifiers to replace conventional diodes. The advantages of improved power efficiency and load transient are reviewed along with implementation problems that must be solved.The use of daughter cards for the ISL6752 and ISL6754 control ICs also allows comparison of cycle-by-cycle peak current limiting and average current limiting.TRANSFORMERSFIGURE 19.CURRENT SENSING TRANSFORMER IN THE COMMON SOURCE LEAD0.980.02⁄()V SMAX49V=•(EQ. 1)FIGURE 20.DRAIN LEADReferences[1]Fred Greenfeld, Intersil Application Note AN1246,“Techniques to Improve ZVS Full-bridge Performance”[2]Fred Greenfeld, Intersil Application Note AN1262, “Designingwith the ISL6752, ISL6753 ZVS Full-bridge Controllers”[3]Richard Garcia, Intersil Application Note AN1619, “Designingwith ISL6752DBEVAL1Z and ISL6754DBEVAL1Z ControlCards”Evaluation Board Set-upThe following sections cover the set-up of theISL6752/54EVAL1Z evaluation board. Also included are waveforms, performance parameters, PCB layout, and schematics.Setting UpLab Equipment Required•DC bias power supply, 12.6VDC @ 200mA minimum •Adjustable 0VDC-400VDC regulated lab power supply, 2.5ADC minimum with current limit•Fan to cool heatsinks•Oscilloscope, digital preferred, with 4 channels, 20MHz minimum bandwidth•Adjustable DC load (electronic or resistor), 70A @ 12V,100A @ 0V min, >850W•DC Multimeter•Infra-red temperature probe (optional but highly recommended)Turn-On Procedure1.Solder a wire between DISABLE and PGND-1 lugs located onthe lower left side of the main board. Optionally connect a switch between these two lugs.2.Install either of the daughter control cards onto the mainboard.3.Connect the DC load to the outputs of the evaluation board.Adjust the load to zero current.4.With both supplies turned off, connect the DC bias supply tothe +13V terminal and PGND.5.Connect the 400V supply to +400V and 400V RTN.6.Turn on the DC bias supply and adjust the current limit to200mA. Adjust the voltage to +12.6 VDC. The lab supplycurrent should be approximately 150mA.7.Turn on the 400V supply and adjust the current limit to 2.5A.Adjust the voltage to 400VDC. Do not exceed 450VDC. The current should be approximately 45mA.8.Turn on the fan and direct the air flow through the heatsinksmounted on the bottom of the board.ing the test points that are adjacent to the output powerlugs, measure the output voltage of 12V ±0.5VDC.The output load and input voltage can now be safely adjusted. Because there is no thermal shut-down circuit, it is important to maintain adequate airflow over the heatsinks, especially when applying large loads. It is recommended to measure the temperature of the power FETs (primary bridge and secondary SRs) to ensure that their temperatures do not exceed +85°C. It is usually necessary to have only a moderate airflow over the heatsinks, even under worst-case loads.Danger•This evaluation unit should be used and operated only by persons experienced and knowledgeable in the design and operation of high voltage power conversion equipment. •Use of this evaluation unit constitutes acceptance of all risk inherent in the operation of equipment having accessible hazardous voltage. Careless operation may result in serious injury or death.•Use safety glasses or other suitable eye protection.•A line isolated 400VDC supply is required. CautionA voltage clamp, D3, is used to protect the primary side control circuit from catastrophic damage should the high voltage bridge fail. In order to prevent this clamp from conducting, do not adjust the bias supply above 13.5VDC.WaveformsZVSIn Figure 21, the drain-source voltage of the low-side FETs relative to the gate voltage is displayed to highlight the ZVS performance of the bridge. The load is at the rated 50A. Notice that full ZVS is not achieved because the minimum resonance voltage is about 25VDC. Also, the gate drive is turning on late (about 25ns), allowing the resonant voltage to start rising. Eventhough the optimum zero voltage switching is not achieved, 98% of the switching losses are still recovered [(4002-502)/4002=98%]. This improvement over the ISL6752EVALZ was achieved by increasing the leakage inductance of thetransformer and by using bridge FETs with less body capacitance.In Figure 22, resonant switching with 50% load still saves 84% of the switching losses. Other techniques can be used to improve ZVS performance. For more information, see Application NoteAN1246, “Techniques to Improve ZVS Ful-bridge Performance”.ZVS WaveformsFIGURE 21.RESONANT SWITCHING WITH 100% (50A) LOADFIGURE 22.RESONANT SWITCHING WITH 50% (25A) LOADLoad Transients WaveformsFIGURE 23.STEP LOAD: 0A TO 12.5A (12.5A DELTA)FIGURE 24.STEP LOAD: 25A TO 37.5A (12.5A DELTA)FIGURE 25.STEP LOAD: 37.5A TO 50AFIGURE 26.STEP LOAD: 0A TO 25AFIGURE 27.STEP LOAD: 0A TO 50AFIGURE 28.SHORT CIRCUIT RELEASE WITH ISL6754V OUT recovers after a short circuit is removed when using the ISL6754DBEVAL controller.After the short is removed, V OUT increases linearly because the output capacitance is being charged with a constant current (~55A).NOTE:Output Ripple and Noise WaveformsFIGURE 29.OUTPUT RIPPLE, 50A LOAD, 40MHz BANDWIDTHFIGURE 30.OUTPUT RIPPLE, 50A LOAD, 145MHz BANDWIDTHTransformer Current, Primary Winding WaveformsFIGURE 31.PRIMARY TRANSFORMER CURRENT vs OUTPUT LOAD TRANSIENT (25A TO 50A)FIGURE 32.PRIMARY TRANSFORMER CURRENT vs OUTPUT LOAD TRANSIENT (50A TO 25A)Performance CurvesFIGURE 33.POWER EFFICIENCY vs LOAD (ISL6752 OR ISL6754)FIGURE 34.LOAD REGULATION FIGURE 35.PULSE BY PULSE vs AVERAGE CURRENT LIMIT21015202570758085909295100OUTPUT CURRENT (A)E F F I C I E N C Y (%)6560555030354045505592% EFFICIENCY WITH 20% LOAD12.0011.9511.9011.8511.80ISL6754ISL6752102030405060I OUT (A)V O U T (V )01020304050607080I OUT (A)V O U T (V )121086420ISL6754ISL6752Application Note 1603Bill of MaterialsPART NUMBERQTY UNITS REFERENCE DESIGNATORDESCRIPTION MANUFACTURER MANUFACTURER PART ISL6752/54EVAL1ZREVBPCB1eaPWB-PCB,ISL6752_54EVAL1Z, REV B, ROHSIMAGINEERING INCISL6752/54EVAL1ZREVBPC BC3216X7R1C475K-T 2eaC11, C17CAPACITOR, SMD, 1206, 4.7µF, 16V, 10%, X7R, ROHSTDK C3216X7R1C475KC4532X7R2J104K-T 2ea C5, C18CAP, SMD, 1812, 0.1µF, 630V, 10%, X7R, ROHSTDKC4532X7R2J104K GA355QR7GF332KW01L-T 2ea C20, C121CAP, SMD, 2220, 3300pF, 250V, 10%, X7R, ROHSMURATA GA355QR7GF332KW01L H1046-00102-100V10-T 2ea C14, C15CAP, SMD, 0805, 1000pF, 100V, 10%, X7R, ROHSVENKEL C0805X7R101-102KNE H1046-00102-50V5-T 2ea C9, C10CAP, SMD, 0805, 1000pF, 50V, 5%, NP0, ROHS PANASONIC ECU-V1H102JCX H1046-00105-25V10-T 5ea C6, C12, C13, C16, C22CAP, SMD, 0805, 1.0µF, 25V, 10%, X5R, ROHS AVX 08053C105KAT2A H1065-00106-25V10-T 1ea C123, C132CAP, SMD, 1206, 10µF, 25V, 10%, X5R, ROHS VENKEL C1206X5R250-106KNE H1082-00475-50V10-T 4ea C7, C8, C127, C129CAP, SMD, 1210, 4.7µF, 50V, 10%, X7R, ROHS MURATA GRM32ER71H475KA88L SER2814L-332KL2eaL102, L103COIL-PWR INDUCTOR, SMD, 3.3µH, 10%, 48A, 1.2m Ω, ROHS COILCRAFTSER2814L-332KLUUG1C222MNL1ZD 4ea C133-C136CAP, SMD, 16X16.5, 2200µF, 16V, 20%, AL.EL., ROHS NICHICON UUG1C222MNL1ZDUUG2W330MNL1MS 4ea C1-C4CAP, SMD, 18X21.5, 33µF, 450V, 20%, ALUM.ELEC, ROHS NICHICON UUG2W330MNL1MS131-4353-001ea VOUT CONN-SCOPE PROBE TEST PT, COMPACT, PCBMNT, ROHSTEKTRONIX 131-4353-001514-26eaa) 13VDC, 400VDC, PGND-1, PGND-2, DISABLE CONN-TURRET, TERMINAL POST, TH, ROHSKEYSTONE 1514-21514-20ea b) 400VDC_RTNCONN-TURRET, TERMINAL POST, TH, ROHSKEYSTONE 1514-250029ea a) CS+, VREF, OUTLL, OUTLR, OUTUL, OUTUR CONN-MINI TEST POINT, VERTICAL, WHITE, ROHS KEYSTONE500250020ea b) SR_EN, OUTLLN, OUTLRNCONN-MINI TEST POINT, VERTICAL, WHITE, ROHSKEYSTONE 50025016-T13eaa) GLL, GLR, LLN, LRN, SR_A, SR_B, PGND-3, 2, +12VOUT, 12V RTN CONN-COMPACT TEST POINT, SMD, ROHS KEYSTONE50165016-T 0ea b) SGND-1, SGND-CONN-COMPACT TEST POINT, SMD, ROHSKEYSTONE 50165016-Teac) L_PHASE, R_PHASE CONN-COMPACT TESTPOINT, SMD, ROHSKEYSTONE5016。

电能质量分仪技术参数对照表

电能质量分析仪技术参数对照表公司共立日置日置測定項目・記録項目型号KEW63103197电能质量分析仪3196电能质量分析仪外観電圧(測定ﾚﾝｼﾞ)○(150/300/600/1000V)○(600Ｖ)○(60(仅CH4)/150/300/600Ｖ)電圧測定確度±0.3％rdg.±0.2％f.s.±0.3％rdg.±0.2％f.s.AC:±0.2％rdg.±0.1％f.sDC:±0.3％rdg.±0.4％f.s 电流○○○电流测试精确度±0.3％rdg.±0.2％f.s.+传感器精确度±0.3％rdg.±0.2％f.s.+传感器精确度±0.2％rdg.±0.1％f.s.+传感器精确度(传感器种类)12种8128(5A:φ24mm)、8141(1000mA:φ24mm)8127(100A:φ24mm)、8142(1000mA:φ40mm)8126(200A:φ40mm)、8143(1000mA:φ68mm)8125(500A:φ40mm)、8146(30A:φ24mm)8124(1000A:φ68mm)、8147(70A:φ40mm)8129(3000A)、8148(100A:φ68mm)7种9660(100Aφ15)9661(500Aφ46)9669(1000Aφ55)9667(5000A:自制φ254)9694(5Aφ15)9695-02(50Aφ15)9695-03(100Aφ15)5种9660(100Aφ15)9661(500Aφ46)9669(1000Aφ55)9667(5000Aφ254)9694(5Aφ15)频率(测试范围)○(40～70Hz)○(45～66Hz)○(42.5～69Hz)有功功率○○○电力测试精确度±0.3％rdg.±0.2％f.s+传感器精确度±0.3％rdg.±0.2％f.s+传感器精确度±0.2％rdg.±0.1％f.s+传感器精确度视在功率○○○有功电量○○○无功电量○○○功率○○○Class A+A2:2001+A3:2003 CLASS AEN61000-3-2:2000EN61000-3-3:1995+A1:2001+A2:2001CLASS AEN61000-3-2:2000EN61000-3-3:1995+A1:200 1安全规格(安全性)EN61010-1:2001CATⅢ600Ｖ汚染度2EN61010-1:2001CATⅢ600ＶCA TⅣ300Ｖ汚染度2EN61010-1:2001CATⅢ600Ｖ汚染度2可在1个画面中确认EN50160规定的电能质量的各项目的功能×其他充電電池(連続5時間):単三アルカリ電池充电电池(连续6小时):电池包定价(1欧元＝120円)本体价格18万円本体价格46万円市场价软件KEW POWER PLUS2(付属)9624-50PQA分析软件６万円9624-50PQA分析软件６万円可选件测试线电源供给线测试线电源供给线9722:5500円电能质量分析仪技术参数对照表2公司日置横河FLUKE測定項目・記録項目型号3169电力质量分析仪CW240电力计FLUKE434/433外観電圧(測定ﾚﾝｼﾞ)○(150/300/600Ｖ)○(150/300/600/1000V)○(1～1000V)電圧測定確度±0.2％rdg.±0.1％f.s.±0.2%rdg±0.1rng基准電圧の0.5％电流○○○电流测试精确度±0.2％rdg.±0.1％f.s.+传感器精确度(96030,31,33,36)±0.6%rdg ±0.4rng(96032,34,35)±1.0%rdg ±0.8rng±1％±5计数(传感器种类)7种9660(100Aφ15)7种i400s(400A)*4个(标准配置)测试线电源供给线9722:5500円测试线电源供给电能质量分析仪技术参数对照表3公司法国CA公司法国CA公司測定項目・記録項目型号CA8334电能质量分析仪CA8335电能质量分析仪外観電圧(測定ﾚﾝｼﾞ)AC线电压：960VacAC相电压：480VacDC电压：680VdcAC线电压：2000VacAC相电压：1000VacDC电压：1000Vdc電圧測定確度AC: ±(0.5% ±2个字)DC: ±(1% ±0.2V)AC: ±(0.5% ±2个字)DC: ±(1% ±5个字)电流○ 三通道○ 四通道电流测试精确度依据各电流钳- MN93A：±(0.5%+2个字)- AmpFlex(>10A)：±(0.5% +1A)- C193：±(0.5%+2个字0- PAC93:交流：±(0.5% +1A)直流：±(1.5%+1A)依据各电流钳- MN93A：±(0.5%+2个字)- AmpFlex(>10A)：±(0.5% +1A)- C193：±(0.5%+2个字0- PAC93:交流：±(0.5% +1A)直流：±(1%+1A )(传感器种类)4种MN93A: 5mA-120Aac或MN93：2A~200AAmpFLEX A193(45cm/80cm):10A~6500AacC193:3~1200AacPAC9310~1000Aac4种MN93A: 5mA-120Aac或MN93：2A~200AAmpFLEX A193(45cm/80cm):10A~6500AacC193:3~1200AacPAC9310~1000Aac。

6754aaz引脚说明

6754aaz引脚说明电源集成块STRW6754A引脚功能STR-W6754A为内藏功率MOSFET和控制器，以准共振方式工作的开关电源用厚膜集成电路。

通常工作以准共振或BottomSkip准共振动作，实现了开关电源的高效率，低噪声等优良性能，待机时以间歇振荡方式工作以降低待机功率。

使用该IC可以大量减少电源元件的数量，简化电路的设计。

一、特点1、在待机的状态下，当输出电压下降时电源以间歇振荡方式工作以降低待机功率。

2、在原来的准共振工作方式的基础上增加了BottomSkip功能，改善了高电压输入时的电源效率。

3、电源启动时，以SOFT-START方式启动。

4、内藏STEP-DRIVER功能以减小开关噪声。

5、使用SENSE-MOSFET，不需要漏极电流检测用的电阻，且可以做到过电流保护的调整。

6、内藏过电流保护电路，过电压保护电路，过负载保护电路，和最大的ON时间限制电路。

7、保证MOSFET 的雪崩耐量。

二、IC引脚介绍：记号名称功能1、DMOSFET漏极端子开关管漏极D2、NC3、S、GNDMOSFET源极端子、GND控制器GND4、VCC电源端子启动电路5、SS、ADJSOFT-START、过电流保护调整端子6、FB反馈端子7、BDBottom检测端子三、启动原理启动电路检测VCC端子（4号端子）的电压，控制IC的动作开始和停止。

当AC电源输入以后，AC输入电压通过启动电阻R803对C808充电。

当C808的电压达到启动开始电压VCC（on）=18V时，STR-W6754A开始工作，开关管开始有开关动作。

随着输出电压和辅助绕组电压的上升，由辅助绕组给IC供电。

1、关于启动①由于IC的启动电流很小，R803可使用高阻值的电阻，来降低待机功耗。

但是要注意R803要向IC提供足够的锁定电路保持电流，特别是低电压输入的时候能向IC提供100UA以上的电流。

②由于STR-W6754A要求的工作电流很小，因此C808不需要很大的电容。

HC(LC)1S-POWER(Y6754)常规测试数据

测试电压分别为交流3500V，漏电流小于5mA；直流500V，漏电流小于1mA。测试时间为1分钟。测试后不能有火花，电弧出现，测试完成后检查所有性能均正常
AC=3750V
输入－PE
1.6mA
OK
输出－PE
1.73mA
输入－输出
1.35mA
DC=500V
输入－PE
0.01mA
输出－PE
0.01mA
输入－输出
输入电压Ui（V）
输出电压Uo（V）
电压稳定度△Uo/Uo
OK
启动电压
V1=23.7
0.4％
V2=23.9
110
V1=23.7
V2=23.9
220
V1=23.7
V2=23.8
265
V1=23.7
V2=23.8
6.负载调整
功率表，被测电压，负载依次接入电路。输入电压为额定范围内的任何值，记录输入电压及输出电压
所确定的测试点各进行一次跌落,每跌落一次均须对其电气及绝缘等进行确认,
记录正常或异常结果
1000mm+10mm是为满足手捂式,拔插式,可携带式需求的设备测试.
跌落条件可参考安规标准要求
1
2
3
4
5
6
跌落后机械性能和电气性能
23.高温带电老化试验
a.环境温度：根据电源运用的区域选用55+/-2℃
b.输入电压：最小输入电压，额定输入电压，最高输入电压
功率因数P/(Ui*Ii)
效率Po/Pi
OK
85
0.84
48.1
V1=23.75
0.8
0.66
0.79
V2=23.84
220

简单而准确的毫伏表直读电感量测试仪

【参赛】简单而准确的毫伏表直读电感量测试仪。

[复制链接]66718金牌会员∙串个门∙加好友∙打招呼∙发消息电梯直达1#发表于 2012-11-30 10:25:19 |只看该作者 |倒序浏览本帖最后由 biterliu 于 2012-12-1 22:55 编辑玩无线电多年，第一的过程中避免不了的要自制一些电感，一直以来都想做一个电感量测试仪。

可是翻遍几个常去的论坛，找百度搜索，关于电感量测试仪的帖子非常少，即使有，也都是用单片机来完成的，可是我不懂单片机编程，而且想液晶屏一类的配件，我地处偏僻的小县城，很难买到。

一直想找一个简单而又准确的电感量测试方案。

当然是不要用单片机，我不会编程玩不转。

终于在一个外国的qsl网站上看到一个简单的电感测试仪，当然只有一副电路原理图的图片，没有任何的文字说明，（有说明，也没用，我不懂英文，呵呵）手头也没有图中的74HC132，看图纸其实这个电路也就是把与非门当非门在用，搞清楚了电路的原理，我想用74HC04就可以了。

跑遍本地电子市场，只搞到两块74HC04，而且好像还是打磨的，重新印字上去的，唉。

立即动手实验，发现按原电路不行，震荡频率严重偏高，在1.几兆，反复修改电路，终于将频率降到100KHZ。

下面是我实际改进的74HC04版的电路图。

下面是1uH，22uH的实际测试结果。

原理：电路原理其实很简单，非门1构成一个100KHZ左右的振荡器，非门2是缓冲，R3与被测电感构成一个微分电路，经过非门3将微分的尖脉冲变成，脉冲宽度与电感量成比例的矩形波，非门4缓冲反向，R4与C3（0.47UF）组成积分电路，将脉冲宽度转变成电压输出。

基本是线性变化的1uH=1mV。

我没有标准的测试电感，做校准，只是随手找了一个33uH的色码电感做校准，误差比较大，实际测试结果。

几个注意事项：1，电源比较重要，因为测试结果是mV级的，如果电源文波大的话，会影响测试结果，最好不要用开关电源供电。

《直流表测试数据》word版

电表测试记录1.电表基本信息1.1. 生产厂家及型号1.2. 电表外形尺寸×85mm[厚]；三相电表国网企标Q/GDW356-2009规定的尺寸有2个：规格一：290mm[高] ×170mm[宽] ×85mm[厚]，适用于不带本地费控功能的三相电表；规格二：290mm[高] ×170mm[宽] ×85mm[厚]，适用于其他功能的三相电表；1.3. 电表所支持通信协议注：通信协议要求DL/T645-2007版必须支持，DL/T645-1997为可选支持项。

结论：通过■不通过1.4. 电表工作温度范围要求要求电表标称的正常工作温度最少要在-20~55℃可正常工作，极限工作温度最少在-30~70℃范围。

将电表放入高低温箱，连接工作电源及通信线，在厂家的标称工作温度范围测试电表是否可正常工作及通信，看是符符合标称范围，每个温度点测试时间不小于2小时。

结论：■通过不通过2.通信协议测试2.1. 波特率2.1.1.出厂默认通信波特率要求电表的出厂默认波特率为2400BPS结论：■通过不通过2.1.2.要求用电表抄表软件可修改通信波特率波特率可修改：1200BPS 2400BPS 4800BPS 9600BPS结论：■通过不通过2.2. 通信地址2.2.1.要求默认的单机通信地址为电表号结论：■通过不通过2.2.2.要求支持缩位寻址AA AA AA AA AA AA地址读取电量信息下发命令帧：FE FE FE FE 68 AA AA AA AA AA AA 68 11 04 33 32 34 33 AD 16返回格式：FE FE FE FE 68 26 16 00 00 15 20 68 91 18 33 32 34 33 98 33 33 33 33 33 33 33 33 33 33 33 98 33 33 33 33 33 33 33 7C 16左图是用串口发寻址指令，无反应上图是，用ec32和直流表通信，再用串口读RS485的报文，下面3图是信号波形，最后一幅图是去掉USB线后的波形结论：通过■不通过2.3. 电量信信读取要求用抄表软件可读取到所有数据，如下信息需要单独重点确认是否支持序号数据标识数据项名称确认结果DI3 DI2 DI1 DI01 00 00 00 00当前组合有功总电能■通过00 00 FF 00当前有功电能数据块■通过结论：通过■不通过2.4. 与EC32监控器通信测试用IARM-EC32与电表通信，要求电表能与EC32正常通信并获取到正确的电量信息。

福禄克 LCR55A 电阻电容电感测试仪数据表

技术资料
LCR55A 电阻电容电感测试仪
主要特性
测量电感、电容、电阻、晶体管、二极管和微波二极管
插入式测试槽和带螺纹连接鳄鱼夹的测试线
高清大数字屏幕
如万用表般便携方便移动
数据保持和最大值保持
欧姆功能“调零”杆
低电量提示
自动关机
可选配TPCN磁性挂件解放双手
产品概述: LCR55A 电阻电容电感测试仪
LCR55A 电阻电容电感测试仪，可用于测量电感、电容、电阻、晶体管、二极管和微波二极管。

具有数据保持和最大值保持，以及欧姆调零功能。

如万用表般便携外观，方便移动和现场测试。

产品规格: LCR55A 电阻电容电感测试仪电气技术指标
(规定精度条件：23 °C ± 5 °C，<75 % RH)
hFE 基极电流 5 μA，约值hFE 电压 C-E 3.0 V DC，约值lceo 量程，漏电流10 nA 至 20 μA
型号
LCR55A 电阻电容电感测试仪LCR55A 测试仪
测试表笔
红黑鳄鱼夹一对
用户手册
TPCN磁性挂件（选配）
Fluke. 让您的工作畅通无阻。

福禄克测试仪器（上海）有限公司电话：400-810-3435北京福禄克世禄仪器维修和服务有限公司电
话：400-615-1563
福禄克测试仪器（上海）有限公司上海维修中心电
福禄克测试仪器（上海）有限公司深圳第一特约维修点©2024 福禄克公司
12/2024
未经许可，本文档禁止修改。

开关电源芯片通用测试要求和步骤-antonychen概论

开关电源芯片通用测试要求和步骤By Antony Chen开关电源必须通过一系列的测试，使其符合所有功能规格、保护特性、安规（如UL、CSA、VDE、DEMKO、SEMKO，长城等之耐压、抗燃、漏电流、接地等安全规格）、电磁兼容（如FCC、CE等之传导与幅射干扰）、可靠性（如老化寿命测试）、及其他特定要求等。

测试开关电源是否通过设计指标，需要各种精密的电子设备去模拟电源在各种环境下实际工作中的性能。

一、理论上的DCDC测试指标清单1.描述输入电压影响输出电压的几个指标形式（line）1.1绝对稳压系数：K=△Uo/△Ui1.2相对稳压系数：S=△Uo/Uo / △Ui/Ui1.3电网调整率（也称线性调整率）：它表示输入电网电压由额定值变化+-10%时，稳压电源输出电压的相对变化量，有时也以绝对值表示。

line reg=△Uo/Uo*100%@ -10%<Ui<+10%1.4电压稳定度：负载电流保持为额定范围内的任何值，输入电压在规定的范围内变化所引起的输出电压相对变化△Uo/Uo(百分值)，称为稳压器的电压稳定度。

STB=△Uo/Uo*100%@ 0<I load<max2.负载对输出电压影响的几种指标形式（load）2.1负载调整率(也称电流调整率)在额定电网电压下，负载电流从零变化到最大时，输出电压的最大相对变化量，常用百分数表示，有时也用绝对变化量表示。

2.2输出电阻(也称等效内阻或内阻)在额定电网电压下，由于负载电流变化△IL 引起输出电压变化△Uo，则输出电阻为Ro=|△Uo/△IL|Ω3.纹波电压的几个指标形式（ripple）3.1最大纹波电压在额定输出电压和负载电流下，输出电压的纹波(包括噪声)的绝对值的大小，通常以峰峰值或有效值表示。

V ripple=V MAX-V MIN3.2纹波系数Y(%)在额定负载电流下，输出纹波电压的有效值Urms 与输出直流电压Uo 之比，即Y=Umrs/Uo x100%3.3纹波电压抑制比（PSRR：Power Supply Rejection Ratio）在规定的纹波频率(例如50HZ)下，输入电压中的纹波电压Ui~与输出电压中的纹波电压Uo~之比，即：纹波电压抑制比=Ui~/Uo~ 。

三相表功能和性能检测报告

产品性能和功能检测报告产品名称：型号规格：检验单位：检验类别：验证日期：检定人：审核人：一、检验标准：二、质量问题记录三、试验项目汇总四、性能试验1基本误差1.1技术要求：GB-T17215.322-2008静止式有功电能表(0.2S级和0.5S级) 1.2试验方法：标准表度量法2常数试验2.1技术要求：GB-T17215.322-2008静止式有功电能表(0.2S级和0.5S级) 2.2试验方法：标准表度量法3启动试验3.1技术要求：GB-T17215.322-2008静止式有功电能表(0.2S级和0.5S级) 3.2试验方法：标准表度量法3.3试验结论：4潜动试验4.1技术要求：GB-T17215.322-2008静止式有功电能表(0.2S级和0.5S级) 4.2试验方法：标准表度量法5日计时误差5.1技术要求：GB-T17215.322-2008静止式有功电能表(0.2S级和0.5S级) 5.2试验方法：5.3试验结论：6工频耐压试验7.1技术要求：GB/T 17215.211-2006《交流电测量设备通用要求》7.2试验方法：GB/T17215.301-2007 多功能电能表特殊要求7.3试验结论7静电放电抗扰度试验7.1技术要求：GB/T 17215.211-2006《交流电测量设备通用要求》7.2试验方法：GB/T17626《电磁兼容试验和测量技术》8电快速瞬变脉冲群抗扰度试验8.1技术要求：GB/T 17215.211-2006《交流电测量设备通用要求》8.2试验方法：GB/T17626《电磁兼容试验和测量技术》9浪涌抗扰度试验9.1技术要求：GB/T 17215.211-2006《交流电测量设备通用要求》 9.2试验方法：GB/T17626《电磁兼容试验和测量技术》10射频电磁场辐射抗扰度10.1技术要求：GB/T 17215.211-2006《交流电测量设备通用要求》 10.2试验方法：GB/T17626《电磁兼容试验和测量技术》11射频场感应的传导骚扰抗扰度11.1技术要求：GB/T 17215.211-2006《交流电测量设备通用要求》11.2试验方法：GB/T17626《电磁兼容试验和测量技术》12衰减振荡波抗扰度12.1技术要求：GB/T 17215.211-2006《交流电测量设备通用要求》12.2试验方法：GB/T17626《电磁兼容试验和测量技术》13高低温试验13.1技术要求：GB/T 17215.211-2006《交流电测量设备通用要求》13.2试验方法：GB/T2423 电工电子产品环境试验实验记录14功耗14.1技术要求：PD1008-9S4AK多功能(网络)电力仪表用户手册V1.0 14.2试验方法：标准表度量法15快速上下电试验15.1.技术要求: 快速上下电后仪表能够正常工作15.2.试验方法: 使用上下电工具进行快速上下电试验五、功能测试1显示2瞬时量检测3电能检测4需量计算5结算日检测6事件记录7通信8清零9广播10其他。

ZVS全桥控制IC-ISL6754

ISL6754比ISL6752增加了四个引脚，加入了许多更优秀的功能。

用于大功率控制电路作PWM-IC。

同样它驱动高边MOS在各50%占空比这下工作，而两个低边MOS采用后沿调制并可调节谐振开关的延迟。

ISL6754比ISL6752增加了软启动功能端（SS），平均电流信号可以用于平均电流限制，电流均衡控制，及平均电流型控制的PWM。

此外ISL6754也可以支持电压型控制，它控制二次侧的同步整流时可以更好地做到ZVS模式。

ISL6754有更准确的死区时间和谐振延迟控制，振荡器最高到2MHZ，此外，多脉冲抑制可以确保两交替输出的脉冲正常进入跳周期模式工作，此为降低空载功耗。

主要特点列出如下：*调节谐振延迟，确保ZVS开关。

*同步整流驱动可调延迟。

*可以电压型，也可以电流型控制。

* 3%的限流阀值。

*可调平均电流限制。

*可调死区时间控制。

* 175uA的起动电流。

* VCC供电的UVLO保护。

*可高达2MHZ的工作频率。

*芯片过热保护。

*振荡器锯齿波输出缓冲器。

*最快速电流检测。

*逐个周期式限流保护。

* 70ns的前沿消隐。

（电流型）*多脉冲抑制。

ISL6754内部电路框图如图1，典型应用电路如图2。

图1ISL6754内部等效方框电路各引脚功能如下：*VDD---IC供电端，加旁路电容到GND。

用瓷介电容紧靠VDD和GND。

*GND---IC公共端，信号地，功率地采用一个端子。

由于在高峰值电流及高频工作台，必须要一个低阻抗布局接地线尽量短。

*VREF---5V基准电压端。

有3%的偏差。

要用0.1---2.2uF的瓷电容旁路。

*C T---振荡器定时电容端。

外接于此端到GND，由内部200uA电流源充电，放电速率由R T D电阻决定。

*RTD---振荡器定时电容放电电阻，接于此端到地。

决定CT电流放电幅度，最小为20*电阻电流。

PWM死区由定时电容放电时间给出。

R T D电压通常为2V。

*CS---此输入送到过流比较器，过流比较器阀值定为1V，CS端短路到地时将终止PWM输出，取决于检测源阻抗，输入电阻可给内部时钟和外部功率开关这间加入延迟，此延迟结果令CS开始在功率开关判断之前放电。

Y584 单相电参数综合测量仪操作规程

一、目的广泛适用于洗衣机、电冰箱、空调器、电风扇、节能灯、吸排油烟机等家用电器生产厂家、照明电器生产厂家、电机、变压器等电器生产厂家。

也可以作为实验室、新产品开发、产品质量监督等部门的分析设备。

本系列仪表可用来测量出口产品（110V/60Hz、220V/50Hz）的电量指标。

二、仪器设备1、单相电参数综合测量仪：包括单相电参数综合测量仪1台。

三、操作说明3.1 测试前准备3.1.1 安全检查（1）测试工位应与其他工位分离且铺设绝缘地垫，非测试者严禁进入测试工位。

（2）测试者应佩戴绝缘手套。

（3）电源良好接地（4）操作者应接受过相关的安全知识培训。

（5）所有连接操作必须确保仪器无输出时进行，严禁测试中插拔测试线和被测电器。

3.1.2被测负载连接先将被测负载的电源开关断开再进行如下操作；将连接线的一端与被测负载连接；将连接线的另一端与测量仪的负载端子连接；3.2 开机3.2.1被测负载电源连接（1）请确认负载电源的输出开关为断开状态后再进行如下操作；（2）将连接线的一端与测量仪的负载电源端子连接；（3）将连接线的另一端与电源输出端连接；3.3参数设置3.3.1自动报警功能电参数测量仪的自动报警功能就是在测量仪检测到测量参数超出设置参数的上、下限时，测量仪自动发出声、光报警。

3.3.2设置报警操作（1）有报警功能的仪表前面板上会有“设置”、“加”、“减”三个键，按“设置”键选择需设置的报警参数，按“加”、“减”键修改相应的限值。

（2）设置报警值时，先按“设置”键进入设置状态，对应上下限指示灯选择需要设置参数的上下限值；继续按“设置”键选择需要设置的报警参数，按“加”、“减”键可进行修改。

单击“加”、“减”键，则参数值变动一个字，按住“加”或“减”键，则参数值快速增减。

若无需修改再按“设置”键跳过。

（3）当设置与电流、功率有关的值时，按“手/自动”键，可切换mA、A或W、kW。

（4）按“功能”键可在基本设置与功能设置间来回切换。

直流开关电源的测试方法

直流开关电源的测试方法发布：明伟技术部添加时间：2007年10月2日直流开关电源是一种将交流电源转换成所需直流V/A/W规格的装置。

一个良好的电源必须可靠、符合所有功能规格、保护特性、安全规范及电磁兼容能力等。

本文主要讨论电源的功能规格及保护特性的测试。

一、电源的功能测试1．输出电压调整制造开关电源时，第一个测试步骤为将输出电压调整至规格范围内。

此步骤完成后才能确保后续的规格能够符合。

通常，做输出电压调整时，将输入交流电压设定为正常值(115Vac或230Vac)，并且将输出电流设定为正常值或满载电流，然后用数字电压表测量电源的输出电压值并调整其电位器(VR)直到电压读数在要求范围内。

2．电源调整率电源调整率的定义为电源在输入电压变化时提供稳定输出电压的能力。

为精确测量电源调整率，需要下列的设备：A．能提供可变电压能力的电源，至少能提供待测电源的最低到最高的输入电压范围。

B．一个均方根值交流电压表用来测量输入电源电压。

C．一个精密直流电压表，具备至少高于待测物调整率十倍以上。

D．连接到待测电源输出端的可变负载。

测试步骤如下，待测电源在正常输入电压和负载情况下热机稳定后，分别于Min（低）Nomal(通常)，和Max(高)输入电压下测量并记录其输出电压值。

电源调整率通常在一正常之固定负载(Nommal Load)下，看具输入电压变化所造成电源输出电压偏差率(deviation)的百分比。

3．负载调整率负载调整率的定义为电源在输出负载电流变化时，其提供稳定输出电压的能力。

所需的设备和连接方式与测电源调整率相似，唯一不同的是需要精密的电流表和与待测电源的输出串联。

测试步骤如下：待测电源在正常输入电压及负载情况下热机稳定后，测量正常负载下的输出电压值，再分别于低(Min)、高(Max)负载下，测量并记录其输出电压值(分别为Vmax与Vmin)。

负载调整率通常以正常的固定输入电压下，由负载电流变化所造成电源输出电压偏差率的百分比。

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