STM32F407引脚图
(完整版)stm32f407引脚分配表
OLED/CAMERA接口的D1脚
98
PC8
SDIO_D0
DCMI_D2
N
1，SD卡接口的D0
2，OLED/CAMERA接口的D2脚
99
PC9
SDIO_D1
DCMI_D3
N
1，SD卡接口的D1
2，OLED/CAMERA接口的D3脚
111
PC10
SDIO_D2
N
SD卡接口的D2
112
PC11
SDIO_D3
PF6
GBC_KEY
Y
接ATK-MODULE接口的KEY脚
19
PF7
LIGHT_SENSOR
N
接光敏传感器(LS1)
20
PF8
BEEP
N
接蜂鸣器(BEEP)
21
PF9
LED0
N
接DS0 LED灯(红色)
22
PF10
LED1
N
接DS1 LED灯(绿色)
49
PF11
T_MOSI
Y
TFTLCD接口触摸屏MOSI信号
如不用LAN8720，并去掉P9跳线帽，可以做普通IO用
该IO通过P9选择连接RS232还是RS485，并同时连接了PWM_DAC, 这里的RS232 TX脚是指SP3232芯片的TX脚，接STM32的RX脚
去掉P9跳线帽，可以做普通IO用
该IO可做DAC输出，同时也连接在OLED/CAMERA接口，如不插外设在OLED/CAMERA接口，
137
PB7
DCMI_VSYNC
Y
OLED/CAMERA接口的VSYNC脚
139
PB8
IIC_SCL
STM32F407VET6开发板原理图
R20 10K
R21 10K
R22 1K
R23 1K
R24 1K
PE10-SW1
PE11-SW2
PE12-SW3 LED1 led LED2 led LED3 led
USB-A
C27 10pF JT3 C28
SW1
SW2
SW3 PE13-LED1 PE14-LED2 PE15-LED3
C
R25 10K
C9 10pF R29 1M
PB10-SPI2-SCK 5 PC2-SPI2-MISO 7
3.3V R6 R7 R8 R9 R10 R11 10K 10K 10K 10K 10K 10K
PC8-------SDIO_D0 PC9-------SDIO_D1 PC10-----SDIO_D2 PC11-----SDIO_D3 PC12-----SDIO_CLK PD2------SDIO_CMD
1
2
3
4
5
6
U1 PE3-FLASH-CS PC2-SPI2-MISO 3.3V 1 2 3 4 CS VCC DO HOLD WP CLK GND DI W25Q128 8 7 6 5
3.3V C29 0.1uF U5 PA9-USART1-TX 3.3V C30 0.1uF 15 6 4 5 C14 10uF C20 0.1uF C21 0.1uF C22 0.1uF C23 0.1uF C24 0.1uF C25 0.1uF C26 0.1uF PA10-USART1-RX C31 0.1uF 11 12 10 9 GND VC2+ C2VCC V+ C1+ C116 2 1 3 14 13 7 8 C36 0.1uF C35 0.1uF J6 1 6 2 7 3 8 4 9 5 3.3V PC串口头，一般是DB9公头（DB9针） 一般，只用记住，2收3发5地。
stm32f407vet6数据手册_引脚图_参数
This is information on a product in full production. June 2013DocID022152 Rev 41/185STM32F405xxSTM32F407xxDatasheet - production dataFeatures•Core: ARM 32-bit Cortex™-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator™) allowing 0-wait state execution from Flash memory, frequency up to 168MHz, memory protection unit, 210DMIPS/1.25DMIPS/MHz (Dhrystone 2.1), and DSP instructions•Memories –Up to 1 Mbyte of Flash memory–Up to 192+4Kbytes of SRAM including 64-Kbyte of CCM (core coupled memory) data RAM–Flexible static memory controller supporting Compact Flash, SRAM, PSRAM, NOR and NAND memories•LCD parallel interface, 8080/6800 modes•Clock, reset and supply management – 1.8 V to 3.6 V application supply and I/Os–POR, PDR, PVD and BOR–4-to-26MHz crystal oscillator–Internal 16 MHz factory-trimmed RC (1% accuracy)–32 kHz oscillator for RTC with calibration–Internal 32 kHz RC with calibration•Low power –Sleep, Stop and Standby modes–V BAT supply for RTC, 20×32 bit backup registers + optional 4 KB backup SRAM•3×12-bit, 2.4MSPS A/D converters: up to 24 channels and 7.2MSPS in triple interleaved mode•2×12-bit D/A converters•General-purpose DMA: 16-stream DMA controller with FIFOs and burst support•Up to 17 timers: up to twelve 16-bit and two 32-bit timers up to 168MHz, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input •Debug mode –Serial wire debug (SWD) & JTAG interfaces –Cortex-M4 Embedded Trace Macrocell™•Up to 140 I/O ports with interrupt capability –Up to 136 fast I/Os up to 84MHz –Up to 138 5 V-tolerant I/Os •Up to 15 communication interfaces –Up to 3 × I 2C interfaces (SMBus/PMBus)–Up to 4 USARTs/2 UARTs (10.5Mbit/s, ISO 7816 interface, LIN, IrDA, modem control)–Up to 3 SPIs (42Mbits/s), 2 with muxed full-duplex I 2S to achieve audio class accuracy via internal audio PLL or external clock – 2 × CAN interfaces (2.0B Active)–SDIO interface •Advanced connectivity –USB 2.0 full-speed device/host/OTG controller with on-chip PHY –USB 2.0 high-speed/full-speed device/host/OTG controller with dedicated DMA, on-chip full-speed PHY and ULPI –10/100 Ethernet MAC with dedicated DMA: supports IEEE 1588v2 hardware, MII/RMII •8- to 14-bit parallel camera interface up to 54Mbytes/s •True random number generator •CRC calculation unit •96-bit unique ID •RTC: subsecond accuracy, hardware calendarTable 1. Device summary Reference Part number STM32F405xx STM32F405RG, STM32F405VG, STM32F405ZG, STM32F405OG, STM32F405OE STM32F407xxSTM32F407VG, STM32F407IG, STM32F407ZG,STM32F407VE, STM32F407ZE, STM32F407IERevision history STM32F405xx, STM32F407xx 176/185DocID022152 Rev 48 Revision historyTable 98. Document revision historyDateRevision Changes 15-Sep-20111Initial release.24-Jan-20122Added WLCSP90 package on cover page.Renamed USART4 and USART5 into UART4 and UART5,respectively.Updated number of USB OTG HS and FS in Table 2: STM32F405xxand STM32F407xx: features and peripheral counts .Updated Figure 3: Compatible board design betweenSTM32F10xx/STM32F2xx/STM32F4xx for LQFP144 package andFigure 4: Compatible board design between STM32F2xx andSTM32F4xx for LQFP176 and BGA176 packages , and removed note1 and 2.Updated Section 2.2.9: Flexible static memory controller (FSMC).Modified I/Os used to reprogram the Flash memory for CAN2 andUSB OTG FS in Section 2.2.13: Boot modes .Updated note in Section 2.2.14: Power supply schemes .PDR_ON no more available on LQFP100 package. UpdatedSection 2.2.16: Voltage regulator . Updated condition to obtain aminimum supply voltage of 1.7V in the whole document.Renamed USART4/5 to UART4/5 and added LIN and IrDA feature forUART4 and UART5 in Table 5: USART feature comparison .Removed support of I2C for OTG PHY in Section 2.2.30: Universalserial bus on-the-go full-speed (OTG_FS).Added Table 6: Legend/abbreviations used in the pinout table .Table 7: STM32F40x pin and ball definitions : replaced V SS _3, V SS _4,and V SS _8 by V SS ; reformatted Table 7: STM32F40x pin and balldefinitions to better highlight I/O structure, and alternate functionsversus additional functions; signal corresponding to LQFP100 pin 99changed from PDR_ON to V SS ; EVENTOUT added in the list ofalternate functions for all I/Os; ADC3_IN8 added as alternate functionfor PF10; FSMC_CLE and FSMC_ALE added as alternate functionsfor PD11 and PD12, respectively; PH10 alternate functionTIM15_CH1_ETR renamed TIM5_CH1; updated PA4 and PA5 I/Ostructure to TTa.Removed OTG_HS_SCL, OTG_HS_SDA, OTG_FS_INTN in Table 7:STM32F40x pin and ball definitions and Table 9: Alternate functionmapping .Changed TCM data RAM to CCM data RAM in Figure 18: STM32F40xmemory map .Added I VDD and I VSS maximum values in Table 12: Currentcharacteristics .Added Note 1 related to f HCLK , updated Note 2 in Table 14: Generaloperating conditions , and added maximum power dissipation values.Updated Table 15: Limitations depending on the operating powersupply range .STM32F405xx, STM32F407xx Revision history24-Jan-20122(continued)Added V12 in Table19: Embedded reset and power control blockcharacteristics.Updated Table21: Typical and maximum current consumption in Runmode, code with data processing running from Flash memory (ARTaccelerator disabled) and Table20: Typical and maximum currentconsumption in Run mode, code with data processing running fromFlash memory (ART accelerator enabled) or RAM. Added Figure,Figure25, Figure26, and Figure27.Updated Table22: Typical and maximum current consumption in Sleepmode and removed Note 1.Updated Table23: Typical and maximum current consumptions in Stopmode and Table24: Typical and maximum current consumptions inStandby mode, Table25: Typical and maximum current consumptionsin VBAT mode, and Table26: Switching output I/O currentconsumption.Section: On-chip peripheral current consumption: modified conditions,and updated Table27: Peripheral current consumption and Note2.Changed f HSE_ext to 50MHz and t r(HSE)/t f(HSE) maximum value inTable29: High-speed external user clock characteristics.Added C in(LSE) in Table30: Low-speed external user clockcharacteristics.Updated maximum PLL input clock frequency, removed related note,and deleted jitter for MCO for RMII Ethernet typical value in Table35:Main PLL characteristics. Updated maximum PLLI2S input clockfrequency and removed related note in Table36: PLLI2S (audio PLL)characteristics.Updated Section: Flash memory to specify that the devices areshipped to customers with the Flash memory erased. UpdatedTable38: Flash memory characteristics, and added t ME in Table39:Flash memory programming.Updated Table42: EMS characteristics, and Table43: EMIcharacteristics.Updated Table56: I2S dynamic characteristicsUpdated Figure46: ULPI timing diagram and Table62: ULPI timing.Added t COUNTER and t MAX_COUNT in Table51: Characteristics of TIMxconnected to the APB1 domain and Table52: Characteristics of TIMxconnected to the APB2 domain. Updated Table65: Dynamiccharacteristics: Ethernet MAC signals for RMII.Removed USB-IF certification in Section: USB OTG FScharacteristics.Table 98. Document revision history (continued)Date Revision ChangesDocID022152 Rev 4177/185Revision history STM32F405xx, STM32F407xx 178/185DocID022152 Rev 424-Jan-20122(continued)Updated Table 61: USB HS clock timing parameters Updated Table 67: ADC characteristics .Updated Table 68: ADC accuracy at fADC = 30MHz .Updated Note 1 in Table 74: DAC characteristics .Section 5.3.25: FSMC characteristics : updated Table 75 to Table 86, changed C L value to 30pF, and modified FSMC configuration for asynchronous timings and waveforms. Updated Figure 60: Synchronous multiplexed PSRAM write timings .Updated Table 96: Package thermal characteristics .Appendix A.1: USB OTG full speed (FS) interface solutions : modified Figure 86: USB controller configured as peripheral-only and used inFull speed mode added Note 2, updated Figure 87: USB controllerconfigured as host-only and used in full speed mode and addedNote 2, changed Figure 88: USB controller configured in dual modeand used in full speed mode and added Note 3.Appendix A.2: USB OTG high speed (HS) interface solutions : removedfigures USB OTG HS device-only connection in FS mode and USBOTG HS host-only connection in FS mode, and updated Figure 89:USB controller configured as peripheral, host, or dual-mode and usedin high speed mode and added Note 2.Added Appendix A.3: Ethernet interface solutions .Table 98. Document revision history (continued)Date Revision ChangesSTM32F405xx, STM32F407xx Revision history31-May-20123Updated Figure5: STM32F40x block diagram and Figure7: Power supply supervisor interconnection with internal reset OFFAdded SDIO, added notes related to FSMC and SPI/I2S in Table2: STM32F405xx and STM32F407xx: features and peripheral counts. Starting from Silicon revision Z, USB OTG full-speed interface is now available for all STM32F405xx devices.Added full information on WLCSP90 package together with corresponding part numbers.Changed number of AHB buses to 3.Modified available Flash memory sizes in Section2.2.4: Embedded Flash memory.Modified number of maskable interrupt channels in Section2.2.10: Nested vectored interrupt controller (NVIC).Updated case of Regulator ON/internal reset ON, RegulatorON/internal reset OFF, and Regulator OFF/internal reset ON in Section2.2.16: Voltage regulator.Updated standby mode description in Section2.2.19: Low-power modes.Added Note1 below Figure16: STM32F40x UFBGA176 ballout. Added Note1 below Figure17: STM32F40x WLCSP90 ballout. Updated Table7: STM32F40x pin and ball definitions.Added Table8: FSMC pin definition.Removed OTG_HS_INTN alternate function in Table7: STM32F40x pin and ball definitions and Table9: Alternate function mapping. Removed I2S2_WS on PB6/AF5 in Table9: Alternate function mapping.Replaced JTRST by NJTRST, removed ETH_RMII _TX_CLK, and modified I2S3ext_SD on PC11 in Table9: Alternate function mapping. Added Table10: STM32F40x register boundary addresses.Updated Figure18: STM32F40x memory map.Updated V DDA and V REF+ decoupling capacitor in Figure21: Power supply scheme.Added power dissipation maximum value for WLCSP90 in Table14: General operating conditions.Updated V POR/PDR in Table19: Embedded reset and power control block characteristics.Updated notes in Table21: Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator disabled), Table20: Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator enabled) or RAM, and Table22: Typical and maximum current consumption in Sleep mode.Updated maximum current consumption at T A = 25°n Table23: Typical and maximum current consumptions in Stop mode.Table 98. Document revision history (continued)Date Revision ChangesDocID022152 Rev 4179/185Revision history STM32F405xx, STM32F407xx 180/185DocID022152 Rev 431-May-2012 3 (continued)Removed f HSE_ext typical value in Table 29: High-speed external user clock characteristics . Updated Table 31: HSE 4-26 MHz oscillator characteristics and Table 32: LSE oscillator characteristics (fLSE = 32.768 kHz).Added f PLL48_OUT maximum value in Table 35: Main PLL characteristics .Modified equation 1 and 2 in Section 5.3.11: PLL spread spectrum clock generation (SSCG) characteristics .Updated Table 38: Flash memory characteristics , Table 39: Flash memory programming , and Table 40: Flash memory programming with VPP .Updated Section : Output driving current .Table 53: I2C characteristics : Note 4 updated and applied to t h(SDA) in Fast mode, and removed note 4 related to t h(SDA) minimum value.Updated Table 67: ADC characteristics . Updated note concerning ADCaccuracy vs. negative injection current below Table 68: ADC accuracyat fADC = 30MHz .Added WLCSP90 thermal resistance in Table 96: Package thermalcharacteristics .Updated Table 90: WLCSP90 - 0.400 mm pitch wafer level chip sizepackage mechanical data .Updated Figure 83: UFBGA176+25 - ultra thin fine pitch ball grid array10 × 10 × 0.6 mm, package outline and Table 94: UFBGA176+25 -ultra thin fine pitch ball grid array 10 × 10 × 0.6 mm mechanical data .Added Figure 85: LQFP176 recommended footprint .Removed 256 and 768 Kbyte Flash memory density from Table 97:Ordering information scheme .Table 98. Document revision history (continued)Date Revision ChangesSTM32F405xx, STM32F407xx Revision history04-Jun-20134Modified Note1 below Table2: STM32F405xx and STM32F407xx: features and peripheral counts.Updated Figure4 title.Updated Note3 below Figure21: Power supply scheme.Changed simplex mode into half-duplex mode in Section2.2.25: Inter-integrated sound (I2S).Replaced DAC1_OUT and DAC2_OUT by DAC_OUT1 andDAC_OUT2, respectively.Updated pin 36 signal in Figure15: STM32F40x LQFP176 pinout. Changed pin number from F8 to D4 for PA13 pin in Table7:STM32F40x pin and ball definitions.Replaced TIM2_CH1/TIM2_ETR by TIM2_CH1_ETR for PA0 and PA5 pins in Table9: Alternate function mapping.Changed system memory into System memory + OTP in Figure18: STM32F40x memory map.Added Note1 below Table16: VCAP_1/VCAP_2 operating conditions. Updated I DDA description in Table74: DAC characteristics.Removed PA9/PB13 connection to VBUS in Figure86: USB controller configured as peripheral-only and used in Full speed mode and Figure87: USB controller configured as host-only and used in full speed mode.Updated SPI throughput on front page and Section2.2.24: Serial peripheral interface (SPI)Updated operating voltages in Table2: STM32F405xx andSTM32F407xx: features and peripheral countsUpdated note in Section2.2.14: Power supply schemesUpdated Section2.2.15: Power supply supervisorUpdated “Regulator ON” paragraph in Section2.2.16: Voltage regulatorRemoved note in Section2.2.19: Low-power modesCorrected wrong reference manual in Section2.2.28: Ethernet MAC interface with dedicated DMA and IEEE1588 supportUpdated Table15: Limitations depending on the operating power supply rangeUpdated Table24: Typical and maximum current consumptions in Standby modeUpdated Table25: Typical and maximum current consumptions in VBAT modeUpdated Table36: PLLI2S (audio PLL) characteristicsUpdated Table43: EMI characteristicsUpdated Table48: Output voltage characteristicsUpdated Table50: NRST pin characteristicsUpdated Table55: SPI dynamic characteristicsUpdated Table56: I2S dynamic characteristicsDeleted Table 59Updated Table62: ULPI timingUpdated Figure47: Ethernet SMI timing diagramTable 98. Document revision history (continued)Date Revision ChangesDocID022152 Rev 4181/185Revision history STM32F405xx, STM32F407xx 182/185DocID022152 Rev 404-Jun-20134(continued)Updated Figure 83: UFBGA176+25 - ultra thin fine pitch ball grid array 10 × 10 × 0.6 mm, package outline Updated Table 94: UFBGA176+25 - ultra thin fine pitch ball grid array 10 × 10 × 0.6 mm mechanical data Updated Figure 5: STM32F40x block diagram Updated Section 2: Description Updated footnote (3) in Table 2: STM32F405xx and STM32F407xx: features and peripheral counts Updated Figure 3: Compatible board design between STM32F10xx/STM32F2xx/STM32F4xx for LQFP144 package Updated Figure 4: Compatible board design between STM32F2xx and STM32F4xx for LQFP176 and BGA176 packages Updated Section 2.2.14: Power supply schemes Updated Section 2.2.15: Power supply supervisor Updated Section 2.2.16: Voltage regulator , including figures.Updated Table 14: General operating conditions , including footnote (2).Updated Table 15: Limitations depending on the operating power supply range , including footnote (3).Updated footnote (1) in Table 67: ADC characteristics .Updated footnote (3) in Table 68: ADC accuracy at fADC = 30MHz .Updated footnote (1) in Table 74: DAC characteristics .Updated Figure 9: Regulator OFF .Updated Figure 7: Power supply supervisor interconnection with internal reset OFF .Added Section 2.2.17: Regulator ON/OFF and internal reset ON/OFFavailability .Updated footnote (2) of Figure 21: Power supply scheme .Replaced respectively “I2S3S_WS" by "I2S3_WS”, “I2S3S_CK” by“I2S3_CK” and “FSMC_BLN1” by “FSMC_NBL1” in Table 9: Alternatefunction mapping .Added “EVENTOUT” as alternate function “AF15” for pin PC13, PC14,PC15, PH0, PH1, PI8 in Table 9: Alternate function mappingReplaced “DCMI_12” by “DCMI_D12” in Table 7: STM32F40x pin andball definitions .Removed the following sentence from Section : I2C interfacecharacteristics : ”Unless otherwise specified, the parametersgiven in Table 53 are derived from tests performed under theambient temperature, f PCLK1 frequency and V DD supply voltageconditions summarized in Table 14.”.In Table 7: STM32F40x pin and ball definitions on page 45:–For pin PC13, replaced “RTC_AF1” by “RTC_OUT, RTC_TAMP1,RTC_TS”–for pin PI8, replaced “RTC_AF2” by “RTC_TAMP1, RTC_TAMP2,RTC_TS”.–for pin PB15, added RTC_REFIN in Alternate functions column.In Table 9: Alternate function mapping on page 60, for portPB15, replaced “RTC_50Hz” by “RTC_REFIN”.Table 98. Document revision history (continued)Date Revision ChangesSTM32F405xx, STM32F407xx Revision history04-Jun-20134(continued)Updated Figure6: Multi-AHB matrix.Updated Figure7: Power supply supervisor interconnection withinternal reset OFFChanged 1.2V to V12 in Section: Regulator OFFUpdated LQFP176 pin 48.Updated Section1: Introduction.Updated Section2: Description.Updated operating voltage in Table2: STM32F405xx andSTM32F407xx: features and peripheral counts.Updated Note1.Updated Section2.2.15: Power supply supervisor.Updated Section2.2.16: Voltage regulator.Updated Figure9: Regulator OFF.Updated Table3: Regulator ON/OFF and internal reset ON/OFFavailability.Updated Section2.2.19: Low-power modes.Updated Section2.2.20: VBAT operation.Updated Section2.2.22: Inter-integrated circuit interface (I²C) .Updated pin 48 in Figure15: STM32F40x LQFP176 pinout.Updated Table6: Legend/abbreviations used in the pinout table.Updated Table7: STM32F40x pin and ball definitions.Updated Table14: General operating conditions.Updated Table15: Limitations depending on the operating powersupply range.Updated Section5.3.7: Wakeup time from low-power mode.Updated Table33: HSI oscillator characteristics.Updated Section5.3.15: I/O current injection characteristics.Updated Table47: I/O static characteristics.Updated Table50: NRST pin characteristics.Updated Table53: I2C characteristics.Updated Figure39: I2C bus AC waveforms and measurement circuit.Updated Section5.3.19: Communications interfaces.Updated Table67: ADC characteristics.Added Table70: Temperature sensor calibration values.Added Table73: Internal reference voltage calibration values.Updated Section5.3.25: FSMC characteristics.Updated Section5.3.27: SD/SDIO MMC card host interface (SDIO)characteristics.Updated Table23: Typical and maximum current consumptions in Stopmode.Updated Section: SPI interface characteristics included Table55.Updated Section: I2S interface characteristics included Table56.Updated Table64: Dynamic characteristics: Ehternet MAC signals forSMI.Updated Table66: Dynamic characteristics: Ethernet MAC signals forMII.Table 98. Document revision history (continued)Date Revision ChangesDocID022152 Rev 4183/185Revision history STM32F405xx, STM32F407xx 184/185DocID022152 Rev 404-Jun-20134(continued)Updated Table 64: Dynamic characteristics: Ehternet MAC signals for SMI .Updated Table 66: Dynamic characteristics: Ethernet MAC signals for MII .Updated Table 79: Synchronous multiplexed NOR/PSRAM read timings .Updated Table 80: Synchronous multiplexed PSRAM write timings .Updated Table 81: Synchronous non-multiplexed NOR/PSRAM read timings .Updated Table 82: Synchronous non-multiplexed PSRAM writetimings .Updated Section 5.3.26: Camera interface (DCMI) timing specificationsincluding Table 87: DCMI characteristics and addition of Figure 73:DCMI timing diagram .Updated Section 5.3.27: SD/SDIO MMC card host interface (SDIO)characteristics including Table 88.Updated Chapter Figure 9.Table 98. Document revision history (continued)Date Revision ChangesSTM32F405xx, STM32F407xxPlease Read Carefully:Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice.All ST products are sold pursuant to ST’s terms and conditions of sale.Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein.No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. 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STM32F407VET6开发板原理图
R1 R2 R3 R4 10K 10K 10K 10K J1 PB4-JNTRST PA15-JTDI PA13-JTMS PA14-JTCK R5 10K PB3-JTDO RESET 1 3 5 7 9 11 13 15 17 19 2 4 6 8 10 12 14 16 18 20
R19 10K
3.3V
3.3V
3.3V
5V J4 PC8-------SDIO_D0 PC9-------SDIO_D1 PC10-----SDIO_D2 PC11-----SDIO_D3 PC12-----SDIO_CLK PD2------SDIO_CMD PA11-USB-DM PA12-USB-DP R36 R37 22 22 1 2 3 4 5 6 7 8 9 VBUS D-(DM) D+(DP) ID GND SHIELD SHIELD SHIELD SHIELD MINI-USB PB14-DM PB15-DP 5V 1 2 3 4 VCC DD+ GND J7
PB10-SPI2-SCK PC3-SPI2-MOSI
3.3V L1 10uH
VDDA MK1 CN1 C7 0.1uF C8 10uF 1 5V 3 2 C12 0.1uF C13 10uF 3 IN
GND
R35 1K
LED4 led
OUT
2
C1 D 0.1uF U2 1 2 3 4 A0 A1 A2 VSS 24C02 VCC WP SCL SDA 8 7 6 5 PB8-I2C1-SCL PB9-I2CI-SDA
3.3V
POW
AMS1117-3.3
1
R17 4.7K
R18 4.7K
T1IN T1OUT R1OUT R1 IN T2IN T2OUT R2OUT R2 IN MAX3232
STM32F407VGT6芯片管脚功能定义
OTG_HS_ULPI_D7 /
ETH_PPS_OUT/TIM3_CH
2 / SPI1_MOSI/
SPI3_MOSI / DCMI_D10 /
I2S3_SD/ EVENTOUT
92 PB6 I2C1_SCL/ TIM4_CH1 /
CAN2_TX /
ETH_MII_TXD0/
OTG_HS_ID/ EVENTOUT 52 PB13 SPI2_SCK / I2S2_CK /
USART3_CTS/
TIM1_CH1N /CAN2_TX /
OTG_HS_ULPI_D6 /
ETH_RMII_TXD1 /
ETH_MII_TXD1/
EVENTOUT
53 PB14 SPI2_MISO/ TIM1_CH2N /
OTG_HS_ULPI_CK /
TIM2_CH1_ETR/
TIM8_CHIN/ EVENTOUT 31 PA6 SPI1_MISO /
TIM8_BKIN/TIM13_CH1 /
DCMI_PIXCLK / TIM3_CH1
/ TIM1_BKIN/ EVENTOUT 32 PA7 SPI1_MOSI/ TIM8_CH1N /
EVENTOUT
56 PD9 FSMC_D14 / USART3_RX/
EVENTOUT
57 PD10 FSMC_D15 / USART3_CK/
EVENTOUT
58 PD11 FSMC_CLE /
FSMC_A16/USART3_CTS/
EVENTOUT
59 PD12 FSMC_ALE/
FSMC_A17/TIM4_CH1 /
USART3_RTS/