MT6595datasheet_中文版

合集下载

mt6582中文规格书(部分)

mt6582HSPA +手机应用处理器技术简明1系统概述mt6582是一个高度集成的基带平台使用调制解调器，应用处理和连接子系统使3G智能手机上的应用。

芯片集成了四核ARM®Cortex-A7 mpcoretm操作高达 1.3GHz，手臂®cortex-r4单片机和强大的多标准的视频加速器。

mt6582 NAND闪存的接口，为获得最佳性能，还支持启动SLC NAND或eMMC减少整体成本LPDDR2和LPDDR3的。

此外，一组广泛的接口，包括接口的摄像头，触摸屏显示，与MMC / SD卡。

应用处理器，四核ARM®Cortex-A7 mpcoretm包括霓虹多媒体处理引擎，提供处理能力要随着它的要求苛刻的应用，如网页浏览，电子邮件的最新openos支持，GPS导航和游戏。

都是在一个高分辨率的触摸屏显示图形的三维图形加速增强视。

多标准视频加速器和一个先进的音频子系统还包括提供先进的多媒体应用和服务，如音频和视频流，众多的解码器和编码器如H.264，MPEG-4。

音频支持包括法国，人力资源，财务，人力资源和AMR FR，AMR宽带AMR 声码器，和弦铃声，如回声消除先进的音频功能，免提扬声器操作和噪声消除。

臂®cortex-r4，DSP，和2G和3G的协处理器提供了一个可支持14级强大的调制解调器（21 Mbps HSDPA 下行链路子系统）和6类（5.76 Mbps）HSUPA上行数据速率以及12级GPRS，边缘。

mt6582包括四无线连接功能，WLAN，蓝牙，GPS，调频接收机。

放在mt6627芯片的射频部分的四块。

四先进的无线技术集成到一个芯片，mt6582 / mt6627提供最便捷的连接解决方案，在工业。

mt6582 / mt6627实施先进的无线技术共存的算法和硬件机制。

它还支持单天线2.4 GHz天线蓝牙共享，为GPS和1.575 GHz WLAN。

LM3655TL资料

LM3655Charge Control and Protection IC for embedded single cell Li-Ion/Polymer batteries1.0General DescriptionThe LM3655provides complete charge control,discharge control and battery safety of a single Lithium-Ion cell.It supports battery charging by using a variety of power supply types including unregulated current-limited wall adapters,regulated wall adapters and vehicle power adapters.Charge current control is achieved using an external bipolar PNP power transistor.Furthermore,the LM3655provides effective and compre-hensive discharge control functionality.All operating load current is supplied by the Li-Ion battery and passes through this IC.This allows the battery power to disconnect due to overload,short-circuit or low battery conditions.The IC also offers extensive battery safety protection against over-voltage and over-current.The internal safety circuit is backed up by an identical circuit to provide safety redun-dancy.The LM3655requires minimal external components and is packaged in a micro surface mount device for inte-gration in a single cell battery pack.2.0Key Specificationsn 1%precision pin-selectable nominal 4.10V and 4.16V termination voltagesn Up to 1.2A full-rate charge current n Safety Shunt voltage 4.35Vn 800mW power regulation of external PNP at 25˚Callows operation up to 30V (peak-to-peak)and 18V DC3.0Featuresn Input over-voltage protection for load and battery pack n Input over-current protection for load and battery pack n Reverse current protection n Reverse charger protectionn Input short circuit protection that protects the cell from a short on the charger-connectorn Output overload current and short circuit protection n Complete charge control with pre-charging for depleted batteries,full-rate and trickle charging.n Support for charging with regulated and non-regulated wall adapters and vehicle power adapters.n Power regulation of the external Power PNP n Chemistry selection for Li-ion and Li-polymern Complete linear Peak detector function for filtering ripple on input power supplynDigital filtering of the cell voltage transients duringtransmit pulses when LM3655is used in a battery pack for cell phones.n25-pin,2.5mm x 2.5mm microSMD package formounting on four layered PCB inside the battery pack.4.0Applicationsn Cell phones and other portable applications which use embedded Li-ion batteries5.0Typical Application Circuit20111501Because the LM3655and associated external components provide safety protection for both the Li-Ion cell and the phone circuitry,appropriate precautions must be taken in system design and layout to ensure proper operation.November 2004LM3655Charge Control and Protection IC for embedded single cell Li-Ion/Polymer batteries©2004National Semiconductor Corporation Table of Contents1.0General Description .....................................................................................................................................12.0Key Specifications ........................................................................................................................................13.0Features .......................................................................................................................................................14.0Applications ..................................................................................................................................................15.0Typical Application Circuit ............................................................................................................................16.0Connection Diagrams and Package Marking ..............................................................................................37.0LM3655Pin Description ...............................................................................................................................38.0Ordering Information ....................................................................................................................................49.0Operation Description ..................................................................................................................................410.0Pin Functions .............................................................................................................................................410.1V IN ............................................................................................................................................................410.2CELL ........................................................................................................................................................410.3RADIO_B+...............................................................................................................................................410.4V DETECT ...................................................................................................................................................510.5DISABLE .................................................................................................................................................510.6CHEMISTRY ............................................................................................................................................510.7HIB_EN ....................................................................................................................................................510.8HIS_DIS ...................................................................................................................................................510.9BATT_DETB ............................................................................................................................................510.10CHRG_STATE .......................................................................................................................................510.11CHRG_DET ...........................................................................................................................................510.12CNTRL ...................................................................................................................................................510.13EXT_PWR_ON ......................................................................................................................................611.0Charge Control Functions ..........................................................................................................................611.1GENERAL OPERATION ..........................................................................................................................611.2EXTERNAL POWER SUPPLY DETECT .................................................................................................611.2.1V DETECT Circuit ...................................................................................................................................611.2.2Debounce Function ............................................................................................................................711.2.3Power Supply Test Pulses .................................................................................................................811.2.4Low Cell Voltage Charging (Pre-Charging).......................................................................................911.2.5Full-Rate Charging ...........................................................................................................................1011.2.6Trickle/Top-Off Mode ........................................................................................................................1111.2.7Peak Detector Function ....................................................................................................................1112.0Discharge Control Functions ....................................................................................................................1212.1GENERAL DESCRIPTION ....................................................................................................................1212.2RADIO+GENERATION ........................................................................................................................1212.3UNDER-VOLTAGE CUT-OFF ...............................................................................................................1312.4POWER CUT OPERATION ..................................................................................................................1312.5HIBERNATION MODE ..........................................................................................................................1313.0Safety Functions ......................................................................................................................................1313.1INPUT OVER-VOLTAGE PROTECTION ..............................................................................................1313.1.1Normal Operation (Q1Control).......................................................................................................1313.1.2Safety Shunt/Crowbar Operation .....................................................................................................1413.1.3Standby Shunt Mode .......................................................................................................................1413.1.4Thermal Crowbar Mode ...................................................................................................................1413.1.5Fast Shunt Operation ......................................................................................................................1413.1.6Shunt Circuit Parametric Specifications ..........................................................................................1413.2SCHOTTKY ELIMINATION MODE (CHARGER INPUT SHORT CIRCUIT/REVERSE CURRENT PRO-TECTION)......................................................................................................................................................1513.3REVERSE CHARGER PROTECTION ..................................................................................................1513.4OUTPUT CURRENT OVERLOAD PROTECTION (“PTC”MODE)......................................................1513.5OUTPUT SHORT CIRCUIT CURRENT PROTECTION .......................................................................1514.0Required External Components ...............................................................................................................1714.1CHARGE PASS TRANSISTOR (Q1)....................................................................................................1714.2DRIVER TRANSISTOR AND BIAS RESISTORS (R2,R3AND R5)....................................................1714.3EXTERNAL CHARGER SENSE RESISTOR (R4)................................................................................1714.4CAPACITORS ........................................................................................................................................1714.5FUSE (F1).............................................................................................................................................1715.0Electrical Characteristics ..........................................................................................................................1715.1GENERAL SPECIFICATION AND ABSOLUTE MAXIMUM RATINGS ................................................1715.2PASS DEVICE AND POWER SUPPLY RATINGS ...............................................................................1815.3IC PIN ELECTRICAL CHARACTERISTICS .. (18)L M 36552Table of Contents(Continued)16.0Physical Dimensions (21)6.0Connection Diagrams and Package Marking20111502MicroSMD Top ViewSee NS Package Number TLA2520111503MicroSMD Bottom View7.0LM3655Pin DescriptionPin #Name I/O Type DescriptionA1CHEMISTRYInputLogicA low input sets the constant voltage and termination voltage to the lower V TERML .A high input sets the constant voltage to the higher voltage level V TERMH .This pin has an internal 100k Ωpull-downresistor and can be controlled by a peripheral IC or can be tied directly to B+or GND.A2HIB_DISB Input LogicThis pin is internally pulled up to the CELL pin by a 100K resistor.When this pin is momentarily pulsed low,Hibernate mode is exited,which turns on M4.A3HIB_EN Input AnalogThe IC is configured in hibernation mode,when this pin is pulled high after a debounce period.Activating hibernation mode turns off the internal M4transistor.A4EXT_PWR_ON Output LogicEXT_PWR_ON is a push-pull output.It is a logic 1(Radio_B+voltage level)when the cell has reached the V phone_on level (nominally 3.0V)while the charger is connected and the battery is present.A5CNTRL Output Analog This output pin regulates the charger current by controlling the base voltage of the external drive and pass transistors Q2and Q1.B1,C1,C2,D1RADIO OutputAnalogThis is the power supply terminal for the phone.ALL load current from the cell must be sourced from this pin.B2NCThis pin must be left floating.It needs to be connected to a nonconnected PCB pad for heat sinking.It cannot be connected to other NC pins.B3,C3,D3CELL I/O Analog These pins need to be connected to the cell’s positive terminal.B4,C4,D4V IN Input AnalogInput from the pass transistor Q1.B5,C5,D5GND GroundGround pin for the circuit and CELL-D2NCThis pin must be left floating.It needs to be connected to a nonconnected PCB pad for heat sinking.It cannot be connected to other NC pins.E1DISABLEInputLogicA logic high applied to this input disables the charging.A logic low enables it.This pin has an internal 100K Ωpull-down resistor and can be left unconnected.LM365537.0LM3655Pin Description(Continued)Pin #Name I/O Type DescriptionE2BATT_DETBInputLogicThis pin is used to detect the presence of a battery.When the battery is missing,the internal 100K resistor will pull up this pin to the voltage on CELL.When the battery is present,this pin should be pulled low.E3CHRG_STATE OutputOpen DrainThis pin is used to indicate the charge status.An external 30K pull-up resistor needs to be connected between this pin and RADIO+if output on this pin is desired.A low output signifies that the IC is charging the battery cell in full-rate mode.A high output indicates that trickle/top-off charging is in process.The output is also high when the charger is disabled (DIS pin tied high).E4CHRG_DETB OutputOpen DrainAn external 30K pull-up resistor needs to be connected between this pin and RADIO+if output on this pin is desired.The CHRG_DETB indicates whether an external power supply has been detected (output =low)or not (output =high).E5VDET Input AnalogVDET provides the internal control with a signal that is proportional to the external voltage level and also provides power to the internal control circuitry.8.0Ordering InformationOrder Number Packaging Type NSC Package Marking (*)Supplied AsLM3655TL 25-bump Wafer LevelChip Scale (micro SMD)XY TT S50250units,Tape-and-Reel LM3655TLXXY TT S503000units,Tape-and-Reel(*)XY -denotes the date code marking (2digits)in production (*)TT -refers to die/lot tracking for production (*)S -product line designatorPackage markings may change over the course of production9.0Operation DescriptionRefer to Typical Application Circuit for external and internal component reference designators such as Q1,M5,etc.10.0Pin Functions10.1V INV IN is the input pin for the charging current from the external power source to the battery/cell.When the phone is operating from an external supply,cell phone operating current also passes through this pin.Total input current into the V IN pin is internally sensed by monitoring the voltage drop across the series sensing FET M5.V IN is derived from the output (collector)of Q1,and not directly connected to the external source.If the external power supply (VPS)potential exceeds a maximum safe limit,Q1will be controlled to protect the cell and phone circuits from over-voltage.Q1provides the primary over-voltage protection mechanism for the phone circuits and the cell.10.2CELLCELL is connected directly to the battery/cell positive terminal.Under normal operation of the phone,it serves as the main power supply pin for the LM3655.When the phone is drawing current from the battery,current will flow into this pin and out through the internal FET M4to supply the phone’s operating rail (RADIO_B+).When connected to an external supply to charge the battery,current will flow through M5and out of this pin into the cell.If the phone is being operated while connected to an external power supply,the phone’s operating current (current out of the RADIO_B+pin)will be the sum of the currents into the CELL and V IN pins.10.3RADIO_B+All power for the phone’s operation (other than battery charging)is derived from this pin.The phone’s operating current flows through M4,which is controlled and monitored to prevent overload or short-circuit currents,and disabled during cell under-voltage conditions.L M 3655 4LM3655 10.0Pin Functions(Continued)10.4V DETECTThis pin is coupled to the external power supply through a series resistance(R4).It is used to determine when an external source (charger)is connected,which in turn initiates the device’s charge control logic.The CHRG_DETB output is set based on input tothis pin.10.5DISABLEThe phone can stop the charge current through use of the DISABLE logic input pin of the IC.Asserting a logic high on the DISABLE Pin of the IC will force the control pin(CNTRL)to turn off the external Drive(Q2)and Pass(Q1)transistors so thereis no charge current to the cell.The DISABLE input can be driven high by the phone’s logic at any time to interrupt the charge e of the DISABLE pin during charging can allow the phone to measure the cell’s true voltage by peripheral circuitry (without the presence of charge current input)if desired.Additionally,a high-to-low transition on the DISABLE pin(thus re-enabling the charger operation),will reset the charge controlstate machine.10.6CHEMISTRYThe CHEMISTRY pin provides a logic input to the IC that determines the termination threshold for Li-ion cell charging.A logic low applied to this pin selects the lower charging threshold or termination voltage(V TERML),a logic high selects the higher charging threshold(V TERMH).Because different cell types may require slightly different charge termination thresholds,the LM3655supports a pin-programmable selection between two different settings.The lower threshold is nominally4.10V,and the higher threshold is nominally4.16V.10.7HIB_ENThis pin provides a logic input to the IC that when held high during a debounce period of32mS,M4will be latched open evenif the cell voltage is above V CHARGE_LOW.This pin has a10K pull-down resistor internal to the IC so that the IC will default on.10.8HIS_DISThis pin provides a logic input to the IC that when held low momentarily,the latch holding M4open is cleared allowing it to beclosed when the cell voltage is above V CHARGE_LOW.This pin has a100K pullup resistor to the CELL pin internal to the IC.10.9BATT_DETBBATT_DETB indicates to the LM3655IC that a cell is present in the system.This pin provides a logic input to the IC that whenheld low,the IC will be able to detect the presence of a charger.There is a100K pull-up resistor internal to the IC on this pin,whichis supplied from the charger(not from the cell).A series10K resistor is to be used between this pin and the removable battery to protect the IC against ESD.10.10CHRG_STATECHRG_STATE is an open-drain logic output to the phone,and can be used to provide a simple battery-metering indication duringcharge mode.During charge mode,with current flowing into the cell,the Li-ion cell voltage cannot be used for an accurate indication of state of charge.If a battery is at a relatively low state of charge,it will remain in the“full-rate”charge mode for someperiod of time when connected to the external power supply.When the cell reaches a higher state of charge,the charge control switches to the trickle/top-off mode.Thus,this signal is logic low during full-rate charge mode and high during the trickle/top-off mode.The exact percentage of“full”at this crossover point will vary depending on many conditions,primarily full-rate charge current level,but is expected to be>60%for typical use with a mid-rate charger.This information can be used to provide a simple“charging”or“ready”indication by the system for the battery status meter during charge.If combined with a timer,or other means of interaction by the system(such as periodic control of the DISABLE pin combined with cell voltage measurements during periods of no current flow)a more complete metering method may be implemented if desired.10.11CHRG_DETThis is an open-drain output to the phone’s power management IC that indicates the connection of an external power supply. Typical application uses a30K pull-up resistor to RADIO_B+.When a charger is detected,this output is pulled LOW by the internal logic of the LM3655.This signal may be pulled up to a low-voltage logic rail such as2.75V or1.8V regulated voltage.Itis assumed that the voltage used to pull-up is no higher than the cell voltage.10.12CNTRLThis is an analog output to control Q2,the NPN drive transistor.The CNTRL output is adjusted to deliver the appropriate level ofcurrent required by the charge algorithm for full-rate or trickle/top-off charging.During full-rate charging,CNTRL is set such thatQ1will be saturated.During trickle/top-off mode,CNTRL will be set in order to maintain the appropriate cell clamp voltage(4.10Vor4.16V as desired).Furthermore,if the power-monitoring circuit determines that excess power is being dissipated in,the CNTRLsignal will be further reduced to limit current flowing through Q1.This ensures that the Q1pass device remains within safe power dissipation limits.510.0Pin Functions(Continued)10.13EXT_PWR_ONEXT_PWR_ON is a digital push-pull output.A logic 1,referenced to the Radio_B+level is output when V cell exceeds V phone_on (nominally 3.00V)and CHRG_DETB =0(charger presence is detected)and BATT_DETB is low.Otherwise,EXT_PWR_ON is held low to prevent the phone from attempting to turn on due to charger connection when there is either no battery present or when the battery is not charged enough for the phone to operate.11.0Charge Control Functions11.1GENERAL OPERATIONThe LM3655circuit is able to operate with different types of charge power supplies with a wide range of input voltage and currents,including but not limited to unregulated current limited wall adapters,regulated wall adapters and Vehicle Power Adapters with 1A of current limit.The IC protects itself from high voltages by using Q1and Q2to stand off these voltages.It also uses resistors to current limit the V DETECT pin.High currents are handled by using current regulation during both the full-rate and the trickle/top-off phases of charging the battery.Power dissipation in Q1is controlled using a constant-power control circuit within the IC.The LM3655has multiple modes of operation for charging and protecting the embedded cell.The three basic modes of operation are low voltage charging,full-rate charging,and trickle charging.During the charge process,the power dissipation in the pass element Q1is monitored and controlled to a safe maximum limit by reducing charge current as necessary.Because of quantization error or power supply voltage fluctuations,the power-limiting circuit may (in some cases)reduce cell current to a level lower than necessary for extended periods of time.To counteract this,the IC periodically activates a charger test pulse during the full-rate and trickle charging modes.This allows the power supply to deliver full-rate current,although the cell voltage is always regulated such that it does not exceed the termination voltage (4.10V or 4.16V as determined by the CHEMISTRY pin).The test pulse allows the cell to be charged at the fastest possible rate by allowing the charge control to re-enter the full-rate charge (Q1saturated)mode whenever possible.The test pulses are enabled during full-rate and trickle/top-off charge modes,have a nominal duration of 256mS,and are repeated every 64seconds.This is referred to as ‘burp’mode.Figure 1shows the cell voltage thresholds used in the selection of the charging modes.The horizontal (time)axis is intended to illustrate the progression of a complete charge/discharge cycle of operation.11.2EXTERNAL POWER SUPPLY DETECT11.2.1V DETECT CircuitThe V DETECT circuit is used to determine the presence of an external charger.The equivalent circuit is illustrated below.20111504FIGURE 1.Voltage ThresholdsL M 3655 611.0Charge Control Functions(Continued)The Shunt Regulator (Z1)on the V DETECT pin is designed to sink a limited amount of current while maintaining certain levels of regulation.These are specified below.When there is excessive current flowing into the V DETECT pin above which Z1can regulate,then current can flow through D1into the cell pin.When the cell pin voltage exceeds V SHUNT ,I CELL_SHUNT turns on.The I CELL_SHUNT circuit is implemented redundantly.I CELL_SHUNT shunts current to ground through effectively 100Ωwhen both redundant circuits are operating.V DETECT circuit parametric specs are summarized below.These specs apply to the entire Normal Temperature Range.Parameter DescriptionMin TypMaxUnits I DETECTMIN1Min V DETECT pin current to allow detection of a charger 100µA I UNDETECTMAX Maximum current into the V DETECT pin for the charger to be not detected.3µA I DETECTMIN2Once a charger is detected,it will remain detected unless the current into the V DETECT pin goes below this threshold 25µA I CELL_SHUNT V CELL current.With V CELL =4.5V (>V SHUNT )2075mA I DETECTMAX Max V DETECT pin current that can maintain V DETECTMAX115mA V DETECTMAX1Normal V DETECT regulation voltage,I DETECTMIN <I DETECT <I DETECTMAXV CELL –5mV V CELL ±50mV V V DETECTMAX2Secondary V DETECT voltage limit,I DETECTMAX <I DETECT <30mAV CELL 1VV11.2.2Debounce FunctionThe charger debounce detects a temporary disconnect/connect of the charging power supply.This can occur when the end-user inserts the power supply to the phone and the connection is not made cleanly,or if the connection is disturbed (such as dropping the phone).When the IC first senses the power supply input voltage it will delay τDEBOUNCE_ON before the charger detect signal is confirmed.If there is disconnect of the charge power supply,the IC will delay τDEBOUNCE_OFF before the disconnection is confirmed.The IC will ignore the interruptions of duration shorter than specified.These specs apply to the entire Normal Temperature Range.20111505FIGURE 2.V DETECT CircuitLM3655711.0Charge Control Functions(Continued)SpecificationTest ConditionsMin Typ Max Units Debounce Connection Delay “τDEBOUNCE_ON ”I DETECT stepped from 0mA to 1mA 223264ms Debounce Connection Delay “τDEBOUNCE_OFF ”I DETECT stepped from 1mA to 0mA223264ms11.2.3Power Supply Test PulsesThe purpose of the test pulse operation is for the IC to periodically test the charging power supply’s full-rate current capability.This operation only occurs when the cell voltage is above V PHONE_ON .The test pulse has a period of τTEST_PERIOD and pulse width of τTEST_WIDTH .During test pulses the IC will fully turn on the M5pass devices and attempts to draw I CHRG_MAX current from the charging power supply.The charging power supply will respond by delivering the full-rate current up to I CHRG-MAX to the load (Q1will be forced into saturation).During the test pulse,the IC constantly monitors the cell voltage with its internal voltage regulation control circuit and the charge current with its current regulation control circuit.The power dissipation of Q1is not controlled during the test pulse.The IC determines which charge rate to apply at the end of each test pulse.The interaction between the three control circuits is such that the voltage regulation is the most dominant so the cell voltage will not exceed V TERMX .(V TERMX being either V TERMH or V TERML ,depending on the logic level applied to the CHEMISTRY pin).When the test pulse is high,one of the following can occur:1.V PHONE_ON <V CELL <V TERMX and Charge Current <I CHRG_MAX :The charging power supply will continue to deliver full-rate current during and after the test pulse.Q1remains in saturation and all M5sense resistor switches remain on.2.V PHONE_ON <V CELL <V TERMX and Charge Power Supply wants to deliver more than I CHRG_MAX (e.g.Failed Vehicular Power Adaptor and phone is connected directly to car battery):The internal current regulation control of the LM3655IC will try to maintain the charge current at I CHRG_MAX by forcing the external Q1and Q2transistors into linear operation.This may exceed Q1power dissipation limit.After the test pulse,the IC internal power regulation control senses the voltage across Q1V CE above Q1UNSAT and determines the appropriate M5sense resistor array switches to turn on.The effective resistance will determine the amount of charge current allow such that Q1power dissipation is within limit of P PASS_MAX .If Q1UNSAT is exceeded at the end of a test pulse,CHRG_STATE will not go high as the Top-off signal is only created when V CELL reaches V TERMX .Unless a non-supported power supply is used,because of burp mode,it is expected that the system will mend itself and go back into full-rate when the next test pulse comes along.3.V CELL reaches V TERMX (desired maximum cell clamp level):The IC internal voltage regulation control will dominate the charger control logic,and control the charge current to maintain V CELL at V TERMX .To accomplish this,the voltage regulation control forces Q1and Q2from saturation back in linear mode to reduce the charge current to a level that will maintain V CELL at V TERMX .After the test pulse,Q1V CE above Q1UNSAT indicates the charge current to be reduced to trickle current.Q1may or may not be in power-limit regulation.In order to prevent a transient situation when transitioning from trickle to full-rate between test pulses,the voltage regulation control will reset to zero for τTEST_DELAY and the current regulation control will then be forced to turn off Q1and Q2.This in effect will set the charge current to zero.After τTEST_DELAY the voltage regulator will be allowed to ramp back up and the charge current will also ramp from zero to full-rate current.Figure 3illustrates the charge profile.L M 3655 8。

951200301资料

F eatures Array•Integer Unit Based on SPARC V7 High-performance RISC Architecture•Optimized Integrated 32/64-bit Floating-point Unit•On-chip Peripherals–EDAC and Parity Generator and Checker–Memory InterfaceChip Select GeneratorWaitstate GenerationMemory Protection–DMA Arbiter–TimersGeneral Purpose Timer (GPT)Real-time Clock Timer (RTCT)Watchdog Timer (WDT)–Interrupt Controller with 5 External Inputs–General Purpose Interface (GPI)–Dual UART•Speed Optimized Code RAM Interface8- or 40-bit boot-PROM (Flash) Interface•IEEE 1149.1 Test Access Port (TAP) for Debugging and Test Purposes•Fully Static Design•Performance: 20 MIPs/5 MFlops (Double Precision) at SYSCLK = 25 MHz•Core Consumption: 1.0W Typ. at 20 MIPs/0.7W typ. at 10 MIPs•Operating Range: 4.5V to 5.5V(1) -55°C to +125°C•Tested up to Total Dose of 300 KRADs (Si) according to MIL STD 883 Method 1019•SEU Event Rate Better than 3 E-8 Error/Component/Day (Worst Case)•No Single Event Latch-up below an LET Threshold of 80 MeV/mg/cm2•Quality Grades: ESCC with 9512/003 and QML-Q or V with 5962-00540•Package: 256 MQFPF; Bare DieNote: 1.For 3.3V capability see the TSC695FL datasheet on the Atmel site. DescriptionThe TSC695F (ERC32 Single-Chip) is a highly integrated, high-performance 32-bit RISC embedded processor implementing the SPARC architecture V7 specification. It has been developed with the support of the ESA (European Space Agency), and offers a full development environment for embedded space applications.The processor is manufactured using the Atmel 0.5 µm radiation tolerant (≥ 300 KRADs(Si)) CMOS enhanced process (RTP). It has been specially designed for space, as it has on-chip concurrent transient and permanent error detection.The TSC695F includes an on-chip Integer Unit (IU), a Floating Point Unit (FPU), a Memory Controller and a DMA arbiter. For real-time applications, the TSC695F offers a high security watchdog, two timers, an interrupt controller, parallel and serial inter-faces. Fault tolerance is supported using parity on internal/external buses and an EDAC on the external data bus. The design is highly testable with the support of anOn-Chip Debugger (OCD), and a boundary scan through JTAG interface.2TSC695F4118J–AERO–08/04Block DiagramFigure 1. TSC695F Block DiagramPin DescriptionsFor pin assignment, refer to package section.General PurposeInterfaceUART ATAPClock ManagtError ManagtGeneral PurposeTimer Real Time ClockTimer32-bit Integer UnitDMA Arbiter Access Controller Address Interface Wait State ControllerInterruptsRxD, TxD GPI bits DMA CtrlMem Ctrl Ready/Busy Add.+Size+ASI Data+Check bits ParitiesEDACWatch DogParity Parity Gen./Check.Reset&UART B Interrupt Controller32/64-bitFloating-PointUnit ParityGen./Chk.Gen./Chk.Table 1. Pin DescriptionsSignal Type Active DescriptionRA[31:0]I/O, 32-bit registered address busOutput buffer: 400 pFRAPAR I/O High Registered address bus parity-RASI[3:0]I/O 4-bit registered address space identifier -RSIZE[1:0]I/O 2-bit registered bus transaction size-RASPAR I/O High Registered ASI and SIZE parity -CPAR I/O HighControl bus parity -D[31:0]I/O 32-bit data bus -CB[6:0]I/O 7-bit check-bit bus-DPAR I/O High Data bus parity-RLDSTO I/O High Registered atomic load-store -ALE O Low Address latch enable -DXFER I/O High Data transfer -LOCK I/O High Bus lock -RD I/O High Read access -WE I/O Low Write enable -WRT I/O High Advanced write -MHOLD O Low Memory bus hold MHOLD+FHOLD +BHOLD+FCCVMDS O Low Memory data strobe -MEXC O Low Memory exception -PROM8I Low Select 8-bit wide PROM-BA[1:0]O Latched address used for 8-bit wide boot PROM -ROMCS O Low PROM chip select -ROMWRT I Low ROM write enable -MEMCS[9:0]O Low Memory chip select Output buffer: 400 pF MEMWROLowMemory write strobeOutput buffer: 400 pF3TSC695F4118J–AERO–08/04Note:If not specified, the output buffer type is 150 pF, the input buffer type is TTL.OE O Low Memory output enable Output buffer: 400 pFBUFFEN O Low Data buffer enable -DDIR O High Data buffer direction -DDIR O Low Data buffer direction -IOSEL[3:0]O Low I/O chip select-IOWR O Low I/O and exchange memory write strobe -EXMCS O Low Exchange memory chip select -BUSRDY I Low Bus ready-BUSERR I Low Bus error -DMAREQ I Low DMA request -DMAGNT O Low DMA grant-DMAAS I High DMA address strobe-DRDY O Low Data ready during DMA access -IUERR O Low IU error-CPUHALT O Low Processor (IU & FPU) halt and freeze -SYSERR O Low System error -SYSHALT I Low System halt -SYSAV O High System availability -NOPAR I Low No parity-INULL O High Integer unit nullify cycle -INST O High Instruction fetch Used to check the executestage of IUinstruction pipelineFLUSH O High FPU instruction flush DIA O High Delay instruction annulled RTC O HighReal Time Clock Counter output -RxA/RxB I Receive data UART ’A’ and ’B’Input triggerTxA/TxB O Transmit data UART ’A’ and ’B’-GPI[7:0]I/O GPI input/output Input triggerGPIINT O High GPI interrupt -EXTINT[4:0]I External interruptInput triggerEXTINTACK O High External interrupt acknowledge -IWDE I High Internal watch dog enable -EWDINT I High External watch dog input interrupt Input triggerWDCLK I Watch dog clock -CLK2I Double frequency clock -SYSCLK O System clock-RESET O Low Output reset-SYSRESET I Low System input reset Input trigger TMODE[1:0]I Factory test mode Functional mode=00DEBUG I High Software debug mode -TCK I T est (JTAG) clock -TRST I Low T est (JTAG) reset pull-up ≈ 37 k ΩTMS I T est (JTAG) mode select pull-up ≈ 37 k ΩTDI I T est (JTAG) data input pull-up ≈ 37 k ΩTDO OT est (JTAG) data output -VCCI/VSSI Main internal power -VCCO/VSSOOutput driver power-Table 1. Pin Descriptions (Continued)Signal Type Active Description4TSC695F4118J–AERO–08/04System ArchitectureThe TSC695F is to be used as an embedded processor requiring only memory and application specific peripherals to be added to form a complete on-board computer. All other system support functions are provided by the core.Figure 2. System Architecture Based on TSC695FTSC695F5TSC695F4118J–AERO–08/04P roduct D escriptionInteger UnitThe Integer Unit (IU) is designed for highly dependable space and military applications,and includes support for error detection. The RISC architecture makes the creation of a processor that can execute instructions at a rate approaching one instruction per pro-cessor clock possible.To achieve that rate of execution, the IU employs a four-stage instruction pipeline that permits parallel execution of multiple instructions. •Fetch - The processor outputs the instruction address to fetch the instruction.•Decode - The instruction is placed in the instruction register and is decoded. The processor reads the operands from the register file and computes the next instruction address.•Execute - The processor executes the instruction and saves the results in temporary registers. Pending traps are prioritized and internal traps are taken during this stage.•Write - If no trap is taken, the processor writes the result to the destination register.All four stages operate in parallel, working on up to four different instructions at a time. A basic ‘single-cycle’ instruction enters the pipeline and completes infour cycles.By the time it reaches the write stage, three more instructions have entered and are moving through the pipeline behind it. So, after the first four cycles, a single-cycle instruction exits the pipeline and a single-cycle instruction enters the pipeline on every cycle. Of course, a ’single-cycle’ instruction actually takes four cycles to complete, but they are called single cycle because with this type of instruction the processor can com-plete one instruction per cycle after the initial four-cycle delay.Floating-point UnitThe FLoating Point Unit (FPU) is designed to provide execution of single and double-precision floating-point instructions concurrently with execution of integer instructions by the IU. The FPU is compliant to the ANSI/IEEE-754 (1985) floating-point standard.The FPU is designed for highly dependable space and military applications, and includes support for concurrent error detection and testability.The FPU uses a four stage instruction pipeline consisting of fetch, decode, execute and write stages (F, D, E and W). The fetch unit captures instructions and their addresses from the data and address buses. The decode unit contains logic to decode the floating-point instruction opcodes. The execution unit handles all instruction execution. The exe-cution unit includes a floating-point queue (FP queue), which contains stored floating-point operate (FPop) instructions under execution and their addresses. The execution unit controls the load unit, the store unit, and the datapath unit. The FPU depends upon the IU to access all addresses and control signals for memory access. Floating-point loads and stores are executed in conjunction with the IU, which provides addresses and control signals while the FPU supplies or stores the data. Instruction fetch for integer and floating-point instructions is provided by the IU.The FPU provides three types of registers: f registers, FSR, and the FP queue. The FSR is a 32-bit status and control register. It keeps track of rounding modes, floating-point trap types, queue status, condition codes, and various IEEE exception information. The floating-point queue contains the floating-point instruction currently under execution,along with its corresponding address.6TSC695F4118J–AERO–08/04Instruction SetTSC695F instructions fall into six functional categories: load/store, arithmetic/logi-cal/shift, control transfer, read/write control register, floating-point, and miscellaneous.Please refer to SPARC V7 Instruction-set Manual.Note:The execution of IFLUSH will cause an illegal instruction trap.On-chip PeripheralsMemory Interface The TSC695F is designed to allow easy interfacing to internal/external memory resources.System RegistersThe system registers are only writable by IU in the supervisor mode or by DMA during halt mode.Table 2. Memory MappingMemory ContentsStart Address Size (bytes)Data Size and Parity Options Boot PROM0x 0000 0000128K → 16M8-bit mode No parity/-No EDAC/-Only byte write 40-bit modeParity + EDAC mandatory/-Only word write Extended PROM0x 0100 0000Max: 15M8-bit mode No parity/-No EDAC/-Only byte write 40-bit modeParity + EDAC mandatory/-Only word writeExchange Memory 0x 01F0 00004k → 512k Parity + EDAC option/-Only word write System Registers 0x 01F8 0000512K (124 used)Parity/-Only word read/write access RAM (8 blocks)0x 0200 00008*32K → 8*4M Parity + EDAC option/-All data sizes allowedExtended RAM 0x 0400 0000Max: 192M I/O Area 00x 1000 00000 → 16M Parity option/-All data sizes allowedI/O Area 10x 1100 00000 → 16M I/O Area 20x 1200 00000 → 16M I/O Area 30x 1300 00000 → 16M Extended I/O Area 0x 1400 0000Max: 1728M Extended General0x 8000 0000Max: 2GNo parity/-All data sizes allowed Table 3. System Registers Address MapSystem Register Name Address System Control Register SYSCTR 0x 01F8 0000Software Reset SWRST 0x 01F8 0004Power DownPDOWN 0x 01F8 0008System Fault Status Register SYSFSR 0x 01F8 00A0Failing Address Register FAILAR 0x 01F8 00A4Error & Reset Status Register ERRRSR 0x 01F8 00B0Test Control RegisterTESCTR0x 01F8 00D07TSC695F4118J–AERO–08/04Wait-state and Time-out GeneratorIt is possible to control the wait-state generation by programming a Wait-state Configu-ration Register. The maximum programmable number of wait-states is applied by default at reset.It is possible to program the number of wait-states for the following combinations:–RAM read and write–PROM read and write (i.e. EEPROM or Flash write)–Exchange Memory read/write–Four individual I/O peripherals read/writeA bus time-out function of 256 system clock cycles is provided for the bus ready con-trolled memory areas, i.e., the Extended PROM, Exchange Memory, Extended RAM,Memory Configuration Register MCNFR 0x 01F8 0010I/O Configuration Register IOCNFR 0x 01F8 0014Waitstate Configuration RegisterWSCNFR 0x 01F8 0018Access Protection Segment 1 Base Register APS1BR 0x 01F8 0020Access Protection Segment 1 End Register APS1ER 0x 01F8 0024Access Protection Segment 2 Base Register APS2BR 0x 01F8 0028Access Protection Segment 2 End Register APS2ER 0x 01F8 002C Interrupt Shape Register INTSHR 0x 01F8 0044Interrupt Pending Register INTPDR 0x 01F8 0048Interrupt Mask Register INTMKR 0x 01F8 004C Interrupt Clear Register INTCLR 0x 01F8 0050Interrupt Force Register INTFCR 0x 01F8 0054Watchdog Timer Register WDOGTR 0x 01F8 0060Watchdog Timer Trap Door SetWDOGST 0x 01F8 0064Real Time Clock Timer <Counter> Register RTCCR 0x 01F8 0080Real Time Clock Timer <Scaler> Register RTCSR 0x 01F8 0084General Purpose Timer <Counter> Register GPTCR 0x 01F8 0088General Purpose Timer <Scaler> Register GPTSR 0x 01F8 008C Timers Control RegisterTIMCTR 0x 01F8 0098General Purpose Interface Configuration Register GPICNFR 0x 01F8 00A8General Purpose Interface Data Register GPIDATR 0x 01F8 00AC UART ’A’ Rx & Tx Register UARTAR 0x 01F8 00E0UART ’B’ Rx & Tx Register UARTBR 0x 01F8 00E4UART Status RegisterUARTSR0x 01F8 00E8Table 3. System Registers Address Map (Continued)System Register Name Address8TSC695F4118J–AERO–08/04Extended I/O and the Extended General areas.EDACThe TSC695F includes a 32-bit EDAC (Error Detection And Correction). Seven bits (CB[6:0]) are used as check bits over the data bus. The Data Bus Parity signal (DPAR)is used to check and generate the odd parity over the 32-bit data bus. This means that altogether 40 bits are used when the EDAC is enabled.The TSC695F EDAC uses a 7-bit Hamming code which detects any double bit error on the 40-bit bus as a non-correctable error. In addition, the EDAC detects all bits stuck-at-one and stuck-at-zero failure for any nibble in the data word as a non-correctable error.Stuck-at-one and stuck-at-zero for all 32 bits of the data word is also detected as a non-correctable error.Memory and I/O ParityThe TSC695F handles parity towards memory and I/O in a special way. The processor can be programmed to use no parity, only parity or parity and EDAC protection towards memory and to use parity or no towards I/O. The signal used for the parity bit is DPAR.Memory RedundancyProgramming the Memory Configuration Register, the TSC695F provides chip selects for two redundant memory banks for replacement of faulty banks.Memory Access Protection•Unimplemented Areas - Access to all unimplemented memory areas are handled by the TSC695F and detected as illegal.•RAM Write Access Protection - The TSC695F can be programmed to detect and mask write accesses in any part of the RAM. The protection scheme is enabled only for data area, not for the instruction area. The programmable write access protection is based on two segments.•Boot PROM Write Protection - The TSC695F supports a qualified PROM write for an 8-bit wide PROM and/or for a 40-bit wide PROM.DMADMA InterfaceThe TSC695F supports Direct Memory Access (DMA). The DMA unit requests access to the processor bus by asserting the DMA request signal (DMAREQ). When the DMA unit receives the DMAGNT signal in response, the processor bus is granted. In case the processor is in the power-down mode the processor is permanent tri-stated, and a DMAREQ will directly give a DMAGNT. The TSC695F includes a DMA session time-out function.Bus ArbiterThe TSC695F always has the lowest priority on the system bus.TrapsA trap is a vectored transfer of control to the supervisor through a special trap table that contains the first four instructions of each trap handler. The base address of the table is established by supervisor and the displacement, within the table, is determined by the trap type. Two categories of traps can appear.9TSC695F4118J–AERO–08/04Synchronous TrapsTable 4. Synchronous TrapsTrapPriorityTrap Type (tt)CommentsReset1–Sources: SYSRESET* pin software reset watchdog resetIU or System error resetH a r d w a r e E r r o rNon-restartable, imprecise error22.164h Severe error requiring a re-bootTSC695F enters (if not masked) in halt or reset mode Non-restartable,precise error 2.262h Error not removable, PC & nPC OKTSC695F enters (if not masked) in halt or reset mode Register file error 2.365h Special case of non-restartable, precise error.TSC695F enters (if not masked) in halt or reset mode Restartable, late error 2.463h Retrying instruction but PC & nPC have to be re-adjusted TSC695F enters (if not masked) in halt or reset mode Restartable,precise error2.561hRetrying instructionTSC695F enters (if not masked) in halt or reset mode Instruction access(Error on instruction fetch )301h Parity error on control bus Parity error on data bus Parity error on address busAccess to protected or unimplemented area Uncorrectable error in memory Bus time out Bus errorIllegal Instruction 402h –Privileged instruction 503h –FPU disabled604h –WindowOverflow705h During SAVE instruction or trap takenUnderflow06h During RESTORE instruction or RETT instructionMemory address not aligned807h–F P U e x c e p t i o nNon-restartable error 99.108hSevere error, cannot restart the instruction Data bus error 9.2Parity error on FPU data busRestartable error 9.3Can be removed restarting the instructionSequence error 9.4–Unimplemented FPop 9.5–IEEE exceptions:9.6Invalid operation Division by zero Overflow Underflow Inexact10TSC695F4118J–AERO–08/04It is possible to mask each individual interrupt (except Watchdog time-out). The interrupts in the Interrupt Pending Register are cleared automatically when the interrupt is acknowledged.By programming the Interrupt Shape Register, it is possible to define the external interrupts to either be active low or active high and to define the external interrupts to either be edge or level sensitive.Data access exception (Error on data load )1009h Idem “instruction access”System register access violation Tag overflow 110Ah TADDccTV and TSUBccTV instructions Trap instructions1280h to FFhTrap on integer condition codes (Ticc)Table 4. Synchronous Traps (Continued)TrapPriorityTrap Type (tt)CommentsTable 5. Interrupts or Asynchronous TrapsTrap Priority Trap Type (tt)CommentsWatchdog time-out 131Fh Internal or external (EWDINT pin)External INT 4141Eh EXTINTAK on only one of EXTINT[4:0]Real time clock timer 151Dh –General purpose timer 161Ch –External INT 3171Bh EXTINTAK on only one of EXTINT[4:0]External INT 2181Ah EXTINTAK on only one of EXTINT[4:0]DMA time-out 1919h –DMA access error 2018h –UART Error2117h –Correctable error in memory 2216h Data read OK but source not updatedUART B Data readyTransmitter ready 2315h –UART AData readyTransmitter ready2414h –External INT 12513h EXTINTAK on only one of EXTINT[4:0]External INT 02612hEXTINTAK on only one of EXTINT[4:0]Masked hardware errors 2711hLogical OR of:IU hardware error masked IU error mode maskedSystem hardware error maskedTSC695F Timers In software debug mode the timers are controlled by a system register bit and the exter-nal pin DEBUG.General Purpose Timer The General Purpose Timer (GPT) provides, in addition to a generalized counter func-tion, a mechanism for setting the step size in which actual time counts are performed.GPT is clocked by the internal system clock. They are possible to program to be eitherof single-shot type or periodical type and in both cases generate an interrupt when thedelay time has elapsed. The current value of the scaler and counter of the GPT can beread.Real Time Clock Timer The only functional differences between the two timers are that the Real Time ClockTimer (RTCT) has an 8-bit scaler (16-bit scaler for GPT) and that the RTCT interrupt hashigher priority than the GPT interrupt.RTCT information is available on RTC output pin.Watchdog Timer Setting the external pin IWDE to V CC enables the internal watchdog timer. Otherwise thewatchdog function must be externally provided.The watchdog is supplied from a separate external input (WDCLK). After reset, the timeris enabled and starts running with the maximum range. If the timer is not refreshed(reprogrammed) before the counter reaches zero value, an interrupt is sent. Simulta-neously, the timer starts counting a reset time-out period. If the timer is notacknowledged before the reset time-out period elapses, a reset is applied to TSC695F. UARTs Two full duplex asynchronous receiver transmitters (UART) are included. In softwaredebug mode the UART’s are controlled by system register bits.The data format of the UART’s is eight bits. It is possible to choose between even or oddparity, or no parity, and between one and two stop bits. The UART’s provide double buff-ering, i.e. each UART consists of a transmitter holding register, a receiver holdingregister, a transmitter shift register, and a receiver shift register. Each of these registersare 8-bit wide. For each UART a RX and TX Register is provided. The UART’s generatean interrupt each time a byte has been received or a byte has been sent. There isanother interrupt to indicate errors.The baud rate of both the UART’s is programmable. The clock is derived either from thesystem clock or can use the watchdog clock.General Purpose Interface The General Purpose Interface (GPI) is an 8-bit parallel I/O port. Each pin can be config-ured as an input or an output.A falling or rising edge detection is made on each selected GPI inputs. Every input tran-sition on GPI generates an external positive pulse on GPIINT pin of two SYSCLK width. Execution ModesReset Mode Reset mode is entered when:–The SYSRES input is asserted–Software reset which is caused by the software writing to a Software ResetRegister–Watchdog reset which is caused by a Watchdog counter time-out–Error reset which is caused by a hardware parity errorThis RESET output has a minimum of 1024 SYSCLK width to allow the usage of Flashmemories.The error and Reset Status Register contain the source of the last processor reset. Run Mode In this mode the IU/FPU is executing, while all peripherals are running (if softwareenabled).System Halt Mode System Halt mode is entered when the SYSHALT input is asserted. In this mode, the IUand FPU are frozen, while the timers (includeing the internal watchdog timer) andUART’s are stopped.Power Down Mode This mode is entered by writing to the Power-down Register. In this mode, the IU andFPU are frozen. The TSC695F leaves the power-down mode if an external interrupt isasserted.Error Halt Mode Error Halt mode is entered under the following circumstances:– A internal hardware parity error.–The IU enters error mode.The only way to exit Error Halt Mode is through Cold Reset by asserting SYSRESET. Error Handler The TSC695F has one error output signal (SYSERR) which indicates that an unmaskederror has occurred. Any error signalled on the error inputs from the IU and the FPU islatched and reflected in the Error and Reset Status Register. By default, an error leadsto a processor halt.Parity Checking The TSC695F includes:–Parity checking and generation (if required) on the external data bus–Parity checking on the external address bus–Parity checking on ASI and SIZE–Parity checking and generation on all system registers–Parity generation and checking on the internal control bus to the IUAll external parity checking can be disabled using the NOPAR signal.System Clock The TSC695F uses CLK2 clock input directly and creates a system clock signal bydividing CLK2 by two. It drives SYSCLK pin with a nominal 50% duty cycle for the appli-cation. It is highly recommended that only SYSCLK rising edge is used as reference asfar as possible.System Availability The SYSAV bit in the Error and Reset Status Register can be used by software to indi-cate system availability.Test Mode The TSC695F includes a number of software test facilities such as EDAC test, Paritytest, Interrupt test, Error test and a simple Test Access Port. These test functions arecontrolled using the Test Control Register.TSC695FTest and Diagnostic Hardware FunctionsA variety of TSC695F test and diagnostic hardware functions, including boundary scan,internal scan, clock control and On-chip Debugger, are controlled through an IEEE 1149.1 (JTAG) standard Test Access Port (TAP).Test Access PortThe TAP interfaces to the JTAG bus via 5 dedicated pins on the TSC695F chip. These pins are:•TCK (input): T est Clock •TMS (input): Test Mode Select •TDI (input): Test Data Input •TDO (output): Test Data Output •TRST (input): Test ResetInstruction RegisterFive standard instructions are supported by the TSC695F TAP.DebuggingThe design is highly testable with the support of an On-Chip Debugger (OCD), an inter-nal and boundary scan through JTAG interface.Binary Value Name of Instruction Data Register Scan Chain Accessed 00. 0000EXTESTBoundary Scan Register Boundary scan chain 00. 0001SAMPLE/PRELOAD Boundary Scan Register Boundary scan chain 00. 0011INTEST Boundary Scan Register Boundary scan chain 11. 1111BYPASS Bypass Register Bypass register 10. 0000IDCODEDevice ID RegisterID register scan chainElectrical CharacteristicsDC Characteristics Note: Stresses at or above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability.Table 6. DC Characteristics at V DD 5V ± 10%Symbol Parameter Min Typ Max Unit Test ConditionsVIL trigger Input Low Voltagefor trigger input––0.8V V CC = 4.5 to 5.5VVIH trigger Input High Voltagefor trigger input3.0––V V CC =4.5 to5.5V∆VT Input Hysteresisfor trigger input–0.9–V V CC = 4.5 to 5.5VVIL TTL Input Low Voltagefor TTL input––0.8V V CC = 4.5 to 5.5VVIH TTL Input High Voltagefor TTL input2.2––V V CC = 4.5 to 5.5VVOL400 pF Output Low Voltagefor 400 pF buffer–0.30.4VV CC = 4.5 to 5.5VIOL = 12 mAVOH400 pF Output High Voltagefor 400 pF buffer2.40.3–VV CC = 4.5 to 5.5VIOH = -16 mAVOL150 pF Output Low Voltagefor 150 pF buffer–0.30.4VV CC = 4.5 to 5.5VIOL = 4 mAVOH150 pF Output High Voltagefor 150 pF buffer2.4 4.3–VV CC = 4.5 to 5.5VIOH = -6 mAIccOP Operating Supply Currentfor core processor––230mAV CC = 5.5V, f = 25 MHz––210V CC = 5.5V, f = 20 MHz––170V CC = 5.5V, f = 10 MHzIccPD Power Down Supply Currentfor core processor––41mAV CC = 5.5V, f = 25MHz––38V CC = 5.5V, f = 20 MHz––30V CC = 5.5V, f = 10 MHz。

STY139N65M5;中文规格书,Datasheet资料

This is information on a product in full production.April 2012Doc ID 022826 Rev 31/12STY139N65M5N-channel 650 V , 0.014 Ω, 130 A, MDmesh™ V Power MOSFETin Max247 packageDatasheet — production dataFeatures■Max247 worldwide best R DS(on)■Higher V DSS rating ■Higher dv/dt capability■Excellent switching performance ■Easy to drive■100% avalanche testedApplications■Switching applicationsDescriptionThe device is an N-channel MDmesh™ V Power MOSFET based on an innovative proprietary vertical process technology, which is combined with STMicroelectronics’ well-knownPowerMESH™ horizontal layout structure. The resulting product has extremely low on-resistance, which is unmatched among silicon-based Power MOSFETs, making it especially suitable for applications which require superior power density and outstanding efficiency.Order code V DSS @T jMAX R DS(on) max I D STY139N65M5710 V< 0.017 Ω130 ATable 1.Device summaryOrder code Marking Package Packaging STY139N65M5139N65M5Max247TubeContents STY139N65M5Contents1Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42.1Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122/12Doc ID 022826 Rev 3STY139N65M5Electrical ratingsDoc ID 022826 Rev 33/121 Electrical ratingsTable 2.Absolute maximum ratingsSymbol ParameterValue Unit V GS Gate- source voltage± 25V I D Drain current (continuous) at T C = 25 °C 130A I D Drain current (continuous) at T C = 100 °C 78A I DM (1)1.Pulse width limited by safe operating area.Drain current (pulsed)520A P TOT Total dissipation at T C = 25 °C625W I AR Max current during repetitive or single pulse avalanche(pulse width limited by T JMAX )15A E AS Single pulse avalanche energy(starting T j = 25°C, I D = I AR , V DD = 50V)2000mJ dv/dt (2)2.I SD ≤ 130 A, di/dt = 400 A/µs, V DD = 400 V, peak V DS < V (BR)DSS.Peak diode recovery voltage slope 15V/ns T stg Storage temperature- 55 to 150°C T jMax. operating junction temperature150°CTable 3.Thermal dataSymbolParameterValue Unit R thj-case Thermal resistance junction-case max 0.2°C/W R thj-amb Thermal resistance junction-ambient max 30°C/W T lMaximum lead temperature for soldering purpose300°CElectrical characteristics STY139N65M54/12Doc ID 022826 Rev 32 Electrical characteristics(T C = 25 °C unless otherwise specified)Table 4.On /off statesSymbol Parameter Test conditionsMin.Typ.Max.Unit V (BR)DSS Drain-sourcebreakdown voltageI D = 1 mA, V GS = 0650V I DSS Zero gate voltage drain current (V GS = 0)V DS = 650 VV DS = 650 V , T C =125 °C 10100µA µA I GSS Gate-body leakage current (V DS = 0)V GS = ± 25 V±100nA V GS(th)Gate threshold voltage V DS = V GS , I D = 250 µA 345V R DS(on)Static drain-source onresistanceV GS = 10 V , I D = 65 A0.0140.017ΩTable 5.DynamicSymbol Parameter Test conditionsMin.Typ.Max.Unit C iss C oss C rss Input capacitance Output capacitance Reverse transfer capacitance V DS = 100 V , f = 1 MHz, V GS = 0-156003659-pF pF pFC o(tr)(1)1.C o(tr) is a constant capacitance value that gives the same charging time as C oss while V DS is rising from 0to 80% V DSS .Equivalentcapacitance time relatedV GS = 0, V DS = 0 to 520 V-1559-pFC o(er)(2)2.C o(er) is a constant capacitance value that gives the same stored energy as C oss while V DS is rising from 0to 80% V DSS .Equivalentcapacitance energy related V GS = 0, V DS = 0 to 520 V -360-pFR GIntrinsic gate resistancef = 1 MHz open drain - 1.2-ΩQg Q gs Q gdT otal gate charge Gate-source charge Gate-drain chargeV DD = 520 V , I D = 65 A,V GS = 10 V (see Figure 15)-36388164-nC nC nCSTY139N65M5Electrical characteristicsDoc ID 022826 Rev 35/12Table 6.Switching timesSymbol ParameterTest conditions Min.Typ.Max.Unitt d(v)t r(v)t f(i)t c(off)Voltage delay time Voltage rise time Current fall time Crossing timeV DD = 400 V , I D = 80 A, R G = 4.7 Ω, V GS = 10 V (see Figure 16)(see Figure 19)-295563784-ns ns ns nsTable 7.Source drain diodeSymbol ParameterTest conditionsMin.Typ.Max.Unit I SD I SDM (1)1.Pulse width limited by safe operating area.Source-drain currentSource-drain current (pulsed)-130520A A V SD (2)2.Pulsed: pulse duration = 300 µs, duty cycle 1.5%Forward on voltage I SD = 130 A, V GS = 0- 1.5V t rr Q rr I RRM Reverse recovery time Reverse recovery charge Reverse recovery current I SD = 130 A, di/dt = 100 A/µs V DD = 100 V (see Figure 16)-5701553ns µC A t rr Q rr I RRMReverse recovery time Reverse recovery charge Reverse recovery currentI SD = 130 A, di/dt = 100 A/µs V DD = 100 V , T j = 150 °C (see Figure 16)-7202468ns µC AElectrical characteristics STY139N65M5 2.1 Electrical characteristics (curves)6/12Doc ID 022826 Rev 3STY139N65M5Electrical characteristicsDoc ID 022826 Rev 37/12Figure 10.Normalized gate threshold voltageFigure 11.Normalized on resistance vsFigure 12.Output capacitance stored energyFigure 13.Switching losses vs gate resistance(1)1.Eon including reverse recovery of a SiC diode.Test circuits STY139N65M58/12Doc ID 022826 Rev 33 Test circuitsFigure 14.Switching times test circuit forFigure 15.Gate charge test circuitFigure 16.Test circuit for inductive loadFigure 17.Unclamped inductive load testFigure 18.Unclamped inductive waveformFigure 19.Switching time waveformSTY139N65M5Package mechanical data 4 Package mechanical dataIn order to meet environmental requirements, ST offers these devices in different grades ofECOP ACK® packages, depending on their level of environmental compliance. ECOPACK®specifications, grade definitions and product status are available at: .ECOP ACK® is an ST trademark.Table 8.Max247 mechanical datammDim.Min.Typ.Max.A 4.70 5.30A1 2.20 2.60b 1.00 1.40b1 2.00 2.40b2 3.00 3.40c0.400.80D19.7020.30e 5.35 5.55E15.3015.90L14.2015.20L1 3.70 4.30Doc ID 022826 Rev 39/12Package mechanical data STY139N65M510/12Doc ID 022826 Rev 3分销商库存信息: STMSTY139N65M5。

1SMB6.5AT3中文资料(motorola)中文数据手册「EasyDatasheet - 矽搜」

tr 10µs
值（％）
50
半值 - RSM I 2
tP
0.1 0.1
µs
1 µs
10 µs 100µs
0
1毫秒 10毫秒
0
1
2
3
4
总磷,脉冲宽度
T,时间（ms）
160 C ° 140
A 120
图 1.脉冲额定值 Curve
图 2.脉冲波形典型防护护电路
Zin
100
80
Vin
LOAD
VL
60
峰值脉冲4降0 容％峰值功20率或电流@ T = 25
性,如图4.
该装置中感应作用是由于实际导通所需设备时间（时间去从零电流到全
电流）和引线电感.这种诱导效应产生
在两端电压设备过冲或
部件防护护,如图5最小化这种过冲是在应用非常重要,因为
用于添加瞬变抑制器主要目是夹紧
电压尖峰.在SMB系列有一个很好反响时间,通常为1纳秒和可以忽略不计电感.然而,
外部感应影响可能产生不能接受过
IPP
峰值脉冲电流 - 见图2
PP
峰值脉冲功率
IR
反向漏
600瓦峰值功率数据表 5-2
芯片中文手册,看全文,戳
一般数据 - 600瓦峰值功率
100 10 PP,峰值1 功率（KW）
非重复脉冲波形
如图2中所示
tr 100
峰值 - IRSM
脉冲宽度（TP）定义因为这地步PEAK 电流衰减到50％ IRSM.作者：
(Refer to Section 10 for more information on Packaging Specifications.)
0.089 2.261

TPS65166RHAR;中文规格书,Datasheet资料

FEATURESAPPLICATIONSDESCRIPTIONTYPICAL APPLICATIONBoost Converter With HVS Buck Converter Negative Shunt Regulator Inverting Buck BoostWith Temperature Compensation Sequencing And LogicPositive Charge Pump Power GoodV s15V / 2.9AV logic3.3V / 2.4A V ONE28V / 150mAV OFFE-22 to -11V / 200mA V ss-7.5V / 100mA V in12VTPS65166 SLVS976–SEPTEMBER 2009Compact LCD Bias Supply for TFT-LCD TV Panels•LCD TV Panel with ASG Technology•8.5V to 14.7V Input Voltage Range •V S Output Voltage Range up to 19V•Boost Converter with 4.2A Switch CurrentThe TPS65166offers a compact power supply •Step Down Converter with 2.6A Switch Current solution to provide all voltages required by a LCD and Adjustable Output 2.5V to 3.3V panel for large TV panel applications running from a •750kHz Fixed Switching Frequency12V supply rail.The device is optimized to support •Temperature Compensated Negative Supply LCD technology using ASG gate drive circuits.•High Voltage Stress Test (HVS)The device generates all voltage rails for the TFT LCD bias (V S ,V ONE ,V OFFE ,V SS ).In addition to that it •Adjustable Sequencingincludes a step-down converter (V logic )to provide the •Gate Drive Signal for Isolation Switch logic voltage.By pulling the HVS pin high an •Short Circuit Protection implemented high voltage stress test feature •Internal Soft-Startprograms the boost converter output voltage V s to higher values.The boost converter operates at a •180°Phase Shift Between Buck and Boost fixed switching frequency of 750kHz.The positive •P2P Short/Open Certifiedcharge pump is running from the boost converter and •Optimized Dual Layer PCB Layout is regulated by an external transistor.A buck-boost converter provides an adjustable temperature •Low EMIdependent negative output voltage V OFFE .The •Undervoltage Lockout negative output voltage V SS is regulated by a shunt •Thermal Shutdownregulator.•Available in 6×6mm 40Pin QFN PackageSafety features like overvoltage protection of the buck-boost input voltage,the boost and buck output voltage,undervoltage lockout,short circuit protection of V ONE ,V OFFE ,and V logic are included as well as thermal shutdown.Please be aware that an important notice concerning availability,standard warranty,and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.PowerPAD is a trademark of Texas Instruments.PRODUCTION DATA information is current as of publication date.Copyright ©2009,Texas Instruments IncorporatedProducts conform to specifications per the terms of the Texas Instruments standard warranty.Production processing does not necessarily include testing of all parameters.ABSOLUTE MAXIMUM RATINGSDISSIPATION RATINGS (1)RECOMMENDED OPERATING CONDITIONS (1)TPS65166SLVS976–SEPTEMBER These devices have limited built-in ESD protection.The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.ORDERING INFORMATION (1)(2)T AORDERING PACKAGE PACKAGE MARKING–40°C to 85°CTPS65166RHAR6×6mm 40Pin QFNTPS65166(1)For the most current package and ordering information,see the Package Option Addendum at the end of this document,or see the TI website at .(2)The RHA package is available taped and reeled.Add R suffix to the device type (TPS65166RHAR)to order the device taped and reeled.The RHA package has quantities of 3000devices per reel.over operating free-air temperature range (unless otherwise noted)(1)VALUEUNIT Input voltage range AVIN,VIN1,VIN2,VIN3(2)–0.3to 20V Voltage range at SW1,SW2,SW3,SW4,GD,BASE2,RHVS,OS –0.3to 20V Voltage range at EN1,EN2,HVS–0.3to 20V Voltage range at COMP,SS,FB1,VSNS,FB2,FB3,FB4,TS,SET,FB5,DLY1,DLY2,PG –0.3to 7.0V Voltage difference VIN3to SW540V BASE1–9.5to 0.3V ESD rating,Human Body Model 2kV ESD rating,Machine Model 200V ESD rating,Charged Device Model 700V Continuous total power dissipation See Dissipation Rating TableOperating junction temperature range,T J –40to 150°C Operating ambient temperature range,T A –40to 85°C Storage temperature range,T stg –65to 150°C(1)Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device.These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied.Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.(2)All voltage values are with respect to network ground terminal.PACKAGE R θJA T A ≤25°C T A =70°C T A =85°C POWER RATINGPOWER RATINGPOWER RATING40pin QFN35°C/W2.8W1.6W1.1W(1)Soldered Power Pad on a standard 2-Layer PCB without vias for thermal pad.See the Texas Instruments Application report (SLMA002)regarding thermal characteristics of the PowerPAD package.MINTYPMAX UNIT V IN Input voltage range (AVIN,VIN1,VIN2,VIN3)8.514.7V V IN3Overvoltage protection 15V for buck-boost converter 15V T A Operating ambient temperature –4085°C T J Operating junction temperature–40125°C(1)Refer to application section for further information2Submit Documentation FeedbackCopyright ©2009,Texas Instruments IncorporatedProduct Folder Link(s):TPS65166ELECTRICAL CHARACTERISTICS TPS65166 SLVS976–SEPTEMBER2009 AVIN=VIN1=VIN2=VIN3=12V,EN1=EN2=VIN,V S=15V,V logic=3.3V,T A=–40°C to85°C,typical values are at T A=25°C(unless otherwise noted)PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY CURRENTV IN Input voltage range8.514.7VI QIN Quiescent current into AVIN,VIN1,2,3Not switching,FB=FB+5% 1.2mAI sd Shutdown current into AVIN,VIN1,2,3EN1=EN2=GND170µAV UVLO Under-voltage lockout threshold V IN falling8.08.2VV UVLO Under-voltage lockout threshold V IN rising8.28.5V Thermal shutdown Temperature rising150°CThermal shutdown hysteresis15°C LOGIC SIGNALS EN1,EN2,HVSV IH High level input voltage V IN=8.5V to14.7V 1.7VV IL Low level input voltage V IN=8.5V to14.7V0.4VI I Input leakage current EN1=EN2=GND0.010.1µA POWER GOODV IL Low level voltage(1)I(sink)=500µA0.3VI lkg Leakage current V PG=5.0V0.010.1µA SEQUENCING DLY1,DLY2,and SOFT-STARTI chrg DLY1,DLY2charge current V threshold=1.24V4 4.9 6.3µAV threshold DLY1,DLY2threshold voltage 1.21 1.24 1.27VR dischrg DLY1,DLY2discharge resistor 3.2kΩI SS Soft-start charge current V threshold=1.24V81012µA SWITCHING FREQUENCYf s Switching frequency600750900kHz BOOST CONVERTER(V s)V s Output voltage range19VV swovp Switch overvoltage protection V s rising19.019.520VV FB1Feedback regulation voltage 1.225 1.24 1.252VI FB1Feedback input bias current V FB1=1.24V10100nAR DS(on)N-MOSFET on-resistance I SW=500mA120170mΩI LIM N-MOSFET switch current limit 4.2 5.2 6.2AI leak Switch leakage current V sw=15V110µAt on Minimum on time80ns Line regulation8.5V≤V IN≤14.7V,I out=1mA0.006%/VLoad regulation1mA≤I out≤2.0A0.1%/A GATE DRIVE(GD)AND BOOST CONVERTER PROTECTIONVGD M V IN–V GD(2)V IN=12V,GD pulled down567VI(GD)Gate drive sink current EN2=high10µAR(GD)Gate drive internal pull up resistance10kΩt on Gate on time during short circuit FB1<100mV 1.4ms BUCK CONVERTER(V logic)V logic Output voltage range 2.2 4.0VFB2connected to resistor divider,V FB2Feedback regulation voltage 1.215 1.24 1.265VI load=10mAI FB2Feedback input bias current V FB2=1.24V10100nAR DS(on)N-MOSFET on-resistance I sw3,I sw4=1.5A150250mΩ(1)PG goes high impedance once V s and V ONE are in regulation.(2)GD goes to V IN–V GD once the boost converter V s is enabled.Copyright©2009,Texas Instruments Incorporated Submit Documentation Feedback3Product Folder Link(s):TPS65166TPS65166SLVS976–ELECTRICAL CHARACTERISTICS(continued)AVIN=VIN1=VIN2=VIN3=12V,EN1=EN2=VIN,V S=15V,V logic=3.3V,T A=–40°C to85°C,typical values are at T A=25°C (unless otherwise noted)PARAMETER TEST CONDITIONS MIN TYP MAX UNIT I LIM N-MOSFET switch current limit 2.6 3.4 4.2AI leak Switch leakage current V sw=0V1µALine regulation8.5V≤V IN≤14.7V,I out=1mA0.006%/V1mA≤I out≤100mA0.042%/mA Load regulation100mA≤I out≤2.5A0.06%/A NEGATIVE SHUNT REGULATOR(V ss)V Base1Base1voltage range Transistor leakage maximum5µA–9.50.3VI Base1Base1drive source current V FB3=V FB3nominal–5%5mA0.75×V FB3Feedback regulation voltage–5%5%VV logicI FB3Feedback input bias current VFB3=1.24V10100nALine regulation8.5V≤V IN≤14.7V,I out=1mA0.006%/VLoad regulation1mA≤I out≤100mA0.0004%/mA NEGATIVE BUCK BOOST CONVERTER(V OFFE)V ovp VIN3overvoltage protection15VV OFFE Adjustable output voltage range–22-5VR DS(on)P-MOSFET on resistance I SW5at current limit0.9 1.6ΩI LIM P-MOSFET current limit 1.1 1.4ARegulation accuracy upper limit V TS=1V,V SET=1.9V 1.8 1.9 2.0VV FB5Regulation accuracy V TS=1V,V SET=2.4V 1.92 2.1V Regulation accuracy lower limit V TS=0.7V,V SET=2.4V 1.57 1.65 1.73VI FB5Feedback input bias current V FB5=2V10100nAI TS TS input bias current V TS=1V10100nAI SET SET input bias current V SET=3V35µALine regulation8.5V≤V IN≤14.7V,I out=1mA0.003%/VLoad regulation1mA≤I out≤200mA,V OFFE=–11V0.0005%/mA POSITIVE CHARGE PUMP(V ONE)Base2drive sink current V FB4=V FB4nominal-5%814mAI Base2Base2drive sink current(SC-Mode)V FB4=GND405070µAV Base2Base drive voltage range20VV FB4Feedback regulation voltage 1.18 1.24 1.30VI FB4Feedback input bias current V FB4=1.24V10100nALine regulation8.5V≤V IN≤14.7V,I out=1mA0.9%/VLoad regulation1mA≤I out≤150mA,V OFFE=–11V0.004%/mA HIGH VOLTAGE STRESS TEST(HVS),RHVSRHVS RHVS pull down resistance HVS=high,I HVS=500µA350450550ΩI RHVS RHVS leakage current HVS=low,V RHVS=5V100nA4Submit Documentation Feedback Copyright©2009,Texas Instruments IncorporatedProduct Folder Link(s):TPS65166DEVICE INFORMATIONPACKAGESW3SW4NC FB2P GD L Y 1E N 1E N 2H V SF B 3SET AGND/VL-NC NC BASE2P G N D 1P G N D 2S W 1S W 2O SS SB A S E 1D L Y 2F B 4SW 5NC NC FB 5TS GD AVIN VIN1VIN2NC C O M PR H V SV I N 3F B 140 Pin 6mm x 6mm QFN(Top View)V L +TPS65166 SLVS976–SEPTEMBER 2009NOTE:The thermally enhance Power Pad is connected to GNDPIN FUNCTIONSPINI/O DESCRIPTIONNAME NO.GD 1I Gate drive pin for the external isolation MOSFET.AVIN 2I Input voltage supply pin for the analog circuit.VIN1,VIN23,4IInput supply for the buck converter generating V logic NC 5Not connectedSW3,SW46,7O Switch pin for the buck converter generating V logic NC 8Not connectedVSNS 9I Reference voltage input for the buck-boost and negative shunt regulator FB210I Feedback pin for the buck converter.PG 11I Power good output latched high when V S and V ONE are in regulation DLY112O Delay pin EN2high to enable boost converter V S EN113I Enable of the buck converter V logicEN214I Enable of the negative supplies V SS and V OFFE ,enable DLY1and DLY2HVS 15I Logic pin to enable high voltage stress test.This allows programming the boost converter V S to ahigher voltageFB316I Feedback of the negative supply V SS SS17O Soft-start for the boost converter V SCopyright ©2009,Texas Instruments IncorporatedSubmit Documentation Feedback5Product Folder Link(s):TPS65166TPS65166SLVS976–PIN FUNCTIONS(continued)PINI/O DESCRIPTIONNAME NO.BASE118O Base drive of the external npn transistor for the negative supply V SSDLY219O Delay pin EN2high to enable charge pump V ONEFB420I Feedback for the positive supply V ONEBASE221I Base drive of the external pnp transistor for the positive charge pump V ONENC22,23Not connectedAGND/VL-24Analog ground and connection of the bypass capacitor of VL-SET25I Input pin for the reference voltage to set the higher limit for the temperature compensation forV OFFETS26I Input pin for the NTC temperature sensorFB527I Feedback pin for the negative buck-boost converter V OFFENC28,29Not connectedSW530O Switch pin for the negative buck-boost converter generating V OFFEVIN331I Input supply for the buck-boost converter generating V OFFERHVS32I This pin is pulled low when HVS is high.The resistor connected to this pin sets the boostconverter output voltage when HVS is pulled highFB133I Feedback for the boost converter V SCOMP34O Compensation pin for the boost converterVL+35O Output of the internal logic regulator.Connect a capacitor between this pin and AGND/VL-OS36I Connect this pin to the boost converter output for overvoltage protectionSW1,SW237,38I Switch pin for the boost converter and the positive charge pump V ONEPGND1,39,40Power ground for the boost converter V SPGND26Submit Documentation Feedback Copyright©2009,Texas Instruments IncorporatedProduct Folder Link(s):TPS65166TPS65166 SLVS976–SEPTEMBER2009Functional Block DiagramCopyright©2009,Texas Instruments Incorporated Submit Documentation Feedback7Product Folder Link(s):TPS65166TPS65166SLVS976–8Submit Documentation Feedback Copyright©2009,Texas Instruments IncorporatedProduct Folder Link(s):TPS65166TYPICAL CHARACTERISTICS TABLE OF GRAPHS TPS65166 SLVS976–SEPTEMBER2009Copyright©2009,Texas Instruments Incorporated Submit Documentation Feedback9Product Folder Link(s):TPS65166TPS65166SLVS976–Figure1.Figure2.Figure3.Figure4.10Submit Documentation Feedback Copyright©2009,Texas Instruments IncorporatedProduct Folder Link(s):TPS65166分销商库存信息: TITPS65166RHAR。

MediaTek-MT6515说明书

PCB layout模块设计使用说明 For MT6515/MT6517
V1.0
Copyright © MediaTek Inc.AAlllrrigighhttssrreesseerrvveedd..
2012/03/26
引言
现今智能手机设计趋势走向轻、薄、与大电池容量等需求，系统电路板(PCB)为符合此设计趋势，必须同时满足CPU 和 mobile memory 上之电源传输网络(PDN)、高频电性等之设计规范，因而大幅增加PCB设计上的时间与复杂度。
– 提升RD circuit design & PCB layout设计效率，减少resource耗费. – 避免不正确的circuit design & PCB layout造成performance issue，
减少review &后续debug的resource耗费.
▪ 什么状况适合运用Schematic & PCB模块化?
▪ MT6515 PCB Layout模块列表
TCogpeytrhigehrt, W© eMmedaiakeTethkeIndcif.feArlel nricgeh.ts reserved. 2012/3/27 6
MT6515 PCB模块说明与使用
▪ 如何选择及使用合适的PCB模块?
决定PCB的迭构、层数、以及 Memory type (LPDDR/LPDDR2)
– 高密度/高速PCB layout区域. (如 Main chip, MCP memory, RF….etc.)
– 较敏感的电路PCB layout. – 机构与PCB迭构可以被修ehrt, W© eMmedaiakeTethkeIndcif.feArlel nricgeh.ts reserved. 2012/3/27 3

EMC45DRYI中文资料(List Unclassifed)中文数据手册「EasyDatasheet - 矽搜」

68.58 73.66 76.20 86.36 88.90 99.06
106.68 109.22 121.92 124.46 129.54 149.86
B
+_ 0.20
12.70 15.24 17.78 20.32 22.86
27.94 33.02 35.56 40.64 45.72 48.26
50.80 53.34 58.42 60.96 66.04 68.58
.275 [6.98]
.225 [5.72]
字母b SIDE
0.016 [0.41]厚, 总体PLATED ONLY
.007 [0.18] THICK
EYELET (TE)
EYELET (RE)
FITS .043 [1.09]
直角
(RA)
.125 [3.18]
.185 [4.70]
.050 [1.27]
C = PPS /铍镍（咨询工厂） N = PEEK /铍铜（咨询工厂） W = PEEK /铍镍（咨询工厂）
F = PPS / Pfinodal ***（咨询工厂）
咨询工厂其他材料
触点表面涂层
接触面
Z = 0.000010"金 X = 0.000030"金 G = 0.000010"金奖 Y = 0.000030"金奖
5.275 5.575
5.475 5.775
6.275 6.575
ቤተ መጻሕፍቲ ባይዱ
E
+_.020
1.275 1.375 1.475 1.575 1.675
1.875 2.075 2.175 2.375 2.575 2.675
2.775 2.875 3.075 3.175 3.375 3.475

19665;中文规格书,Datasheet资料

Dual-Wire Dual-Operator Programmable Monitor DescriptionThe patented* Desco Dual-Wire Dual-OperatorProgrammable Monitor monitors two operators and two ESD work worksurfaces eliminating the need for periodic Figure 1. Desco 19665 Dual-Wire Dual-Operator Programmable MonitorFeatures and ComponentsTECHNICAL BULLETIN TB-3019Made in theUnited States of AmericaFigure 2. Dual-Wire Dual-Operator Programmable CBDE FG H I J K LFRONT VIEWBACK VIEWOperation1. Monitoring of the operators will remain in the STANDBY condition until a wrist cord is plugged into the operator remote. STANDBY mode is indicated by a blinking yellow operator LED.10mm snap needs to pierce and clinch bottom side of mat. Snap needs to be at least 12" apart or 72" max. 10mm snap needs to pierce and clinch bottom side of mat. Snap needs to be at least 12" apart or 72" max.OPERATOR 1WORKSURFACEOPERATOR 2WORKSURFACE10mm PUSH & CLINCH SNAP10mm PUSH & CLINCH SNAPBENCH GROUNDMAT 1 WIRING WHITE CABLEMAT 2 WIRING BLACK CABLEWRIST STRAP MONITORWRIST STRAP MONITORELECTRIC GROUNDOPERATOR 2REMOTE JACK BLACK CABLEOPERATOR 2REMOTE JACK WHITE CABLE Screw allows ground cord to be bolted to mat; keeps cord from disconnecting.Figure 3. Installing the Dual-Wire Dual-Operator Programmable MonitorororFigure 4. Connecting a dual-wire wrist strap to the operator remoteSETTING THE OPERATOR TEST VOLTAGE AND TEST LIMITThe Dual-Wire Dual-Operator Monitor’s operator test voltage and high test limit can be set to different values. The operator test voltage can be set to either +5V or +8V, and the operator high test limit can be set to either 10 megohms or 35 megohms. The default voltage is +8V, and the default operator high test limit is 10 megohms. These settings are controlled by a set of 3 switches located inside the monitor’s enclosure.NOTE: Desco recommends re-calibration of the monitor should either setting be changed. See the “Calibration” section for more information.To gain access to these switches, remove the monitor’s cover and position the monitor so the PCB matches the orientation shown in Figure 5. Switches SW1 and SW2 control the operator test voltage. Switch SW3 controls the operator high test limit.Operator Test Voltage+5VSW1 Position: RIGHTSW2 Position: LEFT+8VSW1 Position: LEFTSW2 Position: RIGHTOperator High Test Limit10 megohmsSW3 Position: RIGHT35 megohmsSW3 Position: LEFTCalibrationFrequency of recalibration should be based on the critical nature of those ESD sensitive items handled and the risk of failure for the ESD protective equipment and materials. In general, Desco recommends that calibration be performed annually.Use the EMIT 50524 Limit Comparator for Dual-Wire Monitors to perform periodic testing (once every 6-12 months) of the Dual-Wire Dual-Operator Programmable Monitor. The Limit Comparator can be used on the shop floor within a few minutes virtually eliminating downtime, verifying that the monitor is operating within tolerances. See TB-6542 for more information.Figure 5. Switches SW1, SW2 and SW3 inside the monitor’s enclosure Figure 6. EMIT 50524 Limit Comparator for Dual-Wire MonitorsNIST CalibrationDesco provides a basic, National Institute of Standardsand Technology (NIST) traceable calibration for theproducts that we manufacture. This is sometimesreferred to as a Level 1 calibration.For more on National Institute of Standards andTechnology see:/index.htmlFor more information on the calibration that Desco’sprovides for products that we manufacture see:/Calibration.aspxSpecificationsOperating Voltage 12 VDCOperating Temperature 32°F - 104°F (0 - 40°C)Monitor Dimensions 4.4" x 4.7" x 2.1"(11.2cm x 11.9cm x 5.3cm)Monitor Weight 1.1 lbs (0.5 kg)TEST VOLTAGESOperator +8 V** or +5 VWorksurface 200 mVTEST LIMITSOperator Low Fail: < 1.72 megohmsPass: 2 - 9 megohms**High Fail: > 11.5 megohms**orPass: 2 - 30 megohmsHigh Fail: > 40 megohmsWorksurface Pass: < 3.5 megohmsFail: > 3.8 megohms**DefaultFigure 7. Operator Remote dimensionsReplacement remotes are available as EMIT itemnumbers 50525 and 50526.分销商库存信息: DESCO19665。

MB85RC16PNF-G-JNE1;中文规格书,Datasheet资料

FUJITSU SEMICONDUCTORDATA SHEETCopyright©2011 FUJITSU SEMICONDUCTOR LIMITED All rights reserved 2011.6Memory FRAM16 K (2 K × 8) Bit I 2CMB85RC16■DESCRIPTIONThe MB85RC16 is an FRAM (F erroelectric Random Access Memory) chip in a configuration of 2,048 words × 8 bits, using the ferroelectric process and silicon gate CMOS process technologies for forming the nonvolatile memory cells.Unlike SRAM, the MB85RC16 is able to retain data without using a data backup battery.The memory cells used in the MB85RC16 have at least 1010 Read/Write operation endurance per bit, which is a significant improvement over the number of read and write operations supported by other nonvolatile memory products.The MB85RC16 can provide writing in one byte units because the long writing time is not required unlike Flash memory and E 2PROM. Therefore, the writing completion waiting sequence like a write busy state is not required.■FEATURES•Bit configuration : 2,048 words × 8 bits •Operating power supply voltage : 2.7 V to 3.6 V •Operating frequency : 1 MHz (Max) •T wo-wire serial interface : Fully controllable by two ports: serial clock (SCL) and serial data (SDA).•Operating temperature range : − 40 °C to + 85 °C •Data retention : 10 years ( + 75 °C) •Read/Write endurance : 1010 times •Package : Plastic / SOP , 8-pin (FPT -8P-M02)•Low power consumption : Operating current 0.1mA (Max: @1 MHz), Standby current 0.1 μA (Typ)DS501-00001-2v0-EMB85RC16■PIN FUNCTIONAL DESCRIPTIONSPinNumberPin Name Functional Description1 to 3NC Unconnected pins Leave it unconnected.4VSS Ground pin5SDA Serial Data I/O pinThis is an I/O pin of serial data for performing bidirectional communication of mem-ory address and writing or reading data. It is possible to connect some devices. It is an open drain output, so a pull-up resistance is required to be connected to the external circuit.6SCL Serial Clock pinThis is a clock input pin for input/output timing serial data. Data is sampled on the rising edge of the clock and output on the falling edge.7WP Write Protect pinWhen Write Protect pin is “H” level, writing operation is disabled. When Write Pro-tect pin is “L” level, the entire memory region can be overwritten. Reading operation is always enabled regardless of the Write Protect pin state. The write protect pin is internally pulled down to VSS pin, and that is recognized as “L” level (the state that writing is enabled) when the pin is the open state.8VDD Supply Voltage pinMB85RC16■I2C (Inter-Integrated Circuit)The MB85RC16 has the two-wire serial interface and the I2C bus, and operates as a slave device.The I2C bus defines communication roles of “master” and “slave” devices, with the master side holding the authority to initiate control. Furthermore, a I2C bus connection is possible where a single master device is connected to multiple slave devices in a party-line configuration.2MB85RC16■I2C COMMUNICATION PROTOCOLThe I2C bus provides communication by two wires only, therefore, the SDA input should change while SCL is the “L” level. However, when starting and stopping the communication sequence, SDA is allowed to change while SCL is the “H” level.•Start ConditionTo start read or write operations by the I2C bus, change the SDA input from the “H” level to the “L” level while the SCL input is in the “H” level.•Stop ConditionTo stop the I2C bus communication, change the SDA input from the “L” level to the “H” level while the SCL input is in the “H” level. In the reading operation, inputting the stop condition finishes reading and enters the standby state. In the writing operation, inputting the stop condition finishes inputting the rewrite data.Note : The FRAM device does not need the programming wait time (t WC) after issuing the Stop Condition during the write operation.MB85RC16■ACKNOWLEDGE (ACK)In the I2C bus, serial data including memory address or memory information is sent in units of 8 bits. The acknowledge signal indicates that every 8 bits of the data is successfully sent and received. The receiver side usually outputs the “L” level every time on the 9th SCL clock after every 8 bits are successfully trans-mitted. On the transmitter side, the bus is temporarily released on this 9th clock to allow the acknowledge signal to be received and checked. During this released period, the receiver side pulls the SDA line down to indicate that the communication works correctly.If the receiver side receives the stop condition before transmitting the acknowledge “L” level, the read operation ends and the I2C bus enters the standby state. If the acknowledge “L” level is not detected, and the Stop condition is not sent, the bus remains in the released state without doing anything.■MEMORY ADDRESS STRUCTUREThe MB85RC16 has the memory address buffer to store the 11-bit information for the memory address.As for byte write, page write and random read commands, the complete 11-bit memory address is configured by inputting the memory upper address (3 bits) and the memory lower address (8 bits), and saving to the memory address buffer and access to the memory is performed.As for a current address read command, the complete 11-bit memory address is configured by inputting the memory upper address (3 bits) and by the memory address lower 8-bit which has saved in the memory address buffer, and saving to the memory address buffer and access to the memory is performed.MB85RC16■DEVICE ADDRESS WORDF ollowing the start condition, the 8 bit device address word is input. Inputting the device address word decideswhether the master or the slave drives the data line. However, the clock is always driven by the master. The device address word (8bits) consists of a device T ype code (4bits), memory upper address code (3bits), anda Read/Write code (1bit).•Device Type Code (4bits)The upper 4 bits of the device address word are a device type code that identifies the device type, and are fixed at “1010” for the MB85RC16.•Memory Upper Address Code (3bits)Following the device type code, the 3 bits of the memory upper address code are input.The slave address selection is not performed by the external pin setting on this device. These 3 bits are not the setting bits for the slave address, but the upper 3-bit setting bits for the memory address.•Read/Write Code (1bit)The 8th bit of the device address word is the R/W (Read/Write) code. When the R/W code is “0” input, a write operation is enabled, and the R/W code is “1” input, a read operation is enabled for the MB85RC16. If the device code is not “1010”, the Read/Write operation is not performed and the standby state is chosen.MB85RC16■DATA STRUCTUREThe master inputs the device address word (8 bits) following the start condition, and then the slave outputs the Acknowledge “L” level on the ninth bit. After confirming the Acknowledge response, the sequential 8-bit memory lower address is input, to the byte write, page write and random read commands.As for the current address read command, inputting the memory lower address is not performed, and the address buffer lower 8-bit is used as the memory lower address.When inputting the memory lower address finishes, the slave outputs the Acknowledge “L” level on the ninth bit again.Afterwards, the input and the output data continue in 8-bit units, and then the Acknowledge “L” level is output for every 8-bit data.MB85RC16■FRAM ACKNOWLEDGE -- POLLING NOT REQUIREDThe MB85RC16 performs the high speed write operations, so any waiting time for an ACK* by the acknowl-edge polling does not occur.*: In E2PROM, the Acknowledge Polling is performed as a progress check whether rewriting is executed or not.It is normal to judge by the 9th bit of Acknowledge whether rewriting is performed or not after inputting the start condition and then the device address word (8 bits) during rewriting.■WRITE PROTECT (WP)The entire memory array can be write protected by setting the WP pin to the “H” level. When the WP pin is set to the “L” level, the entire memory array will be rewritten. Reading is allowed regardless of the WP pin's “H” level or “L” level.Do not change the WP signal level during the communication period from the start condition to the stop condition.Note : The WP pin is pulled down internally to VSS pin, therefore if the WP pin is open, the pin status is detected as the “L” level (write enabled).MB85RC16■COMMAND•Byte WriteIf the device address word (R/W “0” input) is sent after the start condition, an ACK responds from the slave.After this ACK, write memory addresses and write data are sent in the same way, and the write ends by•Page WriteIf data is continuously sent after the following address when the same command (expect stop condition) as Byte Write was sent, a page write is performed. The memory address rolls over to first memory address (000H)at the end of the address. Therefore, if more than 2 Kbytes are sent, the data is overwritten in orderMB85RC16•Current Address ReadIf the last write or read operation finishes correctly up to the end of stop condition, the memory address that was accessed last remains in the memory address buffer (the length is 11 bits).When sending this command without turning the power off, it is possible to read from the memory address n+1 which adds 1 to the total 11-bit memory address n, which consists of the memory upper address 3-bit from the device address word input and the lower 8-bit of the memory address buffer. If the memory address n is the last address, it is possible to read with rolling over to the head of the memory address (000H). The current address (address that the memory address buffer indicates) is undefined immediately after turning•Random ReadThe one byte of data from the memory address as saved in the memory address buffer can be read out synchronously to SCL by specifying the address in the same way as for a write, and then issuing another start condition and sending the Device Address Word (R/W “1” input).Setting values for the first and the second memory upper address codes should be the same.The final NACK (SDA is the “H” level) is issued by the receiver that receives the data. In this case, this bit is分销商库存信息: FUJITSUMB85RC16PNF-G-JNE1。

LM39500T-5.0中文资料

APPLICATIONS•Low-voltage Digatal Ics•LDO linear regulator for PC add-in cards •High-efficiency linear power supplies •Multimedia and PC processor supplies •SMPS post regulator•Low-voltage microcontrollers •Strong ARM™ processor supplyORDERING INFORMATIONDESCRIPTIONHTCTO-263LM39500-X.X LM39500R- X.X TO-220LM39502T-AdjLM39502-AdjLM39500T-X.X TO-220LM39501T-X.X TO-220ADJOUT Device Marking LM39502R-Adj Logic low or open = Shutdown Supply (Input): +16V maximum supply Flag (Output): Open-collector error flag output.LM39501R-X.X TO-263LM39501-X.X Regulator OutputLM39501-X.X GND FLG Ground pin and TAB are internally connected.LM39500-X.X Adjustment Input: Feedback input.Package LM39502-Adj TO-263PIN DESCRIPTIONEnable (Input)IN CMOS-compatible control input.Logic high = enable, logic * X.X = Fixed Vout = 1.5V, 1.8V, 2.5V, 3.3V, 5.0V The LM39500/1/2 is ideal for PC Add-In cards that need to convert from standard 5V or 3.3V, down to new, lower core voltages. A guaranteed maximum dropout voltage of 500mV over all operating conditions allows the LM39500/1/2 to provide 2.5V from a supply as low as 3V. The LM39500 also has fast transient response, for heavy switching applications. The device requires only 47F of output capacitance to maintain stability and achieve fast transient responseThe LM39500/1/2 is fully protected with overcurrentlimiting,thermal shutdown, reversed-battery and reversed-lead in-sertion protection. The LM39501 offers a TTL-logic-compat-ible enable pin and an error flag that indicates undervoltage and overcurrentconditions. The LM39500/1/2 comes in the TO-220 and TO-263 packages and is an ideal upgrade to older,NPN-based linear voltage regulators.The LM39502 is adjustable version.TO263-3L / TO220-3LTO263-5L / TL220-5L(39501-x.x & 39502 only)The LM39500, LM39501 and LM39502 is a 5A low-dropout linear voltage regulator that provides a low-voltage, high-current output with aminimum of external components. Utilizing Super beta PNP pass element, The LM39500 offers extremely low dropout (typically 400mV at 5A)and low ground current (typically 70mA at 5A).Typical Application CircuitAbsolute Maximum Ratings (Note 1)Supply Voltage (VIN) : –20V to +20V Enable Voltage (VEN) : +20VStorage Temperature (TS) : –65°C to +150°C Lead Temperature (soldering, 5 sec) : 260°C ESD, Note 3Operating Ratings (Note 2)Supply Voltage (VIN) : +2.25V to +16V Enable Voltage (VEN) : +16VMaximum Power Dissipation (PD(max)) Note 4 Junction Temperature (TJ) : –40°C to +125°C Package Thermal Resistance TO-263(θJC ) : 2°C/W TO-220(θJC) : 2°C/WLM39500LM39501LM39502Block DiagramLM39500 Fixed (1.5V,1.8V,2.5V,3.3V,5.0V)LM39501 Fixed with Flag and EnableLM39502 AdjustableNote 1. Exceeding the absolute maximum ratings may damage the device.Note 2. The device is not guaranteed to function outside its operating rating.Note 3. Devices are ESD sensitive. Handling precautions recommended.Note 4. P D(max) = (T J(max) – T A) θJA, where θJA depends upon the printed circuit layout. See “Applications Information.”Note 5.Vout temperature coefficient is ∆V OUT(worst case) (T J(max) – T J(min)) where T J(max) is +125℃ and T J(min) is 0℃Note 6. V DO = V IN – V OUT when V OUT decreases to 98% of its nominal output voltage with V IN = V OUT + 1V.Note 7. I GND is the quiescent current. IIN = I GND + I OUT.Note 8. V EN 0.8V, V IN 8V, and V OUT = 0VNote 9. For a 2.5V device, V IN = 2.250V (device is in dropout).Application InformationThe LM39500/1 is a high-performance low-dropout voltage regulator suitable for moderate to high-current voltage regu-lator applications. Its 400mV dropout voltage at full load makes it especially valuable in battery-powered systems and as a high-efficiency noise filter in post-regulator applications. Unlike older NPN-pass transistor designs, where the mini-mum dropout voltage is limited by the base-to-emitter voltage drop and collector-to-emitter saturation voltage, dropout per-formance of the PNP output of these devices is limited only by the low V CE saturation voltage.A trade-off for the low dropout voltage is a varying base drive requirement.The LM39500/1/2 regulator is fully protected from damage due to fault conditions. Current limiting is provided. This limiting is linear output current during overload conditions is constant. Thermal shutdown disables the device when the die temperature exceeds the maximum safe operating tem-perature. Transient protection allows device (and load) sur-vival even when the input voltage spikes above and below nominal. The output structure of these regulators allows voltages in excess of the desired output voltage to be applied without reverse current flow.Thermal DesignLinear regulators are simple to use. The most complicated design parameters to consider are thermal characteristics.Thermal design requires four application-specific param-eters:•Maximum ambient temperature (T A)•Output Current (I OUT)•Output Voltage (V OUT)•Input Voltage (V IN)•Ground Current (I GND)Calculate the power dissipation of the regulator from these numbers and the device parameters from this datasheet,where the ground current is taken from the data sheet.PD = (V IN – V OUT) I OUT + V IN·I GNDThe heat sink thermal resistance is determined by:θSA=(T JMAX-T A)/P D -(θJC+θCS)where TJ (max) 125 ℃ and θCS is between 0℃ and 2℃/W.The heat sink may be significantly reduced in applications where the minimum input voltage is known and is large compared with the dropout voltage. Use a series input resistor to drop excessive voltage and distribute the heat between this resistor and the regulator. The low dropout properties of Taejin regulators allow signifi-cant reductions in regulator power dissipation and the asso-ciated heat sink without compromising performance. When this technique is employed, a capacitor of at least 1.0F is needed directly between the input and regulator ground.Refer to Application Note 9 for further details and examples on thermal design and heat sink specification.Output CapacitorThe LM39500/1/2 requires an output capacitor to maintain stability and improve transient response. Proper capacitor selection is important to ensure proper operation. The LM39500/1/2 output capacitor selection is dependent upon the ESR (equivalent series resistance) of the output capacitor to maintain stability. When the output capacitor is 47F or greater, the output capacitor should have less than 1 of ESR. This will improve transient response as well as promote stability. Ultralow ESR capacitors, such as ceramic chip capacitors may promote instability. These very low ESR levels may cause an oscillation and/or underdamped tran-sient response. A low-ESR solid tantalum capacitor works extremely well and provides good transient response and stability over temperature. Aluminum electrolytics can also be used, as long as the ESR of the capacitor is < 1.The value of the output capacitor can be increased without limit. Higher capacitance values help to improve transient response and ripple rejection and reduce output noise. Input CapacitorAn input capacitor of 1uF or greater is recommended when the device is more than 4 inches away from the bulk ac supply capacitance, or when the supply is a battery. Small, surface-mount, ceramic chip capacitors can be used for the bypass-ing. Larger values will help to improve ripple rejection by bypassing the input to the regulator, further improving the integrity of the output voltage.Transient Response and 3.3V.Fig 1. Capacitor RequirementsMinimum Load CurrentThe LM39500/1/2 regulator is specified between finite loads.If the output current is too small, leakage currents dominate and the output voltage rises.A 10mA minimum load current is necessary for proper regulation.Transient Response and 3.3V to 2.5V ConversionThe LM39500/1/2 has excellent transient response to varia-tions in input voltage and load current. The device has been designed to respond quickly to load current variations and input voltage variations. Large output capacitors are not required to obtain this performance. A standard 47F output capacitor, preferably tantalum, is all that is required. Larger values help to improve performance even further.By virtue of its low-dropout voltage, this device does not saturate into dropout as readily as similar NPN-based de-signs. When converting from 3.3V to 2.5V, the NPN-based regulators are already operating in dropout, with typical dropout requirements of 1.2V or greater. To convert down to 2.5V without operating in dropout, NPN-based regulators require an input voltage of 3.7V at the very least. The LM39500/1/2 regulator will provide excellent performance with an input as low as 3.0V. This gives the PNP-based regulators a distinct advantage over older, NPN-based linear regulators does not have the headroom to dothis conversion.Error FlagThe LM39501 version features an error flag circuit which monitors the output voltage and signals an error condition when the voltage drops 5% below the nominal output voltage. The error flag is an open-collector output that can sink 10mA during a fault condition.Low output voltage can be caused by a number of problems, including an overcurrent fault (device in current limit) or low input voltage. The flag is inoperative during overtemperature shutdown.Enable InputThe LM39501 version features an enable input for on/off control of the device. Its shutdown state draws “zero” current (only microamperes of leakage). The enable input is TTL/ CMOS compatible for simple logic interface, but can be connected to up to 20V.Adjustable Regulator DesignThe LM39502 allows programming the output voltage any-where between 1.25V and the 16V maximum operating rating of the family. Two resistors are used. Resistors can be quite large, up to 1MΩ, because of the very high input impedance and low bias current of the sense comparator: The resistor values are calculated by :R1=R2(Vout/1.250-1)Where VO is the desired output voltage. Figure 1 shows component definition. Applications with widely varying load l h i d h i i l d i d f i(b l)。

ADS8555SPM;ADS8555SPMR;中文规格书,Datasheet资料

BUSY/INTRANGE/XCLKHW/SWREF/WRRESETENSTBYCSRD/DB[15:0]WORD/BYTEPAR/SERFSCH_A0CONVST_AAGNDREFC_AREF_IOAGNDCH_A1AGNDCH_B0CONVST_BAGNDREFC_BCH_B1AGNDCH_C0CONVST_CAGNDREFC_CCH_C1AGNDADS8555 SBAS531B–DECEMBER2010–REVISED FEBRUARY201116-Bit,Six-Channel,Simultaneous SamplingANALOG-TO-DIGITAL CONVERTERCheck for Samples:ADS8555FEATURES DESCRIPTION•Six SAR ADCs Grouped in Three Pairs The ADS8555contains six low-power,16-bit,successive approximation register(SAR)-based •Maximum Data Rate Per Channel with Internalanalog-to-digital converters(ADCs)with true bipolar Clock and Reference:inputs.Each channel contains a sample-and-hold 630kSPS(Parallel)or450kSPS(Serial)circuit that allows simultaneous high-speed •Maximum Data Rate Per Channel with External multi-channel signal acquisition.Clock and Reference:The ADS8555supports data rates of up to630kSPS 800kSPS(Parallel)or500kSPS(Serial)in parallel interface mode or up to450kSPS if the •Pin-Selectable or Programmable Input Voltageserial interface is used.The bus width of the parallel Ranges:Up to±12V interface can be set to eight or16bits.In serial•Excellent AC Performance:mode,up to three output channels can be activated.91.5dB SNR,–94dB THDThe ADS8555is specified over the extended •Programmable and Buffered Internal industrial temperature range of–40°C to+125°C and Reference:0.5V to2.5V and0.5V to3.0V is available in an LQFP-64package.•Comprehensive Power-Down Modes:Deep Power-Down(Standby Mode)Auto-Nap Power-Down•Selectable Parallel or Serial Interface•Operating Temperature Range:–40°C to+125°C•LQFP-64PackageAPPLICATIONS•Power Quality Measurement•Protection Relays•Multi-Axis Motor Control•Programmable Logic Controllers•Industrial Data AcquisitionPlease be aware that an important notice concerning availability,standard warranty,and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.All trademarks are the property of their respective owners.ADS8555SBAS531B–DECEMBER2010–REVISED This integrated circuit can be damaged by ESD.Texas Instruments recommends that all integrated circuits be handled with appropriate precautions.Failure to observe proper handling and installation procedures can cause damage.ESD damage can range from subtle performance degradation to complete device failure.Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.PACKAGE/ORDERING INFORMATIONFor the most current package and ordering information,see the Package Option Addendum at the end of this document,or visit the device product folder at .ABSOLUTE MAXIMUM RATINGS(1)Over operating free-air temperature range,unless otherwise noted.ADS8555UNIT Supply voltage,HVDD to AGND–0.3to+18VSupply voltage,HVSS to AGND–18to+0.3VSupply voltage,AVDD to AGND–0.3to+6VSupply voltage,BVDD to BGND–0.3to+6V Analog input voltage HVSS–0.3to HVDD+0.3V Reference input voltage with respect to AGND AGND–0.3to AVDD+0.3VDigital input voltage with respect to BGND BGND–0.3to BVDD+0.3V Ground voltage difference AGND to BGND±0.3VInput current to all pins except supply–10to+10mA Maximum virtual junction temperature,T J+150°C Human body model(HBM)±2000V JEDEC standard22,test method A114-C.01,all pinsESD ratingsCharged device model(CDM)±500V JEDEC standard22,test method C101,all pins(1)Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device.These are stress ratingsonly and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied.Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.THERMAL INFORMATIONADS8555THERMAL METRIC(1)PM UNITS64PINSθJA Junction-to-ambient thermal resistance48θJCtop Junction-to-case(top)thermal resistance16θJB Junction-to-board thermal resistance N/A°C/WψJT Junction-to-top characterization parameter N/AψJB Junction-to-board characterization parameter N/AθJCbot Junction-to-case(bottom)thermal resistance N/A(1)For more information about traditional and new thermal metrics,see the IC Package Thermal Metrics application report,SPRA953A.ADS8555 SBAS531B–DECEMBER2010–REVISED FEBRUARY2011RECOMMENDED OPERATING CONDITIONSMIN TYP MAX UNIT Supply voltage,AVDD to AGND 4.55 5.5VLow-voltage levels 2.7 3.0 3.6V Supply voltage,BVDD to BGND5V logic levels 4.55 5.5VInput range=±2×V REF2×V REF16.5VInput supply voltage,HVDD to AGNDInput range=±4×V REF4×V REF16.5VInput range=±2×V REF–16.5–2×V REF VInput supply voltage,HVSS to AGNDInput range=±4×V REF–16.5–4×V REF V Reference input voltage(V REF)0.5 2.5 3.0VInput range=±2×V REF–2×V REF2×V REF V Analog inputs(also see the Analog Inputs section)Input range=±4×V–4×V REF4×V REF VREFOperating ambient temperature range,T A–40+125°C ELECTRICAL CHARACTERISTICSOver recommended operating free-air temperature range of–40°C to+125°C,AVDD=4.5V to5.5V,BVDD=2.7V to5.5V, HVDD=10V to15V,HVSS=–15V to–10V,V REF=2.5V(internal),and f DATA=maximum,unless otherwise noted.ADS8555PARAMETER CONDITIONS MIN TYP(1)MAX UNITDC ACCURACYResolution16BitsNo missing codes16BitsAt T A=–40°C to+85°C–3±1.53LSB Integral linearity error INLAt T A=–40°C to+125°C–4±1.54LSBAt T A=–40°C to+85°C–1±0.75 1.5LSB Differential linearity error DNLAt T A=–40°C to+125°C–1±0.752LSB Offset error–4.0±0.8 4.0mV Offset error drift±3.5μV/°C Gain error Referenced to voltage at REFIO–0.75±0.250.75%FSR Gain error drift Referenced to voltage at REFIO±6ppm/°C Power-supply rejection ratio PSRR At output code FFFFh,related to AVDD60dB SAMPLING DYNAMICSAcquisition time t ACQ280ns Conversion time per ADC t CONV 1.26μs18.5t CCLK Internal conversion clock period t CCLK68.0nsParallel interface,internal clock and reference630kSPS Throughput rate f DATASerial interface,internal clock and reference450kSPSAC ACCURACYAt f IN=10kHz,T A=–40°C to+85°C9091.5dB Signal-to-noise ratio SNRAt f IN=10kHz,T A=–40°C to+125°C8991.5dBAt f IN=10kHz,T A=–40°C to+85°C8789.5dB Signal-to-noise ratio+distortion SINADAt f IN=10kHz,T A=–40°C to+125°C86.589.5dBAt f IN=10kHz,T A=–40°C to+85°C–94–90dB Total harmonic distortion(2)THDAt f IN=10kHz,T A=–40°C to+125°C–94–89.5At f IN=10kHz,T A=–40°C to+85°C9095dB Spurious-free dynamic range SFDRAt f IN=10kHz,T A=–40°C to+125°C89.595dB Channel-to-channel isolation At f IN=10kHz100dBInput Range=±4×V REF48MHz–3dB small-signal bandwidthInput Range=±2×V REF24MHz(1)All values are at T A=+25°C.(2)Calculated on the first nine harmonics of the input frequency.ADS8555SBAS531B–DECEMBER2010–REVISED ELECTRICAL CHARACTERISTICS(continued)Over recommended operating free-air temperature range of–40°C to+125°C,AVDD=4.5V to5.5V,BVDD=2.7V to5.5V, HVDD=10V to15V,HVSS=–15V to–10V,V REF=2.5V(internal),and f DATA=maximum,unless otherwise noted.ADS8555PARAMETER CONDITIONS MIN TYP(1)MAX UNIT ANALOG INPUTRANGE pin/RANGE bit=0–4×V REF4×V REF V Bipolar full-scale range CHXXRANGE pin/RANGE bit=1–2×V REF2×V REF VInput range=±4×V REF10pF Input capacitanceInput range=±2×V REF20pF Input leakage current No ongoing conversion±1μA Aperture delay5ns Aperture delay matching Common CONVST for all channels250ps Aperture jitter50ps EXTERNAL CLOCK INPUT(XCLK)External clock frequency f XCLK An external reference must be used for f XCLK>f CCLK11820MHz External clock duty cycle4555% REFERENCE VOLTAGE OUTPUT(REF OUT)2.5V operation,REFDAC=0x3FF 2.485 2.5 2.515V2.5V operation,REFDAC=0x3FF at+25°C 2.496 2.5 2.504V Reference voltage V REF3.0V operation,REFDAC=0x3FF 2.985 3.0 3.015V3.0V operation,REFDAC=0x3FF at+25°C 2.995 3.0 3.005V Reference voltage drift dV REF/dT±10ppm/°C Power-supply rejection ratio PSRR73dB Output current I REFOUT DC current–22mA Short-circuit current(3)I REFSC50mA Turn-on settling time t REFON10msAt CREF_x pins 4.710μF External load capacitanceAt REFIO pins100470nF Tuning range REFDAC Internal reference output voltage range0.2×V REF V REF V REFDAC resolution10Bits REFDAC differential nonlinearity DNL DAC–1±0.11LSB REFDAC integral nonlinearity INL DAC–2±0.12LSB REFDAC offset error V OSDAC V REF=0.5V(DAC=0x0CC)–4±0.654LSB REFERENCE VOLTAGE INPUT(REF IN)Reference input voltage V REFIN0.5 2.5 3.025VInput resistance100MΩInput capacitance5pF Reference input current1μA SERIAL CLOCK INPUT(SCLK)Serial clock input frequency f SCLK0.136MHz Serial clock period t SCLK0.027810μs Serial clock duty cycle4060% DIGITAL INPUTS(4)Logic family CMOS with Schmitt-TriggerHigh-level input voltage0.7×BVDD BVDD+0.3VLow-level input voltage BGND–0.30.3×BVDD VInput current V I=BVDD to BGND–50+50nA Input capacitance5pF(3)Reference output current is not limited internally.(4)Specified by design.ADS8555 SBAS531B–DECEMBER2010–REVISED FEBRUARY2011ELECTRICAL CHARACTERISTICS(continued)Over recommended operating free-air temperature range of–40°C to+125°C,AVDD=4.5V to5.5V,BVDD=2.7V to5.5V, HVDD=10V to15V,HVSS=–15V to–10V,V REF=2.5V(internal),and f DATA=maximum,unless otherwise noted.ADS8555PARAMETER CONDITIONS MIN TYP(1)MAX UNIT DIGITAL OUTPUTS(5)Logic family CMOSHigh-level output voltage I OH=100μA BVDD–0.6BVDD VLow-level output voltage I OH=–100μA BGND BGND+0.4VHigh-impedance-state output current–5050nA Output capacitance5pF Load capacitance30pF POWER-SUPPLY REQUIREMENTSAnalog supply voltage AVDD 4.5 5.0 5.5V Buffer I/O supply voltage BVDD 2.7 3.0 5.5VInput positive supply voltage HVDD 5.010.016.5VInput negative supply voltage HVSS–16.5–10.0–5.0Vf DATA=maximum30.036.0mAf DATA=250kSPS(auto-NAP mode)14.016.5mA Analog supply current(6)IAVDD Auto-NAP mode,no ongoing conversion,4.0 6.0mAinternal conversion clockPower-down mode0.150.0μAf DATA=maximum0.9 2.0mAf DATA=250kSPS(auto-NAP mode)0.5 1.5mA Buffer I/O supply current(7)IBVDD Auto-NAP mode,no ongoing conversion,0.110.0μAinternal conversion clockPower-down mode0.110.0μAf DATA=maximum 3.0 3.5mAf DATA=250kSPS(auto-NAP mode) 1.6 2.0mA Input positive supply current(8)IHVDD Auto-NAP mode,no ongoing conversion,0.20.3μAinternal conversion clockPower-down mode0.110.0μAf DATA=maximum 3.6 4.0mAf DATA=250kSPS(auto-NAP mode) 1.8 2.2mA Input negative supply current(9)IHVSS Auto-NAP mode,no ongoing conversion,0.20.25μAinternal conversion clockPower-down mode0.110.0μAf DATA=maximum251.7298.5mWf DATA=250kSPS(auto-NAP mode)122.5150.0mW Power dissipation(10)Auto-NAP mode,no ongoing conversion,26.038.3mWinternal conversion clockPower-down mode 3.8580.0μW(5)Specified by design.(6)At AVDD=5V.(7)At BVDD=3V,parallel mode,load capacitance=6pF/pin.(8)At HVDD=15V.(9)At HVSS=–15V.(10)At AVDD=5V,BVDD=3V,HVDD=15V,and HVSS=–15V.48474645444342414039383736353433CH_C1AVDD AVDD CH_C0AGND AGND CH_B1AVDD AVDD CH_B0AGND AGND CH_A1AVDD AVDD CH_A012345678910111213141516DB14/REFBUF ENDB13/SDIDB12DB11DB10/SDO_C DB9/SDO_B DB8/SDO_ABGND BVDDDB7/HB /DC EN EN DB6/SCLK DB5/DCIN_A DB4/DCIN_B DB3/DCIN_C DB2/SEL_C DB1/SEL_B D B 15D B 0/SE L _AR E F /W RE N B U S Y /I N TH W /S WC S F S/P A R /S E RR DA V D DC O N V S T _CA G N DC O N V S T _BR E F C _CC O N V S T _AA G N DS T B YR E F C _BA G N DA G N DA V D DR E F C _AR A N G E /X C L KA G N DR E S E TA G N DW O R D /B Y T ER E F I OH V S SA V D DH V D DA G N DA G N D6463626160595857565554171819202122232425262753525150492829303132ADS8555SBAS531B –DECEMBER 2010–REVISED FEBRUARY 2011EQUIVALENT INPUT CIRCUITSPIN CONFIGURATIONPM PACKAGE LQFP-64(TOP VIEW)ADS8555 SBAS531B–DECEMBER2010–REVISED FEBRUARY2011PIN DESCRIPTIONSDESCRIPTIONNAME PIN#TYPE(1)PARALLEL INTERFACE(PAR/SER=0)SERIAL INTERFACE(PAR/SER=1)Hardware mode(HW/SW=0):Reference buffers enable input.When low,all reference buffers are enabled(mandatory ifinternal reference is used).When high,all reference buffers DB14/REFBUF EN1DIO/DI Data bit14input/output are disabled.Software mode(HW/SW=1):Connect to BGND or BVDD.The reference buffers are controlled by bit C24(REFBUF)incontrol register(CR).Hardware mode(HW/SW=0):Connect to BGND DB13/SDI2DIO/DI Data bit13input/outputSoftware mode(HW/SW=1):Serial data input DB123DIO Data bit12input/output Connect to BGNDDB114DIO Data bit11input/output Connect to BGNDWhen SEL_C=1,data output for channel C DB10/SDO_C5DIO/DO Data bit10input/outputWhen SEL_C=0,this pin should be tied to BGNDWhen SEL_B=1,data output for channel BWhen SEL_B=0,this pin should be tied to BGND DB9/SDO_B6DIO/DO Data bit9input/outputWhen SEL_C=0,data from channel C1are also availableon this outputData output for channel AWhen SEL_C=0,data from channel C0are also available DB8/SDO_A7DIO/DO Data bit8input/output on this outputWhen SEL_C=0and SEL_B=0,SDO_A acts as the singledata output for all channelsBGND8P Buffer I/O ground,connect to digital ground planeBuffer I/O supply,connect to digital supply(2.7V to5.5V).Decouple with a1μF ceramic capacitor or a BVDD9Pcombination of100nF and10μF ceramic capacitors to BGND.Word mode(WORD/BYTE=0):Data bit7input/outputDaisy-chain enable input.Byte mode(WORD/BYTE=1):DB7/HB EN/DC EN10DIO/DI/DI When high,DB[5:3]serve as daisy-chain inputs DCIN[A:C].High byte enable input.If daisy-chain mode is not used,connect to BGND.When high,the high byte is output first onDB[15:8].When low,the low byte is output first onDB[15:8].Word mode(WORD/BYTE=0):Data bit6input/outputDB6/SCLK11DIO/DI Serial interface clock input(36MHz max)Byte mode(WORD/BYTE=1):Connect to BGND or BVDDWord mode(WORD/BYTE=0):Data bit5input/output When DCEN =1,daisy-chain data input for channel ADB5/DCIN_A12DIO/DIWhen DC EN=0,connect to BGNDByte mode(WORD/BYTE=1):Connect to BGND or BVDDWord mode(WORD/BYTE=0):When SEL_B=1and DC EN=1,daisy-chain data input forData bit4input/outputDB4/DCIN_B13DIO/DI channel BByte mode(WORD/BYTE=1):When DCEN =0,connect to BGNDConnect to BGND or BVDDWord mode(WORD/BYTE=0):When SEL_C=1and DC EN=1,daisy-chain data input forData bit3input/outputDB3/DCIN_C14DIO/DI channel CByte mode(WORD/BYTE=1):When DCEN =0,connect to BGNDConnect to BGND or BVDDWord mode(WORD/BYTE=0):Data bit2input/output Select SDO_C input.DB2/SEL_C15DIO/DIWhen high,SDO_C is active.When low,SDO_C is disabled.Byte mode(WORD/BYTE=1):Connect to BGND or BVDDWord mode(WORD/BYTE=0):Data bit1input/output Select SDO_B input.DB1/SEL_B16DIO/DIWhen high,SDO_B is active.When low,SDO_B is disabled.Byte mode(WORD/BYTE=1):Connect to BGND or BVDD(1)AI=analog input;AIO=analog input/output;DI=digital input;DO=digital output;DIO=digital input/output;and P=power supply.ADS8555SBAS531B–DECEMBER2010–REVISED PIN DESCRIPTIONS(continued)DESCRIPTIONNAME PIN#TYPE(1)PARALLEL INTERFACE(PAR/SER=0)SERIAL INTERFACE(PAR/SER=1)Word mode(WORD/BYTE=0):Select SDO_A input.Data bit0(LSB)input/outputDB0/SEL_A17DIO/DI When high,SDO_A is active.When low,SDO_A is disabled.Byte mode(WORD/BYTE=1):Should always be high.Connect to BGND or BVDDWhen CR bit C21=0(BUSY/INT),converter busy status output.Transitions high when a conversion has beenstarted and remains high during the entire process.Transitions low when the conversion data of all six channelsare latched to the output register and remains low thereafter.In sequential mode(SEQ=1in the CR),the BUSY output transitions high when a conversion has been started BUSY/INT18DOand goes low for a single conversion clock cycle(t CCLK)whenever a channel pair conversion is completed.When bit C21=1(BUSY/INT in CR),interrupt output.This bit transitions high after a conversion has beencompleted and goes low with the first read data access.The polarity of BUSY/INT output can be changed using bit C20(BUSY L/H)in the control register.Chip select input.Frame synchronization.CS/FS19DI/DI When low,the parallel interface is enabled.WhenThe falling edge of FS controls the frame transfer.high,the interface is disabled.Read data input.RD20DI When low,the parallel data output is enabled.Connect to BGNDWhen high,the data output is disabled.Hardware mode(HW/SW=0):Conversion start of channel pair C.The rising edge of this signal initiates simultaneous conversion of analog signals at inputs CH_C[1:0].CONVST_C21DISoftware mode(HW/SW=1):Conversion start of channel pair C in sequential mode(CR bit C23=1)only;connect to BGND or BVDD otherwiseHardware mode(HW/SW=0):Conversion start of channel pair B.The rising edge of this signal initiates simultaneous conversion of analog signals at inputs CH_B[1:0].CONVST_B22DISoftware mode(HW/SW=1):Conversion start of channel pair B in sequential mode(CR bit C23=1)only;connect to BGND or BVDD otherwiseHardware mode(HW/SW=0):Conversion start of channel pair A.The rising edge of this signal initiates simultaneous conversion of analog signals at inputs CH_A[1:0].CONVST_A23DISoftware mode(HW/SW=1):Conversion start of all selected channels except in sequential mode(CR bit C23=1):Conversion start of channel pair A onlyStandby mode input.When low,the entire device is powered down(including the internal clock and reference).STBY24DIWhen high,the device operates in normal mode.25,32,37,38,Analog ground,connect to analog ground plane43,44,AGND P Pin25may have a dedicated ground if the difference between its potential and AGND is always kept within 49,52,±300mV.53,55,57,5926,34,Analog power supply(4.5V to5.5V).Decouple each pin with a100nF ceramic capacitor to e an 35,40,additional10μF capacitor to AGND close to the device but without compromising the placement of the smaller AVDD41,46,Pcapacitor.Pin26may have a dedicated power supply if the difference between its potential and AVDD is always 47,50,kept within±300mV.60Hardware mode(HW/SW=0):Input voltage range select input.When low,the analog input range is±4V REF.When high,the analog input range is±2V REF.RANGE/XCLK27DI/DIOSoftware mode(HW/SW=1):External conversion clock input,if CR bit C11(CLKSEL)is set high or internalconversion clock output,if CR bit C10(CLKOUT_EN)is set high.If not used,connect to BVDD or BGND.Reset input,active high.Aborts any ongoing conversions.Resets the internal control register to0x000003FF.The RESET28DIRESET pulse should be at least50ns long.Output mode selection input.When low,data are transferred in word mode usingDB[15:0].When high,data are transferred in byteWORD/BYTE29DI Connect to BGNDmode using DB[15:8]with the byte order controlledby HB EN pin while two accesses are required for acomplete16-bit transfer.Negative supply voltage for the analog inputs(–16.5V to–5V).HVSS30P Decouple with a100nF ceramic capacitor to AGND placed next to the device and a10μF capacitor to AGND closeto the device but without compromising the placement of the smaller capacitor.Positive supply voltage for the analog inputs(5V to16.5V).Decouple with a100nF ceramic capacitor to AGND HVDD31P placed next to the device and a10μF capacitor to AGND close to the device but without compromising theplacement of the smaller capacitor.Analog input of channel A0.The input voltage range is controlled by RANGE pin in hardware mode or CR bit C26 CH_A033AI(RANGE_A)in software mode.Analog input of channel A1.The input voltage range is controlled by RANGE pin in hardware mode or CR bit C26 CH_A136AI(RANGE_A)in software mode.ADS8555 SBAS531B–DECEMBER2010–REVISED FEBRUARY2011PIN DESCRIPTIONS(continued)DESCRIPTIONNAME PIN#TYPE(1)PARALLEL INTERFACE(PAR/SER=0)SERIAL INTERFACE(PAR/SER=1)Analog input of channel B0.The input voltage range is controlled by RANGE pin in hardware mode or CR bit C27 CH_B039AI(RANGE_B)in software mode.Analog input of channel B1.The input voltage range is controlled by RANGE pin in hardware mode or CR bit C27 CH_B142AI(RANGE_B)in software mode.Analog input of channel C0.The input voltage range is controlled by RANGE pin in hardware mode or CR bit C28 CH_C045AI(RANGE_C)in software mode.Analog input of channel C1.The input voltage range is controlled by RANGE pin in hardware mode or CR bit C28 CH_C148AI(RANGE_C)in software mode.Reference voltage input/output(0.5V to3.025V).The internal reference is enabled via REF EN/WR pin in hardware mode or CR bit C25(REF EN)in software mode.REFIO51AIOThe output value is controlled by the internal DAC(CR bits C[9:0]).Connect a470nF ceramic decouplingcapacitor between this pin and pin52.Decoupling capacitor for reference of channels A.REFC_A54AIConnect a10μF ceramic decoupling capacitor between this pin and pin53.Decoupling capacitor for reference of channels B.REFC_B56AIConnect a10μF ceramic decoupling capacitor between this pin and pin55.Decoupling capacitor for reference of channels C.REFC_C58AIConnect a10μF ceramic decoupling capacitor between this pin and pin57.Interface mode selection input.PAR/SER61DIWhen low,the parallel interface is selected.When high,the serial interface is enabled.Mode selection input.HW/SW62DI When low,the hardware mode is selected and part works according to the settings of external pins.When high,the software mode is selected in which the device is configured by writing into the control register.Hardware mode(HW/SW=0):Hardware mode(HW/SW=0):Internal reference enable input.Internal reference enable input.When high,the internal reference is enabled(the When high,the internal reference is enabled(the referencereference buffers are to be enabled).When low,buffers are to be enabled).When low,the internal referencethe internal reference is disabled and an external is disabled and an external reference should be applied at REF EN/WR63DI reference is applied at REFIO.REFIO.Software mode(HW/SW=1):Write input.The parallel data input is enabled,when CS and Software mode(HW/SW=1):Connect to BGND or BVDD.WR are low.The internal reference is enabled by The internal reference is enabled by CR bit C25(REF EN).the CR bit C25(REF EN).DB1564DIO Data bit15(MSB)input/output Connect to BGNDADS8555SBAS531B–DECEMBER2010–REVISED TIMING CHARACTERISTICSFigure1.Serial Operation Timing Diagram(All Three SDOs Active)SERIAL INTERFACE TIMING REQUIREMENTS(1)Over recommended operating free-air temperature range at–40°C to+125°C,AVDD=5V,and BVDD=2.7V to5.5V,unless otherwise noted.ADS8555PARAMETER MIN MAX UNITt ACQ Acquisition time280nst CONV Conversion time 1.26µst1CONVST_x low time20nst2BUSY low to FS low time0nst3Bus access finished to next conversion start time40nst D1CONVST_x high to BUSY high delay520nst D2FS low to SDO_x active delay512nst D3SCLK rising edge to new data valid delay15nst D4FS high to SDO_x3-state delay10nst H1Input data to SCLK falling edge hold time5nst H2Output data to SCLK rising edge hold time5nst S1Input data to SCLK falling edge setup time3nst S3CONVST_x high to XCLK falling or rising edge setup time6nst SCLK Serial clock period0.027810μs(1)All input signals are specified with t R=t F=1.5ns(10%to90%of BVDD)and timed from a voltage level of(V IL+V IH)/2.分销商库存信息:TIADS8555SPM ADS8555SPMR。

M51996_datasheet

Connect the heat sink pin to GND.
APPLICATION
Feed forward regulator,fly-back regulator
RECOMMENDED OPERATING CONDITIONS
Supply voltage range............................................12 to 30V Operating frequency.................................less than 500kHz Oscillator frequency setting resistance
IccOVP Circuit current in OVP state
IFBMIND IFBMAXD
∆IFB VFB RFB VTHOVPH ∆VTHOVP ITHOVP IINOVP VCCOVPC VCC(STOP) -VCCOVPC
ITHOVPC
Current at 0% duty Current at maximum duty
Block Symbol
Parameter
VCC
Operating supply voltage range
VCC(START) Operation start up voltage
VCC(STOP) Operation stop voltage
Test conditions
Limits Unit
Min. Typ. Max.
Difference supply voltage between operation stop and OVP reset
Current from OVP terminal for OVP reset

mt9171中文资料_数据手册_IC数据表

1Features•Full duplex transmission over a single twisted pair •Selectable 80 or 160 kbit/s line rate •Adaptive echo cancellation •Up to 3km (9171) and 4 km (9172)•ISDN compatible (2B+D) data format •Transparent modem capability•Frame synchronization and clock extraction •Zarlink ST-BUS compatible•Low power (typically 50mW), single 5V supplyApplications•Digital subscriber lines•High speed data transmission over twisted wires •Digital PABX line cards and telephone sets •80 or 160kbit/s single chip modemDescriptionThe MT9171 (DSIC) and MT9172 (DNIC) are pin for pin compatible replacements for the MT8971 and MT8972, respectively. They are multi-function devices capable of providing high speed, full duplex digital transmission up to 160kbit/s over a twisted wire pair.They use adaptive echo-cancelling techniques and transfer data in (2B+D) format compatible to the ISDN basic rate. Several modes of operation allow an easy interface to digital telecommunication networks including use as a high speed limited distance modemMarch 2006Ordering InformationMT9171/72AE 22 Pin PDIP Tubes MT9171/72AN 24 Pin SSOP Tubes MT9171/72AP 28 Pin PLCC TubesMT9171/72APR 28 Pin PLCC Tape & Reel MT9171/72ANR 24 Pin SSOP Tape & Reel MT9171/72AE122 Pin PDIP*Tubes MT9171/72AP128 Pin PLCC*Tubes MT9171/72AN124 Pin SSOP*TubesMT9171/72APR128 Pin PLCC*Tape & Reel MT9171/72ANR124 Pin SSOP*Tape & Reel*Pb Free Matte Tin-40°C to +85°CISO 2-CMOS ST-BUS FAMILY MT9171/72Digital Subscriber Interface Circuit Digital Network Interface CircuitData SheetFigure 1 - Functional Block DiagramDSTi/Di CDSTi/F0/CLD C4/TCK F0o/RCKMS0MS1MS2RegCDSTo/Do CDSTo/CDoTransmit InterfacePrescrambler ScramblerControl Register Transmit/Clock Receive Timing &Control StatusTransmit Timing Master Clock Phase LockedSync Detect ReceiveDPLLReceive InterfaceDe -PrescramblerDescramblerDifferentially Encoded BiphaseReceiverDifferentially Encoded Biphase Transmitter Transmit Filter &Line DriverReceive Filter-1+2MUXAddressEcho Canceller Error Signal Echo EstimateV BiasV DD V SS V Bias V RefL OUTL OUTDISPrecanL INOSC2OSC1—+∑CDihttps://MT9171/72Data Sheetwith data rates up to 160kbit/s. Both devices function identically but with the DSIC having a shorter maximum loop reach specification. The generic "DNIC" will be used to reference both devices unless otherwise noted.The MT9171/72 is fabricated in Zarlink’s ISO 2-CMOS process.Figure 2 - Pin ConnectionsPin DescriptionPin # Name Description222428112L OUT Line Out. Transmit Signal output (Analog). Referenced to V Bias .223V Bias Internal Bias Voltage output. Connect via 0.33µF decoupling capacitor to V DD .334V RefInternal Reference Voltage output. Connect via 0.33µF decoupling capacitor to V DD .4,5,64,5,65,7,8MS2-MS0Mode Select inputs (Digital). The logic levels present on these pins select thevarious operating modes for a particular application. See Table 1 for the operating modes.779RegC Regulator Control output (Digital). A 512kHz clock used for switch mode power supplies. Unused in MAS/MOD mode and should be left open circuit.8910F0/CLDFrame Pulse/C-Channel Load (Digital). In DN mode a 244ns wide negative pulse input for the MASTER indicating the start of the active channel times of the device. Output for the SLAVE indicating the start of the active channel times of the device. Output in MOD mode providing a pulse indicating the start of the C-channel.1234567891011121314222120191817161522 PIN PDIPLOUT VBias VRef MS2MS1MS0RegC F0/CLD CDSTi/CDi CDSTo/CDoVSS VDD LIN TESTLOUT DIS Precan OSC1OSC2C4/TCK F0o/RCK DSTi/Di DSTo/Do28 PIN PLCC27432128265678910112524232221201917121314151618•L O U T V B i a s V R e f N C V D D L I N T E S TNCLOUT DIS Precan OSC1OSC2NC C4/TCKMS2NC MS1MS0RegC F0/CLDNCC D S T i /C D i C D S T o /C D o V S S D S T o /D o N C F 0o /R C K D S T i /D i 12345678910111213141516242322212019181724 PIN SSOPLOUT VBias VRef MS2MS1MS0RegC F0/CLD CDSTi/CDi CDSTo/CDoVSSNC VDD LIN TESTLOUT DIS Precan OSC1OSC2C4/TCK F0o/RCK DSTi/Di DSTo/DoNC https://MT9171/72Data Sheet91012CDSTi/CDi Control/Data ST-BUS In/Control/Data In (Digital). A 2.048Mbit/s serial control & signalling input in DN mode. In MOD mode this is a continuous bit stream at the bit rate selected.101113CDSTo/CDo Control/Data ST-BUS Out/Control/Data Out (Digital). A 2.048Mbit/s serial control & signalling output in DN mode. In MOD mode this is a continuous bit stream at the bit rate selected.111214V SSNegative Power Supply (0V).121315DSTo/Do Data ST-BUS Out/Data Out (Digital). A 2.048Mbit/s serial PCM/data output inDN mode. In MOD mode this is a continuous bit stream at the bit rate selected.131416DSTi/DiData ST-BUS In/Data In (Digital). A 2.048Mbit/s serial PCM/data input in DN mode. In MOD mode this is a continuous bit stream at the bit rate selected.141517F0o/RCK Frame Pulse Out/Receive Bit Rate Clock output (Digital). In DN mode a 244nswide negative pulse indicating the end of the active channel times of the device to allow daisy chaining. In MOD mode provides the receive bit rate clock to the system.151619C4/TCKData Clock/Transmit Baud Rate Clock (Digital). A 4.096MHz TTL compatible clock input for the MASTER and output for the SLAVE in DN mode. For MOD mode this pin provides the transmit bit rate clock to the system.161721OSC2Oscillator Output . CMOS Output.171922OSC1Oscillator Input . CMOS Input. D.C. couple signals to this pin. Refer to D.C. Electrical Characteristics for OSC1 input requirements.182023PrecanPrecanceller Disable. When held to Logic ’1’, the internal path from L OUT to the precanceller is forced to V Bias thus bypassing the precanceller section. When logic ’0’, the L OUT to the precanceller path is enabled and functions normally. An internal pulldown (50k Ω) is provided on this pin.8,181,6,11,18,20,25NCNo Connection. Leave open circuit192124L OUT DIS L OUT Disable. When held to logic “1”, L OUT is disabled (i.e., output = V Bias ). Whenlogic “0”, L OUT functions normally. An internal pulldown (50k Ω) is provided on this pin.202226TEST Test Pin. Connect to V SS .212327L IN Receive Signal input (Analog). 222428V DDPositive Power Supply (+5V) input.Pin Description (continued)Pin # Name Description222428https://MT9171/72Data SheetFigure 3 - DV Port - 80kbit/s (Modes 2, 3, 6)Figure 4 - DV Port - 160kbit/s (Modes 2, 3, 6)MT9171/72Data Sheet Functional DescriptionThe MT9171/72 is a device which may be used in practically any application that requires high speed data transmission over two wires, including smart telephone sets, workstations, data terminals and computers. The device supports the 2B+D channel format (two 64kbit/s B-channels and one 16kbit/s D-channel) over two wires as recommended by the CCITT. The line data is converted to and from the ST-BUS format on the system side of the network to allow for easy interfacing with other components such as the S-interface device in an NT1 arrangement, or to digital PABX components.Smart telephone sets with data and voice capability can be easily implemented using the MT9171/72 as a line interface. The device’s high bandwidth and long loop length capability allows its use in a wide variety of sets. This can be extended to provide full data and voice capability to the private subscriber by the installation of equipment in both the home and central office or remote concentration equipment. Within the subscriber equipment the MT9171/72 would terminate the line and encode/ decode the data and voice for transmission while additional electronics could provide interfaces for a standard telephone set and any number of data ports supporting standard data rates for such things as computer communications and telemetry for remote meter reading. Digital workstations with a high degree of networking capability can be designed using the DNIC for the line interface, offering up to 160 kbit/s data transmission over existing telephone lines. The MT9171/72 could also be valuable within existing computer networks for connecting a large number of terminals to a computer or for intercomputer links. With the DNIC, this can be accomplished at up to 160kbit/s at a very low cost per line for terminal to computer links and in many cases this bandwidth would be sufficient for computer to computer links.Figure 1 shows the block diagram of the MT9171/72. The DNIC provides a bidirectional interface between the DV (data/voice) port and a full duplex line operating at 80 or 160kbit/s over a single pair of twisted wires. The DNIC has three serial ports. The DV port (DSTi/Di, DSTo/Do), the CD (control/data) port (CDSTi/CDi, CDSTo/CDo) and a line port (L IN, L OUT). The data on the line is made up of information from the DV and CD ports. The DNIC must combine https://information received from both the DV and CD ports and put it onto the line. At the same time, the data received from the line must be split into the various channels and directed to the proper ports. The usable data rates are 72 and144kbit/s as required for the basic rate interface in ISDN. Full duplex transmission is made possible through on board adaptive echo cancellation.The DNIC has various modes of operation which are selected through the mode select pins MS0-2. The two major modes of operation are the MODEM (MOD) and DIGITAL NETWORK (DN) modes. MOD mode is a transparent 80 or 160kbit/s modem. In DN mode the line carries the B and D channels formatted for the ISDN at either 80 or 160 kbit/s. In the DN mode the DV and CD ports are standard ST-BUS and in MOD mode they are transparent serial data streams at 80 or 160kbit/s. Other modes include: MASTER (MAS) or SLAVE (SLV) mode, where the timebase and frame synchronization are provided externally or are extracted from the line and DUAL or SINGLE (SINGL) port modes, where both the DV and CD ports are active or where the CD port is inactive and all information is passed through the DV port. For a detailed description of the modes see “Operating Modes” section.In DIGITAL NETWORK (DN) mode there are three channels transferred by the DV and CD ports. They are the B, C and D channels. The B1 and B2 channels each have a bandwidth of 64kbit/s and are used for carrying PCM encoded voice or data. These channels are always transmitted and received through the DV port (Figures 3, 4, 5, 6). The C-channel, having a bandwidth of 64kbit/s, provides a means for the system to control the DNIC and for the DNIC to pass status information back to the system. The C-channel has a Housekeeping (HK) bit which is the only bit of the C-channel transmitted and received on the line. The 2B+D channel bits and the HK bit are double-buffered. The D-channel can be transmitted or received on the line with either an 8, 16 or 64kbit/s bandwidth depending on the DNIC’s mode of operation. Both the HK bit and the D-channel can be used for end-to-end signalling or low speed data transfer. In DUAL port mode the C and D channels are accessed via the CD port (Figure 7) while in SINGL port mode they are transferred through the DV port (Figures 5, 6) along with the B1 and B2 channels.MT9171/72Data SheetFigure 5 - DV Port - 80kbit/s (Modes 0,4)Figure 6 - DV Port - 160kbit/s (Modes 0,4)In DIGITAL NETWORK (DN) mode, upon entering the DNIC from the DV and CD ports, the B-channel data, D-channel D0 (and D1 for 160kbit/s), the HK bit of the C-channel (160kbit/s only) and a SYNC bit are combined in a serial format to be sent out on the line by the Transmit Interface (Figures 11, 12). The SYNC bit produces an alternating 1-0 pattern each frame in order for the remote end to extract the frame alignment from the line. It is possible for the remote end to lock on to a data bit pattern which simulates this alternating 1-0 pattern that is not the true SYNC. To decrease the probability of this happening the DNIC may be programmed to put the data through a prescrambler that scrambles the data according to a predetermined polynomial with respect to the SYNC bit. This greatly decreases the probability that the SYNC pattern can be reproduced by any data on the line. In order for the echo canceller to function correctly, a dedicated scrambler is used with a scrambling algorithm which is different for the SLV and MAS modes. These algorithms are calculated in such a way as to provide orthogonality between the near and far end data streams such that the correlation between the two signals is very low.For any two DNICs on a link, one must be in SLV mode with the other in MAS mode. The scrambled data is differentially encoded which serves to make the data on the line polarity-independent. It is then biphase encoded as shown in Figure 10. See “Line Interface” section for more details on the encoding. Before leaving the DNIC the differentially encoded biphase data is passed through a pulse-shaping bandpass transmit filter that filters out the high and low frequency components and conditions the signal for transmission on the line.MT9171/72Data SheetFigure 7 - CD Port (Modes 2,6)Figure 8 - CD Port (Modes 1,5)The composite transmit and receive signal is received at L IN . On entering the DNIC this signal passes through a Precanceller which is a summing amplifier and lowpass filter that partially cancels the near-end signal and provides first order antialiasing for the received signal. Internal, partial cancellation of the near end signal may be disabled by holding the Precan pin high. This mode simplifies the design of external line transceivers used for loop extension applications. The Precan pin features an internal pull-down which allows this pin to be left unconnected in applications where this function is not required. The resultant signal passes through a receive filter to bandlimit and equalize it. At this point, the echo estimate from the echo canceller is subtracted from the precancelled received signal. This difference signal is then input to the echo canceller as an error signal and also squared up by a comparator and passed to the biphase receiver. Within the echo canceller, the sign of this error signal is determined. Depending on the sign, the echo estimate is either incremented or decremented and this new estimate is stored back in RAM.The timebase in both SLV and MAS modes (generated internally in SLV mode and externally in MAS mode) is phase-locked to the received data stream. This phase-locked clock operates the Biphase Decoder, Descrambler and Deprescrambler in MAS mode and the entire chip in SLV mode. The Biphase Decoder decodes the received encoded bit stream resulting in the original NRZ data which is passed onto the Descrambler and Deprescrambler where the data is restored to its original content by performing the reverse polynomials. The SYNC bits areCLDTCKCDiCDoC 0C 1C 2C 3C 4C 5C 6C 7C 6C 7C 0C 1C 0C 1C 2C 3C 4C 5C 6C 7C 6C 7C 0C 1https://MT9171/72Data Sheetextracted and the Receive Interface separates the channels and outputs them to the proper ports in the proper channel times. The destination of the various channels is the same as that received on the input DV and CD ports.The Transmit/Receive Timing and Control block generates all the clocks for the transmit and receive functions and controls the entire chip according to the control register. In order that more than one DNIC may be connected to the same DV and CD ports an F0o signal is generated which signals the next device in a daisy chain that its channel times are now active. In this arrangement only the first DNIC in the chain receives the system F0 with the following devices receiving its predecessor’s F0o.In MOD mode, all the ports have a different format. The line port again operates at 80 or 160kbit/s, however, there is no synchronization overhead, only transparent data. The DV and CD ports carry serial data at 80 or 160kbit/s with the DV port transferring all the data for the line and the CD port carrying the C-channel only. In this mode the transfer of data at both ports is synchronized to the TCK and RCK clocks for transmit and receive data, respectively. The CLD signal goes low to indicate the start of the C-channel data on the CD port. It is used to load and latch the input and output C-channel but has no relationship to the data on the DV port.Operating Modes (MS0-2)The logic levels present on the mode select pins MS0, MS1 and MS2 program the DNIC for different operating modes and configure the DV and CD ports accordingly. Table 1 shows the modes corresponding to the state of MS0-2. These pins select the DNIC to operate as a MASTER or SLAVE, in DUAL or SINGLE port operation, in MODEM or DIGITAL NETWORK mode and the order of the C and D channels on the CD port. Table 2 provides a description of each mode and Table 3 gives a pin configuration according to the mode selected for all pins that have variable functions. These functions vary depending on whether it is in MAS or SLV, and whether DN or MOD mode is used.Table 1 - Mode Select Pins E=Enabled X=Not Applicable Blanks are disabledMode Select Pins Mode Operating ModeMS2MS1MS0SLVMAS DUALSINGL MODDN D-C C-D ODE 0000E EE E E 0011E E E X X E 0102E E E EE 0113EEE E E 1004E EE E E1015E E EX X E 1106EE E EE1117EEEEhttps://MT9171/72Data SheetTable 3 - Pin ConfigurationsThe overall mode of operation of the DNIC can be programmed to be either a baseband modem (MOD mode) or a digital network transceiver (DN mode). As a baseband modem, transmit/receive data is passed transparently through the device at 80 or 160kbit/s by the DV port. The CD port transfers the C-channel and D-Channel also at 80 or 160kbit/s.In DN mode, both the DV and CD ports operate as ST-BUS streams at 2.048Mbit/s. The DV port transfers data over pins DSTi and DSTo while on the CD port, the CDSTi and CDSTo pins are used. The SINGL port option only exists in DN mode.Mode FunctionSLVSLAVE - The chip timebase is extracted from the received line data and the external 10.24MHz crystal is phase locked to it to provide clocks for the entire device and are output for the external system to synchronize to.MASMASTER - The timebase is derived from the externally supplied data clocks and 10.24MHz clock which must be frequency locked. The transmit data is synchronized to the system timing with the receive data recovered by a clock extracted from the receive data and resynchronized to the system timing.DUAL DUAL PORT - Both the CD and DV ports are active with the CD port transferring the C&D channels and the DV port transferring the B1& B2 channels.SINGL SINGLE PORT - The B1& B2, C and D channels are all transferred through the DV port. The CD port is disabled and CDSTi should be pulled high.MODMODEM - Baseband operation at 80 or 160kbits/s. The line data is received and transmitted through the DV port at the baud rate selected. The C-channel is transferred through the CD port also at the baud rate and is synchronized to the CLD output.DN DIGITAL NETWORK - Intended for use in the digital network with the DV and CD ports operating at 2.048Mbits/s and the line at 80 or 160kbits/s configured according to the applicable ISDN recommendation.D-C D BEFORE C-CHANNEL - The D-channel is transferred before the C-channel following F0.C-D C BEFORE D-CHANNEL - The C-channel is transferred before the D-channel following F0.ODEOUTPUT DATA ENABLE - When mode 7 is selected, the DV and CD ports are put in highimpedance state. This is intended for power-up reset to avoid bus contention and possible damage to the device during the initial random state in a daisy chain configuration of DNICs. In all the other modes of operation DV and CD ports are enabled during the appropriate channel times.Mode #F0/CLDF0o/RCKC4/TCKName Input/OutputName Input/OutputName Input/Output0F0Input F0o Output C4Input 1CLD Output RCK Output TCK Output 2F0Input F0o Output C4Input 3F0Input F0o Output C4Input 4F0Output F0o Output C4Output 5CLD Output RCK Output TCK Output 6F0Output F0oOutputC4Output 7F0InputF0o OutputC4Inputhttps://MT9171/72Data SheetIn MOD mode, DUAL port operation must be used and the D, B1 and B2 channel designations no longer exist. The selection of SLV or MAS will determine which of the DNICs is using the externally supplied clock and which is phase locking to the data on the line. Due to jitter and end to end delay, one end must be the master to generate all the timing for the link and the other must extract the timing from the receive data and synchronize itself to this timing in order to recover the synchronous data. DUAL port mode allows the user to use two separate serial busses: the DV port for PCM/data (B channels) and the CD port for control and signalling information (C and D channels). In the SINGL port mode, all four channels are concatenated into one serial stream and input to the DNIC via the DV port.The order of the C and D channels may be changed only in DN/DUAL mode. The DNIC may be configured to transfer the D-channel in channel 0 and the C-channel in channel 16 or vice versa. One other feature exists; ODE,where both the DV and CD ports are tristated in order that no devices are damaged due to excessive loading while all DNICs are in a random state on power up in a daisy chain arrangement.DV Port (DSTi/Di, DSTo/Do)The DV port transfers data or PCM encoded voice to and from the line according to the particular mode selected by the mode select pins. The modes affecting the configuration of the DV port are MOD or DN and DUAL or SINGL. In DN mode the DV port operates as an ST-BUS at 2.048Mbit/s with 32, 8 bit channels per frame as shown in Figure 9. In this mode the DV port channel configuration depends upon whether DUAL or SINGL port is selected. When DUAL port mode is used, the C and D channels are passed through the CD port and the B1 and B2 channels are passed through the DV port. At 80kbit/s only one channel of the available 32 at the DV port is utilized, this being channel 0 which carries the B1-channel. This is shown in Figure 3. At 160kbit/s, two channels are used, these being 0 and 16 carrying the B1 and B2 channels, respectively. This is shown in Figure 4. When SINGL port mode is used, channels B1, B2, C and D are all passed via the DV port and the CD port is disabled. See CD port description for an explanation of the C and D channels.Figure 9 - ST-BUS FormatThe D-channel is always passed during channel time 0 followed by the C and B1 channels in channel times 1 and 2, respectively for 80kbit/s. See Figure 5. For 160kbit/s the B2 channel is added and occupies channel time 3 of the DV port. See Figure 6. For all of the various configurations the bit orders are shown by the respective diagram.In MOD mode the DV and CD ports no longer operate at 2.048Mbits/s but are continuous serial bit streams operating at the bit rate selected of 80 or 160kbit/s.While in the MOD mode only DUAL port operation can be used.In order for more than one DNIC to be connected to any one DV and CD port, making more efficient use of the busses, the DSTo and CDSTo outputs are put into high impedance during the inactive channel times of the DNIC.This allows additional DNICs to be cascaded onto the same DV and CD ports. When used in this way a signal called F0o is used as an indication to the next DNIC in a daisy chain that its channel time is now active. Only the first DNIC in the chain receives the system frame pulse and all others receive the F0o from its predecessor in the chain. This allows up to 16 DNICs to be cascaded.ChannelChannel1Channel2• • • • • • • •Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0125 µsecChannel 31Channel 30Channel 31ChannelChannel 29F0ST-BUSMost Significant Bit (First)LeastSignificant Bit (Last)3.9 µsechttps://MT9171/72Data SheetCD Port (CDSTi/CDi, CDSTo/CDo)The CD port is a serial bidirectional port used only in DUAL port mode. It is a means by which the DNIC receives its control information for things such as setting the bit rate, enabling internal loopback tests, sending status information back to the system and transferring low speed signalling data to and from the line.The CD port is composed of the C and D-Channels. The C-channel is used for transferring control and status information between the DNIC and the system. The D-channel is used for sending and receiving signalling information and lower speed data between the line and the system. In DN/DUAL mode the DNIC receives a C-channel on CDSTi while transmitting a C-channel on CDSTo. Fifteen channel times later (halfway through the frame) a D-channel is received on CDSTi while a D-channel is transmitted on CDSTo. This is shown in Figure 7.The order of the C and D bytes in DUAL port mode can be reversed by the mode select pins. See Table 1 for a listing of the byte orientations.The D-channel exists only in DN mode and may be used for transferring low speed data or signalling information over the line at 8, 16 or 64kbit/s (by using the DINB feature). The information passes transparently through the DNIC and is transmitted to or received from the line at the bit rate selected in the Control Register.If the bit rate is 80kbit/s, only D0 is transmitted and received. At 160kbit/s, D0 and D1 are transmitted and received. When the DINB bit is set in the Control Register the entire D-channel is transmitted and received in the B1-channel timeslot.The C-channel is used for transferring control and status information between the DNIC and the system. The Control and Diagnostics Registers are accessed through the C-channel. They contain information to control the DNIC and carry out the diagnostics as well as the HK bit to be transmitted on the line as described in Tables 4 and 5. Bits 0 and 1 of the C-channel select between the Control and Diagnostics Register. If these bits are 0, 0 then the C-channel information is written to the Control Register (Table 4). If they are 0, 1 the C-c hannel is written to the Diagnostics Register (Table 5).Bit Name Description0Reg Sel-1Register Select-1. Must be set to ’0’ to select the Control Register.1Reg Sel-2Register Select-2. Must be set to ’0’ to select the Control Register.2DRRDiagnostics Register Reset. Writing a "0" to this bit will cause a diagnostics register reset to occur coincident with the next frame pulse as in the MT8972A. When this bit is a logic "1", the Diagnostics Register will not be reset.3BRS Bit Rate Select. When set to ’0’ selects 80kbit/s. When set to ’1’, selects 160kbit/s.4DINB 2D-Channel in B Timeslot. When ’0’, the D-channel bits (D0 or D0 and D1) corresponding to the selected bit rate (80 or 160kbit/s) are transmitted during the normal D-channel bit times. When set to ’1’, the entire D-channel (D0-D7) is transmitted during the B1-channel timeslot on the line providing a 64kbit/s D-channel link.5PSEN 2Prescrambler/Deprescrambler Enable. When set to ’1’, the data prescrambler anddeprescrambler are enabled. When set to ’0’, the data prescrambler and deprescrambler are disabled.bit 0bit 1bit 2bit 3bit 4bit 5bit 6bit 7Reg Sel-1Reg Sel-2DRRBRSDINBPSENATTACKTxHKDefault Mode Selection (Refer to Table 4a)https://。

IP6505降压快充芯片datasheet

输出快充
支持 BC1.2、Apple、三星协议支持高通 QC2.0 和 QC3.0（认证编号：
4788120153-2）支持 MTK PE1.1/PE2.0 支持华为快充协议 FCP 支持华为快充协议 SCP 支持三星快充协议 AFC 支持展讯快充协议 SFCP
多重保护、高可靠性
Idc(A)Max.
Saturation Current
图 4 输出应用原理图
7 / 10
TEL:18319027317
IP6505
11 BOM 表
序号元件名称
型号&规格
单位用量
位置
1 IC
IP6505
PCS
2 贴片电阻
0603 3.3K 5%
PCS
3 贴片电阻
0603 75K 1%
PCS
TC-220M-4. 22uH+/-20%，电流 4.5A
4 5A-CS1371 DCR<12mohm
6 / 10
TEL:18319027317
IP6505
10 典型应用原理图
IP6505 外围只需要电感、电容、电阻，即可实现完整功能的车充方案
VOUT R2 3.3K
VOUT
22uH L1
SW 1
DM
DP
C5 C4
SW
C3
2
R4
10uF
220uF
2R 0.1uFBST
3
C6 1nF FS
R3 75k
开关频率设定
IP6505 可以通过 FS 来设定开关频率大小。DCDC 开关频率和电阻的对应关系如下表.
FS 外接电阻（ohm） 47K
75k

MF_RC500_datasheet(中文)

I
2 3
4Leabharlann 55.2.3.1 页寄存器 ....................................................................................... 16 5.2.3.2 TxControl 寄存器 ........................................................................ 16 5.2.3.3 CwConductance 寄存器 ................................................................ 16 5.2.3.4 PreSet13 寄存器 .......................................................................... 17 5.2.3.5 PreSet14 寄存器 .......................................................................... 17 5.2.3.6 ModWidth 寄存器 .......................................................................... 17 5.2.3.7 PreSet16 寄存器 .......................................................................... 17 5.2.3.8 PreSet17 寄存器 .......................................................................