2015《数字逻辑设计》半期考试-试题及参考答案

电子科技大学2014 - 2015 学年第二学期期中考试卷

课程名称：数字逻辑设计及应用考试形式：闭卷考试日期：2015年5月10日考试时长：120分钟

课程成绩构成：平时 30/20 %，期中 30/20 %，小班讨论0/20 %，期末40 % 本试卷试题由__VII___部分构成，共__6___页。

题号 I II III IV V VI VII 合计

得分

I. Please fill out the correct answers in the brackets “( )” . ( 2’ X 20 = 40’ )

1. [510.5] 10 = ( 111111110.1)2 = ( 1FE.8 ) 16

2. (2015)10 =( 0010000000010101)8421BCD =( 0101001101001000) Excess-3

3.If X’s signed-magnitude representation X SM is 000110102, then (2X)’s 8-bit two’s

complement representation is ( 00110100 ), and (-X’2)’s 8-bit two’s complement representation is ( 11110011 ).

4.If a logic function is F = ∑(A,B,C) (1,2,3,6), its complement expression is F' = ∑(A,B,C) ( 0,4,5,7 ), and its dual expression is F D = ∑(A,B,C).( 0,2,3,7 ).

5.For CMOS inverters, can different outputs of common CMOS inverters be connected together?

[Yes or No] ( No); Three-state inverters have three-state outputs, which are HIGH、LOW and ( Hi-Z). Can different outputs of three-state inverters be connected together? [Yes or No] ( Yes ).

6.Given a binary number X=101101012, its corresponding Gray code is ( 11101111 ).

7. If [X] two’s-complement = 0111 00112, [Y] two’s-complement = 1001 11002, then [X-Y] two’s-complement =（1101 0111），whether overflow occurs? [Yes or No] ( Yes ).

8. Given 126 different states, it requires at least ( 7) binary bits to represent them.

9.For CMOS NOR gates, their unused inputs should connect to ( 0) state.

10.From Table 1 below, if 74HC devices drive 74LS devices,

in HIGH state , DC noise margin V NH is ( 1.84 ), Fan-out NH is ( 200);

in LOW state , DC noise margin V NL is ( 0.47 ), Fan-out NL is ( 10 ).

Table 1

Family

Description Symbol 74LS 74HC

LOW-level input voltage (V) V ILmax 0.8 1.35 LOW-level output voltage (V) V OLmax 0.5 0.33 HIGH-level input voltage (V) V IHmin 2.0 3.85 HIGH-level output voltage (V) V OHmin 2.7 3.84 LOW-level input current (uA) I ILmax -400 1 LOW-level output current (mA) I OLmax 8 4 HIGH-level input current (uA) I IHmax 20 -1 HIGH-level output current (mA)

I OHmax -0.4 -4

II. Choose the correct answer and fill the item number in the brackets. (Single selection for question 1~8, Multi-selection for 9~10, 2’ X 10=20 )

1. For logic function

, its minimal sum is ( C ) A. B.

C.

D.

2. Given a circuit design, its output expression with positive logic is

, then its output expression with negative logic is ( C ) A. B.

C.

D.

3. For the priority encoder 74X148, its inputs are: I 0-L , I 1-L , I 2-L , I 3-L , I 4-L , I 5-L , I 6-L , I 7-L ，outputs

are Y 2-L ,Y 1-L ,Y 0-L . The inputs and outputs are all active-low. When active-low enable input EN _L =0, I 1-L = I 4-L = I 5-L = 0, and any other inputs are all 1, then Y 2-L , Y 1-L , Y 0-L is ( B ). A. 110 B. 010 C. 001 D. 101 4. Except enable lines, an 8-1 multiplexer should have ( C ) control’select lines.

A. 1

B. 2

C. 3

D. 4

5. The truth table of a circuit is shown in Table 2, the logic expression of this circuit is ( D ).

A. F=A+B

B. F=S+A+B

C.

D.

Table 2

S A B F 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1

1