计算机体系结构与处理器设计Pipelined MIPS CPU

A Zero Result 0 ALU B
Data memory
A Mem Data imm rd rt
RegFile
Q2
A Mem Data Write data 1 0
Sign extend
1 0 1
IF
ID
EXE
MEM
WB
Pipelined MIPS CPU – p.5/58
Basic Pipelined func MIPS CPU
lw add sub or and slt
$1, $3, $6, $9, $12, $15,
0($2) $4, $7, $10, $13, $16,
imm $5 $8 $11 $14 $17 rd rt
Sign extend
1 0 1
Pipelined MIPS CPU – p.11/58
Pipelined MIPS CPU – Clock Cycle 6
A Zero Result 0 ALU B
Data memory
RegFile
Q2
A Mem Data Write data 1 0
lw add sub or and slt
$1, $3, $6, $9, $12, $15,
0($2) $4, $7, $10, $13, $16,
imm $5 $8 $11 $14 $17 rd rt
MIPS Processor Design
Department of Computer Science Faculty of Computer and Information Sciences Hosei University, Tokyo 184-8584 Japan http://cis.k.hosei.ac.jp/∼yamin/
CC1 CC2 CC3 CC4 CC5 CC6 CC7
Load
Mem
Regs
ALU
Mem
Regs
add
Mem
Regs
ALU
Mem
Regs
sub
Mem
Regs
ALU
Mem
Regs
and
Mem
Regs
ALU
Mem
Pipelined MIPS CPU – p.14/58
Structural Hazard Causes Bubbles to be Inserted
N1 N2 ND DI Q1
Add
Inst memory 0 1 A Mem Data
A Zero Result 0 ALU B
Data memory
RegFile
Q2
A Mem Data Write data 1 0
lw add sub or and slt
$1, $3, $6, $9, $12, $15,
Sign extend
1 0 1
Pipelined MIPS CPU – p.12/58
Three Classes of Pipeline Hazards
There are situations, called hazards, that prevent the next instruction in the instruction stream from executing during its designated clock cycle. 1. Structural hazards arise from resource conflicts when the hardware cannot support all possible combinations of instructions in simultaneous overlapped execution. 2. Data hazards arise when an instruction depends on the results of a previous instruction. 3. Control hazards arise from the pipelining of branches and other instructions that change the PC.
EXE ID IF
MEM EXE ID IF
WB MEM EXE ID IF WB MEM EXE ID IF WB MEM EXE ID IF WB MEM EXE ID IF WB MEM EXE ID WB MEM EXE WB MEM WB
(c) pipeline processor
Pipelined MIPS CPU – p.3/58
CC1 CC2 CC3 CC4 CC5 CC6 CC7 CC8
Load
Mem
Regs
ALU
Mem
Regs
add
Mem
Regs
ALU
Mem
Regs
sub
Mem
Regs
ALU
Mem
Regs
Stall
Bubble
Bubble
Bubble
Bubble
Bubble
and
Mem
Regs
ALU
Mem
Pipelined MIPS CPU – p.15/58
0($2) $4, $7, $10, $13, $16,
imm $5 $8 $11 $14 $17 rd rt
Sign extend
1 0 1
Pipelined MIPS CPU – p.10/58
Pipelined MIPS CPU – Clock Cycle 5
IF ID EXE sub $6, $7, $8 MEM add $3, $4, $5 WB lw $1,
; rd <= rs + rt
rd 5 bits
shamt 5 bits
func 6 bits
Example: add rd, rs, rt
I-format instruction ( lw, sw, beq, addi, andi, ori, bne )
31 26 25 21 20 16 15 0
Pipelined MIPS CPU – p.1/58
Instructions We Will Use
R-format instruction ( add, sub, and, or, slt )
31 26 25 21 20 16 15 11 10 6 5 0
op 6 bits
rs 5 bits
rt 5 bits
beq rs, rt, target
Pipelined MIPS CPU – p.2/58
(a) single cycle processor
IF
ID add
EXE
WB IF ID beq EXE IF ID EXE lw MEM WB
(b) multiple cycle processor
IF
ID IF
Pipelined MIPS CPU – p.9/58
Pipelined MIPS CPU – Clock Cycle 4
IF or $9, $10, $11 ID sub $6, $7, $8 EXE add $3, $4, $5 MEM lw $1, 0($2) WB
4 Add rs rt Shift left 2
1 0 op Cntl unit
RegDes ALUcontrol ALUSrcB
WriteReg MemToReg WriteMem Branch
4 Add Shift left 2
Q1
Add
rs rt P C A Mem Data imm rd rt
N1 N2
WE
A Zero Result 0 ALU B WE A Mem Data Write data 1 0
IF slt $15,$16,$17 ID and $12,$13,$14 EXE or $9, $10, $11 MEM sub $6, $7, $8 WB add $3,
4 Add rs rt Shift left 2
N1 N2 ND DI Q1
Add
Inst memory 0 1 A Mem Data
Pipelined MIPS CPU – p.13/58
Structural Hazard — An Example
A machine with only one memory port will generate a conflict whenever a memory reference occurs.
Concept of Pipelining
CC1 CC2 CC3 CC4 CC5 CC6 CC7 CC8 CC9
Inst mem
Regs
ALU
Data mem
Regs
Inst mem
Regs
ALU
Data mem
Regs
Inst mem
Regs
ALU
Data mem
Regs
Inst mem
Regs
$1, $3, $6, $9, $12, $15,
0($2) $4, $7, $10, $13, $16,
imm $5 $8 $11 $14 $17 rd rt
Sign extend
1 0 1
Pipelined MIPS CPU – p.8/58
Pipelined MIPS CPU – Clock Cycle 3
op 6 bits
lw sw rt, imm(rs) rt, imm(rs)
rs 5 bits
rt 5 bits
immediate 16 bits
; rt <= memory[rs+imm] ; memory[rs + imm] <= rt ; if (rs == rt) PC <= PC + 4 + signExtend(imm << 4)
RegFile
Q2
A Mem Data Write data 1 0
lw add sub or and slt
$1, $3, $6, $9, $12, $15,
0($2) $4, $7, $10, $13, $16,
imm $5 $8 $11 $14 $17 rd rt
Sign extend
1 0 1
4 Add rs rt Shift left 2
N1 N2 ND DI Q1
Add
Inst memory 0 1 A Mem Data
A Zero Result 0 ALU B
Data memory
RegFile
Q2
A Mem Data Write data 1 0
lw add sub or and slt
RegFile
ND DI Q2
Sign extend
1 0 1
IF
ID
EXE
MEM
WB
Pipelined MIPS CPU – p.6/58
Pipelined MIPS CPU – Clock Cycle 1
IF lw $1, 0($2) ID EXE MEM WB
4 Add rs rt Shift left 2
IF sub $6, $7, $8 ID add $3, $4, $5 EXE lw $1, 0($2) MEM WB
4 Add rs rt Shift left 2
N1 N2 ND DI Q1
Add
Inst memory 0 1 A Mem Data
A Zero Result 0 ALU B
Data memory
and $12, $13, $14 or $9, $10, $11
4 Add rs rt Shift left 2
N1 N2 ND DI Q1
Add
Inst memory 0 1 A Mem Data
A Zero Result 0 ALU B
Data memory
RegFile
Q2
Leabharlann Baidu
A Mem Data Write data 1 0
ALU
Data mem
Regs
Inst mem
Regs
ALU
Data mem
Regs
Pipelined MIPS CPU – p.4/58
Pipelined MIPS CPU - Datapath
1 0 4 Add Shift left 2 rs rt
N1 N2 ND DI Q1
Add
Inst memory P C
N1 N2 ND DI Q1
Add
Inst memory 0 1 A Mem Data
A Zero Result 0 ALU B
Data memory
RegFile
Q2
A Mem Data Write data 1 0
lw add sub or and slt
$1, $3, $6, $9, $12, $15,
0($2) $4, $7, $10, $13, $16,
imm $5 $8 $11 $14 $17 rd rt
Sign extend
1 0 1
Pipelined MIPS CPU – p.7/58
Pipelined MIPS CPU – Clock Cycle 2
IF add $3, $4, $5 lw $1, 0($2) ID EXE MEM WB