组合逻辑电路设计案例.

二输入与门
★程序1：
ENTITY and2 IS
PORT (a,b:IN BIT;
c:OUT BIT);
END ENTITY and2;
ARCHITECTURE and2_behav OF and2 IS
BEGIN
c<=a AND b AFTER 5ns;
END ARCHITECTURE and2_behav;
★程序2：
ENTITY and2 IS
目录
简单门电路‥‥‥‥‥‥‥‥‥‥‥‥1 三态门及总线缓冲器‥‥‥‥‥‥‥‥‥‥‥‥3 转换器‥‥‥‥‥‥‥‥‥‥‥‥6
并置运算器‥‥‥‥‥‥‥‥‥‥‥‥8
奇偶校验器‥‥‥‥‥‥‥‥‥‥‥‥9
加法器‥‥‥‥‥‥‥‥‥‥‥‥11
选择器‥‥‥‥‥‥‥‥‥‥‥‥12
编译码器‥‥‥‥‥‥‥‥‥‥‥‥18
GENERIC (rise,fall:TIME); PORT (a,b: IN BIT; c: OUT BIT) END ENTITY and2; ARCHITECTURE behav OF and2 IS SIGNAL internal:BIT; BEGIN internal<=a AND b;
c<=internal AFTER (rise ) WHEN internal='1' ELSE
internal AFTER (fall
); END ARCHITECTURE behav;
★程序3：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; ENTITY nand2 IS PORT (a, b: IN STD_LOGIC; y: OUT STD_LOGIC); END ENTITY nand2;
ARCHITECTURE nand2_2 OF nand2 IS BEGIN
t1:PROCESS (a, b)IS
V ARIABLE comb:STD_LOGIC_VECTOR (1 DOWNTO 0);
BEGIN
comb:=a & b; CASE comb IS
WHEN "00"=>y<='1';
WHEN "01"=>y<='1';
WHEN "10"=>y<='1';
WHEN "11"=>y<='0';
WHEN OTHERS=>y<='X'; END CASE;
END PROCESS t1; END ARCHITECTURE nand2_2;
三态门电路
★程序
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; ENTITY tri_gate IS PORT (din, en: IN STD_LOGIC;
dout: OUT STD_LOGIC); END ENTITY tri_gate;
ARCHITECTURE zas OF tri_gate IS BEGIN
tri_gate1:PROCESS (din, en)IS BEGIN
IF (en='1') THEN
dout<=din; ELSE
dout<='Z'; END IF; END PROCESS;
END ARCHITECTURE zas;
★程序2：
ARCHITECTURE blk OF tri_gate IS BEGIN
tri_gate2:BLOCK (en='1') BEGIN
dout<=GUARDED din; END BLOCK;
END ARCHITECTURE blk;
八位单向总线缓冲器
★程序1：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; ENTITY tri_buf8 IS
PORT (din: IN STD_LOGIC_VECTOR (7 DOWNTO 0) ; dout: OUT STD_LOGIC_VECTOR (7 DOWNTO 0); en:IN STD_LOGIC); END ENTITY tri_buf8;
ARCHITECTURE zas OF tri_buf8 IS BEGIN
tri_buff: PROCESS (en, din)IS
BEGIN
IF (en='1' ) THEN
dout<=din;
ELSE
dout<="ZZZZZZZZ"; END IF END PROCESS;
END ARCHITECTURE zas;
双向总线缓冲器
★程序1：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY tri_bigate IS
PORT (a, b:INOUT STD_LOGIC_VECTOR (7 DOWNTO 0);
en:IN STD_LOGIC;
dr:IN STD_LOGIC);
END ENTITY tri_bigate;
ARCHITECTURE rtl OF tri_bigate
SIGNAL aout, bout:STD_LOGIC_VECTOR (7 DOWNTO 0);
BEGIN
PROCESS (a, dr, en)IS
BEGIN
IF ((en='0') AND (dr='1')) THEN
bout<=a;
bout<="ZZZZZZZZ";
END IF;
b<=bout;
END PROCESS;
PROCESS (b, dr, en)IS
BEGIN
IF ((en='0') AND (dr='0')) THEN
aout<=b;
ELSE
aout<="ZZZZZZZZ";
END IF;
a<=aout;
END PROCESS;
END ARCHITECTURE rtl;
位矢量/整数转换器
★程序1：
PROCEDURE vector_to_int
(z:IN STD_LOGIC_VECTOR;
x_f1ag: OUT BOOLEAN;
q: INOUT INTEGER) IS
BEGIN
q:=0;
x_f1ag:=FALSE;
FOR i IN z'RANGE LOOP
q:=q*2;
IF(z(i)=1) THEN
q:=q+1;
ELSIF(z(i)/=0) THEN
x_f1ag:=TRUE;
END IF
END LOOP;
END PROCEDURE vector_to_int;
标准逻辑矢量/整数转换器
★程序1：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY add5 IS
PORT (num:IN STD_LOGIC_VECTOR (2 DOWNTO 0);
…
);
END ENTITY add5;
ARCHITECTURE rtl OF add5 IS
SIGNAL in_num:INTEGER RANGE 0 TO 5;
…
z(i)
x_flag
q
BEGIN
in_num<=CONV_INTEGER (num);
…
END ARCHITECTURE rtl;
并置运算器
★程序1： …
tmp_b<=b AND (en &en &en &en)； y<=a & tmp_b ； …
八位奇偶校验电路
★程序1：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; ENTITY parity_check IS
PORT(a: IN STD_LOGIC_VECTOR(7 DOWNTO 0); y: OUT STD_LOGIC); END ENTITY parity_check;
ARCHITECTURE rtl OF parity_check IS BEGIN
PROCESS(a) IS
V ARIABLE tmp: STD_LOGIC;
BEGIN
tmp:='0';
FOR i IN 0 TO 7 LOOP
tmp:=tmp XOR a(i); END LOOP; y<=tmp;
END PROCESS; END ARCHITECTURE rtl;
★程序2：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; ENTITY parity_check IS
PORT(a: IN STD_LOGIC_VECTOR(7 DOWNTO 0); y: OUT STD_LOGIC); END ENTITY parity_check;
ARCHITECTURE behav OF parity_check IS BEGIN
PROCESS(a) IS
V
ARIABLE tmp: STD_LOGIC;
BEGIN
tmp:= '0';
WHILE (i<8) LOOP
tmp:=tmp XOR a(i);
i:=i+1;
END LOOP;
y<=tmp;
END PROCESS;
END ARCHITECTURE behav;
加法器
★程序1：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; ENTITY full_adder IS PORT (a, b, cin: IN STD_LOGIC; s, co: OUT STD_LOGIC); END ENTITY full_adder;
ARCHITECTURE full1 OF full_adder IS COMPONENT half_adder IS PORT (a, b: IN STD_LOGIC;
s, co: OUT STD_LOGIC);
END COMPONENT;
SIGNAL u0_co, u0_s, u1_co:STD_LOGIC; BEGIN
u0:half_adder PORT MAP (a, b, u0_s, u0_co); u1:half_adder PORT MAP (u0_s, cin, s, u1_co); co<=u0_co OR u1_co; END ARCHITECTURE full1; 半加器
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; ENTITY half_adder IS PORT (a, b: IN STD_LOGIC; s, co: OUT STD_LOGIC); END ENTITY half_adder;
ARCHITECTURE half1 OF half_adder IS SIGNAL c, d:STD_LOGIC;
BEGIN c<=a OR b; d<=a NAND b; co<=NOT d; s<=c AND d;
END ARCHITECTURE half1;
二选一选择器
★程序1：
ENTITY mux IS
GENERIC(m:TIME: =1ns);
PORT (d0, d1：IN BIT ；
sel ：IN BIT ；
q ：OUT BIT)；
END ENTITY mux ；
ARCHITECTURE connect OF mux IS BEGIN
PROCESS(d0,d1,sel)IS
V ARIBLE temp1,temp2,temp3:BIT;
BEGIN
temp1:=d0 AND sel;
temp2:=d1 AND (NOTsel);
temp3:=temp1 OR temp2; q<=temp3 AFTER m;
END PROCESS
END ARCHITECTURE connect ；
★程序2（与程序1的描述方式一致，但对原件逻辑功能的描述更简单）： ENTITY mux IS PORT (d0, d1：IN BIT ； sel ：IN BIT ；
q ：OUT BIT)；
END ENTITY mux ；
ARCHITECTURE dataflow OF mux IS
BEGIN
q<=(d0 AND sel)OR(NOT sel AND d1);
END ARCHITECTURE dataflow；
★程序3：
ENTITY mux IS
PORT(d0，d1，sel: IN BIT;
q: OUT BIT);
END ENTITY mux;
ARCHITECTURE connect OF mux IS SIGNAL tmp1，tmp2，tmp3: BIT;
BEGIN
cale:BLOCK
BEGIN
tmp1<=d0 AND sel;
tmp2<=d1 AND (NOT sel);
tmp3<=tmp1 OR tmp2;
q<=tmp3;
END BLOCK cale;
END ARCHITECTURE connect;
★程序4：
ENTITY mux IS
PORT(d0,d1,sel: IN BIT;
q: OUT BIT);
END ENTITY mux;
ARCHITECTURE connect OF mux IS
BEGIN
cale: PROCESS(d0,d1,sel) IS
V ARIABLE tmp1,tmp2,tmp3: BIT;
BEGIN
tmp1:=d0 AND sel;
tmp2:=d1 AND (NOT sel);
tmp3:=tmp1 OR tmp2;
q<=tmp3 ;
END PROCESS cale;
END ARCHITECTURE connect;
★程序5：
ENTITY mux2 IS
PORT (d0,d1,sel:IN BIT;
q:OUT BIT);
END ENTITY mux2;
ARCHITECTURE struct OF mux2 IS
COMPONENT and2 IS
PORT (a,b:
IN BIT;
c:OUT BIT); END COMPONENT; COMPONENT or2 IS PORT (a,b:IN BIT;
c:OUT BIT);
END COMPONENT;
COMPONENT inv IS
PORT (a:IN BIT;
c:OUT BIT);
END COMPONENT;
SIGNAL aa,ab,nsel:BIT;
BEGIN
u1:inv PORT MAP (sel,nsel);
u2:and2 PORT MAP (nsel,d1,ab);
u3:and2 PORT MAP (d0,sel,aa);
u4:or2 PORT MAP (aa,ab,q); END ARCHITECTURE struct;
★程序6：
ARCHITECTURE rtl OF mux2 IS
BEGIN
PROCESS (a, b, sel) IS
BEGIN
IF (sel='1') THEN
c<=a;
ELSE
c<=b;
END IF;
END PROCESS;
END ARCHITECTURE rtl;
四选一选择器
★程序1：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY mux4 IS
PORT (i0,i1,i2,i3,a,b:IN STD_LOGIC; q:OUT STD_LOGIC); END ENTITY mux4;
ARCHITECTURE behav OF mux4 IS SIGNAL sel:INTEGER;
BEGIN
WITH sel SELECT
q<=i0 AFTER 10ns WHEN 0, i1 AFTER 10ns WHEN 1, i2 AFTER 10ns WHEN 2, i3 AFTER 10ns WHEN 3,
'X' AFTER 10ns WHEN OTHERS; sel<=0 WHEN a='0' AND b='0' ELSE 1 WHEN a='1' AND b='0' ELSE 2 WHEN a='0' AND b='1' ELSE
3 WHEN a='1' AND b='1' ELSE
4;
END ARCHITECTURE behav;
★程序2：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGEND.ALL; ENTITY mux4 IS
PORT (input:IN STD_LOGIC_VECTOR (3 DOWNTO 0);
sel:IN STD_LOGIC_VECTOR (1 DOWNTO 0); y:OUT STD_LOGIC); END ENTITY mux4;
ARCHITECTURE rtl OF mux4 IS
BEGIN
y<=input(0) WHEN sel="00" ELSE
input(1) WHEN sel="01" ELSE
input(2) WHEN sel="10" ELSE
input(3);
END ARCHITECTURE rtl;
★程序3：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; ENTITY mux4 IS
PORT(input: IN STD_LOGIC_VECTOR (3 DOWNTO 0); sel: IN STD_LOGIC_VECTOR (1 DOWNTO 0); y: OUT STD_LOGIC); END ENTITY mux4;
ARCHITECTURE rtl OF mux4 IS BEGIN
PROCESS(input, sel) IS BEGIN
IF(sel="00") THEN y<=input(0); ELSIF(sel="01") THEN y<=input(1); ELSIF(sel="10") THEN y<=input(2); ELSE y<=input(3);
END IF;
END PROCESS; END ARCHITECTURE rtl;
★程序4：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; ENTITY mux4 IS
PORT(a,b,i0,i1,i2,i3: IN STD_LOGIC;
q: OUT STD_LOGIC);
END ENTITY mux4;
ARCHITECTURE mux4_behave OF mux4 IS
SIGNAL sel: INTEGER RANGE 0 TO 3;
BEGIN
B: PROCESS(a,b,i0,i1,i2,i3) IS
BEGIN
sel<='0';
IF(a='1') THEN
sel<=sel+1;
IF(b='1') THEN
sel<=sel+2;
END IF;
CASE sel IS
WHEN 0=>q<=i0;
WHEN 1=>q<=i1;
WHEN 2=>q<=i2;
WHEN 3=>q<=i3;
END CASE;
END PROCESS;
END ARCHITECTURE mux4_behave;
★程序5：
ENTITY mux4 IS
PORT(i0,i1,i2,i3,a, b: IN STD_LOGIC;
q: OUT STD_LOGIC);
END ENTITY mux4;
ARCHITECTURE rtl OF mux4 IS
SIGNAL sel: STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
sel<=b & a;
q<=i0 WHEN sel="00" ELSE
i1 WHEN sel="01" ELSE
i2 WHEN sel="10" ELSE
i3 WHEN sel="11" ELSE
'X';
END ARCHITECTURE rtl;
三-八译码器
★程序1：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY decode_3to8 IS
PORT(a,b,c,G1,G2A,G2B: IN STD_LOGIC;
y: OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); END ENTITY decode_3to8;
ARCHITECTURE rtl OF decode_3to8 IS
SIGNAL indata: STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
indata<=c & b & a;
PROCESS(indata,G1,G2A,G2B) IS
BEGIN
IF(G1='1' AND G2A='0' AND G2B='0') THEN
CASE indata IS
WHEN "000"=>y<="11111110";
WHEN "010"=>y<="11111011";
WHEN "011"=>y<="11110111";
WHEN "100"=>y<="11101111";
WHEN "101"=>y<="11011111";
WHEN "110"=>y<="10111111";
WHEN "111"=>y<="01111111";
WHEN OTHERS=>y<="XXXXXXXX";
END CASE;
ELSE
y<="11111111";
END IF;
END PROCESS;
END ARCHITECTURE rtl;
具有优先级的编码器
★程序1：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY priorityencoder IS
PORT (input:IN STD_LOGIC_VECTOR (7 DOWNTO 0);
y:OUT STD_LOGIC_VECTOR (2 DOWNTO 0)); END ENTITY priorityencoder;
ARCHITECTURE rtl OF priorityencoder IS
BEGIN
PROCESS (input)IS
IF(input(0)='0') THEN
y<="111";
ELSIF(input(1)='0') THEN Array y<="110";
ELSIF(input(2)='0') THEN
y<="101";
ELSIF(input(3)='0') THEN
y<="100";
ELSIF(input(4)='0') THEN
y<="011";
ELSIF(input(5)='0') THEN
y<="010";
ELSIF(input(6)='0') THEN
y<="001";
y<="000";
END IF;
END PROCESS;
END ARCHITECTURE rtl;。