STM32L4液晶控制模块(LCD)介绍
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• The common has the maximum amplitude VLCD or VSS only in the corresponding phase of a frame cycle.
• During the other phases, the signal amplitude is 1/4 VLCD or 3/4 VLCD in case of 1/4 bias or 1/3 VLCD or 2/3 VLCD in case of 1/3 Bias and 1/2 VLCD in case of 1/2 Bias.
• Buffers prevent the LCD capacitive load from loading the resistor bridge unacceptably and interfering with its voltage generation
• The first frame generated is the odd one followed by an even one
• Five Duty ratios can be selected: Static Duty, 1/2 Duty, 1/3 Duty, 1/4 Duty or 1/8 Duty
=
fLCD
=
fLCDCLK 2PS(16+ DIV)
ck_div
• The frame frequency is obtained from the LCD frequency by dividing it by the number of active common terminals
fFrame = fLCD * duty
COM0
V LCD
2/3 V LCD
1/3 V LCD
V SS
Odd Frame
Even Frame
phase0 phase1 phase2 phase3 3 phase dead time
phase0 phase1 phase2 phase3
2- Method 2 when using the internal voltage: the software can adjust VLCD between 2.6 V to 3.3 V in 8 steps
V SS
Pixels[n] Pixels[n+44] Pixels[n+88] Pixels[n+132]Pixels[n]
Pixels[n+44] Pixels[n+88] Pixels[n+132]
RAM refresh
RAM refresh
LCD RAM
LCD RAM
Double Buffer Memory: LCD RAM AREA ALWAYS ACCESSIBLE
The frame frequency must be selected to be within a range of around ~30 Hz to ~100 Hz
Common/Segment driver(1/3) 81
• Every common signal has identical waveforms but different phases
• Integrated voltage output buffers for higher LCD driving capability.
Frequency generator 80
• The LCD Controller (LCDCLK) uses the same clock as RTCCLK. It can be: LSE, LSI, HSE divided by 32.
• LCD pins powered by either Step-up converter or external VLCD • Unused segments and common pins can be used as I/O
• Full support of Low power modes except Standby/Shutdown mode
• Programmable duty and bias
• Duty: Static, 1/2, 1/3, 1/4, 1/8 • Bias: Static, 1/2, 1/3, 1/4
Frame ~30 Hz to ~100 Hz
• Low Power Waveform to reduce consumption
STM32L4 LCD Glass controller (LCD)
Main features (1/2) 78
• High Flexibility Frame Rates
• Drive up to 320 (8x40) or 176(4x44) picture elements (pixels)
• The LCDCLK input clock must be in the range of 32 kHz to 1MHz.
• The LCDCLK divided by 2PS[3:0] : ck_ps PCLK1
LSE or LSI or HSE/32
16-bits Prescaler
LCD_FCR
• A resistive network is embedded to generate intermediate VLCD voltages
• The structure of the resistive network is configurable by software to adapt the power consumption to match the capacitive charge required by the LCD panel
Common/Segment driver(3/3)
X Digit 16 Segment
31
A
FH
IJ
Example of Writing the
character “A” on the B Liquid crystal display
first digit
…… 3 2 1 0
G
K
83
COM0 COM1 COM2
intermediate voltages
The RL and RH resistive networks are used to
increase the current during
transitions and to reduce
consumption in static state.
The nodes provide several intermediate voltage: One (Bias ½), two (Bias 1/3)or three (Bias ¼)
• Contrast Control whatever power supply voltage source
Main features (2/2) 79
• Blinking programmable pixels and frequency
• 1, 2, 3, 4, 8 or all pixels at programmable frequency • Software adjustable blink frequency to achieve around 0.5 Hz, 1 Hz, 2 Hz or 4 Hz.
SEGn COM3 COM2 COM1 COM0
V LCD
2/3 V LCD
1/3 V LCD
V SS
V LCD
2/3 V LCD
1/3 V LCD
V SS
V LCD
2/3 V LCD
1/3 V LCD
V SS
V LCD
2/3 V LCD
1/3 V LCD
V SS
V LCD
2/3 V LCD
1/3 V LCD
• Software selection between external and internal voltage source
• In case of an external source,the internal boost circuit is disabled to reduce power consumption
The LCD remains active in LP RUN, Sleep, LP sleep, STOP1 and STOP2 modes. The LCD is not active in STANDBY and SHUTDOWN mode
LCD voltage output buffers 86
Power Consumption
85
The LCD voltage levels can be generated : Internally using an internal booster or externally using VLCD voltage An internal resistor divider network which generates all VLCD
To deactivate pixels[n] connected to COM1, SEGn needs to be active during the phase 1 of an odd frame and inactive during the phase 1 of an even frame when COM1 is active
• Three modes can be selected: 1/2 Bias, 1/3 Bias or 1/4 Bias
Common/Segment driver(2/3)
82
Odd Frame
Even Frame
The segment terminals are multiplexed and each of them controls four pixels
A pixel is active if the corresponding segment line gets a maximum voltage opposite to the common
Common signals are phase inverted in order to reduce EMI
• Double buffer memory
• LCD data RAM of up to 16 x 32-bit registers which contain pixel information (active/inactive)
• Start of frame interrupt to synchronize the software when updating the LCD d0]
LCDCLK/65536
Clock MUX
• The ck_ps to be also divided by 16 to 31 to adjust the resolution rate: ck_div
DIV[3:0]
ck_ps
Divide by 16 to31
fck_div
1- Methode1 using external voltage: contrast can be controlled by programming a dead time (up to 8 phase periods) between each couple of frames where the COM and SEG value is tied to Vss in the same time.
To activate pixels[n] connected to COM0, SEGn needs to be inactive (VSS) during phase 0 of an odd frame and active (VLCD) during phase 0 of an even frame when COM0 is active
E L M NC
D
DP
SEG0
COM0 COM1 COM2 COM3
XF E D
SEG1
IJ KN
SEG2 SEG3
0x
AB HG
4D
C DP LM
70
LCD RAM
COM3
. . .
COM7
LCD Contrast Control
84
The contrast can be adjusted using two different methods:
• During the other phases, the signal amplitude is 1/4 VLCD or 3/4 VLCD in case of 1/4 bias or 1/3 VLCD or 2/3 VLCD in case of 1/3 Bias and 1/2 VLCD in case of 1/2 Bias.
• Buffers prevent the LCD capacitive load from loading the resistor bridge unacceptably and interfering with its voltage generation
• The first frame generated is the odd one followed by an even one
• Five Duty ratios can be selected: Static Duty, 1/2 Duty, 1/3 Duty, 1/4 Duty or 1/8 Duty
=
fLCD
=
fLCDCLK 2PS(16+ DIV)
ck_div
• The frame frequency is obtained from the LCD frequency by dividing it by the number of active common terminals
fFrame = fLCD * duty
COM0
V LCD
2/3 V LCD
1/3 V LCD
V SS
Odd Frame
Even Frame
phase0 phase1 phase2 phase3 3 phase dead time
phase0 phase1 phase2 phase3
2- Method 2 when using the internal voltage: the software can adjust VLCD between 2.6 V to 3.3 V in 8 steps
V SS
Pixels[n] Pixels[n+44] Pixels[n+88] Pixels[n+132]Pixels[n]
Pixels[n+44] Pixels[n+88] Pixels[n+132]
RAM refresh
RAM refresh
LCD RAM
LCD RAM
Double Buffer Memory: LCD RAM AREA ALWAYS ACCESSIBLE
The frame frequency must be selected to be within a range of around ~30 Hz to ~100 Hz
Common/Segment driver(1/3) 81
• Every common signal has identical waveforms but different phases
• Integrated voltage output buffers for higher LCD driving capability.
Frequency generator 80
• The LCD Controller (LCDCLK) uses the same clock as RTCCLK. It can be: LSE, LSI, HSE divided by 32.
• LCD pins powered by either Step-up converter or external VLCD • Unused segments and common pins can be used as I/O
• Full support of Low power modes except Standby/Shutdown mode
• Programmable duty and bias
• Duty: Static, 1/2, 1/3, 1/4, 1/8 • Bias: Static, 1/2, 1/3, 1/4
Frame ~30 Hz to ~100 Hz
• Low Power Waveform to reduce consumption
STM32L4 LCD Glass controller (LCD)
Main features (1/2) 78
• High Flexibility Frame Rates
• Drive up to 320 (8x40) or 176(4x44) picture elements (pixels)
• The LCDCLK input clock must be in the range of 32 kHz to 1MHz.
• The LCDCLK divided by 2PS[3:0] : ck_ps PCLK1
LSE or LSI or HSE/32
16-bits Prescaler
LCD_FCR
• A resistive network is embedded to generate intermediate VLCD voltages
• The structure of the resistive network is configurable by software to adapt the power consumption to match the capacitive charge required by the LCD panel
Common/Segment driver(3/3)
X Digit 16 Segment
31
A
FH
IJ
Example of Writing the
character “A” on the B Liquid crystal display
first digit
…… 3 2 1 0
G
K
83
COM0 COM1 COM2
intermediate voltages
The RL and RH resistive networks are used to
increase the current during
transitions and to reduce
consumption in static state.
The nodes provide several intermediate voltage: One (Bias ½), two (Bias 1/3)or three (Bias ¼)
• Contrast Control whatever power supply voltage source
Main features (2/2) 79
• Blinking programmable pixels and frequency
• 1, 2, 3, 4, 8 or all pixels at programmable frequency • Software adjustable blink frequency to achieve around 0.5 Hz, 1 Hz, 2 Hz or 4 Hz.
SEGn COM3 COM2 COM1 COM0
V LCD
2/3 V LCD
1/3 V LCD
V SS
V LCD
2/3 V LCD
1/3 V LCD
V SS
V LCD
2/3 V LCD
1/3 V LCD
V SS
V LCD
2/3 V LCD
1/3 V LCD
V SS
V LCD
2/3 V LCD
1/3 V LCD
• Software selection between external and internal voltage source
• In case of an external source,the internal boost circuit is disabled to reduce power consumption
The LCD remains active in LP RUN, Sleep, LP sleep, STOP1 and STOP2 modes. The LCD is not active in STANDBY and SHUTDOWN mode
LCD voltage output buffers 86
Power Consumption
85
The LCD voltage levels can be generated : Internally using an internal booster or externally using VLCD voltage An internal resistor divider network which generates all VLCD
To deactivate pixels[n] connected to COM1, SEGn needs to be active during the phase 1 of an odd frame and inactive during the phase 1 of an even frame when COM1 is active
• Three modes can be selected: 1/2 Bias, 1/3 Bias or 1/4 Bias
Common/Segment driver(2/3)
82
Odd Frame
Even Frame
The segment terminals are multiplexed and each of them controls four pixels
A pixel is active if the corresponding segment line gets a maximum voltage opposite to the common
Common signals are phase inverted in order to reduce EMI
• Double buffer memory
• LCD data RAM of up to 16 x 32-bit registers which contain pixel information (active/inactive)
• Start of frame interrupt to synchronize the software when updating the LCD d0]
LCDCLK/65536
Clock MUX
• The ck_ps to be also divided by 16 to 31 to adjust the resolution rate: ck_div
DIV[3:0]
ck_ps
Divide by 16 to31
fck_div
1- Methode1 using external voltage: contrast can be controlled by programming a dead time (up to 8 phase periods) between each couple of frames where the COM and SEG value is tied to Vss in the same time.
To activate pixels[n] connected to COM0, SEGn needs to be inactive (VSS) during phase 0 of an odd frame and active (VLCD) during phase 0 of an even frame when COM0 is active
E L M NC
D
DP
SEG0
COM0 COM1 COM2 COM3
XF E D
SEG1
IJ KN
SEG2 SEG3
0x
AB HG
4D
C DP LM
70
LCD RAM
COM3
. . .
COM7
LCD Contrast Control
84
The contrast can be adjusted using two different methods: