(内存基本知识)_DRAM工作原理

DRAM Single Bank Architecture
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•������ •������ •������ DRAM stands for Dynamic Random Access Memory. Random access refers to the ability to access any of the information within the DRAM in random order. Dynamic refers to temporary or transient data storage.
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DRAM Density
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What is a DRAM?
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Main memory
Main Memory Everything that happens in the computer is resident memory Capacity: around 100 Mbyte to 100 Gbyte Random access Typical access time is 10- 100 nanoseconds Why DRAM for Main Memory ?? ������ Cost effective (small chip area than SRAM) ������ High Speed(than HDD, flash) ������ High Density(~Gbyte) ������ Mass Production ……
Word Line
Capacitance Leakage
Bit Line DRAM Cell
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SRAM vs. DRAM
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������ Computer engineers have adopted K as the symbol for a factor of 1,024 (210 ) ������ K: 1,024 (210 ) ������ M: 1,048,576 (220 ) ������ G: 1,073,741,824 (230 ) ������ DRAM‘ density ������ 256M-bit ������ 512M-bit
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SRAM Element Enable Line
Bit Line
/Bit Line
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Dynamic RAM
• DRAM – Denser type of memory – Made up of one-transistor (1-T) memory cell which consists of a single access transistor and a capacitor – Cheaper than SRAM – Used in main memory – More complicated addressing scheme
DRAM Block Diagram(1)
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DRAM Block Diagram(2)
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DRAM Lead Frame and Wire bonding
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– Very small size – SRAM uses six transistors per cell
• Divided into banks, rows & columns
– Each bank can be independently controlled
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DRAM Architecture
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Multi Bank Architecture
– SDRAM has the multi bank architecture. – Conventional DRAM was product that have single bank architecture. – The bank is independent active. memory array have independent internal data bus that have same width as external data bus. – Every bank can be activating with interleaving manner. – Another bank can be activated while 1st bank being accessed. (Burst read or write)
Data stored in dynamic memories naturally decays over time. Therefore, DRAM need periodic refresh operation to prevent data loss.
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Word Line
Bit Line DRAM Cell
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Refresh in DRAMs
Capacitor leaks over time, the DRAM must be ―REFRESHED‖.
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DRAM Trend : Future ������ High Speed - DDR(333MHz~500MHz), DDR2(533~800Mbps), DDR3(800~1600Mbps) - Skew-delay minimized circuit/logic : post-charge logic, wave-pipelining - New Architecture : multi-bank structure, high speed Interface ������ Low Power - 5.5V => 3.3V(sdr) => 2.5V(ddr) => 1.8V(ddr2) => 1.5v (ddr3) => 1.2v? - Small voltage swing I/O interface : LVTTL to SSTL, open drain - Low Power DRAM(PASR, TCSR, DPD) ������ High Density - Memory density: 32MB => 64MB => ..... 1GB => 2GB => 4GB - application expansion : mobile, memory DB for shock (than HDD) - Process shrink :145nm(‗03) =>120nm(‗04) => 100nm => 90nm => 80nm… ������ Other Trends - Cost Effectiveness, Technical Compatibility, Stability, Environment. Reliability
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Memory: DRAM position ������ Semiconductor memory device ������ ROM: Non volatile ������ Mask ROM ������ EPROM ������ EEPROM ������ Flash ������ NAND: low speed, high density ������ NOR: high speed, low density ������ RAM: Volatile ������ DRAM: Dynamic Random Access Memory ������ SRAM: Static Random Access Memory ������ Pseudo SRAM
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Notation: K, M, G ������ In standard scientific nomenclature, the metric modifiers K, M, and G to refer to factors of 1,000, 1,000,000 and 1,000,000,000 respectively.
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Static RAM
• SRAM
– Basic storage element is a 4 or 6 transistor circuit which will hold a 1 or 0 as long as the system continues to receive power – No need for a periodic refreshing signal or a clock – Used in system cache – Fastest memory, but expensive
DRAM工作原理 DRAM工作原理
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DRAM
• Dynamic Random Access Memory • Each cell is a capacitor + a transistor
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DRAM Multi Bank Architecture
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