ispLever使用教程

library ieee; use ieee.std_logic_1164.all; entity decoder_38 is PORT(input:IN std_logic_vector(2 downto 0); output:OUT std_logic_vector(7 downto 0)); end;
ISPLEVER 软件的使用方法
1、VHDL的文本方式设计
百度文库
点击程序－>Lattice Semiconductor—> ispLEVER Project Navigator
点击File —>New Project
输入项目名，选VHDL，点下一步
选器件
点击下一步
点击完成
点击Source —New
architecture rtl1 of and_gate is begin X<=A AND B; end rtl1;
library ieee; use ieee.std_logic_1164.all;
entity decoder is PORT(input:IN std_logic_vector(2 downto 0); output:OUT std_logic_vector(7 downto 0)); end;
点击器件ispLSI1032E-70LJ84
双击Fit Design
下载
（八）ISPLEVER 软件的使用方法
2、VHDL的原理图方式设计
点击File —>New Project
选器件
点击下一步
点击完成
点击Source —New
后面的操作同前
作业：用VHDL语言： 1、设计一个3线－8线译码器； 2、设计一个上升沿触发JK触发器。
architecture rtl1 of decoder is begin process(input) case input is when 0=>output<="11111110"; when 1=>output<="11111101"; when 2=>output<="11111011"; when 3=>output<="11110111"; when 4=>output<="11101111"; when 5=>output<="11011111"; when 6=>output<="10111111"; when 7=>output<="01111111"; end case; end process; end rtl1;
选VHDL Module
填入文件名、实体名（两者要一致）和 结构体名
点 OK
输入程序
保存
退出
点击dff1(dff1.vhd)
源程序编写完成以后是综合 双击Synplify Synthesize VHDL File
双击VHDL Test Bench Template
双击Generate Schematic Symbol
library ieee; use ieee.std_logic_1164.all; entity decoder is PORT(input:IN std_logic_vector(2 downto 0); yout:OUT std_logic_vector(7 downto 0)); end; architecture rtl1 of decoder is begin process(input) case input is when "000"=>yout<="11111110"; when "001"=>yout<="11111101"; when "010"=>yout<="11111011"; when "011"=>yout<="11110111"; when "100"=>yout<="11101111"; when "101"=>yout<="11011111"; when "110"=>yout<="10111111"; when "111"=>yout<="01111111"; end case; end process; end rtl1;
library ieee; use ieee.std_logic_1164.all;
entity ym3_8 is port(a:in std_logic_vector(2 downto 0); y:out std_logic_vector(7 downto 0)); end ym3_8; architecture rtl of ym3_8 is begin process(a) case a is when "000"=>y<="11111110"; when "001"=>y<="11111101"; when "010"=>y<="11111011"; when "011"=>y<="11110111"; when "100"=>y<="11101111"; when "101"=>y<="11011111"; when "110"=>y<="10111111"; when others=>y<="01111111"; end case; end process; end rtl;
CLR
J Q
CLK
K
library ieee; use ieee.std_logic_1164.all;
entity dff1 is port(clk,d:in std_logic; q:out std_logic); end;
architecture rtl of dff1 is begin process(clk) begin if(clk'event and clk='1')then q<=d; end if; end process; end rtl;
library ieee; use ieee.std_logic_1164.all; entity and_gate is PORT(A,B:IN std_logic;X:OUT std_logic); end; architecture rtl of and_gate is begin X<=A AND B; end rtl;