CCpciexpress_board_design_guidelines

FR4 cross-section
11
Trace length
Longer trace length loss ↑ 0.25 to 0.35 dB inherent loss per inch for FR4 microstrip traces Limit motherboard trace to < 12 inches and add-in card trace to < 3 inches
UI = Unit Interval 400ps
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PCI-SIG Developers Conference
AGP8X Layout Challenges
Data and Strobe must be length matched
AGP Connector
PCI-SIG Developers Conference
Strobe
Data
5
Copyright 2003, PCI-SIG, All Rights Reserved
PCI Express makes layout easy
Trace length matching between pairs is not required
Loss and Jitter are key parameters Impedance is not as critical Maintain differential pair symmetry Design tradeoffs for PCB: component loss vs. trace length Manage loss and symmetry to meet budget Manage loss and symmetry to meet budget
12”+ possible
AC Coupling Caps No trace serpentines x16 PCI Express Connector
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ε r = 4.1, +/- 0.3
62.4 mils
ε r = 4.1, +/- 0.3
1.4 mils 4.4 mils 1.9 mils 1.2 mils
Follow simple layout rules & design tradeoffs Follow simple layout rules & design tradeoffs
Copyright 2003, PCI-SIG, All Rights Reserved
1
Agenda
Background Layout considerations Simulations Validations Summary
PCI-SIG Developers Conference
Copyright 2003, PCI-SIG, All Rights Reserved
Receiver & package
TX
Transmitter & package
800 mV
TX Spec Eye 0.7 UI
Interconnect Loss < 13.2 dB Jitter < 0.3 UI
RX Spec 175 mV 0.4 UI
AC coupled Lane-to-lane de-skew Polarity inversion On-chip equalization On-chip terminations
Tx 5 7 5 Tx
h
20 mil
Microstrip
Non-interleaved Topology example Tx 5 5 5 Rx Stripline
20 mil
h
Interleaved Topology example
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Serpentine routing is needed for length matching
Short Motherboard Trace Lengths
2”–6” max MCH to connector
Tight Timing Budget
Data-to-strobe timing skew
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CONN
2
T 5+G .
/sMCH
Serial differential
Baseboard RX
AC caps D+ D-
Add-in card PCI Express Connector TX RX RX
Nominal 4-layer PCB Stackup
Soldermask L1 Signal Pre-preg L2 VCC Core L3 VSS Pre-preg L4 Signal Soldermask Trace Trace Spacing Width 1.2 mils 1.9 mils 4.4 mils 1.4 mils 47 mils
/s MT MCH 533
CONN
PCI Express serial differential
Point-to-point, match per data pair only Longer route, creative device placement
Point-to-point routing is straightforward Point-to-point routing is straightforward
Trace Symmetry & Matching
Match each differential pair per segment
Match overall length ≤ 5 mils Symmetric routing for each pair
Preferred matching Match near mismatch ≤ 45 mils Alternative matching
Localized Zo variation due to material weave loss ↑
Wide differential Impedance variation on strip
Etching and Plating process loss ↑
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2
Bus Topologies
PCI common clock
Meet setup/hold timing Multi-drop parallel I/O
CONN CONN
M 133 T/s
MCH
CLK
AGP source synchronous
Match all data to strobe Single strobe, multiple data
Board Design Guidelines for PCI Express Architecture
Cliff Lee Staff Engineer Intel Corporation Member, PCI Express Electrical and Card WGs
The facts, techniques and applications presented by the following person and company are solely those of the presenter and not in any way endorsed, certified, or necessarily the opinion of PCI-SIG or its members.
Copyright 2003, PCI-SIG, All Rights Reserved
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Stackup design
No new PCB technology required Standard 4-layer stackup 0.062” thick PCB Microstrip oz Cu plated Ok Stripline 1 oz Cu (6+ layers) Better
Embedded clock simplifies routing rules
GND reference preferred
Avoid splits and voids
Use GND stitching vias when changing layers Longer motherboard trace
PCB material dominates loss
Stackup FR4 material
Copper roughness loss ↑ Thinner dielectrics loss ↑
Glass Material Resin Material
Non-homogeneous dielectric
6
Interconnect budget
Interconnect Baseboard (connector and/or riser card) Add-in card Near-end crosstalk Impedance mismatch Total Loss 6.6 dB 1.4 dB 2.7 dB 2.5 dB 13.2 dB Jitter 0.19 UI 0.035 UI 0.075 UI 0.3 UI
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Agenda
Background Layout considerations Simulations Validations Summary
PCI-SIG Developers Conference
Reference plane
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Trace Geometry & Impedance
Use wider trace width Minimize loss Use wider traces for long routes More pair-to-pair spacing Minimize crosstalk Target differential Zo of 100 ±20%
1.25GHz freq
-5.百度文库3dB
20-inch line
dB
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VNA measurements for trace insertion loss
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PCI-SIG Developers Conference
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13
Pin field breakout
Use side-by-side breakout for package to maintain symmetry Avoid tight bends
Side-by-side Best Adjacent w/ small serpentine Ok Adjacent w/ bend Fair Diagonal routing Fair
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