计算机设计与实践——32位ALU设计
合集下载
相关主题
- 1、下载文档前请自行甄别文档内容的完整性，平台不提供额外的编辑、内容补充、找答案等附加服务。
- 2、"仅部分预览"的文档,不可在线预览部分如存在完整性等问题,可反馈申请退款(可完整预览的文档不适用该条件!)。
- 3、如文档侵犯您的权益，请联系客服反馈,我们会尽快为您处理(人工客服工作时间：9:00-18:30)。
assign alu_db_n=~alu_db;//加减运算 always@(*) begin
if(Sub==1) alu_db_mux=alu_db_n; else alu_db_mux=alu_db;
end alu_32 alu_32_1(alu_add,alu_da,alu_db_mux,Sub,c2); assign overflow=alu_da[31]&alu_db_mux[31]&~alu_add[31]|~alu_da[31]&~alu_db_mux[31]&alu_add[31]; assign
32位ALU设计
——Verilog HDL语言
module alu(alu_da,alu_db,alu_clt,alu_shift,alu_zero_out,overflow_out,alu_dc );
input [31:0]alu_da; input [31:0]alu_db; input [3:0]alu_clt; input [4:0]alu_shift; output reg alu_zero_out; output reg overflow_out; output reg [31:0]alu_dc; wire alu_zero; wire overflow; wire [31:0]alu_and;//与结果 wire [31:0]alu_or;//或结果 wire [31:0]alu_xor;//异或结果 reg [31:0]alu_sll;//左移结果 reg [31:0]alu_srl;//右移结果 reg [31:0]alu_sra;//算数右移 wire [31:0]alu_add;//加减运算结果 wire c2;//加法器进位输出 reg Sub;//加法器控制端 wire [31:0]alu_db_n;//b取非运算 reg [31:0]alu_db_mux;//b的加减选择运算 wire ci;//进位输出
//无符号加运算 //无符号减运算 //有符号加运算 //有符号减运算
Fra Baidu bibliotek
overflow_out=overflow; end 10: begin Sub=1; if(c2==0) alu_dc=1; else alu_dc=0; end 11: begin Sub=1; if(alu_add[31]==1) alu_dc=1; else alu_dc=0; end default:alu_dc=alu_dc; endcase end
30:alu_sll<=alu_da<<30; 31:alu_sll<=alu_da<<31; default:alu_sll<=alu_da; endcase end
always@(*) begin
case(alu_shift) 0:alu_srl<=alu_da; 1:alu_srl<=alu_da>>1; 2:alu_srl<=alu_da>>2; 3:alu_srl<=alu_da>>3; 4:alu_srl<=alu_da>>4; 5:alu_srl<=alu_da>>5; 6:alu_srl<=alu_da>>6; 7:alu_srl<=alu_da>>7; 8:alu_srl<=alu_da>>8; 9:alu_srl<=alu_da>>9; 10:alu_srl<=alu_da>>10; 11:alu_srl<=alu_da>>11; 12:alu_srl<=alu_da>>12; 13:alu_srl<=alu_da>>13; 14:alu_srl<=alu_da>>14; 15:alu_srl<=alu_da>>15; 16:alu_srl<=alu_da>>16; 17:alu_srl<=alu_da>>17; 18:alu_srl<=alu_da>>18; 19:alu_srl<=alu_da>>19; 20:alu_srl<=alu_da>>20;
13:alu_sra<={{13{alu_da[31]}},alu_da[31:13]}; 14:alu_sra<={{14{alu_da[31]}},alu_da[31:14]}; 15:alu_sra<={{15{alu_da[31]}},alu_da[31:15]}; 16:alu_sra<={{16{alu_da[31]}},alu_da[31:16]}; 17:alu_sra<={{17{alu_da[31]}},alu_da[31:17]}; 18:alu_sra<={{18{alu_da[31]}},alu_da[31:18]}; 19:alu_sra<={{19{alu_da[31]}},alu_da[31:19]}; 20:alu_sra<={{20{alu_da[31]}},alu_da[31:20]}; 21:alu_sra<={{21{alu_da[31]}},alu_da[31:21]}; 22:alu_sra<={{22{alu_da[31]}},alu_da[31:22]}; 23:alu_sra<={{23{alu_da[31]}},alu_da[31:23]}; 24:alu_sra<={{24{alu_da[31]}},alu_da[31:24]}; 25:alu_sra<={{25{alu_da[31]}},alu_da[31:25]}; 26:alu_sra<={{26{alu_da[31]}},alu_da[31:26]}; 27:alu_sra<={{27{alu_da[31]}},alu_da[31:27]}; 28:alu_sra<={{28{alu_da[31]}},alu_da[31:28]}; 29:alu_sra<={{29{alu_da[31]}},alu_da[31:29]}; 30:alu_sra<={{30{alu_da[31]}},alu_da[31:30]}; 31:alu_sra<={{31{alu_da[31]}},alu_da[31]}; default:alu_sra<=alu_da; endcase end
alu_zero=~(alu_add[0]|alu_add[1]|alu_add[2]|alu_add[3]|alu_add[4]|alu_add[5]|alu_add[6]|alu_add[7]|alu_add[8]|alu_add[9]|alu_ add[10]|alu_add[11]|alu_add[12]|alu_add[13]|alu_add[14]|alu_add[15]|alu_add[16]|alu_add[17]|alu_add[18]|alu_add[19]|alu_add [20]|alu_add[21]|alu_add[22]|alu_add[23]|alu_add[24]|alu_add[25]|alu_add[26]|alu_add[27]|alu_add[28]|alu_add[29]|alu_add[30] |alu_add[31]);
assign alu_and=alu_da&alu_db; assign alu_or=alu_da|alu_db; assign alu_xor=alu_da^alu_db;
always@(*) begin
case(alu_shift)
//无符号小于置1运算 //有符号小于置1运算
0:alu_sll<=alu_da; 1:alu_sll<=alu_da<<1; 2:alu_sll<=alu_da<<2; 3:alu_sll<=alu_da<<3; 4:alu_sll<=alu_da<<4; 5:alu_sll<=alu_da<<5; 6:alu_sll<=alu_da<<6; 7:alu_sll<=alu_da<<7; 8:alu_sll<=alu_da<<8; 9:alu_sll<=alu_da<<9; 10:alu_sll<=alu_da<<10; 11:alu_sll<=alu_da<<11; 12:alu_sll<=alu_da<<12; 13:alu_sll<=alu_da<<13; 14:alu_sll<=alu_da<<14; 15:alu_sll<=alu_da<<15; 16:alu_sll<=alu_da<<16; 17:alu_sll<=alu_da<<17; 18:alu_sll<=alu_da<<18; 19:alu_sll<=alu_da<<19; 20:alu_sll<=alu_da<<20; 21:alu_sll<=alu_da<<21; 22:alu_sll<=alu_da<<22; 23:alu_sll<=alu_da<<23; 24:alu_sll<=alu_da<<24; 25:alu_sll<=alu_da<<25; 26:alu_sll<=alu_da<<26; 27:alu_sll<=alu_da<<27; 28:alu_sll<=alu_da<<28; 29:alu_sll<=alu_da<<29;
always@(*) begin
case(alu_clt) 0:alu_dc=alu_and;//逻辑与运算 1:alu_dc=alu_or;//逻辑或运算
2:alu_dc=alu_xor;//逻辑异或运算 3:alu_dc=alu_sll;//左移运算 4:alu_dc=alu_srl;//右移运算 5:alu_dc=alu_sra;//算数右移运算 6: begin Sub=0; alu_dc=alu_add; alu_zero_out=0; overflow_out=0; end 7: begin Sub=1; alu_dc=alu_add; alu_zero_out=0; overflow_out=0; end 8: begin Sub=0; alu_dc=alu_add; alu_zero_out=alu_zero; overflow_out=overflow; end 9: begin Sub=1; alu_dc=alu_add; alu_zero_out=alu_zero;
21:alu_srl<=alu_da>>21; 22:alu_srl<=alu_da>>22; 23:alu_srl<=alu_da>>23; 24:alu_srl<=alu_da>>24; 25:alu_srl<=alu_da>>25; 26:alu_srl<=alu_da>>26; 27:alu_srl<=alu_da>>27; 28:alu_srl<=alu_da>>28; 29:alu_srl<=alu_da>>29; 30:alu_srl<=alu_da>>30; 31:alu_srl<=alu_da>>31; default:alu_srl<=alu_da; endcase end always@(*) begin case(alu_shift) 0:alu_sra<=alu_da; 1:alu_sra<={{alu_da[31]},alu_da[31:1]}; 2:alu_sra<={{2{alu_da[31]}},alu_da[31:2]}; 3:alu_sra<={{3{alu_da[31]}},alu_da[31:3]}; 4:alu_sra<={{4{alu_da[31]}},alu_da[31:4]}; 5:alu_sra<={{5{alu_da[31]}},alu_da[31:5]}; 6:alu_sra<={{6{alu_da[31]}},alu_da[31:6]}; 7:alu_sra<={{7{alu_da[31]}},alu_da[31:7]}; 8:alu_sra<={{8{alu_da[31]}},alu_da[31:8]}; 9:alu_sra<={{9{alu_da[31]}},alu_da[31:9]}; 10:alu_sra<={{10{alu_da[31]}},alu_da[31:10]}; 11:alu_sra<={{11{alu_da[31]}},alu_da[31:11]}; 12:alu_sra<={{12{alu_da[31]}},alu_da[31:12]};
if(Sub==1) alu_db_mux=alu_db_n; else alu_db_mux=alu_db;
end alu_32 alu_32_1(alu_add,alu_da,alu_db_mux,Sub,c2); assign overflow=alu_da[31]&alu_db_mux[31]&~alu_add[31]|~alu_da[31]&~alu_db_mux[31]&alu_add[31]; assign
32位ALU设计
——Verilog HDL语言
module alu(alu_da,alu_db,alu_clt,alu_shift,alu_zero_out,overflow_out,alu_dc );
input [31:0]alu_da; input [31:0]alu_db; input [3:0]alu_clt; input [4:0]alu_shift; output reg alu_zero_out; output reg overflow_out; output reg [31:0]alu_dc; wire alu_zero; wire overflow; wire [31:0]alu_and;//与结果 wire [31:0]alu_or;//或结果 wire [31:0]alu_xor;//异或结果 reg [31:0]alu_sll;//左移结果 reg [31:0]alu_srl;//右移结果 reg [31:0]alu_sra;//算数右移 wire [31:0]alu_add;//加减运算结果 wire c2;//加法器进位输出 reg Sub;//加法器控制端 wire [31:0]alu_db_n;//b取非运算 reg [31:0]alu_db_mux;//b的加减选择运算 wire ci;//进位输出
//无符号加运算 //无符号减运算 //有符号加运算 //有符号减运算
Fra Baidu bibliotek
overflow_out=overflow; end 10: begin Sub=1; if(c2==0) alu_dc=1; else alu_dc=0; end 11: begin Sub=1; if(alu_add[31]==1) alu_dc=1; else alu_dc=0; end default:alu_dc=alu_dc; endcase end
30:alu_sll<=alu_da<<30; 31:alu_sll<=alu_da<<31; default:alu_sll<=alu_da; endcase end
always@(*) begin
case(alu_shift) 0:alu_srl<=alu_da; 1:alu_srl<=alu_da>>1; 2:alu_srl<=alu_da>>2; 3:alu_srl<=alu_da>>3; 4:alu_srl<=alu_da>>4; 5:alu_srl<=alu_da>>5; 6:alu_srl<=alu_da>>6; 7:alu_srl<=alu_da>>7; 8:alu_srl<=alu_da>>8; 9:alu_srl<=alu_da>>9; 10:alu_srl<=alu_da>>10; 11:alu_srl<=alu_da>>11; 12:alu_srl<=alu_da>>12; 13:alu_srl<=alu_da>>13; 14:alu_srl<=alu_da>>14; 15:alu_srl<=alu_da>>15; 16:alu_srl<=alu_da>>16; 17:alu_srl<=alu_da>>17; 18:alu_srl<=alu_da>>18; 19:alu_srl<=alu_da>>19; 20:alu_srl<=alu_da>>20;
13:alu_sra<={{13{alu_da[31]}},alu_da[31:13]}; 14:alu_sra<={{14{alu_da[31]}},alu_da[31:14]}; 15:alu_sra<={{15{alu_da[31]}},alu_da[31:15]}; 16:alu_sra<={{16{alu_da[31]}},alu_da[31:16]}; 17:alu_sra<={{17{alu_da[31]}},alu_da[31:17]}; 18:alu_sra<={{18{alu_da[31]}},alu_da[31:18]}; 19:alu_sra<={{19{alu_da[31]}},alu_da[31:19]}; 20:alu_sra<={{20{alu_da[31]}},alu_da[31:20]}; 21:alu_sra<={{21{alu_da[31]}},alu_da[31:21]}; 22:alu_sra<={{22{alu_da[31]}},alu_da[31:22]}; 23:alu_sra<={{23{alu_da[31]}},alu_da[31:23]}; 24:alu_sra<={{24{alu_da[31]}},alu_da[31:24]}; 25:alu_sra<={{25{alu_da[31]}},alu_da[31:25]}; 26:alu_sra<={{26{alu_da[31]}},alu_da[31:26]}; 27:alu_sra<={{27{alu_da[31]}},alu_da[31:27]}; 28:alu_sra<={{28{alu_da[31]}},alu_da[31:28]}; 29:alu_sra<={{29{alu_da[31]}},alu_da[31:29]}; 30:alu_sra<={{30{alu_da[31]}},alu_da[31:30]}; 31:alu_sra<={{31{alu_da[31]}},alu_da[31]}; default:alu_sra<=alu_da; endcase end
alu_zero=~(alu_add[0]|alu_add[1]|alu_add[2]|alu_add[3]|alu_add[4]|alu_add[5]|alu_add[6]|alu_add[7]|alu_add[8]|alu_add[9]|alu_ add[10]|alu_add[11]|alu_add[12]|alu_add[13]|alu_add[14]|alu_add[15]|alu_add[16]|alu_add[17]|alu_add[18]|alu_add[19]|alu_add [20]|alu_add[21]|alu_add[22]|alu_add[23]|alu_add[24]|alu_add[25]|alu_add[26]|alu_add[27]|alu_add[28]|alu_add[29]|alu_add[30] |alu_add[31]);
assign alu_and=alu_da&alu_db; assign alu_or=alu_da|alu_db; assign alu_xor=alu_da^alu_db;
always@(*) begin
case(alu_shift)
//无符号小于置1运算 //有符号小于置1运算
0:alu_sll<=alu_da; 1:alu_sll<=alu_da<<1; 2:alu_sll<=alu_da<<2; 3:alu_sll<=alu_da<<3; 4:alu_sll<=alu_da<<4; 5:alu_sll<=alu_da<<5; 6:alu_sll<=alu_da<<6; 7:alu_sll<=alu_da<<7; 8:alu_sll<=alu_da<<8; 9:alu_sll<=alu_da<<9; 10:alu_sll<=alu_da<<10; 11:alu_sll<=alu_da<<11; 12:alu_sll<=alu_da<<12; 13:alu_sll<=alu_da<<13; 14:alu_sll<=alu_da<<14; 15:alu_sll<=alu_da<<15; 16:alu_sll<=alu_da<<16; 17:alu_sll<=alu_da<<17; 18:alu_sll<=alu_da<<18; 19:alu_sll<=alu_da<<19; 20:alu_sll<=alu_da<<20; 21:alu_sll<=alu_da<<21; 22:alu_sll<=alu_da<<22; 23:alu_sll<=alu_da<<23; 24:alu_sll<=alu_da<<24; 25:alu_sll<=alu_da<<25; 26:alu_sll<=alu_da<<26; 27:alu_sll<=alu_da<<27; 28:alu_sll<=alu_da<<28; 29:alu_sll<=alu_da<<29;
always@(*) begin
case(alu_clt) 0:alu_dc=alu_and;//逻辑与运算 1:alu_dc=alu_or;//逻辑或运算
2:alu_dc=alu_xor;//逻辑异或运算 3:alu_dc=alu_sll;//左移运算 4:alu_dc=alu_srl;//右移运算 5:alu_dc=alu_sra;//算数右移运算 6: begin Sub=0; alu_dc=alu_add; alu_zero_out=0; overflow_out=0; end 7: begin Sub=1; alu_dc=alu_add; alu_zero_out=0; overflow_out=0; end 8: begin Sub=0; alu_dc=alu_add; alu_zero_out=alu_zero; overflow_out=overflow; end 9: begin Sub=1; alu_dc=alu_add; alu_zero_out=alu_zero;
21:alu_srl<=alu_da>>21; 22:alu_srl<=alu_da>>22; 23:alu_srl<=alu_da>>23; 24:alu_srl<=alu_da>>24; 25:alu_srl<=alu_da>>25; 26:alu_srl<=alu_da>>26; 27:alu_srl<=alu_da>>27; 28:alu_srl<=alu_da>>28; 29:alu_srl<=alu_da>>29; 30:alu_srl<=alu_da>>30; 31:alu_srl<=alu_da>>31; default:alu_srl<=alu_da; endcase end always@(*) begin case(alu_shift) 0:alu_sra<=alu_da; 1:alu_sra<={{alu_da[31]},alu_da[31:1]}; 2:alu_sra<={{2{alu_da[31]}},alu_da[31:2]}; 3:alu_sra<={{3{alu_da[31]}},alu_da[31:3]}; 4:alu_sra<={{4{alu_da[31]}},alu_da[31:4]}; 5:alu_sra<={{5{alu_da[31]}},alu_da[31:5]}; 6:alu_sra<={{6{alu_da[31]}},alu_da[31:6]}; 7:alu_sra<={{7{alu_da[31]}},alu_da[31:7]}; 8:alu_sra<={{8{alu_da[31]}},alu_da[31:8]}; 9:alu_sra<={{9{alu_da[31]}},alu_da[31:9]}; 10:alu_sra<={{10{alu_da[31]}},alu_da[31:10]}; 11:alu_sra<={{11{alu_da[31]}},alu_da[31:11]}; 12:alu_sra<={{12{alu_da[31]}},alu_da[31:12]};