KM432S2030B中文资料

Preliminary CMOS SDRAM
Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM. Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disables input buffers for power down mode. Row/column addresses are multiplexed on the same pins. Row address : RA 0 ~ RA 10, Column address : CA 0 ~ CA 7 Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. Enables write operation and row precharge. Latches data in starting from CAS, WE active. Makes data output Hi-Z, t SHZ after the clock and masks the output. Blocks data input when DQM active. Data inputs/outputs are multiplexed on the same pins. Power and ground for the input buffers and the core logic. Isolated power supply and ground for the output buffers to provide improved noise immunity. This pin is recommended to be left No Connection on the device.
Preliminary CMOS SDRAM
86Pin TSOP (II) (400mil x 875mil) (0.5 mm Pin pitch)
REV. 4 July 1998
元器件交易网
KM432S2030B
PIN FUNCTION DESCRIPTION
Pin CLK CS Name System clock Chip select Input Function Active on the positive going edge to sample all inputs.
FUNCTIONAL BLOCK DIAGRAM
I/O Control
LWE
Data Input Regielect 512K x 32 Sense AMP 512K x 32 512K x 32 512K x 32 Refresh Counter
Output Buffer
Preliminary CMOS SDRAM
GENERAL DESCRIPTION
The KM432S2030B is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 524,288 words by 32 bits, fabricated with SAMSUNG ′s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.
• • • • •
ORDERING INFORMATION
Part No. KM432S2030BT-G/F8 KM432S2030BT-G/FL KM432S2030BT-G/F10 Max Freq. 125MHz 100MHz 100MHz LVTTL Interface Package 86 TSOP (II)
Note : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
ABSOLUTE MAXIMUM RATINGS
Parameter Voltage on any pin relative to Vss Voltage on V DD supply relative to Vss Storage temperature Power dissipation Short circuit current Symbol VIN, VOUT VDD, VDDQ TSTG PD IOS Value -1.0 ~ 4.6 -1.0 ~ 4.6 -55 ~ +150 1 50 Unit V V °C W mA
Preliminary CMOS SDRAM
REV. 4 July 1998
元器件交易网
KM432S2030B
512K x 32Bit x 4 Banks Synchronous DRAM
FEATURES
• • • • JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave) All inputs are sampled at the positive going edge of the system clock Burst read single-bit write operation DQM for masking Auto & self refresh 64ms refresh period (4K cycle)
Timing Register
CLK
CKE
CS
RAS
CAS
WE
DQM * Samsung Electronics reserves the right to change products or specification without notice.
REV. 4 July 1998
元器件交易网
元器件交易网
KM432S2030B
Revision History Revision .2 (May 1998) -. Pin #70 MCH is changed to N.C. Revision .3 (June 1998) - ICC3N & ICC3NS is updated. - The Desciption of MCH on the "Pin Function Description" is deleted and that of NC is added. - Address pin description is changed. (A0 ~ A11 to A0 ~ A10) Revision .4 (July 1998) -.DQ Buffer and IBIS characteristics are eliminated.
Row Decoder
Row Buffer
DQi
Address Register
CLK ADD
Column Decoder Col. Buffer Latency & Burst Length
LRAS
LCBR
LCKE LRAS LCBR LWE LCAS
Programming Register LWCBR LDQM
CKE
Clock enable
A0 ~ A10 BA0,1 RAS CAS WE DQM0 ~ 3 DQ0 ~ 31 VDD/VSS VDDQ /VSSQ NC
Address Bank select address Row address strobe Column address strobe Write enable Data input/output mask Data input/output Power supply/ground Data output power/ground No Connection