可编程ASIC技术

可编程ASIC技术组合电路模块一、采用不同的描述方式设计本章中的组合电路模块，并综合。

1. 基本组合电路①门级结构描述module gate_1(F,A,B,C,D);input A,B,C,D;output F;nand(F1,A,B);and(F2,B,C,D);or(F,F1,F2);endmodule综合后RTL视图：②数据流描述module gate_1(F,A,B,C,D);input A,B,C,D;output F;assign F = (~(A&B))|(B&C&D);endmodule综合后RTL视图：③行为描述module gate_1(F,A,B,C,D);input A,B,C,D;output F;reg F;always @(A or B or C or D)beginF=(~(A&B))|(B&C&D);endendmodule综合后RTL视图：2. 三态门描述①门级结构描述module tri_1(in,en,out);input in,en;output out;tri out;bufif1 b1(out,in,en);endmodule综合后RTL视图：②数据流描述module tri_1(in,en,out);input in,en;output out;assign out = en?in:1'bZ;endmodule综合后RTL视图：③行为描述module tri_1(in,en,out);input in,en;output out;reg out;always @(in,en)beginif(en)out = in;elseout = 1'bZ;endendmodule综合后RTL视图：3. 3-8译码器①门级描述module decoder_38(out,in);output[7:0] out;input[2:0] in;// 3 to 8 decoderor(out[0],in[2],in[1],in[0]);or(out[1],in[2],in[1],~in[0]);or(out[2],in[2],~in[1],in[0]);or(out[3],in[2],~in[1],~in[0]);or(out[4],~in[2],in[1],in[0]);or(out[5],~in[2],in[1],~in[0]);or(out[6],~in[2],~in[1],in[0]);or(out[7],~in[2],~in[1],~(in[0]));endmodule综合后RTL视图：②数据流描述module decoder_38(out,in);output[7:0] out;input[2:0] in;wire[7:0] out;assign out[0]=in[2]|in[1]|in[0];assign out[1]=in[2]|in[1]|(~in[0]);assign out[2]=in[2]|(~in[1])|in[0];assign out[3]=in[2]|(~in[1])|(~in[0]);assign out[4]=(~in[2])|in[1]|in[0];assign out[5]=(~in[2])|in[1]|(~in[0]);assign out[6]=(~in[2])|(~in[1])|in[0];assign out[7]=(~in[2])|(~in[1])|(~in[1]);endmodule综合后RTL视图：③行为描述module decoder_38(out,in);output[7:0] out;input[2:0] in;reg[7:0] out;always @(in)begincase(in)3'd0: out=8'b11111110;3'd1: out=8'b11111101;3'd2: out=8'b11111011;3'd3: out=8'b11110111;3'd4: out=8'b11101111;3'd5: out=8'b11011111;3'd6: out=8'b10111111;3'd7: out=8'b01111111;endcaseendendmodule综合后RTL视图：4. 奇偶校验位产生器①门级描述module parity(even_bit,odd_bit,input_bus);output even_bit,odd_bit;input[7:0] input_bus;xor XR1(r1,input_bus[1],input_bus[0]);xor XR2(r2,input_bus[3],input_bus[2]);xor XR3(r3,input_bus[5],input_bus[4]);xor XR4(r4,input_bus[7],input_bus[6]);xor XR5(r5,r2,r1);xor XR6(r6,r4,r3);xor XR7(r7,r6,r5);not N1(odd_bit,r7);not N2(even_bit,odd_bit);endmodule综合后RTL视图：②数据流描述module parity(even_bit,odd_bit,input_bus);output even_bit,odd_bit;input[7:0] input_bus;assign odd_bit = ~(^input_bus);assign even_bit = ~odd_bit;endmodule综合后RTL视图：③行为描述module parity(even_bit,odd_bit,input_bus);output even_bit,odd_bit;input[7:0] input_bus;reg odd_bit,even_bit;always @(input_bus)beginodd_bit = ~(^input_bus);endalways @(input_bus)begineven_bit = ~odd_bit;endendmodule综合后RTL视图：5. 4选1 MUX①门级结构描述module mux4_1(out,in0,in1,in2,in3,sel);output out;input in0,in1,in2,in3;input[1:0] sel;not (sel1_n,sel[1]);not (sel0_n,sel[0]);and (g1,sel1_n,sel0_n);and (out0,g1,in0); //in0and (g2,sel1_n,sel[0]);and (out1,g2,in1); //in1and (g3,sel[1],sel0_n);and (out2,g3,in2); //in2and (g4,sel[1],sel[0]);and (out3,g4,in3); //in3or (res1,out2,out1);or (res2,out4,out3);or (out,res2,res1); //outendmodule综合后RTL视图：②数据流描述module mux4_1(out,in0,in1,in2,in3,sel);output out;input in0,in1,in2,in3;input[1:0] sel;assign out = (~sel[1]&~sel[0]&in0)|(~sel[1]&sel[0]&in1)|(sel[1]&~sel[0]&in2)|(sel[1]&sel[0]&in3);endmodule综合后RTL视图：③行为描述module mux4_1(out,in0,in1,in2,in3,sel);output out;input in0,in1,in2,in3;input[1:0] sel;reg out;always @(in0 or in1 or in2 or in3 or sel)beginif(sel==2'b00)out=in0;else if(sel==2'b01)out=in1;else if(sel==2'b10)out=in2;elseout=in3;endendmodule综合后RTL视图：时序电路模块二、采用不同的描述方式设计本章中的时序电路模块，并综合。

1. D-FF designs（基本D触发器）①门级结构描述module dffx (d,clk,q,qbar);input d,clk;output q,qbar;nandnd1 (d1_n,d,d2),nd2 (d1,d1_n,d2_n),nd3 (d2,clk,d1_n,d2_n),nd4 (d2_n,clk,d1),nd5 (qbar,d2,q),nd6 (q,qbar,d2_n);endmodule综合后RTL视图:②数据流描述module dffx(d,clk,q,qbar);input d,clk;output q,qbar;wire d1,d2,d1_n,d2_n;assign d1_n = ~(d&d2);assign d1 = ~(d1_n&d2_n);assign d2_n = ~(clk&d1);assign d2 = ~(clk&d1_n&d2_n);assign qbar = ~(d2&q);assign q = ~(qbar&d2_n);endmodule综合后RTL图：③行为描述module dffx3(q,d,clk);output q;input d,clk;reg q;always @(posedge clk)beginq <= d;endendmodule综合后RTL视图：2. 带异步清0、异步置1的D触发器①门级描述module dffx1 (d,clk,q,qbar,set,reset);input d,clk,set,reset;output q,qbar;not (set_n,set);not(reset_n,reset);nandnd1 (d1_n,d,d2),nd2 (d1,d1_n,d2_n),nd3 (d2,clk,d1_n,d2_n),nd4 (d2_n,clk,d1),nd5 (qbar,d2,q,reset_n),nd6 (q,qbar,d2_n,set_n);endmodule综合后RTL视图：②数据流描述module dffx1(d,clk,q,qbar,set,reset);input d,clk,set,reset;output q,qbar;assign d1_n = ~(d&d2);assign d1 = ~(d1_n&d2_n);assign d2_n = ~(clk&d1);assign d2 = ~(clk&d1_n&d2_n);assign qbar = ~(d2&q&(~reset));assign q = ~(qbar&d2_n&(~set));endmodule综合后RTL视图：③行为描述module dff1(q, qn, d, clk, set, reset);input d, clk, set, reset;output q, qn;reg q, qn;always @(posedge clk or negedge set or negedge reset)beginif (!reset)beginq <= 0; // clearqn <= 1;endelse if (!set)beginq <= 1; // setqn <= 0;endelsebeginq <= d;qn <= ~d;endendendmodule综合后RTL视图:3. 带同步清0、同步置1的D触发器①门级描述module dffx2(q,qn,d,clk,set,reset);input d, clk, set, reset;output q, qn;nandnd1 (d1_n,d,d2),nd2 (d1,d1_n,d2_n),nd3 (d2,clk,d1_n,d2_n),nd4 (d2_n,clk,d1),nd5 (r_cp,clk,reset),nd6 (s_cp,clk,set),nd7 (qbar,d2,q,r_cp),nd8 (q,qbar,d2_n,s_cp);endmodule综合后RTL视图：②数据流描述module dffx2(q,qn,d,clk,set,reset);input d,clk,set,reset;output q,qn;wire r_cp,s_cp;assign d1_n = ~(d&d2);assign d1 = ~(d1_n&d2_n);assign d2_n = ~(clk&d1);assign d2 = ~(clk&d1_n&d2_n);assign r_cp = ~(reset&clk);assign s_cp = ~(set&clk);assign qn = ~(d2&q&r_cp);assign q = ~(qn&d2_n&s_cp);endmodule综合后RTL视图：③行为级描述module dffx2(q, qn, d, clk, set, reset);input d, clk, set, reset;output q, qn;reg q, qn;always @(posedge clk)beginif (reset)beginq <= 0;qn <= 1;end //clear,high enableelse if (set)beginq <= 1;qn <= 0;end //set,high enableelsebeginq<= d;qn<=~d;endendendmodule综合后RTL视图：4. 8位数据锁存器①门级描述module latch_8(qout,data,clk);output[7:0] qout;input[7:0] data;input clk;andad1(qout[0],data[0],clk),ad2(qout[1],data[1],clk),ad3(qout[2],data[2],clk),ad4(qout[3],data[3],clk),ad5(qout[4],data[4],clk),ad6(qout[5],data[5],clk),ad7(qout[6],data[6],clk),ad8(qout[7],data[7],clk);endmodule综合后RTL视图：②数据流描述module latch_8(qout,data,clk);output[7:0] qout;input[7:0] data;input clk;assign qout[0]= data[0]&clk;assign qout[1]= data[1]&clk;assign qout[2]= data[2]&clk;assign qout[3]= data[3]&clk;assign qout[4]= data[4]&clk;assign qout[5]= data[5]&clk;assign qout[6]= data[6]&clk;assign qout[7]= data[7]&clk;endmodule综合后RTL视图：③行为描述module latch_8(qout,data,clk);output[7:0] qout;input[7:0] data;input clk;reg[7:0] qout;always @(clk or data)beginif(clk)qout <= data;endendmodule综合后RTL视图：5. 8位数据寄存器①门级描述module reg8(out_data,in_data,clk,clr);output[7:0] out_data;input[7:0] in_data;input clk,clr;wire[7:0] out_data;wire[7:0] qb;dffx_clk dfx_ck0(.d(in_data[0]),.clk(clk),.q(out_data[0]),.qbar(qb[0]));dffx_clk dfx_ck1(.d(in_data[1]),.clk(clk),.q(out_data[1]),.qbar(qb[1]));dffx_clk dfx_ck2(.d(in_data[2]),.clk(clk),.q(out_data[2]),.qbar(qb[2]));dffx_clk dfx_ck3(.d(in_data[3]),.clk(clk),.q(out_data[3]),.qbar(qb[3]));dffx_clk dfx_ck4(.d(in_data[4]),.clk(clk),.q(out_data[4]),.qbar(qb[4]));dffx_clk dfx_ck5(.d(in_data[5]),.clk(clk),.q(out_data[5]),.qbar(qb[5]));dffx_clk dfx_ck6(.d(in_data[6]),.clk(clk),.q(out_data[6]),.qbar(qb[6]));dffx_clk dfx_ck7(.d(in_data[7]),.clk(clk),.q(out_data[7]),.qbar(qb[7]));endmodule//dffx with clk(positive edge enable)module dffx_clk (d,clk,q,qbar);input d,clk;output q,qbar;wire d_q1;wire d_qbar1;wire clk_n;assign clk_n = ~clk;dffx_en d_m1(.dat(d),.en(clk),.q(d_q1),.qbar(d_qbar1));dffx_en d_m2(.dat(d_q1),.en(clk_n),.q(q),.qbar(qbar));endmodule//gate control D_latchmodule dffx_en(dat,en,q,qbar);input dat,en;output q,qbar;wire x1,x2;wire q,qbar;not (dat_n,dat);nandnd1 (x1,dat,en),nd2 (x2,dat_n,en),nd3 (q,x1,qbar),nd4 (qbar,q,x2);endmodule综合后RTL视图：②数据流描述module reg8(out_data,in_data,clk,clr);output[7:0] out_data;input[7:0] in_data;input clk,clr;wire[7:0] out_data;wire[7:0] qb;dffx_clk dfx_ck0(.d(in_data[0]),.clk(clk),.q(out_data[0]),.qbar(qb[0]));dffx_clk dfx_ck1(.d(in_data[1]),.clk(clk),.q(out_data[1]),.qbar(qb[1]));dffx_clk dfx_ck2(.d(in_data[2]),.clk(clk),.q(out_data[2]),.qbar(qb[2]));dffx_clk dfx_ck3(.d(in_data[3]),.clk(clk),.q(out_data[3]),.qbar(qb[3]));dffx_clk dfx_ck4(.d(in_data[4]),.clk(clk),.q(out_data[4]),.qbar(qb[4]));dffx_clk dfx_ck5(.d(in_data[5]),.clk(clk),.q(out_data[5]),.qbar(qb[5]));dffx_clk dfx_ck6(.d(in_data[6]),.clk(clk),.q(out_data[6]),.qbar(qb[6]));dffx_clk dfx_ck7(.d(in_data[7]),.clk(clk),.q(out_data[7]),.qbar(qb[7]));endmodule//dffx with clk(positive edge enable) module dffx_clk (d,clk,q,qbar);input d,clk;output q,qbar;wire d_q1;wire d_qbar1;wire clk_n;assign clk_n = ~clk;dffx_en d_m1(.dat(d),.en(clk),.q(d_q1),.qbar(d_qbar1));dffx_en d_m2(.dat(d_q1),.en(clk_n),.q(q),.qbar(qbar)); endmodule//gate control D_latchmodule dffx_en(dat,en,q,qbar);input dat,en;output q,qbar;wire x1,x2;wire q,qbar;assign dat_n = ~dat;assign x1 = ~(dat&en);assign x2 = ~(dat_n&en);assign q = ~(x1&qbar);assign qbar = ~(q&x2);endmodule综合后RTL视图：③行为级描述module reg8(out_data,in_data,clk,clr);output[7:0] out_data;input[7:0] in_data;input clk,clr;reg[7:0] out_data;always @(posedge clk or posedge clr)begin if(clr)out_data <= 0;elseout_data <= in_data;endendmodule综合后RTL视图：6. 可变模加法/减法计数器①门级描述module updown_count(d,clk,clear,load,up_down,qd);input[7:0] d;input clk,clear,load,up_down;output[7:0] qd;wire[7:0] j;wire[7:0] k;wire[7:0] sd_n;wire[7:0] xd_n;wire[7:0] rd_n;wire[7:0] qd_n;wire clear_n;not (clear_n,clear);not (up_down_n,up_down);nandsd1 (sd_n[0],load,d[0]),sd2 (sd_n[1],load,d[1]),sd3 (sd_n[2],load,d[2]),sd4 (sd_n[3],load,d[3]),sd5 (sd_n[4],load,d[4]),sd6 (sd_n[5],load,d[5]),sd7 (sd_n[6],load,d[6]),sd8 (sd_n[7],load,d[7]);nandrd1 (xd_n[0],sd_n[0],load),rd2 (xd_n[1],sd_n[1],load),rd3 (xd_n[2],sd_n[2],load),rd4 (xd_n[3],sd_n[3],load),rd5 (xd_n[4],sd_n[4],load),rd6 (xd_n[5],sd_n[5],load),rd7 (xd_n[6],sd_n[6],load),rd8 (xd_n[7],sd_n[7],load);andad1 (rd_n[0],xd_n[0],clear_n),ad2 (rd_n[1],xd_n[1],clear_n),ad3 (rd_n[2],xd_n[2],clear_n),ad4 (rd_n[3],xd_n[3],clear_n),ad5 (rd_n[4],xd_n[4],clear_n),ad6 (rd_n[5],xd_n[5],clear_n),ad7 (rd_n[6],xd_n[6],clear_n),ad8 (rd_n[7],xd_n[7],clear_n);//JK Trigernot (j[0],0);not (k[0],0);wire[7:1] patA;wire[7:1] patB;andadp1 (patA[1],qd[0],up_down), adp2 (patB[1],qd_n[0],up_down_n), adp3 (patA[2],patA[1],qd[1]),adp4 (patB[2],patB[1],qd_n[1]), adp5 (patA[3],patA[2],qd[2]),adp6 (patB[3],patB[2],qd_n[2]), adp7 (patA[4],patA[3],qd[3]),adp8 (patB[4],patB[3],qd_n[3]), adp9 (patA[5],patA[4],qd[4]),adp10 (patB[5],patB[4],qd_n[4]), adp11 (patA[6],patA[5],qd[5]),adp12 (patB[6],patB[5],qd_n[5]), adp13 (patA[7],patA[6],qd[6]),adp14 (patB[7],patB[6],qd_n[6]);ororp1 (j1,patA[1],patB[1]),orp2 (j2,patA[2],patB[2]),orp3 (j3,patA[3],patB[3]),orp4 (j4,patA[4],patB[4]),orp5 (j5,patA[5],patB[5]),orp6 (j6,patA[6],patB[6]),orp7 (j7,patA[7],patB[7]); jk_tri jkm0(.j(j[0]),.k(j[0]),.clk(clk),.sd_n(sd_n[0]),.rd_n(rd_n[0]),.q(qd[0]),.qbar(qd_n[0])); jk_tri jkm1(.j(j[1]),.k(j[1]),.clk(clk),.sd_n(sd_n[1]),.rd_n(rd_n[1]),.q(qd[1]),.qbar(qd_n[1])); jk_tri jkm2(.j(j[2]),.k(j[2]),.clk(clk),.sd_n(sd_n[2]),.rd_n(rd_n[2]),.q(qd[2]),.qbar(qd_n[2])); jk_tri jkm3(.j(j[3]),.k(j[3]),.clk(clk),.sd_n(sd_n[3]),.rd_n(rd_n[3]),.q(qd[3]),.qbar(qd_n[3])); jk_tri jkm4(.j(j[4]),.k(j[4]),.clk(clk),.sd_n(sd_n[4]),.rd_n(rd_n[4]),.q(qd[4]),.qbar(qd_n[4]));jk_tri jkm5(.j(j[5]),.k(j[5]),.clk(clk),.sd_n(sd_n[5]),.rd_n(rd_n[5]),.q(qd[5]),.qbar(qd_n[5]));jk_tri jkm6(.j(j[6]),.k(j[6]),.clk(clk),.sd_n(sd_n[6]),.rd_n(rd_n[6]),.q(qd[6]),.qbar(qd_n[6]));jk_tri jkm7(.j(j[7]),.k(j[7]),.clk(clk),.sd_n(sd_n[7]),.rd_n(rd_n[7]),.q(qd[7]),.qbar(qd_n[7])); endmodulemodule jk_tri(j,k,clk,sd_n,rd_n,q,qbar);input j,k,clk,sd_n,rd_n;output q,qbar;wire ss,rr;andnd1 (ss,j,qbar),nd2 (rr,k,q);SR_ms srms1(.s(ss),.r(rr),.clk(clk),.sd_n(sd_n),.rd_n(rd_n),.q(q),.qbar(qbar)); endmodulemodule SR_ms(s,r,clk,sd_n,rd_n,q,qbar);input s,r,clk,sd_n,rd_n;output q,qbar;wire q,qbar;wire clk_n;not (clk_n,clk);wire qm,qm_bar;//SR triger: master_slaveSR sr1(.s(s),.r(r),.cp(clk_n),.sd_n(sd_n),.rd_n(rd_n),.q(qm),.qbar(qm_bar));SR sr2(.s(qm),.r(qm_bar),.cp(clk),.sd_n(sd_n),.rd_n(rd_n),.q(q),.qbar(qbar));endmodule//SR trigermodule SR(s,r,cp,sd_n,rd_n,q,qbar);input s,r,cp,sd_n,rd_n;output q,qbar;wire x1,x2;nandnd1 (x1,r,cp,sd_n),nd2 (x2,s,cp,rd_n),nd3 (qbar,q,x1,rd_n),nd4 (q,qbar,x2,sd_n);endmodule综合后RTL视图：②数据流描述module updown_count(d,clk,clear,load,up_down,qd);input[7:0] d;input clk,clear,load,up_down;output[7:0] qd;wire[7:0] j;wire[7:0] sd_n;wire[7:0] rd_n;wire[7:0] qd_n;wire down;wire up,clear_n;assign up = up_down;assign down = ~up_down;assign load_n = ~load;// jk signalassign j[0] = 1;assign j[1] = (qd[0]&up) |(~qd[0]&down);assign j[2] = (qd[0]&qd[1]&up)|((~qd[0])&(~qd[1])&down);assign j[3] = (qd[0]&qd[1]&qd[2]&up)|((~qd[0])&(~qd[1])&(~qd[2])&down);assign j[4] = (qd[0]&qd[1]&qd[2]&qd[3]&up)|((~qd[0])&(~qd[1])&(~qd[2])&(~qd[3])&down);assign j[5] = (qd[0]&qd[1]&qd[2]&qd[3]&qd[4]&up)|((~qd[0])&(~qd[1])&(~qd[2])&(~qd[3])&(~qd[4])&down);assign j[6] = (qd[0]&qd[1]&qd[2]&qd[3]&qd[4]&qd[5]&up)|((~qd[0])&(~qd[1])&(~qd[2])&(~qd[3])&(~qd[4])&(~qd[5])&down); assign j[7] = (qd[0]&qd[1]&qd[2]&qd[3]&qd[4]&qd[5]&qd[6]&up) |((~qd[0])&(~qd[1])&(~qd[2])&(~qd[3])&(~qd[4])&(~qd[5])&(~qd[6])&down);//sd valueassign sd_n[0] = ~(d[0]&load_n);assign sd_n[1] = ~(d[1]&load_n);assign sd_n[2] = ~(d[2]&load_n);assign sd_n[3] = ~(d[3]&load_n);assign sd_n[4] = ~(d[4]&load_n);assign sd_n[5] = ~(d[5]&load_n);assign sd_n[6] = ~(d[6]&load_n);assign sd_n[7] = ~(d[7]&load_n);//rd valueassign rd_n[0] = (~(sd_n[0]&load_n))&clear_n;assign rd_n[1] = (~(sd_n[1]&load_n))&clear_n;assign rd_n[2] = (~(sd_n[2]&load_n))&clear_n;assign rd_n[3] = (~(sd_n[3]&load_n))&clear_n;assign rd_n[4] = (~(sd_n[4]&load_n))&clear_n;assign rd_n[5] = (~(sd_n[5]&load_n))&clear_n;assign rd_n[6] = (~(sd_n[6]&load_n))&clear_n;assign rd_n[7] = (~(sd_n[7]&load_n))&clear_n;jk_tri jkm0(.j(j[0]),.k(j[0]),.clk(clk),.sd_n(sd_n[0]),.rd_n(rd_n[0]),.q(qd[0]),.qbar(qd_n[0]));jk_tri jkm1(.j(j[1]),.k(j[1]),.clk(clk),.sd_n(sd_n[1]),.rd_n(rd_n[1]),.q(qd[1]),.qbar(qd_n[1])); jk_tri jkm2(.j(j[2]),.k(j[2]),.clk(clk),.sd_n(sd_n[2]),.rd_n(rd_n[2]),.q(qd[2]),.qbar(qd_n[2])); jk_tri jkm3(.j(j[3]),.k(j[3]),.clk(clk),.sd_n(sd_n[3]),.rd_n(rd_n[3]),.q(qd[3]),.qbar(qd_n[3])); jk_tri jkm4(.j(j[4]),.k(j[4]),.clk(clk),.sd_n(sd_n[4]),.rd_n(rd_n[4]),.q(qd[4]),.qbar(qd_n[4])); jk_tri jkm5(.j(j[5]),.k(j[5]),.clk(clk),.sd_n(sd_n[5]),.rd_n(rd_n[5]),.q(qd[5]),.qbar(qd_n[5])); jk_tri jkm6(.j(j[6]),.k(j[6]),.clk(clk),.sd_n(sd_n[6]),.rd_n(rd_n[6]),.q(qd[6]),.qbar(qd_n[6])); jk_tri jkm7(.j(j[7]),.k(j[7]),.clk(clk),.sd_n(sd_n[7]),.rd_n(rd_n[7]),.q(qd[7]),.qbar(qd_n[7])); endmodulemodule jk_tri(j,k,clk,sd_n,rd_n,q,qbar);input j,k,clk,sd_n,rd_n;output q,qbar;wire ss,rr;assign ss = j&qbar;assign rr = k&q;SR_ms srms1(.s(ss),.r(rr),.clk(clk),.sd_n(sd_n),.rd_n(rd_n),.q(q),.qbar(qbar)); endmodulemodule SR_ms(s,r,clk,sd_n,rd_n,q,qbar);input s,r,clk,sd_n,rd_n;output q,qbar;wire q,qbar;wire clk_n;not (clk_n,clk);wire qm,qm_bar;//SR triger: master_slaveSR sr1(.s(s),.r(r),.cp(clk_n),.sd_n(sd_n),.rd_n(rd_n),.q(qm),.qbar(qm_bar));SR sr2(.s(qm),.r(qm_bar),.cp(clk),.sd_n(sd_n),.rd_n(rd_n),.q(q),.qbar(qbar));endmodule//SR trigermodule SR(s,r,cp,sd_n,rd_n,q,qbar);input s,r,cp,sd_n,rd_n;output q,qbar;wire x1,x2;assign x1 = ~(r&cp&sd_n);assign x2 = ~(s&cp&rd_n);assign qbar = ~(q&x1&rd_n);assign q = ~(qbar&x2&sd_n);endmodule综合后RTL视图：③行为描述module updown_count(d,clk,clear,load,up_down,qd);input[7:0] d;input clk,clear,load,up_down;output[7:0] qd;reg[7:0] cnt;assign qd=cnt;always @ (posedge clk)beginif(!clear)cnt = 8'h00; //clear,low enableelse if(load)cnt = d; //set,high enableelse if(up_down)cnt = cnt+1; //countelsecnt=cnt-1; //discountendendmodule综合后RTL视图：功能模块设计1.十进制计数器设计设计一个带同步复位的十进制计数器，编辑波形激励文件测试程序。