AD408M166RBB-5中文资料 - 360文档中心

3845B中文资料

TOP-SIDE MARKING TL2842BP TL2843BP TL2844BP TL2845BP 2842B
2843B
2844B
2845B
TL2842B
TL2843B
TL2844B
TL2845B TL3842BP TL3843BP TL3844BP TL3845BP 3842B
3843B
3844B
元器件交易网

TL284xB, TL384xB HIGH-PERFORMANCE CURRENT-MODE PWM CONTROLLERS
SLVS610A – AUGUST 2006 – REVISED SEPTEMBER 2006
FEATURES
• Low Start-Up Current (<0.5 mA) • Trimmed Oscillator Discharge Current • Current Mode Operation to 500 kHz • Automatic Feed-Forward Compensation • Latching PWM for Cycle-by-Cycle Current
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TL2842BD-8
Reel of 2500

mini smd 可编程数字AD型热释电红外传感器S22-P340R 使用说明书

MINI SMD 可编程数字AD 型热释电红外传感器Mini SMD Programmable AD Pyroelectric Infrared SensorsS22-P340R 使用说明书V1.2森霸传感科技股份有限公司Senba Sensing Technology Co.,Ltd.森霸传感科技股份有限公司1.企业及产品概况：1.1体系认证●ISO14001认证公司获得ISO14001认证，在遵守国家环保法的基础上，通过采取各种改进措施，实现企业可持续性发展。

●ISO 9001认证公司获得国际标准化机构（ISO）的品质保证标准-即“ISO 9001”的认证。

1.2关于欧盟ROHS指令ROHS指令：欧盟提出的“关于在电子电气设备中限制使用某些有害物质的指令2011/65/EC”，公司生产的所有产品均符合欧盟ROHS指令。

1.3产品型号及检测原理1.3.1产品规格型号：本产品为SMD 数字AD 型双元热释电红外传感器，产品型号为S22-P340R ，版本号为V1.2，若使用产品超出了产品列举的应用范围，请及时咨询产品应用或销售工程师。

1.3.2产品探测原理：传感器核心部件由热释电探测敏感元、红外滤光片和芯片IC三部分组成，其中探测敏感元为双元结构。

是一款用于低功耗运动检测的红外热释电传感器（PIR）。

利用MCU进行通信，当S22-P340R 进行连续运动传感时，MCU不需要激活，它只在检测到运动时才激活外部MCU。

运动检测结果通过输出中断信号发出。

运动检测的算法是可编程的，可以通过外部MCU配置来改变。

PIR信号在芯片上转换为一个14位的数字值，然后进入运动算法检测单元。

所有的信号处理都是数字化的，可支持运动检测结果输出和原始数据输出。

2.非商业用途说明森霸传感科技股份有限公司（以下简称森霸）免费授权用户非商业性使用本产品说明书，并为用户提供产品变更和咨询服务。

若要进行商业性的销售、复制、散发或其他商业活动，须事先获取森霸的书面授权和许可。

MM24512-BN5T中文资料

1/24February 2005M24512512 Kbit Serial I²C Bus EEPROMFEATURES SUMMARY■Two-Wire I 2C Serial Interface Supports 400kHz Protocol ■Supply Voltage Ranges:– 1.8V to 5.5V (M24512 − R)– 2.5V to 5.5V (M24512 − W)■Write Control Input■BYTE and PAGE WRITE (up to 128 Bytes)■RANDOM and SEQUENTIAL READ Modes ■Self-Timed Programming Cycle ■Automatic Address Incrementing ■Enhanced ESD/Latch-Up Protection ■More than 100,000 Erase/Write Cycles ■More than 40-Year Data RetentionTable 1. M24512 devicesReference Part Number M24512M24512 − W M24512 − RM24512TABLE OF CONTENTSFEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Table 1.M24512 devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Figure 1.Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Figure 2.Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Table 2.Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Power On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Figure 3.DIP, SO and TSSOP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5Serial Clock (SCL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Chip Enable (E0, E1, E2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Write Control (WC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Figure 4.Maximum R P Value versus Bus Parasitic Capacitance (C) for an I2C Bus. . . . . . . . . . . .5 Figure 5.I2C Bus Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Table 3.Device Select Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Table 4.Most Significant Byte. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Table 5.Least Significant Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6DEVICE OPERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7Start Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Stop Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Acknowledge Bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Data Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Memory Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Table 6.Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Figure 6.Write Mode Sequences with WC=1 (data write inhibited). . . . . . . . . . . . . . . . . . . . . . . . .8 Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Byte Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Figure 7.Write Mode Sequences with WC=0 (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . .9 Figure 8.Write Cycle Polling Flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Minimizing System Delays by Polling On ACK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Figure 9.Read Mode Sequences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Random Address Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Sequential Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Acknowledge in Read Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12INITIAL DELIVERY STATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Table 7.Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132/24M24512DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14Table 8.Operating Conditions (M24512 – W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Table 9.Operating Conditions (M24512 – R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Table 10.AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Figure 10.AC Measurement I/O Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Table 11.Input Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Table 12.DC Characteristics (M24512 – W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Table 13.DC Characteristics(1) (M24512 – R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Table 14.AC Characteristics (M24512 – W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Table 15.AC Characteristics(1) (M24512 – R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Figure 11.AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18Figure 12.PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Outline . . . . . . . . . . . . . . . . .18 Table 16.PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Mechanical Data. . . . . . . . . .18 Figure 13.SO8W – 8 lead Plastic Small Outline, 208 mils body width, Package Outline . . . . . . . .19 Table 17.SO8W – 8 lead Plastic Small Outline, 208 mils body width, Package Mechanical Data.19 Figure 14.SO8N – 8 lead Plastic Small Outline, 150 mils body width, Package Outline. . . . . . . . .20 Table 18.SO8N – 8 lead Plastic Small Outline, 150 mils body width, Package Mechanical Data .20 Figure 15.TSSOP8 – 8 lead Thin Shrink Small Outline, Package Outline . . . . . . . . . . . . . . . . . . .21 Table 19.TSSOP8 – 8 lead Thin Shrink Small Outline, Package Mechanical Data. . . . . . . . . . . .21PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Table 20.Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Table 21.Document Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .233/24M245124/24SUMMARY DESCRIPTIONThese I 2C-compatible electrically erasable pro-grammable memory (EEPROM) devices are orga-nized as 64K x 8 bits.Table 2. Signal NamesI 2C uses a two-wire serial interface, comprising a bi-directional data line and a clock line. The devic-es carry a built-in 4-bit Device Type Identifier code (1010) in accordance with the I 2C bus definition.The device behaves as a slave in the I 2C protocol,with all memory operations synchronized by the serial clock. Read and Write operations are initiat-ed by a Start condition, generated by the bus mas-ter. The Start condition is followed by a Device Select Code and Read/Write bit (RW) (as de-scribed in Table 3.), terminated by an acknowl-edge bit.When writing data to the memory, the device in-serts an acknowledge bit during the 9th bit time,following the bus master’s 8-bit transmission.When data is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. Data transfers are terminated by a Stop condition after an Ack for Write, and after a NoAck for Read.Power On ResetIn order to prevent data corruption and inadvertent Write operations during Power-up, a Power On Reset (POR) circuit is included. At Power-up, the device will not respond to any command until V CC has reached the Power On Reset threshold volt-age (this threshold is lower than the V CC min oper-ating voltage defined in Tables 8 and 9). In the same way, as soon as V CC drops from the normal operating voltage, below the Power On Reset threshold voltage, the device stops to respond to any command.Prior to selecting and issuing commands to the memory, a valid and stable V CC voltage must be applied. This voltage must remain stable and valid until the end of the transmission of the command and, for a Write instruction, until the completion of the internal write cycle (t W ).sions, and how to identify pin-1.E0, E1, E2Chip Enable SDA Serial Data SCL Serial Clock WC Write Control V CC Supply Voltage V SSGroundM24512 SIGNAL DESCRIPTIONSerial Clock (SCL).This input signal is used to strobe all data in and out of the device. In applica-tions where this signal is used by slave devices to synchronize the bus to a slower clock, the bus master must have an open drain output, and a pull-up resistor must be connected from Serial Clock (SCL) to V CC. (Figure 4. indicates how the value of the pull-up resistor can be calculated). In most applications, though, this method of synchro-nization is not employed, and so the pull-up resis-tor is not necessary, provided that the bus master has a push-pull (rather than open drain) output. Serial Data (SDA).This bi-directional signal is used to transfer data in or out of the device. It is an open drain output that may be wire-OR’ed with other open drain or open collector signals on the bus. A pull up resistor must be connected from Se-rial Data (SDA) to V CC. (Figure 4. indicates how the value of the pull-up resistor can be calculated).Chip Enable (E0, E1, E2).These input signals are used to set the value that is to be looked for on the three least significant bits (b3, b2, b1) of the 7-bit Device Select Code. These inputs must be tied to V CC or V SS, to establish the Device Select Code. When not connected (left floating), these in-puts are read as Low (0,0,0).Write Control (WC).This input signal is useful for protecting the entire contents of the memory from inadvertent write operations. Write opera-tions are disabled to the entire memory array when Write Control (WC) is driven High. When uncon-nected, the signal is internally read as V IL, and Write operations are allowed.When Write Control (WC) is driven High, Device Select and Address bytes are acknowledged, Data bytes are not acknowledged.25/24M245122Table 3. Device Select CodeDevice Type Identifier1Chip Enable Address2RW b7b6b5b4b3b2b1b0 Device Select Code1010E2E1E0RW Note: 1.The most significant bit, b7, is sent first.2.E0, E1 and E2 are compared against the respective external pins on the memory device.Table 4. Most Significant Byte Table 5. Least Significant Byteb15 b14 b13 b12 b11 b10 b9 b8b7 b6 b5 b4 b3 b2 b1 b0 6/247/24M24512DEVICE OPERATIONThe device supports the I 2C protocol. This is sum-marized in Figure 5.. Any device that sends data on to the bus is defined to be a transmitter, and any device that reads the data to be a receiver.The device that controls the data transfer is known as the bus master, and the other as the slave de-vice. A data transfer can only be initiated by the bus master, which will also provide the serial clock for synchronization. The M24512 device is always a slave in all communication.Start ConditionStart is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in the High state. A Start condition must precede any data transfer command. The device continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock (SCL) for a Start condition,and will not respond unless one is given.Stop ConditionStop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable and driv-en High. A Stop condition terminates communica-tion between the device and the bus master. A Read command that is followed by NoAck can be followed by a Stop condition to force the device into the Stand-by mode. A Stop condition at the end of a Write command triggers the internal Write cycle.Acknowledge Bit (ACK)The acknowledge bit is used to indicate a success-ful byte transfer. The bus transmitter, whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits of data. During the 9th clock pulse period, the receiver pulls SerialData (SDA) Low to acknowledge the receipt of the eight data bits.Data InputDuring data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock (SCL).For correct device operation, Serial Data (SDA)must be stable during the rising edge of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock (SCL) is driv-en Low.Memory AddressingTo start communication between the bus master and the slave device, the bus master must initiate a Start condition. Following this, the bus master sends the Device Select Code, shown in Table 3.(on Serial Data (SDA), most significant bit first).The Device Select Code consists of a 4-bit Device Type Identifier, and a 3-bit Chip Enable “Address”(E2, E1, E0). To address the memory array, the 4-bit Device Type Identifier is 1010b.Up to eight memory devices can be connected on a single I 2C bus. Each one is given a unique 3-bit code on the Chip Enable (E0, E1, E2) inputs.When the Device Select Code is received, the de-vice only responds if the Chip Enable Address is the same as the value on the Chip Enable (E0, E1,E2) inputs.The 8th bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations.If a match occurs on the Device Select code, the corresponding device gives an acknowledgment on Serial Data (SDA) during the 9th bit time. If the device does not match the Device Select code, it deselects itself from the bus, and goes into Stand-by mode.Table 6. Operating ModesNote: 1.X = V IH or V IL .ModeRW bit WC 1Bytes Initial SequenceCurrent Address Read 1X 1START, Device Select, RW = 1Random Address Read 0X 1START, Device Select, RW = 0, Address 1X reSTART, Device Select, RW = 1Sequential Read 1X ≥ 1Similar to Current or Random Address Read Byte Write 0V IL 1START, Device Select, RW = 0Page WriteV IL≤ 128START, Device Select, RW = 0M245128/24Write OperationsFollowing a Start condition the bus master sends a Device Select Code with the Read/Write bit (RW) reset to 0. The device acknowledges this, as shown in Figure 7., and waits for two address bytes. The device responds to each address byte with an acknowledge bit, and then waits for the data byte.Writing to the memory may be inhibited if Write Control (WC) is driven High. Any Write instruction with Write Control (WC) driven High (during a pe-riod of time from the Start condition until the end of the two address bytes) will not modify the memory contents, and the accompanying data bytes are not acknowledged, as shown in Figure 6..Each data byte in the memory has a 16-bit (two byte wide) address. The Most Significant Byte (Ta-ble 4.) is sent first, followed by the Least Signifi-cant Byte (Table 5.). Bits b15 to b0 form the address of the byte in memory.When the bus master generates a Stop condition immediately after the Ack bit (in the “10th bit” time slot), either at the end of a Byte Write or a Page Write, the internal Write cycle is triggered. A Stop condition at any other time slot does not trigger the internal Write cycle.After the Stop condition, the delay t W , and the suc-cessful completion of a Write operation, the de-vice’s internal address counter is incremented automatically, to point to the next byte address af-ter the last one that was modified.During the internal Write cycle, Serial Data (SDA)is disabled internally, and the device does not re-spond to any requests.Byte WriteAfter the Device Select code and the address bytes, the bus master sends one data byte. If the addressed location is Write-protected, by Write Control (WC) being driven High, the device replies with NoAck, and the location is not modified. If, in-stead, the addressed location is not Write-protect-M24512ed, the device replies with Ack. The bus master terminates the transfer by generating a Stop con-dition, as shown in Figure 7.Page WriteThe Page Write mode allows up to 128 bytes to be written in a single Write cycle, provided that they are all located in the same ’row’ in the memory: that is, the most significant memory address bits (b15-b7) are the same. If more bytes are sent than will fit up to the end of the row, a condition known as ‘roll-over’ occurs. This should be avoided, as data starts to become overwritten in an implemen-tation dependent way.The bus master sends from 1 to 128 bytes of data, each of which is acknowledged by the device if Write Control (WC) is Low. If Write Control (WC) is High, the contents of the addressed memory loca-tion are not modified, and each data byte is fol-lowed by a NoAck. After each byte is transferred, the internal byte address counter (the 7 least sig-nificant address bits only) is incremented. The transfer is terminated by the bus master generat-ing a Stop condition.9/24M2451210/24Minimizing System Delays by Polling On ACK During the internal Write cycle, the device discon-nects itself from the bus, and writes a copy of the data from its internal latches to the memory cells.The maximum Write time (t w ) is shown in Table 14., but the typical time is shorter. To make use of this, a polling sequence can be used by the bus master.The sequence, as shown in Figure 8., is:–Initial condition: a Write cycle is in progress.–Step 1: the bus master issues a Start condition followed by a Device Select Code (the first byte of the new instruction).–Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and the bus master goes back to Step 1. If the device has terminated the internal Write cycle, it responds with an Ack, indicating that the device is ready to receive the second part of the instruction (the first byte of this instruction having been sent during Step 1).Note: 1.The seven most significant bits of the Device Select Code of a Random Read (in the 1st and 4th bytes) must be identical.Read OperationsRead operations are performed independently of the state of the Write Control (WC) signal.After the successful completion of a Read opera-tion, the device’s internal address counter is incre-mented by one, to point to the next byte address. Random Address ReadA dummy Write is first performed to load the ad-dress into this address counter (as shown in Fig-ure 9.) but without sending a Stop condition. Then, the bus master sends another Start condition, and repeats the Device Select Code, with the Read/ Write bit (RW) set to 1. The device acknowledges this, and outputs the contents of the addressed byte. The bus master must not acknowledge the byte, and terminates the transfer with a Stop con-dition.Current Address ReadFor the Current Address Read operation, following a Start condition, the bus master only sends a De-vice Select Code with the Read/Write bit (RW) set to 1. The device acknowledges this, and outputs the byte addressed by the internal address counter. The counter is then incremented. The bus master terminates the transfer with a Stop condi-tion, as shown in Figure 9., without acknowledging the byte.11/24Sequential ReadThis operation can be used after a Current Ad-dress Read or a Random Address Read. The bus master does acknowledge the data byte output,and sends additional clock pulses so that the de-vice continues to output the next byte in sequence. To terminate the stream of bytes, the bus master must not acknowledge the last byte, and must generate a Stop condition, as shown in Figure 9. The output data comes from consecutive address-es, with the internal address counter automatically incremented after each byte output. After the last memory address, the address counter ‘rolls-over’, and the device continues to output data from memory address 00h.Acknowledge in Read ModeFor all Read commands, the device waits, aftereach byte read, for an acknowledgment during the 9th bit time. If the bus master does not drive SerialData (SDA) Low during this time, the device termi-nates the data transfer and switches to its Stand-by mode.INITIAL DELIVERY STATEThe device is delivered with all bits in the memory array set to 1 (each byte contains FFh).12/2413/24MAXIMUM RATINGStressing the device outside the ratings listed in Table 7. may cause permanent damage to the de-vice. These are stress ratings only, and operation of the device at these, or any other conditions out-side those indicated in the Operating sections of this specification, is not implied. Exposure to Ab-solute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.Table 7. Absolute Maximum RatingsNote: pliant with JEDEC Std J-STD-020C (for small body, Sn-Pb or Pb assembly), the ST ECOPACK ® 7191395 specification, andthe European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU2.AEC-Q100-002 (compliant with JEDEC Std JESD22-A114A, C1=100pF, R1=1500Ω, R2=500Ω)Symbol ParameterMin.Max.Unit T A Ambient Operating Temperature –40125°C T STG Storage Temperature–65150°C T LEAD Lead Temperature during Soldering See note (1)°C V IO Input or Output range –0.50 6.5V V CC Supply Voltage–0.50 6.5V V ESDElectrostatic Discharge Voltage (Human Body model) 2–40004000V14/24DC AND AC PARAMETERSThis section summarizes the operating and mea-surement conditions, and the DC and AC charac-teristics of the device. The parameters in the DC and AC Characteristic tables that follow are de-rived from tests performed under the Measure-ment Conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parame-ters.Table 8. Operating Conditions (M24512 – W)Table 9. Operating Conditions (M24512 – R)Table 10. AC Measurement ConditionsSymbol ParameterMin.Max.Unit V CC Supply Voltage2.5 5.5V T AAmbient Operating Temperature–4085°CSymbol ParameterMin.Max.Unit V CC Supply Voltage1.8 5.5V T AAmbient Operating Temperature–4085°CSymbol ParameterMin.Max.Unit C LLoad Capacitance 100pF Input Rise and Fall Times 50ns Input Levels0.2V CC to 0.8V CC V Input and Output Timing Reference Levels0.3V CC to 0.7V CCV15/24Table 11. Input ParametersNote: 1.T A = 25 °C, f = 400 kHz2.Sampled only, not 100% tested.3.E2,E1,E0: Input impedance when the memory is selected (after a Start condition).Table 12. DC Characteristics (M24512 – W)Note: 1.When the device is selected (after a START condition), the Ei inputs have a different input impedance, as defined in Table 11.Table 13. DC Characteristics (1) (M24512 – R)Note: 1.The information contained in Table 13. is related to the new M24512 (process letter “A”) and is subject to change without previousnotice.Symbol Parameter (1,2)Test ConditionMin.Max.Unit C IN Input Capacitance (SDA)8pF C IN Input Capacitance (other pins)6pF Z L (3)Input Impedance (E2, E1, E0, WC)V IN < 0.3V CC 30k ΩZ H (3)Input Impedance (E2, E1, E0, WC)V IN > 0.7V CC 500k Ωt NSPulse width ignored(Input Filter on SCL and SDA)Single glitch100nsSymbol ParameterTest Condition Min.Max.Unit I LI Input Leakage Current (SCL, SDA, E0, E1, E2)V IN = V SS or V CCdevice in Standby mode (1)± 2µA I LO Output Leakage Current V OUT = V SS or V CC, SDA in Hi-Z± 2µA I CCSupply CurrentV CC = 2.5V, f c =400kHz (rise/fall time < 30ns)1mA V CC = 5.5V, f c =400kHz (rise/fall time < 30ns)2mA I CC1Stand-by Supply Current V IN = V SS or V CC , V CC = 2.5V 2µA V IN = V SS or V CC , V CC = 5.5V5µA V IL Input Low Voltage (SCL, SDA, WC)–0.450.3V CC V V IH Input High Voltage (SCL, SDA, WC)0.7V CCV CC +1V V OLOutput Low VoltageI OL = 2.1mA, V CC = 2.5V0.4VSymbol ParameterTest Condition Min.Max.Unit I LI Input Leakage Current (SCL, SDA, E2, E1, E0)V IN = V SS or V CCdevice in Stand-by mode ± 2µA I LO Output Leakage Current V OUT = V SS or V CC, SDA in Hi-Z ± 2µA I CC Supply Current V CC =1.8V, f c = 400kHz (rise/fall time <30ns)1mA I CC1Standby Supply Current V IN = V SS or V CC , V CC = 1.8V2µA V IL Input Low Voltage –0.450.3V CC V V IH Input High Voltage 0.7V CC V CC +1V V OLOutput Low VoltageI OL = 0.7mA, V CC = 1.8V0.2VTable 14. AC Characteristics (M24512 – W)Symbol Alt.Parameter Min.Max.Unitf C f SCL Clock Frequency400kHzt CHCL t HIGH Clock Pulse Width High600ns t CLCH t LOW Clock Pulse Width Low1300ns t CH1CH2t R Clock Rise Time300ns t CL1CL2t F Clock Fall Time300nst DH1DH2 (2)t R SDA Rise Time20300ns t DL1DL2 (2)t F SDA Fall Time20300ns t DXCX t SU:DAT Data In Set Up Time100ns t CLDX t HD:DAT Data In Hold Time0ns t CLQX t DH Data Out Hold Time200ns t CLQV (3)t AA Clock Low to Next Data Valid (Access Time)200900ns t CHDX (1)t SU:STA Start Condition Set Up Time600ns t DLCL t HD:STA Start Condition Hold Time600ns t CHDH t SU:STO Stop Condition Set Up Time600ns t DHDL t BUF Time between Stop Condition and Next Start Condition1300ns t W t WR Write Time 5 or 10(4)ms Note: 1.For a reSTART condition, or following a Write cycle.2.Sampled only, not 100% tested.3.To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.4.For M24512 devices whose package marking shows the process letter “A” t W(max) = 5ms whereas for M24512 devices whosepackage marking shows the process letter “V” t W(max) = 10msTable 15. AC Characteristics(1) (M24512 – R)Symbol Alt.Parameter Min.Max.Unitf C f SCL Clock Frequency400kHzt CHCL t HIGH Clock Pulse Width High600ns t CLCH t LOW Clock Pulse Width Low1300nst DL1DL2 (3)t F SDA Fall Time20300ns t DXCX t SU:DAT Data In Set Up Time100ns t CLDX t HD:DAT Data In Hold Time0ns t CLQX t DH Data Out Hold Time200nst CLQV (4)t AA Clock Low to Next Data Valid (Access Time)200900nst CHDX (2)t SU:STA Start Condition Set Up Time600ns t DLCL t HD:STA Start Condition Hold Time600ns t CHDH t SU:STO Stop Condition Set Up Time600ns t DHDL t BUF Time between Stop Condition and Next Start Condition1300ns t W t WR Write Time10ms Note: 1.The information contained in Table 15. is related to the new M24512 (process letter “A”) and is subject to change without previous notice.2.For a reSTART condition, or following a Write cycle.3.Sampled only, not 100% tested.4.To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA. 16/24。

NTE0505M中文资料

Reflected Ripple Current
TYP 3.30
5 12 30
MAX Units 3.63 5.5 V 13.2
47 mA p-p
OUTPUT CHARACTERISTICS
Parameter
Conditions
Rated Power2
Voltage Set Point Accuracy
元器件交易网
NTE SERIES
Isolated 1W Single Output SM DC-DC Converters
FEATURES s Wide Temperature Performance at
Full 1 Watt Load, –40°C to 85°C s Lead Frame Technology s CECC00802 Reflow (280°C) s Single Isolated Output s 1kVDC Isolation s Efficiency to 78% s Power Density 1.8W/cm3 s 3.3V, 5V & 12V Input s 3.3V, 5V, 9V, 12V and 15V Output s Footprint Over Pins 1.64cm 2 s UL 94V-0 Package Material s No Heatsink Required s Internal SMD Construction s Toroidal Magnetics s Plastic Encapsulated s MTTF up to 2.9 Million Hours s Custom Solutions Available s Multi Layer Ceramic Capacitors s Lead Free Compatible

MB3845资料

s RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Condition
Min.
Value Typ.
Max.
Input voltage ENABLE voltage
VIN
—
VEN
VEN ≤ VIN
2.5
5.0
5.5
0
—
5.5
Switch current
ISW
Control signal input pin. Set “L” to turn switch on, “H” to turn off. At “H” level = VIN, the chip is in STBY state and current consumption is less than 1µA. Normally used as CMOS inverter input, so that recommended use is “L” level at GND +0.5V or less, and “H” level is VIN -0.5V or greater.
Slow start setting pin. Used to adjust the switch on/off timing. Add external capacitance to delay operation. Leave open when not in use. In open mode voltages up to 12 V are present. Care should be taken in mounting to prevent leakage current generation because high impedance is required.

MB40166中文资料

R-2R RESISTOR NETWORK
24 VOUT
15 28
D.GND
17 26
A.GND
16 27
VCCD
18 25
VCCA
23
COMP
Note : The circuits within the dotted lines above are different for MB40166 and MB40176.
– Clamp capacitor is connected between these pins.
–
I A/D conversion clock input.
O Analog signal output.
I Digital signal input. (DD1: MSB, DD6: LSB)
Phase compensation capacitor is connected. – Insert a capacitor of 1 µF or more between this pin and
VINA
-0.5 to VCCA +0.5
V
Storage Temperature
TSTG
-55 to +125
°C
NOTE:
Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

AD6645中文说明手册

应用
多通道、多模式接收机基站Байду номын сангаас础设施 AMPS、IS-136、CDMA、GSM、W-CDMA 单通道数字接收机天线阵列处理通信仪器雷达、红外成像
仪器仪表
产品聚焦
1. 中频采样。AD6645在最高200 MHz的输入频率范围内保持出色的交流性能，适用于多载波3G宽带蜂窝中频采样接收机。 2. 引脚兼容性。该ADC与14位、40 MSPS/65 MSPS ADC AD6644具有相同的尺寸和引脚布局。 3. SFDR性能和过采样。多音SFDR性能达100 dBFS，可以降低高端RF元件的要求，支持使用AD6620、 AD6624/AD6624A或AD6636等接收信号处理器。
ADC1 VREF 2.4V 5 ENCODE ENCODE
DAC1
ADC2 5
DAC2
6
INTERNAL TIMING
DIGITAL ERROR CORRECTION LOGIC
GND
DMID
OVR
DRY
D13 MSB
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0 LSB
图1
Rev. D
修订历史
2008年10月—修订版C至修订版D 增加TQFP_EP封装 .................................................................... 通篇重命名“热特性”和“热阻”部分 ...................................................... 7 增加表6；重新排序 ........................................................................ 7 移动“等效电路”部分 ..................................................................... 14 移动“术语”部分 .............................................................................. 15 更改表9 ............................................................................................ 20 更改“外形尺寸”.............................................................................. 24 更改“订购指南”.............................................................................. 24 2006年12月—修订版B至修订版C 更新格式 ...................................................................................... 通篇更改“技术规格”................................................................................ 3 更改“抖动考虑”部分 ..................................................................... 19 更改表8“物料清单” ....................................................................... 20 更改图43“评估板原理图” ............................................................ 21 更改图44和图46 ............................................................................. 22 更新“外形尺寸”.............................................................................. 23 更改“订购指南”.............................................................................. 23

SUB75P05-08中文资料

30
0 0 20 40 60 80 100
0 0 20 40 60 80 100 120
ID – Drain Current (A)
ID – Drain Current (A)
Capacitance
12000 20
Gate Charge
V GS – Gate-to-Source Voltage (V)
元器件交易网
SUP/SUB75P05-08
New Product
Vishay Siliconix
P-Channel 55-V (D-S), 175_C MOSFET
PRODUCT SUMMARY
V(BR)DSS (V)
–55
rDS(on) (W)
0.008
ID (A)
–75a
120 TC = –55_C g fs – Transconductance (S) 90 25_C 125_C r DS(on)– On-Resistance ( W ) 0.06
On-Resistance vs. Drain Current
0.05
0.04
60
0.03
0.02 VGS = 4.5 V 0.01 VGS = 10 V
Source-Drain Diode Ratings and Characteristics (TC = 25_C)b
Continuous Current Pulsed Current Forward Voltagea Reverse Recovery Time Peak Reverse Recovery Current Reverse Recovery Charge Is ISM VSD trr IRM(REC) Qrr IF = –75 A, di/dt = 100 A/ms 75 A di/d A/ IF = –75 A, VGS = 0 V –1.1 60 2.2 0.176 –75 A –240 –1.3 120 3.5 0.21 V ns A mC

AD408M182VBB-5中文资料

ASCEND Semiconductor 4Mx4 EDO Data sheetDescriptionThe device CMOS Dynamic RAM organized as 4,194,304 words x 4 bits with extended data out access mode. It is fabricated with an advanced submicron CMOS technology and designed to operate from a single 3.3V oniy power supply. Low voltage operation is more suitable to be used on battery backup, portable elec-tronic application. lt is packaged in JEDEC standard 26/24-pin plastic SOJ or TSOP(II).Features• Single 3.3V(%) only power supply • High speed t RAC acess time: 50/60ns • Low power dissipation- Active mode : 432/396 mW (Mas) - Standby mode: 0.54 mW (Mas)• Extended - data - out(EDO) page mode access • I/O level: CMOS level (Vcc = 3.3V)• 2048 refresh cycle in 32 ms(Std.) or 128 ms(S-version)• 4 refresh modesh: - RAS only refresh- CAS - before - RAS refresh - Hidden refresh - Self-refresh(S-version)10±Pin Name FunctionA0-A10Address inputs- Row address - Column address - Refresh address DQ1~DQ4Data-in / data-out RAS Row address strobe CAS Column address strobe WE Write enable OE Output enable Vcc Power (+ 3.3V)VssGroundVCC 1DQ12DQ23DQ34DQ45VCC6891011 NC 12 WE 13A0 A117 A218 A319VSS RAS CAS OE A8A7A6A5A4VSSAD404M42VSPin Description Pin Configuration21222324 2526151416 A1026/24-PIN 300mil Plastic SOJA9VCC 1DQ12DQ23DQ34DQ45VCC6891011 NC 12 WE 13A0 A117 A218 A319VSS RAS CAS OE A8A7 A6A5 A4VSSAD404M42VT212223242526151416 A1026/24-PIN 300mil Plastic TSOP (ll)A9A0-A10A0-A10A0-A10WECASNO. 2 CLOCK GENERATORCOLUMN ADDRESS BUFFERS (11)REFRESH CONTROLLERREFRESH COUNTERBUFFERS (11)ADDRESS ROW NO. 1 CLOCK GENERATORA0RASA1A2A3A4A5A6A7A8CONTROLLOGICDATA-IN BUFFERDATA-OUT BUFFEROEDQ1.DQ4.COLUMN DECODER2048SENSE AMPLIFIERSI/O GATING2048x42048x2048x4MEMORY ARRAY2048R O W D E C O D E RVcc VssBlock DiagramA9A10TRUTH TABLENotes: 1. EARLY WRITE only.FUNCTIONRASCAS WE OE ADDRESSESDQ SNotesROW COL STANDBY H X X X X High-Z READL L H L ROW COL Data-Out WRITE: (EARLY WRITE )L L L X ROW COL Data-lnREAD WRITE L L ROW COL Data-Out,Data-ln EDO-PAGE-MODE READ1st Cycle L H L ROW COL Data-Out 2nd CycleL H L n/a COL Data-Out EDO-PAGE MODE WRITE1st CycleL L X ROW COL Data-In 2nd Cycle L L Xn/a COL Data-InEDO-PAGE-MODEREAD-WRITE 1st Cycle L ROW COL Data-Out, Data-In 2nd Cycle L n/a COL Data-Out, Data-In HIDDEN REFRESHREAD L H L ROW COL Data-Out WRITEL L X ROW COL Data-In 1RAS-ONLY REFRESH L H X X ROW n/a High-Z CBR REFRESHLHXXXHigh-ZH X →H L →L H →H L →H L →H L →H L →H L →H L →L H →H L →H L →L H→L H L →→L H L→→H L→Absolute Maximum RatingsRecommended DC Operating ConditionsCapacitanceTa = 25°C, V CC = 3.3V%, f = 1MHz Note: 1. Capacitance measured with effective capacitance measuring method. 2. RAS, CAS = V IH to disable Dout.ParameterSymbol Value Unit Voltage on any pin relative to Vss V T -0.5 to + 4.6V Supply voltage relative to Vss V CC -0.5 to + 4.6V Short circuit output current I OUT 50mA Power dissipation P D 1.0WOperating temperature T OPT 0 to + 70°C Storage temperatureT STG-55 to + 125°CParameter/Condition Symbol3.3 Volt VersionUnitMinTyp MaxSupply VoltageV CC 3.0 3.33.6V Input High Voltage, all inputs V IH 2.0-V CC + 0.3V Input Low Voltage, all inputsV IL-0.3-0.8VParameterSymbol Typ Max Unit Note Input capacitance (Address)C I1 -5pF 1Input capacitance (RAS, CAS, OE, WE)C I2-7pF 1Output capacitance(Data-in, Data-out)C I/O-7pF1, 210±DC Characteristics :(T a = 0 to 70°C, V CC = + 3.3V%, V SS = 0V)Parameter Symbol Test Conditions AD404M42V Unit Notes-5-6Min Max Min MaxOperating current I CC1RAS cyclingCAS, cyclingt RC = min-120-110mA1, 2Standby Current LowpowerS-versionI CC2LVTTL interfaceRAS, CAS = V IHDout = High-Z-0.5-0.5mACMOS interfaceRAS, -0.2VDout = High-Z-0.15-0.15mAStandardpowerversionLVTTL interfaceRAS, CAS = V IHDout = High-Z-2-2mACMOS interfaceRAS,-0.2VDout = High-Z-0.5-0.5mARAS- only refresh current I CC3RAS cycling, CAS = V IHt RC = min-120-110mA1, 2 EDO page mode current I CC4t PC = min-90-80mA1, 3CAS- before- RAS refresh current I CC5t RC = minRAS, CAS cycling-120-110mA1, 2Self- refresh current (S-Version)I CC8 - 550 - 55010±CAS V CC≥CAS V CC≥t RASS100µs≥µADC Characteristics :(T a = 0 to 70°C , V CC = +3.3V %, V SS = 0V)Notes:1. I CC is specified as an average current. It depends on output loading condition and cycle rate when the device is selected. I CC max is specified at the output open condition.2. Address can be changed once or less while RAS = V IL .3. For I CC4, address can be changed once or less within one EDO page mode cycle time.Parameter Symbol Test Conditions AD404M42VUnitNotes-5-6Min MaxMin MaxInput leakage current I LI + 0.3V -55-55Output leakage current I LO + 0.3V Dout = Disable -55-55Output high Voltage V OH I OH = -2mA 2.4- 2.4-V Output low voltage V OLI OL = +2mA-0.4-0.4V10±0V Vin V CC ≤≤µA 0V Vout V CC ≤≤µAAC Characteristics(T a = 0 to + 70°C , V cc = 3.3V %, V ss = 0V) *1, *2, *3, *4Test conditions• Output load: one TTL Load and 100pF (V CC = 3.3V %)• Input timing reference levels:V IH = 2.0V, V IL = 0.8V (V CC = 3.3V %)• Output timing reference levels:V OH = 2.0V, V OL = 0.8V10±10±10±Read, Write, Read- Modify- Write and Refresh Cycles (Common Parameters)ParameterSymbol AD404M42V UnitNotes-5-6Min MaxMin MaxRandom read or write cycle time t RC 84-104-ns RAS precharge timet RP 30-40-ns CAS precharge time in normal mode t CPN 10-10-ns RAS pulse width t RAS 50100006010000ns 5CAS pulse width t CAS 8100001010000ns 6Row address setup time t ASR 0-0-ns Row address hold time t RAH 8-10-ns Column address setup time t ASC 0-0-ns 7Column address hold time t CAH 8-10-ns RAS to CAS delay timet RCD 12371445ns 8RAS to column address delay time t RAD 10251230ns 9Column address to RAS lead time t RAL 25-30-ns RAS hold time t RSH 8-10-ns CAS hold timet CSH 38-40-ns CAS to RAS precharge time t CRP 5-5-ns 10OE to Din delay time t OED 12-15-ns Transition time (rise and fall)t T 150150ns 11Refresh periodt REF -32-32ms Refresh period (S- Version)t REF -128-128ms CAS to output in Low- Z t CLZ 0-0-ns CAS delay time from Din t DZC 0-0-ns OE delay time from Dint DZO-0-nsRead CycleWrite Cycle Parameter SymbolAD404M42V Unit Notes-5-6Min Max Min MaxAccess time from RAS t RAC-50-60ns12 Access time from CAS t CAC-14-15ns13, 14 Access time from column address t AA-25-30ns14, 15 Access time from OE t OEA-12-15nsRead command setup time t RCS0-0-ns7 Read command hold time to CAS t RCH0-0-ns10, 16 Read command hold time to RAS t RRH0-0-ns16 Output buffer turn-off time t OFF012015ns17 Output buffer turn-off time from OE t OEZ012015ns17Parameter SymbolAD404M42V Unit Notes -5-6Min Max Min MaxWrite command setup time t WCS0-0-ns7, 18 Write command hold time t WCH8-10-nsWrite command pulse width t WP8-10-nsWrite command to RAS lead time t RWL13-15-nsWrite command to CAS lead time t CWL8-10-nsData-in setup time t DS0-0-ns19 Data-in hold time t DH8-10-ns19 WE to Data-in delay t WED10-10-nsRead- Modify- Write CycleRefresh Cycle Parameter SymbolAD404M42V Unit Notes-5-6Min Max Min MaxRead-modify- write cycle time t RWC108-133-nsRAS to WE delay time t RWD64-77-ns18 CAS to WE dealy time t CWD26-32-ns18 Column address to WE delay time t AWD39-47-ns18 OE hold time from WE t OEH8-10-nsParameter SymbolAD404M42VUnit Notes -5-6Min Max Min MaxCAS setup time (CBR refresh) t CSR5-5-nsCAS hold time (CBR refresh)t CHR8-10-ns10 RAS precharge to CAS hold time t RPC5-5-ns7 RAS pulse width (self refresh)t RASS100-100-RAS precharge time (self refresh)t RPS90-110-nsCAS hold time (CBR self refresh)t CHS-50--50-nsWE setup time t WSR0-0-nsWE hold time t WHR10-10-nsµsEDO Page Mode CycleEDO Page Mode Read Modify Write CycleParameterSymbol AD404M42VUnit Notes-5-6Min MaxMin MaxEDO page mode cycle timet PC 20-25-ns EDO page mode CAS precharge time t CP 10-10-ns EDO page mode RAS pulse width t RASP 5010560105ns 20Access time from CAS precharge t CPA -30-35ns 10, 14RAS hold time from CAS precharge t CPRH 30-35-ns OE high hold time from CAS high t OEHC 5-5-ns OE high pulse widtht OEP 10-10-ns Data output hold time after CAS low t COH 5-5-ns Output disable delay from WEt WHZ 310310ns WE pulse width for output disable whenCAS hight WPZ7-7-nsParameterSymbol AD404M42V Unit Notes -5-6Min MaxMin MaxEDO page mode read- modify- write cycle CAS precharge to WE delay timet CPW 45-55-ns 10EDO page mode read- modify- write cycle timet PRWC56-68-nsNotes :1. AC measurements assume t T = 2ns.2. An initial pause of 100 is required after power up, and it followed by a minimum of eightinitialization cycles (RAS - only refresh cycle or CAS - before - RAS refresh cycle). If the internal refresh counter is used, a minimun of eight CAS - before - RAS refresh cycles are required.3. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device.4. All the V CC and V SS pins shall be supplied with the same voltages.5. t RAS (min) = t RWD (min)+t RWL (min)+t T in read-modify-write cycle.6. t CAS (min) = t CWD (min)+t CWL (min)+t T in read-modify-write cycle.7. t ASC (min), t RCS (min), t WCS (min), and t RPC are determined by the falling edge of CAS .8. t RCD (max) is specified as a reference point only, and t RAC (max) can be met with the t RCD (max) limit.Otherwise, t RAC is controlled exclusively by t CAC if t RCD is greater than the specified t RCD (max) limit. 9. t RAD (max) is specified as a reference point only, and t RAC (max) can be met with the t RAD (max) limit.Otherwise, t RAC is controlled exclusively by t AA if t RAD is greater than the specified t RAD (max) limit. 10. t CRP , t CHR , t RCH , t CPA and t CPW are determined by the rising edge of CAS .11. V IH (min) and V IL (max) are reference levels for measuring timing or input signals. Therefore, transitiontime is measured between V IH and V IL .12. Assumes that t RCD tRCD (max) and t RAD t RAD (max). If t RCD or t RAD is greater than the maximum recommended value shown in this table, t RAC exceeds the value shown. 13. Assumes that (max) and (max).14. Access time is determined by the maximum of t AA , t CAC , t CPA . 15. Assumes that (max) and (max). 16. Either t RCH or t RRH must be satisfied for a read cycle.17. t OFF (max) and t OEZ (max) define the time at which the output achieves the open circuit condition (highimpedance). t OFF is determined by the later rising edge of RAS or CAS.18. t WCS , t RWD , t CWD , and t AWD are not restrictive operating parameters. They are included in the datasheet as electrical characteristics only. If (min), the cycle is an early write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. If (min),(min), (min) and (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell. If neither of the above sets of conditions is satisfied, the condition of the data output (at access time) is indeterminate.19. These parameters are referenced to CAS separately in an early write cycle and to WE edge in adelayed write or a read-modify-write cycle.20. t RASP defines RAS pulse width in EDO page mode cycles.µs ≤≤t RCD t RCD ≥t RADt RAD ≤t RCD t RCD ≤t RAD t RAD ≥t WCS t WCS ≥t RWD t RWD ≥t CWDt CWD ≥t AWD t AWD ≥t CPW t CPW≥Timing Waveforms• Read Cyclet RC t RASt RPtCRPtCPNtRRHtRCHt OEZ t OFF tOEA tCACt AAtRACt CLZD OUTtRCS t ASR tRAH tASC tCAH tRAD t RALtCAStRSH tRCDt TtCSHRASCASADDRESSWEDQ1~DQ4Note : = don’t care OEt OFFRowColumn= Invalid Dout•Early Write CycletRC t RASt RPt WCHt DSt DHt WCS t RALtCAStRSH tRCDt TtCSHRASCASWEDQ1~DQ4tCRPtASRtRAH tASCtCAH ADDRESSColumnRowtCPND INtRADt RAL• Delayed Write CycletRC t RASt RPt RWL t RCSt CAStRSH tRCDt TtCSHRASCAStASR tRAH tCAHADDRESSColumnRow tASC D INDQ1~DQ4WEtCRPtCPNt DHt DSt OEHt OEDOEt DSOPENt WPt CWL• Read - Modify - Write CycletRWC t RASt RPtRWDt WPtRADtRWL tCAStCWL tRCDt TtCPNRASCASWEtCRP t ASRtRAHtASCtCAHADDRESS Column RowDQ1~DQ4t DHt DSOEtRCStAWD tCWD D INt OEDt OEHt OEZt OEA t CAC t RACt AADQ1~DQ4D OUTOPENtDZCtDZO• EDO Page Mode Read CycletRASPtCPRHt RCStCAStRSH tRCDt OEAtCSHRASCAStASRtRAHtCAHADDRESStCASWEtCRPt CPOEDQ1~DQ4OPENtOEPD OUT 1t PCt CPtCAStCPNtCRPtRADtCAHtASCt ASCtCAHt ASCt RAL Row Column 1t OEAt OEHCtRRH tRCHt RACt AAt AAt AA t CPA t CPA t OEZt OFFt OFFt CACt OEZt CAC t CACt COHD OUT NWE OE Column 2Column N Rowt RPD OUT 2• EDO Page Mode Early Write CycletRASPtRPt WCSt CAStRSH tRCDRASCAStASRtRAHtCAHADDRESStCASWEt CPDQ1~DQ4t PCt CPt CAStCPNtCRP tCAH tASCtASC tCAH tASC Row Column 1t DS WE Column 2Column Nt WCH t WCS t WCH t WCS t WCHt DH t DS t DH t DS t DHD IN 1D IN 2D IN Nt TtCSH• EDO Page Mode Read-Early-Write Cyclet RASPtCPRHt RCStCAStRSH tRCDt OEAtCSHRASCAStASRtRAHtCAHADDRESStCASWEtCRPt CPOEDQ1~DQ4OPENtWEDt PCt CPtCAStCPNtCRPtRADtRAHtASCt ASCtCAHt ASCt RAL Row Column 1tWCStRCHt RACt AAt AAt CPA t DHt WHZt CACt CACt COHWE OE Column 2Column N Rowt RPt CAL tWCHDataDoutput 2Data Input NDataDoutput 1t DStCSH• EDO Page Mode Read-Modify-Write Cyclet RASPt CPRHt RCStCASt WP RASCASt ASRtRAHtCAHADDRESSt CASWEtRCDCPDQ1~DQ4tPRWCt CPtCAStCRPtRADtCAHtASCt ASCtCAH tASC Row Column 1tRWLtRCSt OEDt DZOt CAC WE OEt RPt RAL D OUT 2D OUT ND OUT 1tTt Column NColumn 2Column 1tRWD tAWD tCWDtCWLtRCStCWDtAWD tCPW tCWL tCPW tAWD tCWDtCWL t OEDt OEDt OEHt OEHt OEHt CAC t CAC t OEA t AAt RACt OEZt OEAt AA t CPAt OEZt OEAt AA t CPAt OEZ t DSt DHt WP t DSt DHt WP t DSt DHOPENOPENOPEN D IN 1D IN ND IN 2DQ1~DQ4t DZCt DZOt DZCt DZCt DZO• Read Cycle with WE Controlled Disablet WPZt RCStCAStRCDt TtCSHRASCASt ASRtRAHtCAHADDRESSColumnRow tASCD DQ1~DQ4WEt OEZt DSt WHZOEt RCH t OEA t CACt AAt RACt CLZOUTtRADRASADDRESSt RC t CRPt ASRt RAHt Tt RPCROWt OFFCAS t RASt RPOPENt CRPDQ1~DQ4RASt CSRt WSRt RPt T t RPCt OFFCAS t RASt RPOPENt CRPDQ1~DQ4t RPCt CHRt RASt RPt RCt RCt CHRt CSRt WHRt WSRt WHRWECAS-Before-RAS Refresh CycleRASWEt RPCt OFFt CSRt CHSt WSRCASt RASS t RPSOPENDQ1~DQ4t WHRHigh lmpedance• Hidden Refresh Cyclet RPt RASRASt RCDt CRPADDRESSWEt CHRt CASt RSHt RAHt ASRt ASCt CAHt RAL ROW t RCHt OEZCASDQ1~DQ4t Tt RCSD t RASt RASt RPt RPt RC t RCt RCt RADt RRHt OFF t OFFt OEA t CACt AAt RACCOlumnOUTOE(READ)(REFRESH)(REFRESH)Ordering informationAD404M42VSA-5• AD• Ascend Memory Product • 40 • Device Type• 4M4 • Density and Organization • 2• Refresh Rate, 2: 2K Refresh • V• T: 5V, V: 3.3V• S • Package Type (S : SOJ, T : TSOP II)• A• Version• 5• Speed (5: 50 ns, 6: 60 ns)Part Number Access time PackageAD404M42VSA-5AD404M42VSA-6AD404M42VTA-5AD404M42VTA-650 ns 60 ns 50 ns 60 ns300mil 26/24-Pin Plastic SOJTSOP IIPackaging information • 300 mil, 26/24-Pin Plastic SOJ• 300 mil, 26/24-Pin TSOP II。

AD8005中文资料

TMIN to TMAX Offset Drift +Input Bias Current TMIN to TMAX –Input Bias Current Input Bias Current Drift (± ) Open-Loop Transimpedance INPUT CHARACTERISTICS Input Resistance Input Capacitance Input Common-Mode Voltage Range Common-Mode Rejection Ratio OUTPUT CHARACTERISTICS Output Voltage Swing Output Current Short Circuit Current POWER SUPPLY Quiescent Current Power Supply Rejection Ratio OPERATING TEMPERATURE RANGE
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FEATURES Ultralow Power 400 ␮ A Power Supply Current (4 mW on ؎5 VS) Specified for Single Supply Operation High Speed 270 MHz, –3 dB Bandwidth (G = +1) 170 MHz, –3 dB Bandwidth (G = +2) 280 V/␮ s Slew Rate (G = +2) 28 ns Settling Time to 0.1%, 2 V Step (G = +2) Low Distortion/Noise –63 dBc @ 1 MHz, V O = 2 V p-p –50 dBc @ 10 MHz, VO = 2 V p-p 4.0 nV/√Hz Input Voltage Noise @ 10 MHz Good Video Specifications (RL = 1 k⍀, G = +2) Gain Flatness 0.1 dB to 30 MHz 0.11% Differential Gain Error 0.4؇ Differential Phase Error APPLICATIONS Signal Conditioning A/D Buffer Power-Sensitive, High-Speed Systems Battery Powered Equipment Loop/Remote Power Systems Communication or Video Test Systems Portable Medical Instruments PRODUCT DESCRIPTION

M393T5166AZA-CC中文资料

DDR2 Registered SDRAM MODULE 240pin Registered Module based on 1Gb A-die72-bit ECCINFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,AND IS SUBJECT TO CHANGE WITHOUT NOTICE.NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDEDON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.1. For updates or additional information about Samsung products, contact your nearest Samsung office.2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similarapplications where Product failure couldresult in loss of life or personal or physical harm, or any military ordefense application, or any governmental procurement to which special terms or provisions may apply.* Samsung Electronics reserves the right to change products or specification without notice.Table of Contents1.0 DDR2 Registered DIMM Ordering Information (4)2.0 Features (4)3.0 Address Configuration (4)4.0 Pin Configurations (Front side/Back side) (5)5.0 Pin Description (6)6.0 Input/Output Function Description (7)7.0 Functional Block Diagram (8)7.1 1GB, 128Mx72 Module (M393T2863AZ3/M393T2863AZA) (8)7.2 2GB, 256Mx72 Module (M393T5663AZ3/M393T5663AZA) (9)7.3 2GB, 256Mx72 Module (M393T5660AZ3/M393T5660AZA) (10)7.4 4GB, 512Mx72 Module (M393T5168AZ0/M393T5166AZA) (11)8.0 Absolute Maximum DC Ratings (12)9.0 AC & DC Operating Conditions (12)9.1 Operating Temperature Condition (13)9.2 Input DC Logic Level (13)9.3 Input AC Logic Level (13)9.4 AC Input Test Conditions (13)10.0 IDD Specification Parameters Definition (14)11.0 Operating Current Table(1-1) (15)11.1 M393T2863AZ3/M393T2863AZA : 1GB(128Mx8 *9) Module (15)11.2 M393T5663AZ3/M393T5663AZA : 2GB(128Mx8 *18) Module (15)11.3 M393T5660AZ3/M393T5660AZA : 2GB(256Mx4 *18) Module (16)11.4 M393T5168AZ0/M393T5166AZA : 4GB(st.512Mx4 *18) Module (16)12.0 Input/Output Capacitance (17)13.0 Electrical Characteristics & AC Timing for DDR2-667/533/400 (18)13.1 Refresh Parameters by Device Density (18)13.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin (18)13.3 Timing Parameters by Speed Grade (18)14.0 Physical Dimensions (20)14.1 128Mbx8 based 128Mx72 Module(1 Rank) (M393T2863AZ3/M393T2863AZA) (20)14.2 128Mbx8/256Mbx4 based 256Mx72 Module(2/1 Ranks)(M393T5663AZ3/M393T5663AZA/ M393T5660AZ3/M393T5660AZA) (21)14.3 st.512Mbx4 based 512Mx72 Module(2 Ranks) (M393T5168AZ0/M393T5166AZA) (22)15.0 240 Pin DDR2 Registered DIMM Clock Topology (23)Revision HistoryRevision Month Year History1.0July2005 - Initial Release1.1Aug.2005 - Revised IDD Current Values1.2Sep.2005 - Revised the Ordering InformationDDR2 Registered DIMM Ordering InformationPart Number Density Organization Component Composition Number of Rank Parity Register Height M393T2863AZ3-CD5/CC1GB128Mx72128Mx8(K4T1G084QA)*9EA1X30mm M393T2863AZA-CE6/D5/CC1GB128Mx72128Mx8(K4T1G084QA)*9EA1O30mm M393T5663AZ3-CD5/CC2GB256Mx72128Mx8(K4T1G084QA)*18EA2X30mm M393T5663AZA-CE6/D5/CC2GB256Mx72128Mx8(K4T1G084QA)*18EA2O30mm M393T5660AZ3-CD5/CC2GB256Mx72256Mx4(K4T1G044QA)*18EA1X30mm M393T5660AZA-CE6/D5/CC2GB256Mx72256Mx4(K4T1G044QA)*18EA1O30mm M393T5168AZ0-CD5/CC4GB512Mx72st.512Mx4(K4T2G064QA)*18EA2X30mm M393T5166AZA-CE6/D5/CC4GB512Mx72st.512Mx4(K4T2G264QA)*18EA2O30mm Note: “Z” of Part number(11th digit) stand for Lead-free products.Note: “3” of Part number(12th digit) stand for Dummy Pad PCB products.Note: "A" of Part number(12th digit) stand for Parity Register products.Features•Performance rangeE6(DDR2-667)D5(DDR2-533)CC(DDR2-400)UnitSpeed@CL3400400400MbpsSpeed@CL4533533400MbpsSpeed@CL5667533-MbpsCL-tRCD-tRP5-5-54-4-43-3-3CK•JEDEC standard 1.8V ± 0.1V Power Supply•V DDQ = 1.8V ± 0.1V•200 MHz f CK for 400Mb/sec/pin, 267MHz f CK for 533Mb/sec/pin, 333MHz f CK for 667Mb/sec/pin•8Banks•Posted CAS•Programmable CAS Latency: 3, 4, 5•Programmable Additive Latency: 0, 1 , 2 , 3 and 4•Write Latency(WL) = Read Latency(RL) -1•Burst Length: 4 , 8(Interleave/nibble sequential)•Programmable Sequential / Interleave Burst Mode•Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional feature)•Off-Chip Driver(OCD) Impedance Adjustment•On Die Termination with selectable values(50/75/150 ohms or disable)•PASR(Partial Array Self Refresh)•Average Refresh Period 7.8us at lower than a T CASE 85°C, 3.9us at 85°C < T CASE < 95 °C- support High Temperature Self-Refresh rate enable feature•Serial presence detect with EEPROM•DDR2 SDRAM Package: 68ball FBGA - 256Mx4/128Mx8, 56ball BGA - st.512Mbx4•All of Lead-free products are compliant for RoHSNote: For detailed DDR2 SDRAM operation, please refer to Samsung’s Device operation & Timing diagram..Address ConfigurationOrganization Row Address Column Address Bank Address Auto Precharge 256Mx4(1Gb) based Module A0-A13A0-A9, A11BA0-BA2A10128Mx8(1Gb) based Module A0-A13A0-A9BA0-BA2A10NC = No Connect, RFU = Reserved for Future Use1. RESET (Pin 18) is connected to both OE of PLL and Reset of register.2. The Test pin (Pin 102) is reserved for bus analysis probes and is not connected on normal memory modules (DIMMs)3. NC/Err_Out ( Pin 55) and NC/Par_In (Pin 68) are for optional function to check address and command parity.4. CKE1,S1 Pin is used for double side Registered DIMM.Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back 1V REF 121V SS 31DQ19151V SS 61A4181V DDQ 91V SS 211DM5/DQS142V SS 122DQ432V SS 152DQ2862V DDQ 182A392DQS5212NC/DQS143DQ0123DQ533DQ24153DQ2963A2183A193DQS5213V SS 4DQ1124V SS 34DQ25154V SS 64V DD184V DD94V SS 214DQ465V SS 125DM0/DQS935V SS 155DM3/DQS12KEY95DQ42215DQ476DQS0126NC/DQS936DQS3156NC/DQS1265V SS 185CK096DQ43216V SS 7DQS0127V SS 37DQS3157V SS 66V SS 186CK097V SS 217DQ528V SS 128DQ638V SS 158DQ3067V DD 187V DD 98DQ48218DQ539DQ2129DQ739DQ26159DQ3168NC/Par_In 188A099DQ49219V SS 10DQ3130V SS 40DQ27160V SS 69V DD 189V DD 100V SS 220RFU 11V SS 131DQ1241V SS 161CB470A10/AP 190BA1101SA2221RFU 12DQ8132DQ1342CB0162CB571BA0191V DDQ 102NC(TEST)222V SS 13DQ9133V SS 43CB1163V SS 72V DDQ 192RAS 103V SS 223DM6/DQS1514V SS 134DM1/DQS1044V SS 164DM8/DQS1773WE 193S0104DQS6224NC/DQS1515DQS1135NC/DQS1045DQS8165NC/DQS1774CAS 194V DDQ 105DQS6225V SS 16DQS1136V SS 46DQS8166V SS 75V DDQ 195ODT0106V SS 226DQ5417V SS 137RFU 47V SS 167CB676S14196A13107DQ50227DQ5518RESET 138RFU 48CB2168CB777ODT1197V DD 108DQ51228V SS 19NC 139V SS 49CB3169V SS 78V DDQ 198V SS 109V SS 229DQ6020V SS 140DQ1450V SS 170V DDQ 79V SS 199DQ36110DQ56230DQ6121DQ10141DQ1551V DDQ 171CKE1480DQ32200DQ37111DQ57231V SS 22DQ11142V SS 52CKE0172V DD 81DQ33201V SS 112V SS 232DM7/DQS1623V SS 143DQ2053V DD 173NC 82V SS 202DM4/DQS13113DQS7233NC/DQS1624DQ16144DQ2154BA2174NC 83DQS4203NC/DQS13114DQS7234V SS 25DQ17145V SS 55NC/Err_Out 175V DDQ 84DQS4204V SS 115V SS 235DQ6226V SS 146DM2/DQS1156V DDQ 176A1285V SS 205DQ38116DQ58236DQ6327DQS2147NC/DQS1157A11177A986DQ34206DQ39117DQ59237V SS 28DQS2148V SS 58A7178V DD 87DQ35207V SS 118V SS 238VDDSPD 29V SS 149DQ2259V DD 179A888V SS 208DQ44119SDA 239SA030DQ18150DQ2360A5180A689DQ40209DQ45120SCL240SA190DQ41210V SS Pin Configurations (Front side/Back side)* The VDD and VDDQ pins are tied to the single power-plane on PCB.Pin Name DescriptionPin Name Description CK0Clock Inputs, positive line ODT0~ODT1On die termination CK0Clock inputs, negative line DQ0~DQ63Data Input/OutputCKE0, CKE1Clock Enables CB0~CB7Data check bits Input/Output RAS Row Address Strobe DQS0~DQS8Data strobesCAS Column Address Strobe DQS0~DQS8Data strobes, negative line WE Write Enable DM(0~8), DQS(9~17)Data Masks / Data strobes (Read)S0, S1Chip Selects DQS9~DQS17Data strobes (Read), negative line A0~A9, A11~A13Address InputsRFU Reserved for Future Use A10/AP Address Input/Autoprecharge NC No ConnectBA0~BA2DDR2 SDRAM Bank AddressTEST Memory bus test tool(Not Connect and Not Useable on DIMMs)SCL Serial Presence Detect (SPD) Clock Input V DD Core Power SDA SPD Data Input/Output V DDQ I/O Power SA0~SA2SPD addressV SS GroundPar_In Parity bit for the Address and Control bus V REF Input/Output Reference Err_Out Parity error found in the Address and Control bus V DDSPDSPD PowerRESETRegister and PLL control pinPin DescriptionSymbol Type DescriptionCK0Input Positive line of the differential pair of system clock inputs that drives input to the on-DIMM PLL.CK0Input Negative line of the differential pair of system clock inputs that drives the input to the on-DIMM PLL.CKE0~CKE1Input Activates the SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low initiates the Power Down mode, or the Self Refresh mode.S0~S1Input Enables the associated SDRAM command decoder when low and disables decoder when high. When decoder is dis-abled, new commands are ignored but previous operations continue.These input signals also disable all outputs (except CKE and ODT) of the register(s) on the DIMM when both inputs are high.ODT0~ODT1Input I/O bus impedance control signals.RAS, CAS, WE Input When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the operation to be executed by the SDRAM.V REF Supply Reference voltage for SSTL_18 inputsV DDQ Supply Isolated power supply for the DDR SDRAM output buffers to provide improved noise immunity BA0~BA2Input Selects which SDRAM bank of eight is activated.A0~A9,A10/APA11~A13Input During a Bank Activate command cycle, Address defines the row address.During a Read or Write command cycle, Address defines the column address. In addition to the column address, AP is used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high, autoprecharge is selected and BA0, BA1, BA2 defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge com-mand cycle, AP is used in conjunction with BA0, BA1, BA2 to control which bank(s) to precharge. If AP is high, all banks will be precharged regardless of the state of BA0 or BA1 or BA2. If AP is low, BA0 and BA1 and BA2 are used to define which bank to precharge.DQ0~63,CB0~CB7In/Out Data and Check Bit Input/Output pinsDM0~DM8Input Masks write data when high, issued concurrently with input data. Both DM and DQ have a write latency of one clock once the write command is registered into the SDRAM.V DD, V SS Supply Power and ground for the DDR SDRAM input buffers and core logicDQS0~DQS17In/Out Positive line of the differential data strobe for input and output data.DQS0~DQS17In/Out Negative line of the differential data strobe for input and output data.SA0~SA2Input These signals are tied at the system planar to either V SS or V DDSPD to configure the serial SPD EEPROM address range.SDA In/Out This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be connected from the SDA bus line to V DDSPD to act as a pullup.SCL Input This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from the SCL bus time to V DDSPD to act as a pullup.V DDSPD Supply Serial EEPROM positive power supply (wired to a separate power pin at the connector which supports from 1.7 Volt to 3.6 Volt operation).RESET Input The RESET pin is connected to the RST pin on the register and to the OE pin on the PLL. When low, all register outputs will be driven low and the PLL clocks to the DRAMs and register(s) will be set to low level (The PLL will remain synchro-nized with the input clock )Par_In Input Parity bit for the Address and Control bus. ( “1 “ : Odd, “0 “ : Even) Err_Out Input Parity error found in the Address and Control busTEST In/Out Used by memory bus analysis tools (unused on memory DIMMs) Input/Output Function Description(populated as 1 rank of x8 DDR2 SDRAMs)1GB, 128Mx72 Module (M393T2863AZ3/M393T2863AZA)RS0DQS0DQS0DM0/DQS9NC/DQS9DM/ RDQS NU/RDQSCS DQS DQSDQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7I/O 0I/O 1I/O 2I/O 3I/O 4I/O 5I/O 6I/O 7D0DQS1DQS1DM1/DQS10 NC/DQS10DM/ RDQS NU/RDQSCS DQS DQSDQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15I/O 0I/O 1I/O 2I/O 3I/O 4I/O 5I/O 6I/O 7D1DQS2DQS2DM2/DQS11 NC/DQS11DM/ RDQS NU/RDQSCS DQS DQSDQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23I/O 0I/O 1I/O 2I/O 3I/O 4I/O 5I/O 6I/O 7D2DQS3DQS3DM3/DQS12 NC/DQS12DM/ RDQS NU/RDQSCS DQS DQSDQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31I/O 0I/O 1I/O 2I/O 3I/O 4I/O 5I/O 6I/O 7D3DQS8DQS8DM8/DQS17 NC/DQS17DM/ RDQS NU/RDQSCS DQS DQSCB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7I/O 0I/O 1I/O 2I/O 3I/O 4I/O 5I/O 6I/O 7D8DQS4DQS4DM4/DQS13NC/DQS13DM/RDQSNU/RDQSCS DQS DQSDQ32DQ33DQ34DQ35DQ36DQ37DQ38DQ39I/O 0I/O 1I/O 2I/O 3I/O 4I/O 5I/O 6I/O 7D4DQS5DQS5DM5/DQS14NC/DQS14DM/RDQSNU/RDQSCS DQS DQSDQ40DQ41DQ42DQ43DQ44DQ45DQ46DQ47I/O 0I/O 1I/O 2I/O 3I/O 4I/O 5I/O 6I/O 7D5DQS6DQS6DM6/DQS15NC/DQS15DM/RDQSNU/RDQSCS DQS DQSDQ48DQ49DQ50DQ51DQ52DQ53DQ54DQ55I/O 0I/O 1I/O 2I/O 3I/O 4I/O 5I/O 6I/O 7D6DQS7DQS7DM7/DQS16NC/DQS16DM/RDQSNU/RDQSCS DQS DQSDQ56DQ57DQ58DQ59DQ60DQ61DQ62DQ63I/O 0I/O 1I/O 2I/O 3I/O 4I/O 5I/O 6I/O 7D7A0Serial PDA1A2SA0SA1SA2SCL SDAV SS D0 - D8V DD/V DDQ D0 - D8D0 - D8VREFV DDSPD Serial PDWPNotes :1. DQ-to-I/O wiring may be changed within a byte.2. DQ/DQS/DM/CKE/S relationships must be maintained as shown.3. Unless otherwise noted, resister values are 22 Ohms1:1REGISTERRSTS0*BA0-BA2A0-A13RASCASWECKE0ODT0RESETPCK7PCK7RSO-> CS : DDR2 SDRAMs D0-D8RBA0-RBA2 -> BA0-BA2 : DDR2 SDRAMs D0-D8RA0-RA13 -> A0-A13 : DDR2 SDRAMs D0-D8RRAS -> RAS : DDR2 SDRAMs D0-D8RCAS -> CAS : DDR2 SDRAMs D0-D8RWE -> WE : DDR2 SDRAMs D0-D8RCKE0 -> CKE : DDR2 SDRAMs D0-D8RODT0 -> ODT0 : DDR2 SDRAMs D0-D8PLLOECK0CK0RESETPCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D8PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D8PCK7 -> CK : RegisterPCK7 -> CK : Register* S0 connects to DCS and VDD connects to CSR on the register.Functional Block DiagramSignals for Address and Command Parity Function (M393T2863AZA)V SSV SS PAR_IN C0C1PPOQERR Err_Out RegisterPAR_IN100K ohmsThe resistors on Par_In, A13, A14, A15, BA2 and the signal line of Err_Out refer to the section: "Register Options for Unused Address inputs"RS0DQS0DQS0DM0/DQS9NC/DQS9DM/RDQS NU/RDQSCS DQS DQSDQ0DQ1DQ2DQ3DQ4DQ5DQ6DQ7I/O 0I/O 1I/O 2I/O 3I/O 4I/O 5I/O 6I/O 7D0DQS1DQS1DM1/DQS10NC/DQS10DM/RDQS NU/RDQSCS DQS DQSDQ8DQ9DQ10DQ11DQ12DQ13DQ14DQ15I/O 0I/O 1I/O 2I/O 3I/O 4I/O 5I/O 6I/O 7D1DQS2DQS2DM2/DQS11NC/DQS11DM/RDQS NU/RDQSCS DQS DQSDQ16DQ17DQ18DQ19DQ20DQ21DQ22DQ23I/O 0I/O 1I/O 2I/O 3I/O 4I/O 5I/O 6I/O 7D2DQS3DQS3DM3/DQS12NC/DQS12DM/RDQS NU/RDQSCS DQS DQSDQ24DQ25DQ26DQ27DQ28DQ29DQ30DQ31I/O 0I/O 1I/O 2I/O 3I/O 4I/O 5I/O 6I/O 7D3DQS8DQS8DM8/DQS17NC/DQS17DM/RDQS NU/RDQSCS DQS DQSCB0CB1CB2CB3CB4CB5CB6CB7I/O 0I/O 1I/O 2I/O 3I/O 4I/O 5I/O 6I/O 7D8DQS4DQS4DM4/DQS13NC/DQS13DM/RDQS NU/RDQSCS DQS DQSDQ32DQ33DQ34DQ35DQ36DQ37DQ38DQ39I/O 0I/O 1I/O 2I/O 3I/O 4I/O 5I/O 6I/O 7D4DQS5DQS5DM5/DQS14NC/DQS14DM/RDQS NU/RDQSCS DQS DQSDQ40DQ41DQ42DQ43DQ44DQ45DQ46DQ47I/O 0I/O 1I/O 2I/O 3I/O 4I/O 5I/O 6I/O 7D5DQS6DQS6DM6/DQS15NC/DQS15DM/RDQS NU/RDQSCS DQS DQSDQ48DQ49DQ50DQ51DQ52DQ53DQ54DQ55I/O 0I/O 1I/O 2I/O 3I/O 4I/O 5I/O 6I/O 7D6DQS7DQS7DM7/DQS16NC/DQS16DM/RDQS NU/RDQSCS DQS DQSDQ56DQ57DQ58DQ59DQ60DQ61DQ62DQ63I/O 0I/O 1I/O 2I/O 3I/O 4I/O 5I/O 6I/O 7D7DM/RDQS NU/RDQSCS DQS DQSI/O 0I/O 1I/O 2I/O 3I/O 4I/O 5I/O 6I/O 7D9DM/RDQS NU/RDQSCS DQS DQSI/O 0I/O 1I/O 2I/O 3I/O 4I/O 5I/O 6I/O 7D10DM/RDQS NU/RDQSCS DQS DQSI/O 0I/O 1I/O 2I/O 3I/O 4I/O 5I/O 6I/O 7D11DM/RDQS NU/RDQSCS DQS DQSI/O 0I/O 1I/O 2I/O 3I/O 4I/O 5I/O 6I/O 7D12DM/RDQS NU/RDQSCS DQS DQSI/O 0I/O 1I/O 2I/O 3I/O 4I/O 5I/O 6I/O 7D17DM/RDQS NU/RDQSCS DQS DQSI/O 0I/O 1I/O 2I/O 3I/O 4I/O 5I/O 6I/O 7D13DM/RDQS NU/RDQSCS DQS DQSI/O 0I/O 1I/O 2I/O 3I/O 4I/O 5I/O 6I/O 7D14DM/RDQS NU/RDQSCS DQS DQSI/O 0I/O 1I/O 2I/O 3I/O 4I/O 5I/O 6I/O 7D15DM/RDQS NU/RDQSCS DQS DQSI/O 0I/O 1I/O 2I/O 3I/O 4I/O 5I/O 6I/O 7D16RS1A0Serial PDA1A2SA0SA1SA2SCLSDAV SSD0 - D17V DD /V DDQ D0 - D17D0 - D17VREF V DDSPDSerial PD WP Notes :1. DQ-to-I/O wiring may be changed per nibble.2. Unless otherwise noted, resister values are 22 Ohms3. RS0 and RS1 alternate between the back and front sides of the DIMM1:2R E G I S T E RRSTS1*BA0-BA2A0-A13RAS CAS WE CKE0CKE1RESET**PCK7**PCK7**RS1-> CS : DDR2 SDRAMs D9-D17RBA0-RBA2 -> BA0-BA2: DDR2 SDRAMs D0-D17RA0-RA13 -> A0-A13 : DDR2 SDRAMs D0-D17RRAS -> RAS : DDR2 SDRAMs D0-D17RCAS -> CAS : DDR2 SDRAMs D0-D17RWE -> WE : DDR2 SDRAMs D0-D17RCKE0 -> CKE : DDR2 SDRAMs D0-D8RCKE1 -> CKE : DDR2 SDRAMs D9-D17P L LOECK0CK0RESETPCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D17PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D17PCK7 -> CK : Register PCK7 -> CK : RegisterODT0ODT1RODT0 -> ODT0 : DDR2 SDRAMs D0-D8RODT1 -> ODT1 : DDR2 SDRAMs D9-D17S0*RSO-> CS : DDR2 SDRAMs D0-D8(populated as 2 rank of x8 DDR2 SDRAMs)2GB, 256Mx72 Module (M393T5663AZ3/M393T5663AZA)* S0 connects to DCS and S0 connects to CSR on a Register,S1 connects to DCS and S0 connects to CSR on another Register.** RESET, PCK7 and PCK7 connects to both Registers. Other signals connect to one of two Registers.Signals for Address and Command Parity Function (M393T5663AZA)V SS V DDPAR_IN C0C1PPO QERRRegister APAR_IN 100K ohmsThe resistors on Par_In, A13, A14, A15, BA2 and the signal line of Err_Out refer to the section: "Register Options for Unused Address inputs"V DD V DDC0C1PPO QERRErr_OutRegister BPAR_INVSSRS0DQS0DQS0DM CS DQS DQSDQ0 DQ1 DQ2 DQ3I/O 0I/O 1I/O 2I/O 3D0DM0/DQS9NC/DQS9DM CS DQS DQSDQ4DQ5DQ6DQ7I/O 0I/O 1I/O 2I/O 3D9DQS1DQS1DM CS DQS DQSDQ8 DQ9 DQ10 DQ11I/O 0I/O 1I/O 2I/O 3D1DM1/DQS10NC/DQS10DM CS DQS DQSDQ12DQ13DQ14DQ15I/O 0I/O 1I/O 2I/O 3D10DQS2DQS2DM CS DQS DQSDQ16 DQ17 DQ18 DQ19I/O 0I/O 1I/O 2I/O 3D2DM2/DQS11NC/DQS11DM CS DQS DQSDQ20DQ21DQ22DQ23I/O 0I/O 1I/O 2I/O 3D11DQS3DQS3DM CS DQS DQSDQ24 DQ25 DQ26 DQ27I/O 0I/O 1I/O 2I/O 3D3DM3/DQS12NC/DQS12DM CS DQS DQSDQ28DQ29DQ30DQ31I/O 0I/O 1I/O 2I/O 3D12DQS5DQS5DM CS DQS DQSDQ40 DQ41 DQ42 DQ43I/O 0I/O 1I/O 2I/O 3D5DM5/DQS14NC/DQS14DM CS DQS DQSDQ44DQ45DQ46DQ47I/O 0I/O 1I/O 2I/O 3D14DQS4DQS4DM CS DQS DQSDQ32 DQ33 DQ34 DQ35I/O 0I/O 1I/O 2I/O 3D4DM4/DQS13NC/DQS13DM CS DQS DQSDQ36DQ37DQ38DQ39I/O 0I/O 1I/O 2I/O 3D13DQS6DQS6DM CS DQS DQSDQ48 DQ49 DQ50 DQ51I/O 0I/O 1I/O 2I/O 3D6DM6/DQS15NC/DQS15DM CS DQS DQSDQ52DQ53DQ54DQ55I/O 0I/O 1I/O 2I/O 3D15DQS8DQS8DM CS DQS DQSCB0 CB1 CB2 CB3I/O 0I/O 1I/O 2I/O 3D8DM8/DQS17NC/DQS17DM CS DQS DQSCB4CB5CB6CB7I/O 0I/O 1I/O 2I/O 3D17DQS7DQS7DM CS DQS DQSDQ56 DQ57 DQ58 DQ59I/O 0I/O 1I/O 2I/O 3D7DM7DQS16NC/DQS16DM CS DQS DQSDQ60DQ61DQ62DQ63I/O 0I/O 1I/O 2I/O 3D16A0Serial PDA1A2SA0SA1SA2SCL SDAV SS D0 - D17V DD/V DDQ D0 - D17D0 - D17VREFV DDSPD Serial PDWPNotes :1. DQ-to-I/O wiring may be changed per nibble.2. Unless otherwise noted, resister values are 22 Ohms 1:2REGISTERRSTS0*BA0-BA2A0-A13RASCASWECKE0ODT0RESET**PCK7** PCK7**RSO-> CS : DDR2 SDRAMs D0-D17RBA0-RBA2 -> BA0-BA2 : DDR2 SDRAMs D0-D17RA0-RA13 -> A0-A13 : DDR2 SDRAMs D0-D17RRAS -> RAS : DDR2 SDRAMs D0-D17RCAS -> CAS : DDR2 SDRAMs D0-D17RWE -> WE : DDR2 SDRAMs D0-D17RCKE0 -> CKE : DDR2 SDRAMs D0-D17RODT0 -> ODT0 : DDR2 SDRAMs D0-D17PLLOECK0CK0RESETPCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D8PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D8PCK7 -> CK : RegisterPCK7 -> CK : Register(populated as 1 rank of x4 DDR2 SDRAMs)2GB, 256Mx72 Module (M393T5660AZ3/M393T5660AZA)* S0 connects to DCS of Register1, CSR of Register2. CSR of reg-ister 1 and DCS of register 2 connects to VDD.** RESET, PCK7 and PCK7 connects to both Registers. Other sig-nals connect to one of two Registers.Signals for Address and Command Parity Function (M393T5660AZA)V SSV DDPAR_INC0C1PPOQERRRegister APAR_IN100K ohmsThe resistors on Par_In, A13, A14, A15, BA2 and thesignal line of Err_Out refer to the section: "RegisterOptions for Unused Address inputs"V DDV DDC0C1PPOQERR Err_OutRegister BPAR_IN(populated as 2 rank of x4 DDR2 SDRAMs)A0Serial PDA1A2SA0SA1SA2SCLSDAV SSD0 - D35V DD /V DDQ D0 - D35D0 - D35VREF V DDSPDSerial PD WP P L LOECK0CK0RESET PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D35PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D35PCK7 -> CK : Register PCK7 -> CK : Register1:2R E G I S T E RRSTS1*BA0-BA2A0-A13RAS CAS WE CKE0CKE1RESET**PCK7**PCK7**RS1-> CS : DDR2 SDRAMs D18-D35RBA0-RBA2 -> BA0-BA2 : DDR2 SDRAMs D0-D35RA0-RA13 -> A0-A13 : DDR2 SDRAMs D0-D35RRAS -> RAS : DDR2 SDRAMs D0-D35RCAS -> CAS : DDR2 SDRAMs D0-D35RWE -> WE : DDR2 SDRAMs D0-D35RCKE0 -> CKE : DDR2 SDRAMs D0-D17RCKE1 -> CKE : DDR2 SDRAMs D18-D35ODT0ODT1RODT0 -> ODT0 : DDR2 SDRAMs D0-D17RODT1 -> ODT1 : DDR2 SDRAMs D18-D35S0*RSO-> CS : DDR2 SDRAMs D0-D174GB, 512Mx72 Module (M393T5168AZ0/M393T5166AZA)* S0 connects to DCS and S0 connects to CSR on a Register,S1 connects to DCS and S0 connects to CSR on another Register.** RESET, PCK7 and PCK7 connects to both Registers. Other signals connect to one of two Registers.VSS RS0DQS0DQS0DMCSDQS DQSDQ0DQ1DQ2DQ3I/O 0I/O 1I/O 2I/O 3D0DM0/DQS9NC/DQS9DMCSDQS DQSDQ4DQ5DQ6DQ7I/O 0I/O 1I/O 2I/O 3D9DQS1DQS1DM CS DQS DQS DQ8DQ9DQ10DQ11I/O 0I/O 1I/O 2I/O 3D1DM1/DQS10NC/DQS10DM CS DQS DQS DQ12DQ13DQ14DQ15I/O 0I/O 1I/O 2I/O 3D10DQS2DQS2DM CS DQS DQS DQ16DQ17DQ18DQ19I/O 0I/O 1I/O 2I/O 3D2DM2/DQS11NC/DQS11DM CS DQS DQS DQ20DQ21DQ22DQ23I/O 0I/O 1I/O 2I/O 3D11DQS3DQS3DM CS DQS DQS DQ24DQ25DQ26DQ27I/O 0I/O 1I/O 2I/O 3D3DM3/DQS12NC/DQS12DM CS DQS DQS DQ28DQ29DQ30DQ31I/O 0I/O 1I/O 2I/O 3D12DQS5DQS5DM CS DQS DQS DQ40DQ41DQ42DQ43I/O 0I/O 1I/O 2I/O 3D5DM5/DQS14NC/DQS14DM CS DQS DQS DQ44DQ45DQ46DQ47I/O 0I/O 1I/O 2I/O 3D14DQS4DQS4DM CS DQS DQS DQ32DQ33DQ34DQ35I/O 0I/O 1I/O 2I/O 3D4DM4/DQS13NC/DQS13DM CS DQS DQS DQ36DQ37DQ38DQ39I/O 0I/O 1I/O 2I/O 3D13DQS6DQS6DM CS DQS DQS DQ48DQ49DQ50DQ51I/O 0I/O 1I/O 2I/O 3D6DM6/DQS15NC/DQS15DM CS DQS DQS DQ52DQ53DQ54DQ55I/O 0I/O 1I/O 2I/O 3D15DQS8DQS8DM CS DQS DQS CB0CB1CB2CB3I/O 0I/O 1I/O 2I/O 3D8DM8/DQS17NC/DQS17DM CS DQS DQS CB4CB5CB6CB7I/O 0I/O 1I/O 2I/O 3D17DQS7DQS7DM CS DQS DQS DQ56DQ57DQ58DQ59I/O 0I/O 1I/O 2I/O 3D7DM7DQS16NC/DQS16DM CS DQS DQS DQ60DQ61DQ62DQ63I/O 0I/O 1I/O 2I/O 3D16DM/CSDQS DQSI/O 0I/O 1I/O 2I/O 3D18DM/CS DQS DQS I/O 0I/O 1I/O 2I/O 3D19DM/CS DQS DQS I/O 0I/O 1I/O 2I/O 3D20DM CS DQS DQS I/O 0I/O 1I/O 2I/O 3D21DM CS DQS DQS I/O 0I/O 1I/O 2I/O 3D23DM CS DQS DQS I/O 0I/O 1I/O 2I/O 3D22DM CS DQS DQS I/O 0I/O 1I/O 2I/O 3D24DM CS DQS DQS I/O 0I/O 1I/O 2I/O 3D26DM CS DQS DQS I/O 0I/O 1I/O 2I/O 3D25DMCSDQS DQSI/O 0I/O 1I/O 2I/O 3D27DM CS DQS DQSI/O 0I/O 1I/O 2I/O 3D28DM CS DQS DQSI/O 0I/O 1I/O 2I/O 3D29DM CS DQS DQSI/O 0I/O 1I/O 2I/O 3D30DM CS DQS DQSI/O 0I/O 1I/O 2I/O 3D32DM CS DQS DQSI/O 0I/O 1I/O 2I/O 3D31DM CS DQS DQSI/O 0I/O 1I/O 2I/O 3D33DM CS DQS DQSI/O 0I/O 1I/O 2I/O 3D35DM CS DQS DQSI/O 0I/O 1I/O 2I/O 3D34RS1Signals for Address and Command The resistors on Par_In, A13, A14, A15, BA2and the signal line of Err_Out refer to the sec-tion: "Register Options for Unused Address inputs"PAR_INErr_Out100K ohmsV SS V DDC0C1PPO QERRRegister A1PAR_INV DD V DDC0C1PPO QERRRegister B1PAR_INV SS V DDC0C1PPO QERRRegister A2PAR_INV DD V DDC0C1PPO QERRRegister B2PAR_INParity Function (M393T5166AZA)Register A1 and A2 share the a part of Add/Cmd input signal set.Register B1 and B2 share the rest part of Add/Cmd input signal set.Recommended DC Operating Conditions (SSTL - 1.8)Note : There is no specific device V DD supply voltage requirement for SSTL-1.8 compliance. However under all conditions V DDQ must be less than or equalto V DD .1. The value of V REF may be selected by the user to provide optimum noise margin in the system. Typically the value of V REF is expected to be about 0.5 x V DDQ of the transmitting device and V REF is expected to track variations in V DDQ .2. Peak to peak AC noise on V REF may not exceed +/-2% V REF (DC).3. V TT of transmitting device must track V REF of receiving device.4. AC parameters are measured with V DD , V DDQ and V DDL tied together.Symbol ParameterRatingUnits NotesMin.Typ. Max.V DD Supply Voltage 1.7 1.8 1.9V V DDL Supply Voltage for DLL 1.7 1.8 1.9V 4V DDQ Supply Voltage for Output 1.7 1.8 1.9V 4V REF Input Reference Voltage 0.49*V DDQ 0.50*V DDQ0.51*V DDQ mV 1,2V TTTermination VoltageV REF -0.04V REFV REF +0.04V3 Note :1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2standard.Symbol ParameterRating Units Notes V DD Voltage on V DD pin relative to V SS - 1.0 V ~ 2.3 V V 1V DDQ Voltage on V DDQ pin relative to V SS - 0.5 V ~ 2.3 V V 1V DDL Voltage on V DDL pin relative to V SS - 0.5 V ~ 2.3 V V 1V IN, V OUT Voltage on any pin relative to V SS - 0.5 V ~ 2.3 V V1T STGStorage Temperature-55 to +100°C 1, 2AC & DC Operating ConditionsAbsolute Maximum DC Ratings。

AD408M166RCA-5中文资料

ASCEND Semiconductor 4Mx4 EDO Data sheetDescriptionThe device CMOS Dynamic RAM organized as 4,194,304 words x 4 bits with extended data out access mode. It is fabricated with an advanced submicron CMOS technology and designed to operate from a single 3.3V oniy power supply. Low voltage operation is more suitable to be used on battery backup, portable elec-tronic application. lt is packaged in JEDEC standard 26/24-pin plastic SOJ or TSOP(II).Features• Single 3.3V(%) only power supply • High speed t RAC acess time: 50/60ns • Low power dissipation- Active mode : 432/396 mW (Mas) - Standby mode: 0.54 mW (Mas)• Extended - data - out(EDO) page mode access • I/O level: CMOS level (Vcc = 3.3V)• 2048 refresh cycle in 32 ms(Std.) or 128 ms(S-version)• 4 refresh modesh: - RAS only refresh- CAS - before - RAS refresh - Hidden refresh - Self-refresh(S-version)10±Pin Name FunctionA0-A10Address inputs- Row address - Column address - Refresh address DQ1~DQ4Data-in / data-out RAS Row address strobe CAS Column address strobe WE Write enable OE Output enable Vcc Power (+ 3.3V)VssGroundVCC 1DQ12DQ23DQ34DQ45VCC6891011 NC 12 WE 13A0 A117 A218 A319VSS RAS CAS OE A8A7A6A5A4VSSAD404M42VSPin Description Pin Configuration21222324 2526151416 A1026/24-PIN 300mil Plastic SOJA9VCC 1DQ12DQ23DQ34DQ45VCC6891011 NC 12 WE 13A0 A117 A218 A319VSS RAS CAS OE A8A7 A6A5 A4VSSAD404M42VT212223242526151416 A1026/24-PIN 300mil Plastic TSOP (ll)A9A0-A10A0-A10A0-A10WECASNO. 2 CLOCK GENERATORCOLUMN ADDRESS BUFFERS (11)REFRESH CONTROLLERREFRESH COUNTERBUFFERS (11)ADDRESS ROW NO. 1 CLOCK GENERATORA0RASA1A2A3A4A5A6A7A8CONTROLLOGICDATA-IN BUFFERDATA-OUT BUFFEROEDQ1.DQ4.COLUMN DECODER2048SENSE AMPLIFIERSI/O GATING2048x42048x2048x4MEMORY ARRAY2048R O W D E C O D E RVcc VssBlock DiagramA9A10TRUTH TABLENotes: 1. EARLY WRITE only.FUNCTIONRASCAS WE OE ADDRESSESDQ SNotesROW COL STANDBY H X X X X High-Z READL L H L ROW COL Data-Out WRITE: (EARLY WRITE )L L L X ROW COL Data-lnREAD WRITE L L ROW COL Data-Out,Data-ln EDO-PAGE-MODE READ1st Cycle L H L ROW COL Data-Out 2nd CycleL H L n/a COL Data-Out EDO-PAGE MODE WRITE1st CycleL L X ROW COL Data-In 2nd Cycle L L Xn/a COL Data-InEDO-PAGE-MODEREAD-WRITE 1st Cycle L ROW COL Data-Out, Data-In 2nd Cycle L n/a COL Data-Out, Data-In HIDDEN REFRESHREAD L H L ROW COL Data-Out WRITEL L X ROW COL Data-In 1RAS-ONLY REFRESH L H X X ROW n/a High-Z CBR REFRESHLHXXXHigh-ZH X →H L →L H →H L →H L →H L →H L →H L →H L →L H →H L →H L →L H→L H L →→L H L→→H L→Absolute Maximum RatingsRecommended DC Operating ConditionsCapacitanceTa = 25°C, V CC = 3.3V%, f = 1MHz Note: 1. Capacitance measured with effective capacitance measuring method. 2. RAS, CAS = V IH to disable Dout.ParameterSymbol Value Unit Voltage on any pin relative to Vss V T -0.5 to + 4.6V Supply voltage relative to Vss V CC -0.5 to + 4.6V Short circuit output current I OUT 50mA Power dissipation P D 1.0WOperating temperature T OPT 0 to + 70°C Storage temperatureT STG-55 to + 125°CParameter/Condition Symbol3.3 Volt VersionUnitMinTyp MaxSupply VoltageV CC 3.0 3.33.6V Input High Voltage, all inputs V IH 2.0-V CC + 0.3V Input Low Voltage, all inputsV IL-0.3-0.8VParameterSymbol Typ Max Unit Note Input capacitance (Address)C I1 -5pF 1Input capacitance (RAS, CAS, OE, WE)C I2-7pF 1Output capacitance(Data-in, Data-out)C I/O-7pF1, 210±DC Characteristics :(T a = 0 to 70°C, V CC = + 3.3V%, V SS = 0V)Parameter Symbol Test Conditions AD404M42V Unit Notes-5-6Min Max Min MaxOperating current I CC1RAS cyclingCAS, cyclingt RC = min-120-110mA1, 2Standby Current LowpowerS-versionI CC2LVTTL interfaceRAS, CAS = V IHDout = High-Z-0.5-0.5mACMOS interfaceRAS, -0.2VDout = High-Z-0.15-0.15mAStandardpowerversionLVTTL interfaceRAS, CAS = V IHDout = High-Z-2-2mACMOS interfaceRAS,-0.2VDout = High-Z-0.5-0.5mARAS- only refresh current I CC3RAS cycling, CAS = V IHt RC = min-120-110mA1, 2 EDO page mode current I CC4t PC = min-90-80mA1, 3CAS- before- RAS refresh current I CC5t RC = minRAS, CAS cycling-120-110mA1, 2Self- refresh current (S-Version)I CC8 - 550 - 55010±CAS V CC≥CAS V CC≥t RASS100µs≥µADC Characteristics :(T a = 0 to 70°C , V CC = +3.3V %, V SS = 0V)Notes:1. I CC is specified as an average current. It depends on output loading condition and cycle rate when the device is selected. I CC max is specified at the output open condition.2. Address can be changed once or less while RAS = V IL .3. For I CC4, address can be changed once or less within one EDO page mode cycle time.Parameter Symbol Test Conditions AD404M42VUnitNotes-5-6Min MaxMin MaxInput leakage current I LI + 0.3V -55-55Output leakage current I LO + 0.3V Dout = Disable -55-55Output high Voltage V OH I OH = -2mA 2.4- 2.4-V Output low voltage V OLI OL = +2mA-0.4-0.4V10±0V Vin V CC ≤≤µA 0V Vout V CC ≤≤µAAC Characteristics(T a = 0 to + 70°C , V cc = 3.3V %, V ss = 0V) *1, *2, *3, *4Test conditions• Output load: one TTL Load and 100pF (V CC = 3.3V %)• Input timing reference levels:V IH = 2.0V, V IL = 0.8V (V CC = 3.3V %)• Output timing reference levels:V OH = 2.0V, V OL = 0.8V10±10±10±Read, Write, Read- Modify- Write and Refresh Cycles (Common Parameters)ParameterSymbol AD404M42V UnitNotes-5-6Min MaxMin MaxRandom read or write cycle time t RC 84-104-ns RAS precharge timet RP 30-40-ns CAS precharge time in normal mode t CPN 10-10-ns RAS pulse width t RAS 50100006010000ns 5CAS pulse width t CAS 8100001010000ns 6Row address setup time t ASR 0-0-ns Row address hold time t RAH 8-10-ns Column address setup time t ASC 0-0-ns 7Column address hold time t CAH 8-10-ns RAS to CAS delay timet RCD 12371445ns 8RAS to column address delay time t RAD 10251230ns 9Column address to RAS lead time t RAL 25-30-ns RAS hold time t RSH 8-10-ns CAS hold timet CSH 38-40-ns CAS to RAS precharge time t CRP 5-5-ns 10OE to Din delay time t OED 12-15-ns Transition time (rise and fall)t T 150150ns 11Refresh periodt REF -32-32ms Refresh period (S- Version)t REF -128-128ms CAS to output in Low- Z t CLZ 0-0-ns CAS delay time from Din t DZC 0-0-ns OE delay time from Dint DZO-0-nsRead CycleWrite Cycle Parameter SymbolAD404M42V Unit Notes-5-6Min Max Min MaxAccess time from RAS t RAC-50-60ns12 Access time from CAS t CAC-14-15ns13, 14 Access time from column address t AA-25-30ns14, 15 Access time from OE t OEA-12-15nsRead command setup time t RCS0-0-ns7 Read command hold time to CAS t RCH0-0-ns10, 16 Read command hold time to RAS t RRH0-0-ns16 Output buffer turn-off time t OFF012015ns17 Output buffer turn-off time from OE t OEZ012015ns17Parameter SymbolAD404M42V Unit Notes -5-6Min Max Min MaxWrite command setup time t WCS0-0-ns7, 18 Write command hold time t WCH8-10-nsWrite command pulse width t WP8-10-nsWrite command to RAS lead time t RWL13-15-nsWrite command to CAS lead time t CWL8-10-nsData-in setup time t DS0-0-ns19 Data-in hold time t DH8-10-ns19 WE to Data-in delay t WED10-10-nsRead- Modify- Write CycleRefresh Cycle Parameter SymbolAD404M42V Unit Notes-5-6Min Max Min MaxRead-modify- write cycle time t RWC108-133-nsRAS to WE delay time t RWD64-77-ns18 CAS to WE dealy time t CWD26-32-ns18 Column address to WE delay time t AWD39-47-ns18 OE hold time from WE t OEH8-10-nsParameter SymbolAD404M42VUnit Notes -5-6Min Max Min MaxCAS setup time (CBR refresh) t CSR5-5-nsCAS hold time (CBR refresh)t CHR8-10-ns10 RAS precharge to CAS hold time t RPC5-5-ns7 RAS pulse width (self refresh)t RASS100-100-RAS precharge time (self refresh)t RPS90-110-nsCAS hold time (CBR self refresh)t CHS-50--50-nsWE setup time t WSR0-0-nsWE hold time t WHR10-10-nsµsEDO Page Mode CycleEDO Page Mode Read Modify Write CycleParameterSymbol AD404M42VUnit Notes-5-6Min MaxMin MaxEDO page mode cycle timet PC 20-25-ns EDO page mode CAS precharge time t CP 10-10-ns EDO page mode RAS pulse width t RASP 5010560105ns 20Access time from CAS precharge t CPA -30-35ns 10, 14RAS hold time from CAS precharge t CPRH 30-35-ns OE high hold time from CAS high t OEHC 5-5-ns OE high pulse widtht OEP 10-10-ns Data output hold time after CAS low t COH 5-5-ns Output disable delay from WEt WHZ 310310ns WE pulse width for output disable whenCAS hight WPZ7-7-nsParameterSymbol AD404M42V Unit Notes -5-6Min MaxMin MaxEDO page mode read- modify- write cycle CAS precharge to WE delay timet CPW 45-55-ns 10EDO page mode read- modify- write cycle timet PRWC56-68-nsNotes :1. AC measurements assume t T = 2ns.2. An initial pause of 100 is required after power up, and it followed by a minimum of eightinitialization cycles (RAS - only refresh cycle or CAS - before - RAS refresh cycle). If the internal refresh counter is used, a minimun of eight CAS - before - RAS refresh cycles are required.3. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device.4. All the V CC and V SS pins shall be supplied with the same voltages.5. t RAS (min) = t RWD (min)+t RWL (min)+t T in read-modify-write cycle.6. t CAS (min) = t CWD (min)+t CWL (min)+t T in read-modify-write cycle.7. t ASC (min), t RCS (min), t WCS (min), and t RPC are determined by the falling edge of CAS .8. t RCD (max) is specified as a reference point only, and t RAC (max) can be met with the t RCD (max) limit.Otherwise, t RAC is controlled exclusively by t CAC if t RCD is greater than the specified t RCD (max) limit. 9. t RAD (max) is specified as a reference point only, and t RAC (max) can be met with the t RAD (max) limit.Otherwise, t RAC is controlled exclusively by t AA if t RAD is greater than the specified t RAD (max) limit. 10. t CRP , t CHR , t RCH , t CPA and t CPW are determined by the rising edge of CAS .11. V IH (min) and V IL (max) are reference levels for measuring timing or input signals. Therefore, transitiontime is measured between V IH and V IL .12. Assumes that t RCD tRCD (max) and t RAD t RAD (max). If t RCD or t RAD is greater than the maximum recommended value shown in this table, t RAC exceeds the value shown. 13. Assumes that (max) and (max).14. Access time is determined by the maximum of t AA , t CAC , t CPA . 15. Assumes that (max) and (max). 16. Either t RCH or t RRH must be satisfied for a read cycle.17. t OFF (max) and t OEZ (max) define the time at which the output achieves the open circuit condition (highimpedance). t OFF is determined by the later rising edge of RAS or CAS.18. t WCS , t RWD , t CWD , and t AWD are not restrictive operating parameters. They are included in the datasheet as electrical characteristics only. If (min), the cycle is an early write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. If (min),(min), (min) and (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell. If neither of the above sets of conditions is satisfied, the condition of the data output (at access time) is indeterminate.19. These parameters are referenced to CAS separately in an early write cycle and to WE edge in adelayed write or a read-modify-write cycle.20. t RASP defines RAS pulse width in EDO page mode cycles.µs ≤≤t RCD t RCD ≥t RADt RAD ≤t RCD t RCD ≤t RAD t RAD ≥t WCS t WCS ≥t RWD t RWD ≥t CWDt CWD ≥t AWD t AWD ≥t CPW t CPW≥Timing Waveforms• Read Cyclet RC t RASt RPtCRPtCPNtRRHtRCHt OEZ t OFF tOEA tCACt AAtRACt CLZD OUTtRCS t ASR tRAH tASC tCAH tRAD t RALtCAStRSH tRCDt TtCSHRASCASADDRESSWEDQ1~DQ4Note : = don’t care OEt OFFRowColumn= Invalid Dout•Early Write CycletRC t RASt RPt WCHt DSt DHt WCS t RALtCAStRSH tRCDt TtCSHRASCASWEDQ1~DQ4tCRPtASRtRAH tASCtCAH ADDRESSColumnRowtCPND INtRADt RAL• Delayed Write CycletRC t RASt RPt RWL t RCSt CAStRSH tRCDt TtCSHRASCAStASR tRAH tCAHADDRESSColumnRow tASC D INDQ1~DQ4WEtCRPtCPNt DHt DSt OEHt OEDOEt DSOPENt WPt CWL• Read - Modify - Write CycletRWC t RASt RPtRWDt WPtRADtRWL tCAStCWL tRCDt TtCPNRASCASWEtCRP t ASRtRAHtASCtCAHADDRESS Column RowDQ1~DQ4t DHt DSOEtRCStAWD tCWD D INt OEDt OEHt OEZt OEA t CAC t RACt AADQ1~DQ4D OUTOPENtDZCtDZO• EDO Page Mode Read CycletRASPtCPRHt RCStCAStRSH tRCDt OEAtCSHRASCAStASRtRAHtCAHADDRESStCASWEtCRPt CPOEDQ1~DQ4OPENtOEPD OUT 1t PCt CPtCAStCPNtCRPtRADtCAHtASCt ASCtCAHt ASCt RAL Row Column 1t OEAt OEHCtRRH tRCHt RACt AAt AAt AA t CPA t CPA t OEZt OFFt OFFt CACt OEZt CAC t CACt COHD OUT NWE OE Column 2Column N Rowt RPD OUT 2• EDO Page Mode Early Write CycletRASPtRPt WCSt CAStRSH tRCDRASCAStASRtRAHtCAHADDRESStCASWEt CPDQ1~DQ4t PCt CPt CAStCPNtCRP tCAH tASCtASC tCAH tASC Row Column 1t DS WE Column 2Column Nt WCH t WCS t WCH t WCS t WCHt DH t DS t DH t DS t DHD IN 1D IN 2D IN Nt TtCSH• EDO Page Mode Read-Early-Write Cyclet RASPtCPRHt RCStCAStRSH tRCDt OEAtCSHRASCAStASRtRAHtCAHADDRESStCASWEtCRPt CPOEDQ1~DQ4OPENtWEDt PCt CPtCAStCPNtCRPtRADtRAHtASCt ASCtCAHt ASCt RAL Row Column 1tWCStRCHt RACt AAt AAt CPA t DHt WHZt CACt CACt COHWE OE Column 2Column N Rowt RPt CAL tWCHDataDoutput 2Data Input NDataDoutput 1t DStCSH• EDO Page Mode Read-Modify-Write Cyclet RASPt CPRHt RCStCASt WP RASCASt ASRtRAHtCAHADDRESSt CASWEtRCDCPDQ1~DQ4tPRWCt CPtCAStCRPtRADtCAHtASCt ASCtCAH tASC Row Column 1tRWLtRCSt OEDt DZOt CAC WE OEt RPt RAL D OUT 2D OUT ND OUT 1tTt Column NColumn 2Column 1tRWD tAWD tCWDtCWLtRCStCWDtAWD tCPW tCWL tCPW tAWD tCWDtCWL t OEDt OEDt OEHt OEHt OEHt CAC t CAC t OEA t AAt RACt OEZt OEAt AA t CPAt OEZt OEAt AA t CPAt OEZ t DSt DHt WP t DSt DHt WP t DSt DHOPENOPENOPEN D IN 1D IN ND IN 2DQ1~DQ4t DZCt DZOt DZCt DZCt DZO• Read Cycle with WE Controlled Disablet WPZt RCStCAStRCDt TtCSHRASCASt ASRtRAHtCAHADDRESSColumnRow tASCD DQ1~DQ4WEt OEZt DSt WHZOEt RCH t OEA t CACt AAt RACt CLZOUTtRADRASADDRESSt RC t CRPt ASRt RAHt Tt RPCROWt OFFCAS t RASt RPOPENt CRPDQ1~DQ4RASt CSRt WSRt RPt T t RPCt OFFCAS t RASt RPOPENt CRPDQ1~DQ4t RPCt CHRt RASt RPt RCt RCt CHRt CSRt WHRt WSRt WHRWECAS-Before-RAS Refresh CycleRASWEt RPCt OFFt CSRt CHSt WSRCASt RASS t RPSOPENDQ1~DQ4t WHRHigh lmpedance• Hidden Refresh Cyclet RPt RASRASt RCDt CRPADDRESSWEt CHRt CASt RSHt RAHt ASRt ASCt CAHt RAL ROW t RCHt OEZCASDQ1~DQ4t Tt RCSD t RASt RASt RPt RPt RC t RCt RCt RADt RRHt OFF t OFFt OEA t CACt AAt RACCOlumnOUTOE(READ)(REFRESH)(REFRESH)Ordering informationAD404M42VSA-5• AD• Ascend Memory Product • 40 • Device Type• 4M4 • Density and Organization • 2• Refresh Rate, 2: 2K Refresh • V• T: 5V, V: 3.3V• S • Package Type (S : SOJ, T : TSOP II)• A• Version• 5• Speed (5: 50 ns, 6: 60 ns)Part Number Access time PackageAD404M42VSA-5AD404M42VSA-6AD404M42VTA-5AD404M42VTA-650 ns 60 ns 50 ns 60 ns300mil 26/24-Pin Plastic SOJTSOP IIPackaging information • 300 mil, 26/24-Pin Plastic SOJ• 300 mil, 26/24-Pin TSOP II。

瑞纳捷半导体 RJGT102 V3.11数据手册说明书

RJGT102V3.11数据手册武汉瑞纳捷半导体有限公司—Wuhan Runjet Semiconductor Co.Ltd特性高性能防复制加密芯片提供看门狗定时器和对外复位功能SHA-256加密认证提供用于写入用户自定义的EEPROM单元遵循标准I²C总线协议可锁定的64位用户ID号2.97V～3.63V的工作电压可以对密钥和每个数据存储区单独加写保护独立看门狗定时器，溢出周期用户可自定义POR（Power On Reset）上电复位延迟时间由厂家编程支持低功耗模式应用汽车导航，车载DVD，汽车定位，汽车监控，行车记录仪手机，通信模块，路由器，对讲机监控设备，IP Camera，NVR/DVR订购信息型号功能封装引脚RJGT102WDP8看门狗复位、加密保护SOP-8LRJGT102P8加密保护SOP-8LRJGT102WDT6看门狗复位、加密保护SOT23-6LRJGT102T6加密保护SOT23-6L目录特性 (2)应用 (2)订购信息 (3)1.简介 (7)1.1特性 (7)1.1.1安全性 (7)1.1.2存储器 (7)1.1.3外部设备特性 (7)1.1.4特殊功能 (7)1.1.5工作电压 (7)1.1.6封装 (7)1.2RJGT102架构图 (8)1.3引脚配置 (8)1.3.1SOP-8L引脚配置 (8)1.3.2SOT23-6L引脚配置 (9)2.EEPROM和寄存器 (10)2.1数据存储区 (10)2.2密钥存储区 (10)2.3控制存储区 (10)2.4其他寄存器定义 (11)3.I/O端口 (13)3.1ESD保护电路 (13)3.2I/O类型 (13)3.2.1时钟输入端口（SCL） (13)3.2.2双向端口（SDA） (14)3.3SDA和SCL I/O级特性 (14)4.I²C接口 (16)4.1I²C总线总体特征 (16)4.2低功耗待机模式 (16)4.3I²C总线位传输 (16)4.3.1起始位与停止位 (16)4.3.2数据有效性 (17)4.4I²C数据传输 (17)4.4.1I²C字节格式 (17)4.4.2应答 (18)4.5时钟的同步 (18)4.6I²C总线寻址 (19)4.6.17位地址格式 (19)4.6.27位地址寻址 (19)4.7数据传输 (20)4.8I²C总线特性 (20)5.初始化 (22)5.1初始化波形 (22)6.UID的使用 (23)6.1UID使用特点 (23)6.2寄存器的具体使用 (23)7.加密认证 (24)7.1SHA-256认证 (24)7.2SHA-256输入与输出格式 (24)8.上电复位设计 (25)8.1WDOG工作模式 (25)8.2复位管脚输出 (25)8.3功能描述 (25)8.3.1看门狗定时器 (25)8.3.2复位输出 (25)8.3.3寄存器描述 (26)9.操作命令 (28)9.1初始化命令 (28)9.2主机认证命令 (28)9.3更新密钥命令 (28)9.4读/写命令 (29)10.认证方案 (30)10.1认证方案流程 (30)10.2认证方案一 (31)10.3认证方案二 (32)10.4认证方案三 (33)11.电气特性 (34)11.1最大额定参数 (34)11.2推荐工作条件 (34)11.3DC特性 (34)11.4模拟IP参数 (35)12.封装尺寸 (36)12.1SOP-8L (36)12.2SOT23-6L (37)1.简介RJGT102在单个芯片内集成了176Byte的EEPROM，128Byte寄存器页，8Byte密钥，8Byte 的用户ID/Serial Number，和16Byte的控制信息。

ADM2486_CN

隔离型半双工RS-485收发器收发器————ADM248ADM24866一、功能描述ADM2486是ADI （Analog device,inc ）公司推出的基于其专利iCoupler 磁隔离技术的隔离型RS-485收发芯片。

内部集成了三通道的数字隔离器、带三态输出的差分驱动器和一个带三态输入的RS485差分接收器。

节点数可允许多达50个，最高传输速率可达20M bps 。

iCoupler 磁隔离技术是ADI 公司的一项专利隔离技术，是一种基于芯片尺寸的变压器隔离技术，它采用了高速CMOS 工艺和芯片级的变压器技术。

所以，在性能、功耗、体积等各方面都有传统光电隔离器件（光耦）无法比拟的优势。

由于磁隔离在设计上取消了光电耦合器中影响效率的光电转换环节，因此它的功耗仅为光电耦合器的1/6--1/10，具有比光电耦合器更高的数据传输速率、时序精度和瞬态共模抑制能力。

同时也消除了光电耦合中不稳定的电流传输率，非线性传输，温度和使用寿命等方面的问题。

ADM2486具有限流和过热关断特性，能够防止输出短路，并防止出现由于总线争用而引起功耗过大的情况。

集成的热关断电路可将驱动器输出置为高阻状态，防止过度的功率损耗。

该芯片封装采用易于使用的SOW-16封装，工业级温度范围，无需任何分立元件就可实现RS-485通信功能。

二、性能特征�带隔离的RS-485收发器�隔离电压：2500Vrms �最高传输速率20Mbps �总线最大节点数：50个�热关断保护模式�支持PROFIBUS 总线�瞬态高共模抑制能力：25KV/μs �低功耗：逻辑侧1.0mA 工作电流�工作电压：V DD1：2.7~5.5V V DD2：4.75~5.25V�工作温度范围：-40℃--+85℃小封装：SOIC-16宽体图1,ADM2486功能框图三、应用范围�所有RS-485通信场合�需要电平转换器485通信�工业控制局域网�PROFIBUS总线隔离图2、ADM2486引脚功能图四、芯片引脚说明（如图2所示）引脚名称功能描述1V DD1逻辑端供电电源(2.7V~5.5V)2,8GND1逻辑端电源地(2脚、8脚内部已连接)3RxD接收输出，当RE(接收使能)为高电平时，此位禁止输出。

夏普M160M205零件手册中文_部分2

O第二纸盒给纸组件 (AR-M205)O第二纸盒给纸组件AR-RP6 MODEL目录为确保安全性、可靠性，更换部品务必使用正规品。

指定的部品。

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AD5165BUJZ100 256-Position，低功耗1.8 V逻辑级数字潜动电阻说明书

AD5165BUJZ100-R2AD5165BUJZ100256-Position, Ultralow Power1.8 V Logic-Level Digital PotentiometerAD5165 Rev. 0Information furnished by Analog Devices is believed to be accurate and reliable.However, no responsibility is assumed by Analog Devices for its use, nor for anyinfringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: Fax: 781.326.8703© 2004 Analog Devices, Inc. All rights reserved.FEATURESUltralow standby power I DD = 50 nA typical256-positionEnd-to-end resistance 100 kΩLogic high voltage 1.8 VPower supply 2.7 V to 5.5 VLow temperature coefficient 35 ppm/°CCompact thin 8-lead TSOT-8 (2.9 mm × 2.8 mm) package Simple 3-wire digital interfaceWide operating temperature −40°C to +125°CPin-to-pin compatible to AD5160 with CS inverted APPLICATIONSBattery-operated electronics adjustmentRemote utilities meter adjustmentMechanical potentiometer replacementTransducer circuit adjustmentAutomotive electronics adjustmentGain control and offset adjustmentSystem calibrationVCXO adjustmentGENERAL OVERVIEWThe AD5165 provides a compact 2.9 mm × 2.8 mm packaged solution for 256-position adjustment applications. These devices perform the same electronic adjustment function as mechanical potentiometers or variable resistors, with enhanced resolution, solid-state reliability, and superior low temperature coefficient performance. The AD5165’s supply voltage requirement is 2.7 V to 5.5 V, but its logic voltage requirement is 1.8 V to V DD. The AD5165 consumes very low quiescent power during standby mode and is ideal for battery-operated applications.Wiper settings are controlled through a simple 3-wire interface. The interface is similar to the SPI® digital interface except for the inverted chip-select function that minimizes logic power con-sumption in the idling state. The resistance between the wiper and either endpoint of the fixed resistor varies linearly with respect to the digital code transferred into the wiper register. Operating from a 2.7 V to 5.5 V power supply and consuming less than 50 nA typical standby power allows use in battery-operated portable or remote utility device applications.FUNCTIONAL BLOCK DIAGRAMCSSDICLKGND04749--1Figure 1.PIN CONFIGURATIONV4749--2Figure 2.TYPICAL APPLICATION4749--3A,V B,V W< 5VFigure 3.Note:The terms digital potentiometer, RDAC, and VR are used interchangeably.AD5165Rev. 0 | Page 2 of 16TABLE OF CONTENTSElectrical Characteristics—100 k Ω Version..................................3 Absolute Maximum Ratings............................................................5 Pin Configuration and Functional Descriptions..........................6 Typical Performance Characteristics.............................................7 Test Circuits.....................................................................................11 3-Wire Digital Interface.................................................................12 Theory of Operation......................................................................13 Programming the Variable Resistor.........................................13 Programming the Potentiometer Divider. (14)3-Wire Serial Bus Digital Interface..........................................14ESD Protection...........................................................................14 Terminal Voltage Operating Range..........................................14 Power-Up Sequence...................................................................14 Layout and Power Supply Bypassing.......................................15 Evaluation Board........................................................................15 Outline Dimensions.......................................................................16 Ordering Guide.. (16)REVISION HISTORY4/04—Revision 0: Initial VersionAD5165Rev. 0 | Page 3 of 16ELECTRICAL CHARACTERISTICS—100 k Ω VERSIONV DD = 5 V ± 10%, or 3 V ± 10%; V A = V DD ; V B = 0 V; –40°C < T A < +125°C; unless otherwise noted. Table 1.Parameter Symbol Conditions M in Typ 1M ax Unit DC CHARACTERISTICS—RHEOSTAT MODEResistor Differential Nonlinearity 2R-DNL R WB , V A = no connect−1 ±0.1 +1 LSB Resistor Integral Nonlinearity 2R-INL R WB , V A = no connect −2 ±0.25 +2 LSB Nominal Resistor Tolerance 3∆R AB /R AB T A = 25°C −20 +20 %Resistance Temperature Coefficient (∆R AB /R AB )/∆Tx106V AB = V DD , wiper = no connect 35 ppm/°C Wiper Resistance R W V DD = 2.7 V/5.5 V 85/50 150/120 Ω DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE Resolution N 8 Bits Differential Nonlinearity 4DNL −1 ±0.1 +1 LSBIntegral Nonlinearity 4INL −1 ±0.3 +1 LSBVoltage Divider TemperatureCoefficient (∆V W /V W )/∆Tx106Code = 0x80 15 ppm/°C Full-Scale Error V WFSE Code = 0xFF −0.5 −0.3 0 LSB Zero-Scale Error V WZSE Code = 0x00 0 0.1 0.5 LSB RESISTOR TERMINALSVoltage Range 5V A,B,W GND V DD V Capacitance 6 A, B C A,B f = 1 MHz, measured to GND,Code = 0x8090 pF Capacitance 6W C W f = 1 MHz, measured to GND,Code = 0x8095 pF Common-Mode Leakage I CM V A = V B = V DD /2 1 nA DIGITAL INPUTS AND OUTPUTS Input Logic High V IH V DD = 2.7 V to 5.5 V 1.8 V Input Logic Low V IL V DD = 2.7 V to 5.5 V 0.6 VInput Capacitance 6C IL 5 pF POWER SUPPLIES Power Supply Range V DD RANGE 2.7 5.5 V Supply Current I DD Digital inputs = 0 V or V DD 0.05 1 µA V DD = 2.7 V, digital inputs = 1.8 V 10 µA V DD = 5 V, digital inputs = 1.8 V 500 µA Power Dissipation 7P DISS Digital inputs = 0 V or V DD 5.5 µWPower Supply Sensitivity PSS V DD = +5 V ± 10%,Code = Midscale±0.001 ±0.005 %/% DYNAMIC CHARACTERISTICS 6, 8 Bandwidth −3 dB BW Code = 0x80 55 kHz Total Harmonic Distortion THD W V A =1 V rms, V B = 0 V, f = 1 kHz, 0.05 %V W Settling Time t S V A = 5 V, V B = 0 V,±1 LSB error band2 µs Resistor Noise Voltage Density e N_WB R WB = 50 kΩ 28 nV/√Hz1 Typical specifications represent average readings at +25°C and V DD = 5 V.2Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. 3V AB = V DD , wiper (V W ) = no connect. 4INL and DNL are measured at V W with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V A = V DD and V B = 0 V. 5Resistor terminals A, B, and W have no limitations on polarity with respect to each other. 6Guaranteed by design and not subject to production test. 7P DISS is calculated from (I DD × V DD ). CMOS logic level inputs result in minimum power dissipation. 8All dynamic characteristics use V DD = 5 V.AD5165Rev. 0 | Page 4 of 16TIMING CHARACTERISTICS—100 kΩ VERSIONV DD = +5 V ± 10%, or +3 V ± 10%; V A = V DD ; V B = 0 V; −40°C < T A < +125°C; unless otherwise noted. Table 2.Parameter Symbol Conditions M in Typ 1M ax Unit 3-WIRE INTERFACE TIMING CHARACTERISTICS 2, , 34(specifications apply to all parts) Clock Frequency f CLK = 1/( t CH + t CL ) 25 MHz Input Clock Pulse Width t CH , t CL Clock level high or low 20 ns Data Setup Time t DS 5 ns Data Hold Time t DH 5 ns CS Setup Time t CSS 15 ns CS Low Pulse Width t CSW 40 ns CLK Fall to CS Rise Hold Time t CSH0 0 ns CLK Fall to CS Fall Hold Time t CSH1 0 ns CS Fall to Clock Rise Setup t CS1 10 ns1 Typical specifications represent average readings at +25°C and V DD = 5 V. 2Guaranteed by design and not subject to production test. 3All dynamic characteristics use V DD = 5 V. 4See and for location of measured values. All input control voltages are specified with t Figure 34Figure 35R = t F = 2 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V.AD5165Rev. 0 | Page 5 of 16ABSOLUTE MAXIMUM RATINGST A = +25°C, unless otherwise noted.1, 2Table 3.Parameter ValueV DD to GND –0.3 V to +7 VV A , V B , V W to GND V DDMaximum Current I WB , I WA Pulsed I WB Continuous (R WB ≤ 1 kΩ, A open)2I WA Continuous (R WA ≤ 1 kΩ, B open)2±20 mA±5 mA ±5 mA Digital Inputs and Output Voltage to GND 0 V to +7 V Operating Temperature Range –40°C to +125°C Maximum Junction Temperature (T JMAX ) 150°C Storage Temperature –65°C to +150°C Lead Temperature (Soldering, 10 – 30 sec) 245°CThermal Resistance 2θJA : TSOT-8 200°C/W1Maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the A, B, and W terminals at a given resistance. 2Package power dissipation = (T JMAX − TA)/θJA .Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or anyother conditions above those indicated in the operationalsection of this specification is not implied. Exposure to absolutemaximum rating conditions for extended periods may affectdevice reliability.ESD CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.AD5165Rev. 0 | Page 6 of 16PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONSV 04749-0-002Figure 4.Table 4.Pin Name Description1 W Wiper terminal. GND ≤ V A ≤ V DD.2 V DD Positive Power Supply.3 GND Digital Ground.4 CLK Serial Clock Input. Positive-edge triggered.5 SDI Serial Data Input (data loads MSB first).6 CS Chip Select Input, active high. When CS returns low, data is loaded into the wiper register.7 B B terminal. GND ≤ V A ≤ V DD .8 A A terminal. GND ≤ V A ≤ V DD .AD5165Rev. 0 | Page 7 of 16TYPICAL PERFORMANCE CHARACTERISTICS–0.5–0.4–0.3–0.2–0.100.10.20.30.40.5R H E O S T A T M O D E I N L (L S B )1289632640160192224256CODE (Decimal)04749-0-011Figure 5. R-INL vs. Code vs. Supply Voltages–0.5–0.4–0.3–0.2–0.100.10.20.30.40.5R E H O S T A T M O D E D N L (L S B )128963264160192224256CODE (Decimal)04749-0-013Figure 6. R-DNL vs. Code vs. Supply Voltages–0.5–0.4–0.3–0.2–0.100.10.20.30.40.5P O T E N T I O M E T E R M O D E I N L (L S B )128963264160192224256CODE (Decimal)04749-0-006Figure 7. INL vs. Code vs. Temperature , V DD = 5 V –0.5–0.4–0.3–0.2–0.100.10.20.30.40.5P O T E N T I O M E T E R M O D E D N L (L S B )1289632640160192224256CODE (Decimal)04749-0-008Figure 8. DNL vs. Code vs. Temperature, V DD = 5 V–0.5–0.4–0.3–0.2–0.100.10.20.30.40.5P O T E N T I O M E T E R M O D E I N L (L S B )1289632640160192224256CODE (Decimal)04749-0-007Figure 9. INL vs. Code vs. Supply Voltages–0.5–0.4–0.3–0.2–0.100.10.20.30.40.5P O T E N T I O M E T E R M O D E D N L (L S B )1289632640160192224256CODE (Decimal)04749-0-009Figure 10. DNL vs. Code vs. Supply VoltagesAD5165Rev. 0 | Page 8 of 16–0.5–0.4–0.3–0.2–0.100.10.20.30.40.5R H E O S T A T M O D E I N L (L S B )1289632640160192224256CODE (Decimal)04749-0-010Figure 11. R-INL vs. Code vs. Temperature, V DD = 5 V–0.5–0.4–0.3–0.2–0.100.10.20.30.40.5R H E O S T A T M O D E D N L (L S B )128963264160192224256CODE (Decimal)04749-0-012Figure 12. R-DNL vs. Code vs. Temperature, V DD = 5 V–0.5–0.4–0.3–0.2–0.100.10.20.30.40.5F S E (L S B )4020–20–406080100120TEMPERATURE (°C)04749-0-023Figure 13. Full-Scale Error vs. Temperature –0.5–0.4–0.3–0.2–0.100.10.20.30.40.5Z S E (L S B )4020–200–406080100120TEMPERATURE (°C)04749-0-022Figure 14. Zero-Scale Error vs. Temperature–0.5–0.4–0.3–0.2–0.100.10.20.30.40.5S U P P L Y C U R R E N T (µA )4020–200–406080100120TEMPERATURE (°C)04749-0-020Figure 15. Supply Current vs. Temperature0.010.1110100100010000I D D (µA )12345V IH (0) (V)04749-0-025Figure 16. Supply Current vs. Digital Input VoltageAD5165Rev. 0 | Page 9 of 160.010.11101001000I D D (µA )12345V IH (1MHz) (V)04749-0-026Figure 17. Supply Current vs. Digital Input Voltage–20–15–10–505R H E O S T A T M O D E T E M C O (p p m /°C )1015201289632640160192224256CODE (Decimal)04749-0-015Figure 18. Rheostat Mode Tempco ∆R WB /∆T vs. Code–8–6–4–202P O T E N T I O M E T E R M O D E T E M P C O (p p m /°C )4681289632640160192224256CODE (Decimal)04749-0-014Figure 19. Potentiometer Mode Tempco ∆V WB /∆T vs. Code1k 10k 100k 1M–6–12–18–24–30–36–42–48–54–600x800x400x200x100x080x040x020x01REF LEVEL 0.000dB /DIV 6.000dBMARKER 54 089.173Hz MAG (A/R)–9.052dBSTART 1 000.000Hz STOP 1 000 000.000Hz04749-0-048Figure 20. Gain vs. Frequency vs. Code, R AB = 100 kΩ10k10M–5.5–6.0–6.5–7.0–7.5–8.0–8.5–9.0–9.5–10.0–10.5REF LEVEL –5.000dB /DIV 0.500dBSTART 1 000.000Hz STOP 1 000 000.000Hz04749-0-047Figure 21. –3 dB Bandwidth @ Code = 0x80P S R R (–d B )020406080FREQUENCY (Hz)1k 10010k100k 1M04749-0-019Figure 22. PSRR vs. FrequencyAD5165Rev. 0 | Page 10 of 160100200300400500I D D (µA )600700800FREQUENCY (Hz)10k1M100k10M04749-0-018Figure 23. I DD vs. FrequencyCh 1 200mV B W Ch 2 5.00 V B W M 100ns A CH2 3.00 V04749-0-030Figure 24. Large Signal Settling Time, Code 0xFF–0x00CLK04749-0-030Figure 25. Digital FeedthroughCSCh 1 100mV B W Ch 2 5.00 V B W M 200ns A CH1 152mV V A = 5V V B = 0V04749-0-028Figure 26. Midscale Glitch, Code 0x80–0x7FAD5165Rev. 0 | Page 11 of 16TEST CIRCUITSFigure 27 to Figure 33 illustrate the test circuits that define the test conditions used in the product specification tables.V MSDDN04749-0-031Figure 27. Test Circuit for Potentiometer Divider Nonlinearity Error(INL, DNL)04749-0-032Figure 28. Test Circuit for Resistor Position Nonlinearity Error(Rheostat Operation; R-INL, R-DNL)V MS2MS2]/I W04749-0-033Figure 29. Test Circuit for Wiper Resistance04749-0-034∆V MS %DD %PSS (%/%) =V+ = V DD 10%PSRR (dB) = 20 LOGMSDD( )V V MS∆V ∆V∆VFigure 30. Test Circuit for Power Supply Sensitivity (PSS, PSSR)V OUT04749-0-035Figure 31. Test Circuit for Gain vs. FrequencyR SW =0.1V I 04749-0-036Figure 32. Test Circuit for Incremental ON ResistanceCM04749-0-037Figure 33. Test Circuit for Common-Mode Leakage CurrentAD5165Rev. 0 | Page 12 of 163-WIRE DIGITAL INTERFACENote that in the AD5165 data is loaded MSB first. Table 5. AD5165 Serial Data-Word FormatB7 B6 B5 B4 B3 B2 B1 B0 D7 D6 D5 D4 D3 D2 D1 D0 MSBLSB 2720SDI CLK CS VOUTFigure 34. 3-Wire Digital Interface Timing Diagram(V A = 5 V, V B = 0 V, V W = V OUT )SDICLKCSVOUT(DATA IN)04749-0-005Figure 35. 3-Wire Digital Interface Detailed Timing Diagram (V A = 5 V, V B = 0 V, V W = V OUT )AD5165Rev. 0 | Page 13 of 16THEORY OF OPERATIONThe AD5165 is a 256-position digitally controlled variable resistor (VR) device.PROGRAMMING THE VARIABLE RESISTORRheostat OperationThe nominal resistance of the RDAC between terminals A and B is available in 100 kΩ. The nominal resistance (R AB ) of the VR has 256 contact points accessed by the wiper terminal, plus the B terminal contact. The 8-bit data in the RDAC latch is decoded to select one of the 256 possible settings.04749-0-038Figure 36. Rheostat Mode ConfigurationAssuming that a 100 kΩ part is used, the wiper’s first connec-tion starts at the B terminal for data 0x00. Because there is a50 Ω wiper contact resistance, such a connection yields a mini-mum of 100 Ω (2 × 50 Ω) resistance between terminals W and B. The second connection is the first tap point, which corres-ponds to 490 Ω (R WB = R AB /256 + 2 × R W = 390 Ω + 2 × 50 Ω) for data 0x01. The third connection is the next tap point,representing 880 Ω (2 × 390 Ω + 2 × 50 Ω) for data 0x02, and so on. Each LSB data value increase moves the wiper up the resistor ladder until the last tap point is reached at 100,100 Ω (R AB + 2 × R W ).04749-0-039Figure 37. AD5165 Equivalent RDAC CircuitThe general equation determining the digitally programmed output resistance between W and B isW AB WB R R DD R ×+×=2256)((1) where:D is the decimal equivalent of the binary code loaded in the 8-bit RDAC register.R AB is the end-to-end resistance.R W is the wiper resistance contributed by the on resistance of the internal switch.In summary, if R AB = 100 kΩ and the A terminal is open circuited, the following output resistance R WB is set for the indicated RDAC latch codes.Table 6. Codes and Corresponding R WB ResistanceD (Dec.) R WB (Ω) Output State 255 99,710 Full scale (R AB – 1 LSB + R W ) 128 50,100 Midscale 1 490 1 LSB 0 100 Zero scale (wiper contact resistance)Note that, in the zero-scale condition, a finite wiper resistance of 100 Ω is present. Care should be taken to limit the current flow between W and B in this state to a maximum pulse current of no more than 20 mA. Otherwise, degradation or possible destruction of the internal switch contact can occur.Similar to the mechanical potentiometer, the resistance of the RDAC between the wiper W and terminal A also produces a digitally controlled complementary resistance, R WA . When these terminals are used, the B terminal can be opened. Setting the resistance value for R W A starts at a maximum value of resistance and decreases as the data loaded in the latch increases in value. The general equation for this operation isW AB WA R R DD R ×+×−=2256256)( (2) For R AB = 100 kΩ with the B terminal open circuited, the following output resistance R W A is set for the indicated RDAC latch codes.Table 7. Codes and Corresponding R WA ResistanceD (Dec.) R WA (Ω) Output State 255 490 Full scale 128 50,100 Midscale 1 99, 710 1 LSB 0 100,100 Zero scaleTypical device-to-device matching is process-lot dependent and may vary by up to ±20%. Because the resistance element is processed in thin film technology, the change in R AB with temperature has a very low 35 ppm/°C temperature coefficient.AD5165Rev. 0 | Page 14 of 16PROGRAMMING THE POTENTIOMETER DIVIDERVoltage Output OperationThe digital potentiometer easily generates a voltage divider at wiper-to-B and wiper-to-A proportional to the input voltage at A to B. Unlike the polarity of V DD to GND, which must be positive, voltage across A to B, W to A, and W to B can be at either polarity.04749-0-040Figure 38. Potentiometer Mode ConfigurationIf ignoring the effect of the wiper resistance for approximation, connecting the A terminal to 5 V and the B terminal to ground produces an output voltage at the wiper-to-B starting at 0 V up to 1 LSB less than 5 V . Each LSB of voltage is equal to the voltage applied across terminals A and B divided by the 256 positions of the potentiometer divider. The general equation defining the output voltage at V W with respect to ground for any valid input voltage applied to terminals A and B isB A W D V DD V 256256256)(−+=(3) A more accurate calculation, which includes the effect of wiper resistance, V W , isB ABWA A AB WB W V R D R V R D R D V )()()(+=(4) Operation of the digital potentiometer in the divider mode results in a more accurate operation over temperature. Unlike the rheostat mode, the output voltage is dependent mainly on the ratio of the internal resistors R W A and R WB and not the absolute values. Therefore, the temperature drift reduces to 15 ppm/°C.3-WIRE SERIAL BUS DIGITAL INTERFACEThe AD5165 contains a 3-wire digital interface (SDI, CS, andCLK). The 8-bit serial word must be loaded MSB first. The format of the word is shown in Table 5.The positive-edge sensitive CLK input requires clean transitions to avoid clocking incorrect data into the serial input register. Standard logic families work well. If mechanical switches are used for product evaluation, they should be debounced by a flip-flop or other suitable means. When CS is high, the clock loads data into the serial register on each positive clock edge, as shown in Figure 34.The data setup and data hold times in the specifications table determine the valid timing requirements. The AD5165 uses an 8-bit serial input data register word that is transferred to the internal RDAC register when the CS line returns to logic low. Extra MSB bits are ignored.ESD PROTECTIONAll digital inputs are protected with a series of input resistors and parallel Zener ESD structures, shown in Figure 39 and Figure 40. This applies to the digital input pins SDI, CLK, and CS.04749-0-041Figure 39. ESD Protection of Digital Pins04749-0-042Figure 40. ESD Protection of Resistor TerminalsTERMINAL VOLTAGE OPERATING RANGEThe AD5165 V DD and GND power supply defines the boundaryconditions for proper 3-terminal digital potentiometer oper-ation. Supply signals present on terminals A, B, and W thatexceed V DD or GND are clamped by the internal forward-biaseddiodes, as shown in Figure 41.GNDA W BV DD04749-0-043Figure 41. Maximum Terminal Voltages Set by V DD and GNDPOWER-UP SEQUENCEBecause the ESD protection diodes limit the voltage compliance at terminals A, B, and W (see Figure 41), it is important topower V DD /GND before applying any voltage to terminals A, B, and W; otherwise, the diode is forward biased such that V DD is powered unintentionally and may affect the rest of the user’s circuit. The ideal power-up sequence is in the following order: GND, V DD , digital inputs, and then V A , V B , and V W . The relative order of powering V A , V B , V W , and the digital inputs is not important as long as they are powered after V DD /GND.AD5165Rev. 0 | Page 15 of 16LAYOUT AND POWER SUPPLY BYPASSINGIt is good practice to employ compact, minimum lead length layout design. The leads to the inputs should be as direct as possible with a minimum conductor length. Ground paths should have low resistance and low inductance.Similarly, it is also good practice to bypass the power supplies with quality capacitors for optimum stability. Supply leads to the device should be bypassed with disk or chip ceramiccapacitors of 0.01 µF to 0.1 µF. Low ESR 1 µF to 10 µF tantalum or electrolytic capacitors should also be applied at the supplies to minimize any transient disturbance and low frequency ripple (see Figure 42). Note that the digital ground should also be joined remotely to the analog ground at one point to minimize the ground bounce.V 04749-0-044Figure 42. Power Supply BypassingEVALUATION BOARDAn evaluation board, along with all necessary software, is available to program the AD5165 from any PC runningWindows® 98/2000/XP . The graphical user interface, as shown in Figure 43, is straightforward and easy to use. More detailed information is available in the user manual, which comes with the board.04749-0-046Figure 43. AD5165 Evaluation Board SoftwareThe AD5165 starts at midscale upon power-up. To increment or decrement the resistance, the user may move the scroll bars on the left. To write any specific value, the user should use the bit pattern in the upper screen and click the Run button. The format of writing data to the device is shown in Figure 32.AD5165Rev. 0 | Page 16 of 16OUTLINE DIMENSIONSCOMPLIANT TO JEDEC STANDARDS MO-193BAPLANEFigure 44. 8-Lead Thin Small Outline Transistor Package [Thin SOT-23](UJ-8)Dimensions shown in millimetersORDERING GUIDEodel R AB (Ω) Temperature Package Description Package Option Quantity on Reel BrandingAD5165BUJZ100-R21100 k –40°C to +125°C Thin SOT-23 UJ-8 250 D3N AD5165BUJZ100-R71 100 k –40°C to +125°C Thin SOT-23 UJ-8 3,000 D3N AD5165EVAL Evaluation Board1Z = Pb-free part.© 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04749–0–4/04(0)AD5165BUJZ100-R2AD5165BUJZ100。

M38B55ECXXXFP资料

Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp.The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself.Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices and power devices.Renesas Technology Corp.Customer Support Dept.April 1, 2003To all our customers元器件交易网DESCRIPTIONThe 38B5 group is the 8-bit microcomputer based on the 740 familycore technology.The 38B5 group has six 8-bit timers, a 16-bit timer, a fluorescent display automatic display circuit, 12-channel 10-bit A-D converter, a serial I/O with automatic transfer function, which are available for controlling musical instruments and household appliances.The 38B5 group has variations of internal memory size and packag-ing. For details, refer to the section on part numbering.For details on availability of microcomputers in the 38B5 group, refer to the section on group expansion.MITSUBISHI MICROCOMPUTERS38B5 GroupSINGLE-CHIP 8-BIT CMOS MICROCOMPUTERFEATURES•Basic machine-language instructions .......................................71•The minimum instruction execution time ..........................0.48 µs (at 4.19 MHz oscillation frequency)•Memory sizeROM.............................................24K to 60K bytes RAM ............................................512 to 2048 bytes•Programmable input/output ports .............................................55•High-breakdown-voltage output ports.......................................36•Software pull-up resistors ......(Ports P5, P61 to P65, P7, P84 to P87, P9)•Interrupts..................................................21 sources, 16 vectors •Timers ...........................................................8-bit ! 6, 16-bit ! 1•Serial I/O1 (Clock-synchronized)....................................8-bit ! 1......................(max. 256-byte automatic transfer function)•Serial I/O2 (UART or Clock-synchronized).....................8-bit ! 1•PWM .............................................................................14-bit ! 18-bit ! 1 (also functions as timer 6)•A-D converter..............................................10-bit ! 12 channels •Fluorescent display function ........................Total 40 control pins •Interrupt interval determination function .....................................1•Watchdog timer.............................................................20-bit ! 1•Buzzer output.............................................................................1•2 Clock generating circuitMain clock (X IN –X OUT ).........................Internal feedback resistor Sub-clock (X CIN –X COUT ).........Without internal feedback resistor (connect to external ceramic resonator or quartz-crystal oscillator )•Power source voltageIn high-speed mode ...................................................4.0 to 5.5 V (at 4.19 MHz oscillation frequency and high-speed selected)In middle-speed mode ...............................................2.7 to 5.5 V (at 4.19 MHz oscillation frequency and middle-speed selected)In low-speed mode ....................................................2.7 to 5.5 V (at 32 kHz oscillation frequency and low-speed selected)•Power dissipationIn high-speed mode ..........................................................35 mW (at 4.19 MHz oscillation frequency)In low-speed mode ............................................................60 µW (at 32 kHz oscillation frequency, at 3 V power source voltage)•Operating temperature range ...................................–20 to 85 °CAPPLICATIONMusical instruments, VCR, household appliances, etc.PR E L I M I N A R Y N o t i c e: T h i s i s no t a f i n a l s p e c i f i c a t i o n .So m e p a r am e t r i c l i m i t s a r e s u b j e c t t oc h a n g e .元器件交易网38B5 GroupSINGLE-CHIP 8-BIT CMOS MICROCOMPUTER2PR E L I M I N A R Y N o t i c e : T h i s i s n o t a f i n a l s p e c i f i c a t i o n .S om e p a r a m e t r i c l i mi t s a r e s u b j e c tt o c h a n g e .FUNCTIONAL BLOCK38B5 GroupSINGLE-CHIP 8-BIT CMOS MICROCOMPUTER3PR E L I M I N A R Y N o t i c e : T h i s i s n o t a f i n a l s p e c i f i c a t i o n .S om e p a r a m e t r i c l i mi t s a r e s u b j e c tt o c h a n g e .PIN DESCRIPTIONTable 1 Pin Description (1)Pin Name FunctionV CC , V SS Power source • Apply voltage of 4.0–5.5 V to V CC , and 0 V to V SS .V EE Pull-down • Apply voltage supplied to pull-down resistors of ports P0, P1, and P3.power sourceV REF Reference • Reference voltage input pin for A-D converter.voltage AV SSAnalog power • Analog power source input pin for A-D converter.source • Connect to V SS .______RESET Reset input • Reset input pin for active “L.”X INClock input• Input and output pins for the main clock generating circuit.• Feedback resistor is built in between X IN pin and X OUT pin.• Connect a ceramic resonator or quartz-crystal oscillator between the X IN and X OUT pins to set the oscillation frequency.• When an external clock is used, connect the clock source to the X IN pin and leave the X OUT pin open.• The clock is used as the oscillating source of system clock.P00/FLD 8–I/O port P0• 8-bit I/O port.• FLD automatic display P07/FLD 15• I/O direction register allows each pin to be individually programmed as either pinsinput or output.• At reset, this port is set to input mode.• A pull-down resistor is built in between port P0 and the V EE pin.• CMOS compatible input level.• High-breakdown-voltage P-channel open-drain output structure.• At reset, this port is set to V EE level.P10/FLD 16–Output port P1• 8-bit output port.• FLD automatic display P17/FLD 23• A pull-down resistor is built in between port P1 and the V EE pin.pins• High-breakdown-voltage P-channel open-drain output structure.• At reset, this port is set to V EE level.P20/B UZ02/I/O port P2• 8-bit I/O port with the same function as port P0.• FLD automatic display FLD 0–• Low-voltage input level.pinsP27/FLD 7• High-breakdown-voltage P-channel open-drain output structure.• Buzzer output pin (P20)P30/FLD 24–Output port P3• 8-bit output port.• FLD automatic display P37/FLD 31• A pull-down resistor is built in between port P3 and the V EE pin.pins• High-breakdown-voltage P-channel open-drain output structure.• At reset, this port is set to V EE level.P40/INT 0,I/O port P4• 7-bit I/O port with the same function as port P0.• Interrupt input pinsP41/INT 1,• CMOS compatible input level.P42/INT 3• N-channel open-drain output structure.P43/B UZ01• Buzzer output pin P44/PWM 1• PWM output pin (Timer output pin)P45/T 1OUT ,• Timer output pinP46/T 3OUT P47/INT 2Input port P4• 1-bit input port.• Interrupt input pin• CMOS compatible input level.Function except a port functionX OUT Clock output38B5 GroupSINGLE-CHIP 8-BIT CMOS MICROCOMPUTER4PR E L I M I N A R Y N o t i c e : T h i s i s n o t a f i n a l s p e c i f i c a t i o n .S om e p a r a m e t r i c l i mi t s a r e s u b j e c tt o c h a n g e .Table 2 Pin Description (2)Function except a port function Pin Name FunctionP50/S IN1,I/O port P5• 8-bit CMOS I/O port with the same function as port P0.• Serial I/O1 function pinsP51/S OUT1,• CMOS compatible input level.P52/S CLK11,• CMOS 3-state output structure.P53/S CLK12P54/R X D,• Serial I/O2 function pinsP55/T X D,P56/S CLK21,________P57/S RDY2/S CLK22P60/CNTR 1I/O port P6• 1-bit I/O port with the same function as port P0.• Timer input pin• CMOS compatible input level.• N-channel open-drain output structure.P61/CNTR 0/• 5-bit CMOS I/O port with the same function as port P0.• Timer I/O pinCNTR 2• CMOS compatible input level.________P62/S RDY1/• CMOS 3-state output structure.• Serial I/O1 function pin AN 8• A-D conversion input pin P63/AN 9• A-D conversion input pin P64/INT 4/• Serial I/O1 function pin S BUSY1/AN 10,• A-D conversion input pin P65/S STB1/• Interrupt input pin (P64)AN 11P70/AN 0–I/O port P7• 8-bit CMOS I/O port with the same function as port P0.• A-D conversion input pinP77/AN 7• CMOS compatible input level.• CMOS 3-state output structure.P80/FLD 32–I/O port P8• 4-bit I/O port with the same function as port P0.• FLD automatic display pins P83/FLD 35• Low-voltage input level.• High-breakdown-voltage P-channel open-drain output structure.P84/FLD 36• 4-bit CMOS I/O port with the same function as port P0.P85/RTP 0/• Low-voltage input level.• FLD automatic display pins FLD 37,P86/RTP 1/FLD 38P87/PWM 0/• FLD automatic display pins FLD 39• 14-bit PWM output P90/X CIN ,I/O port P9• 2-bit CMOS I/O port with the same function as port P0.• I/O pins for sub-clock generatingP91/X COUT• CMOS compatible input level. circuit (connect a ceramic resona-• CMOS 3-state output structure.tor or a quarts-crystal oscillator)38B5 GroupSINGLE-CHIP 8-BIT CMOS MICROCOMPUTER5PR E L I M I N A R Y N o t i c e : T h i s i s n o t a f i n a l s p e c i f i c a t i o n .S om e p a r a m e t r i c l i mi t s a r e s u b j e c tt o c h a n g e .PART NUMBERINGFig. 3 Part Numbering38B5 GroupSINGLE-CHIP 8-BIT CMOS MICROCOMPUTER6PR E L I M I N A R Y N o t i c e : T h i s i s n o t a f i n a l s p e c i f i c a t i o n .S om e p a r a m e t r i c l i mi t s a r e s u b j e c tt o c h a n g e .GROUP EXPANSIONMitsubishi plans to expand the 38B5 group as follows:Memory TypeSupport for Mask ROM, One Time PROM and EPROM versions.Memory SizeROM/PROM size ..................................................24K to 60K bytes RAM size ...........................................................1024 to 2048 bytesPackage80P6N-A .....................................0.8 mm-pitch plastic molded QFP 80D0........................0.8 mm-pitch ceramic LCC (EPROM version)Currently supported products are listed below.Table 3 List of Supported Products(P) ROM size (bytes)Product RAM size (bytes)Package RemarksROM size for User ( )As of Jan. 1998M38B57MC-XXXFP49152(49022)102480P6N-AMask ROM version38B5 GroupSINGLE-CHIP 8-BIT CMOS MICROCOMPUTER7PR E L I M I N A R Y N o t i c e : T h i s i s n o t a f i n a l s p e c i f i c a t i o n .S om e p a r a m e t r i c l i mi t s a r e s u b j e c tt o c h a n g e .FUNCTIONAL DESCRIPTION Central Processing Unit (CPU)The 38B5 group uses the standard 740 family instruction set. Refer to the table of 740 family addressing modes and machine instruc-tions or the 740 Family Software Manual for details on the instruction set.Machine-resident 740 Family instructions are as follows:•The FST and SLW instructions cannot be used.•The MUL, DIV, WIT and STP instructions can be used.Fig. 5 Structure of CPU Mode Register[CPU Mode Register] CPUMThe CPU mode register contains the stack page selection bit and internal system clock control bits. The CPU mode register is allo-cated at address 003B 16.38B5 GroupSINGLE-CHIP 8-BIT CMOS MICROCOMPUTER8PR E L I M I N A R Y N o t i c e : T h i s i s n o t a f i n a l s p e c i f i c a t i o n .S om e p a r a m e t r i c l i mi t s a r e s u b j e c tt o c h a n g e .MemorySpecial function register (SFR) areaThe special function register (SFR) area in the zero page contains control registers such as I/O ports and timers.RAMRAM is used for data storage and for stack area of subroutine calls and interrupts.ROMThe first 128 bytes and the last 2 bytes of ROM are reserved for device testing, and the other areas are user areas for storing pro-grams.Interrupt vector areaThe interrupt vector area contains reset and interrupt vectors.Zero pageThe 256 bytes from addresses 000016 to 00FF 16 are called the zero page area. The internal RAM and the special function registers (SFR)are allocated to this area.The zero page addressing mode can be used to specify memory and register addresses in the zero page area. Access to this area with only 2 bytes is possible in the zero page addressing mode.Special pageThe 256 bytes from addresses FF0016 to FFFF 16 are called the spe-cial page area. The special page addressing mode can be used to specify memory addresses in the special page area. Access to this area with only 2 bytes is possible in the special page addressing mode.Fig. 6 Memory Map Diagram38B5 GroupSINGLE-CHIP 8-BIT CMOS MICROCOMPUTER9PR E L I M I N A R Y N o t i c e : T h i s i s n o t a f i n a l s p e c i f i c a t i o n .S om e p a r a m e t r i c l i mi t s a r e s u b j e c tt o c h a n g e .Fig. 7 Memory Map of Special Function Register (SFR)I/O Ports[Direction Registers] PiD Array The 38B5 group has 55 programmable I/O pins arranged in eightindividual I/O ports (P0, P2, P40–P46, and P5–P9). The I/O portshave direction registers which determine the input/output direction ofeach individual pin. Each bit in a direction register corresponds toone pin, and each pin can be set to be input port or output port. When“0” is written to the bit corresponding to a pin, that pin becomes aninput pin. When “1” is written to that pin, that pin becomes an outputpin. If data is read from a pin set to output, the value of the portoutput latch is read, not the value of the pin itself. Pins set to input(the bit corresponding to that pin must be set to “0”) are floating andthe value of that pin can be read. If a pin set to input is written to, onlythe port output latch is written to and the pin remains floating.[High-Breakdown-Voltage Output Ports]The 38B5 group microprocessors have 5 ports with high-breakdown-voltage pins (ports P0–P3and P80–P83). The high-breakdown-volt-age ports have P-channel open-drain output with Vcc- 45 V of break-down voltage. Each pin in ports P0, P1, and P3 has an internal pull-down resistor connected to V EE. At reset, the P-channel output tran-sistor of each port latch is turned off, so that it goes to V EE level (“L”)by the pull-down resistor.Writing “1” (weak drivability) to bit 7 of the FLDC mode register (ad-dress 0EF416) shows the rising transition of the output transistors forreducing transient noise. At reset, bit 7 of the FLDC mode register isset to “0” (strong drivability).[Pull-up Control Register] PULLPorts P5, P61–P65, P7, P84–P87 and P9 have built-in programmablepull-up resistors. The pull-up resistors are valid only in the case thatthe each control bit is set to “1” and the corresponding port directionregisters are set to input mode.Fig. 8 Structure of Pull-up Control Registers (PULL1 and PULL2)SINGLE-CHIP 8-BIT CMOS MICROCOMPUTERTable 4 List of I/O Port Functions (1)Pin Name Input/Output I/O Format Non-Port Function Related SFRs Ref.No. P00/FLD8–Port P0Input/output,CMOS compatible input level FLD automatic display function FLDC mode register(1)P07/FLD15individual bits High-breakdown voltage P-Port P0FLD/port switch registerchannel open-drain outputwith pull-down resistorP10/FLD16–Port P1Output High-breakdown voltage P-FLDC mode register(2)P17/FLD23channel open-drain outputwith pull-down resistorP20/B UZ02/Port P2Input/output,Low-voltage input level Buzzer output (P20)FLDC mode register(3) FLD0individual bits High-breakdown voltage P-Port P2FLD/port switch registerP21/FLD1–channel open-drain output Buzzer output control register(1)P27/FLD7P30/FLD24–Port P3Output High-breakdown voltage P-FLDC mode register(2)P37/FLD31channel open-drain outputwith pull-down resistorP40/INT0,Port P4Input/output,CMOS compatible input level External interrupt input Interrupt edge selection register(4)P41/INT1,individual bits N-channel open-drain outputP42/INT3P43/B UZ01Buzzer output Buzzer output control register(5)P44/PWM1PWM output Timer 56 mode register(6)P45/T1OUT Timer output Timer 12 mode register(7)P46/T3OUT Timer output Timer 34 mode register(7)P47/INT2Input CMOS compatible input level External interrput input I nterrupt edge selection register(8)Interrupt interval determinationcontrol registerP50/SIN1Port P5Input/output,CMOS compatible input level Serial I/O1 function I/O Serial I/O1 control register 1, 2(9)P51/S OUT1,individual bits CMOS 3-state output(10)P52/S CLK11,P53/S CLK12P54/R X D,Serial I/O2 function I/O Serial I/O2 control register(9)P55/T X D,UART control register(10)P56/S CLK21________P57/S RDY2/(11)S CLK22P60/CNTR1Port P6CMOS compatible input level External count I/O Interrupt edge selection register(4)N-channel open-drain outputP61/CNTR0/CMOS compatible input level(12) CNTR2CMOS 3-state output________P62/S RDY1/Serial I/O1 function I/O Serial I/O1 control register 1, 2(13) AN8A-D conversion input A-D control registerP63/AN9A-D conversion input A-D control register(14)P64/INT4/Serial I/O1 function I/O Serial I/O1 control register 1, 2(15)S BUSY1/AN10A-D conversion input A-D control registerExternal interrupt input Interrupt edge selection registerP65/S STB1/Serial I/O1 function I/O Serial I/O1 control register 1, 2(16) AN11A-D conversion input A-D control registerP70/AN0–Port P7A-D conversion input A-D control register(14)P77/AN7Table 5 List of I/O Port Functions (2)Pin Name Input/Output I/O Format Non-Port Function Related SFRs Ref.No. P80/FLD32–Port P8Input/output,Low-voltage input level FLD automatic display function FLDC mode register(1)P83/FLD35individual bits High-breakdown voltage P-Port P8FLD/port switch registerchannel open-drain outputP84/FLD36Low-voltage input level(17) P85/RTP0/CMOS 3-state output FLD automatic display function FLDC mode register(18) FLD37,Real time port output Port P8FLD/port switch registerP86/RTP1/Timer X mode register 2FLD38P87/PWM0/FLD automatic display function FLDC mode register(19) FLD39PWM output Port P8FLD/port switch registerPWM control registerP90/X CIN Port P9CMOS compatible input level Sub-clock generating circuit I/O CPU mode register(20) P91/X COUT CMOS 3-state output(21) Notes 1 : How to use double-function ports as function I/O ports, refer to the applicable sections.2 : Make sure that the input level at each pin is either 0 V or Vcc during execution of the STP instruction.When an input level is at an intermediate potential, a current will flow from Vcc to Vss through the input-stage gate.SINGLE-CHIP 8-BIT CMOS MICROCOMPUTERSINGLE-CHIP 8-BIT CMOS MICROCOMPUTERInterruptsInterrupts occur by twenty one sources: five external, fifteen internal, and one software.(1) Interrupt ControlEach interrupt except the BRK instruction interrupt have both an interrupt request bit and an interrupt enable bit, and is controlled by the interrupt disable flag. An interrupt occurs if the corresponding interrupt request and enable bits are “1” and the interrupt disable flag is “0.” Interrupt enable bits can be set or cleared by software. Inter-rupt request bits can be cleared by software, but cannot be set by software. The BRK instruction interrupt and reset cannot be disabled with any flag or bit. The I flag disables all interrupts except the BRK instruction interrupt and reset. If several interrupts requests occurs at the same time the interrupt with highest priority is accepted first.(2) Interrupt OperationUpon acceptance of an interrupt the following operations are auto-matically performed:1. The contents of the program counter and processor statusregister are automatically pushed onto the stack.2. The interrupt disable flag is set and the correspondinginterrupt request bit is cleared.3. The interrupt jump destination address is read from the vectortable into the program counter.s Notes on UseWhen the active edge of an external interrupt (INT0–INT4) is set or when switching interrupt sources in the same vector address, the corresponding interrupt request bit may also be set. Therefore, please take following sequence:(1) Disable the external interrupt which is selected.(2) Change the active edge in interrupt edge selection register(3) Clear the set interrupt request bit to “0.”(4) Enable the external interrupt which is selected.SINGLE-CHIP 8-BIT CMOS MICROCOMPUTERTable 6 Interrupt Vector Addresses and PriorityVector Addresses (Note 1)Interrupt RequestInterrupt Source Priority RemarksHigh Low Generating ConditionsReset (Note 2)1FFFD16FFFC16At reset Non-maskableINT02FFFB16FFFA16At detection of either rising or falling edge of External interruptINT0 input(active edge selectable)INT13FFF916FFF816At detection of either rising or falling edge of External interruptINT1 input(active edge selectable)INT24FFF716FFF616At detection of either rising or falling edge of External interruptINT2 input(active edge selectable)Remort control/At 8-bit counter overflow Valid when interrupt interval counter overflow determination is operatingSerial I/O15FFF516FFF416At completion of data transfer Valid when serial I/O1 ordinarymode is selectedSerial I/O1 auto-At completion of the last data transfer Valid when serial I/O1 automatic matic transfer transfer mode is selectedTimer X6FFF316FFF216At timer X underflowTimer 17FFF116FFF016At timer 1 underflowTimer 28FFEF16FFEE16At timer 2 underflow STP release timer underflowTimer 39FFED16FFEC16At timer 3 underflowTimer 410FFEB16FFEA16At timer 4 underflowTimer 511FFE916FFE816At timer 5 underflowTimer 612FFE716FFE616At timer 6 underflowSerial I/O2 receive13FFE516FFE416At completion of serial I/O2 data receiveINT314FFE316FFE216At detection of either rising or falling edge of External interruptINT3 input(active edge selectable)Serial I/O2 transmit At completion of data transmitINT415FFE116FFE016At detection of either rising or falling edge of External interruptINT4 input(active edge selectable)Valid when INT4 interrupt is selectedA-D conversion At completion of A-D conversion Valid when A-D conversion is selected FLD blanking16FFDF16FFDE16At falling edge of the last timing immediately Valid when FLD blankingbefore blanking period starts interrupt is selectedFLD digit At rising edge of each digit Valid when FLD digit interrupt is selected BRK instruction17FFDD16FFDC16At BRK instruction execution Non-maskable software interrupt Notes 1 : Vector addresses contain interrupt jump destination addresses.2 : Reset function in the same way as an interrupt with the highest priority.SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Timers Array 8-Bit TimerThe 38B5 group has six built-in timers : Timer 1, Timer 2, Timer 3,Timer 4, Timer 5, and Timer 6.Each timer has the 8-bit timer latch. All timers are down-counters.When the timer reaches “0016,” an underflow occurs with the nextcount pulse. Then the contents of the timer latch is reloaded into thetimer and the timer continues down-counting. When a timerunderflows, the interrupt request bit corresponding to that timer isset to “1.”The count can be stopped by setting the stop bit of each timer to “1.”The internal system clock can be set to either the high-speed modeor low-speed mode with the CPU mode register. At the same time,timer internal count source is switched to either f(X IN) or f(X CIN).q Timer 1, Timer 2The count sources of timer 1 and timer 2 can be selected by settingthe timer 12 mode register. A rectangular waveform of timer 1underflow signal divided by 2 is output from the P45/T1OUT pin. Thewaveform polarity changes each time timer 1 overflows. The activeedge of the external clock CNTR0 can be switched with the bit 6 ofthe interrupt edge selection register.At reset or when executing the STP instruction, all bits of the timer 12mode register are cleared to “0,” timer 1 is set to “FF16,” and timer 2is set to “0116.”q Timer 3, Timer 4The count sources of timer 3 and timer 4 can be selected by settingthe timer 34 mode register. A rectangular waveform of timer 3underflow signal divided by 2 is output from the P46/T3OUT pin. Thewaveform polarity changes each time timer 3 overflows. The activeedge of the external clock CNTR1 can be switched with the bit 7 ofthe interrupt edge selection register.q Timer 5, Timer 6The count sources of timer 5 and timer 6 can be selected by settingthe timer 56 mode register. A rectangular waveform of timer 6underflow signal divided by 2 is output from the P44/PWM1 pin. Thewaveform polarity changes each time timer 6 overflows.q Timer 6 PWM1 ModeTimer 6 can output a rectangular waveform with “H” duty cycle n/(n+m) from the P44/PWM1 pin by setting the timer 56 mode register(refer to Figure 16). The n is the value set in timer 6 latch (address002516) and m is the value in the timer 6 PWM register (address002716). If n is “0,” the PWM output is “L,” if m is “0,” the PWM outputis “H” (n = 0 is prior than m = 0). In the PWM mode, interrupts occurat the rising edge of the PWM output.38B5 GroupSINGLE-CHIP 8-BIT CMOS MICROCOMPUTER20PR E L I M I N A R Y N o t i c e : T h i s i s n o t a f i n a l s p e c i f i c a t i o n .S om e p a r a m e t r i c l i mi t s a r e s u b j e c tt o c h a n g e .38B5 GroupSINGLE-CHIP 8-BIT CMOS MICROCOMPUTER21PR E L I M I N A R Y N o t i c e : T h i s i s n o t a f i n a l s p e c i f i c a t i o n .S om e p a r a m e t r i c l i mi t s a r e s u b j e c tt o c h a n g e .116-Bit TimerTimer X is a 16-bit timer that can be selected in one of four modes by the Timer X mode register 1, 2 and can be controlled the timer X write and the real time port by setting the timer X mode registers. Read and write operation on 16-bit timer must be performed for both high- and low-order bytes. When reading a 16-bit timer, read from the high-order byte first. When writing to 16-bit timer, write to the low-order byte first. The 16-bit timer cannot perform the correct operation when reading during write operation, or when writing during read operation.q Timer XTimer X is a down-counter. When the timer reaches “000016,” an underflow occurs with the next count pulse. Then the contents of the timer latch is reloaded into the timer and the timer continues down-counting. When a timer underflows, the interrupt request bit corre-sponding to that timer is set to “1.”(1) Timer modeA count source can be selected by setting the Timer X count source selection bits (bits 1 and 2) of the Timer X mode register 1.(2) Pulse output modeEach time the timer underflows, a signal output from the CNTR2 pin is inverted. Except for this, the operation in pulse output mode is the same as in timer mode. When using a timer in this mode, set the port shared with the CNTR2 pin to output.(3) Event counter modeThe timer counts signals input through the CNTR2 pin. Except for this, the operation in event counter mode is the same as in timer mode. When using a timer in this mode, set the port shared with the CNTR2 pin to input.(4) Pulse width measurement modeA count source can be selected by setting the Timer X count source selection bits (bits 1 and 2) of the Timer X mode register 1. When CNTR2 active edge switch bit is “0,” the timer counts while the input signal of the CNTR2 pin is at “H.” When it is “1,” the timer counts while the input signal of the CNTR2 pin is at “L.” When using a timer in this mode, set the port shared with the CNTR2 pin to input.s Note•Timer X Write ControlIf the timer X write control bit is “0,” when the value is written in the address of timer X, the value is loaded in the timer X and the latch at the same time.If the timer X write control bit is “1,” when the value is written in the address of timer X, the value is loaded only in the latch. The value in the latch is loaded in timer X after timer X underflows.When the value is written in latch only, unexpected value may be set in the high-order counter if the writing in high-order latch and the underflow of timer X are performed at the same timing.•Real Time Port ControlWhile the real time port function is valid, data for the real time port are output from ports P85 and P86 each time the timer X underflows. (However, if the real time port control bit is changed from “0” to “1,”data are output without the timer X.) When the data for the real time port is changed while the real time port function is valid, the changed data are output at the next underflow of timer X.Before using this function, set the corresponding port direction regis-ters to output mode.22。

AD800 变频器电子版

第四章:操作与显示 …………………………………………………………………………27 4.1 操作界面介绍 ………………………………………………………………27 4.2 按键功能说明 ………………………………………………………………27 4.3 监控状态一览表………………………………………………………………22 4.4 功能码查看及修改方法………………………………………………………30 4.5 密码设置………………………………………………………………………30 4.6 电机试运行……………………………………………………………………31
3）、变频器已经内置适配电机标准参数，根据实际情况有必要进行电机参数辨识或修改缺省值
以尽量符合实际值，否则会影响运行效果及保护性能。 4）、由于电缆或电机内部出现短路会造成变频器报警，甚至炸机。因此，请首先对初始安装的
变频器型号空开mccb推荐接触器推荐输入侧主回路导线mm推荐输出侧主回路导线mm推荐控制回路导线mm单相220vad800s04gb1610252510ad800s07gb1610252510ad800s15gb2016402510ad800s22gb3220604010第三章产品安装ad800系列矢量型变频器用户手册变频器型号空开mccb推荐接触器推荐输入侧主回路导线mm推荐输出侧主回路导线mm推荐控制回路导线mm三相220vad8002t04gb1010252510ad8002t075gb1610252510ad8002t11gb1610252510ad8002t22gb2516404010ad8002t37gb3225404010ad8002t55gb6340404010ad8002t75gb6340606010ad8002t11g10063101015ad8002t15g125100161015ad8002t185g160100161615ad8002t22g200125252515ad8002t30g200125352515ad8002t37g250160503515ad8002t45g250160703515ad8002t55g35035012012015ad8002t75g50040018518515三相380vad8004t07gb1010252510ad8004t15gb1610252510ad8004t22gb1610252510ad8004t37gb2516404010ad8004t55gbad8004t75pb3225404010ad800系列矢量型变频器用户手册第三章产品安装变频器型号空开mccb推荐接触器推荐输入侧主回路导线mm推荐输出侧主回路导线mm推荐控制回路导线mmad8004t75gbad8004t11pb4032404010ad8004t11gbad8004t15pb6340404010ad8004t15gbad8004t185pb6340606010ad8004t185gbad8004t22p1006315ad8004t22gad8004t30p10063101015ad8004t30gad8004t37p125100161015ad8004t37gad8004t45p160100161615ad8004t45gad8004t55p200125252515ad8004t55

MT6516_BOM

MT6516_BOM1二合一存储器，4Gbit(256M*16bits)NAND flash 1.8V + 2Gbit(61模拟开关13mm*5mm*1mm LGA-14 Package ;Self test for Z-Axis ;1接近传感器＋环境光传感器 (2.35 x 1.8 x 1.0 mm)13-axis Magnetic Sensor,2.7V~5.25V,3.0x3.0x1.0mm132.768KHZ晶振（±20ppm，12.5pF） LeadFree5键盘背光灯//跑马灯白灯 0603封装1顶发光红外LED，850nm红外光，与CM3601配套，尺寸2.2*1.4*1.4mm1正发光RGB三色灯，尺寸：1.6*1.5*0.5MM,Vf红/绿/蓝=1.8-2.0/2.7-3.19单路TVS,单向 VRWM=5V VBR=6.2V C=65pF 1.0 mm x 0.60 mm1EMI_Filter: 共模阻抗370欧（100MHz20摄氏度）；额定电流：280mA；额定电压5 1单路TVS,双向，Working Voltage 5V，Cj=4pF，1.0 x 0.6 x 0.4ESD+EMI Filter-4，直流阻抗10R1.3V or less 6.5uAh 容量0.02F 充电电流：<0.005mA,顶部极性：正极，1模拟TV芯片支持PAL，NTSC，SECAM 三种制式QFn(56Pin,7*7*1mm),Rohs1带LDOmode的充电保护IC Overvoltage and Overcurrent Protec2CAP,15pF±5%,50V,04021CAP,C0G,10PF±0.5PF,50V,0402,RoHs140402-C0G-22p±5%-50V90402-C0G-27p±5%-50V200402-C0G-33p±5%-50V10402-C0G-47p±5%-50V1CAP,C0G,2.2PF±0.25pF,50V,0402,RoHs1CAP,C0G,4.7PF±0.25pF,50V,0402,RoHS12CAP,X7R,1NF±10%,50V,0402,RoHs8CAP,X7R,10NF±10%,16V,0402,RoHs1CAP,X7R,33NF±10%,10V,0402,RoHs44CAP,X5R,100NF±10%,10V,0402,RoHs40402-C0G-5.6PF±0.25PF-50V1CAP,X7R,220PF±5%,50V,0402,RoHs20402-X7R-220n±10%-6.3V6CAP,C0G,18PF±5%,50V,0402,RoHs53CAP,X5R,1UF±10%,6.3V,0402,RoHs4CAP,C0G,100PF±5%,50V,0402,RoHs2CAP,C0G,39PF±5%,50V,0402,RoHs3CAP,C0G,56PF±5%,50V,0402,RoHs2CAP,X7R,1UF±10%,16V,0805,RoHs2CAP,COG，120pF±5%，50V，0402，ROHS2CAP,C0G,82PF±5%,50V,0402,RoHs1CAP,C0G,0.75PF±0.25p,50V,04022TAIYOYUDEN//TDK//MURATA4CAP,X5R,2.2UF±10%,6.3V,0603,RoHs260603-X5R-4.7u±10%-6.3V7CAP,X5R,10UF±10%,16V,08052TAN CAP,47uF±20%,6.3V，1206(3.2*1.6*1.6mm),RoHs2肖特基二极管,Vr=30V,Io=100mA,Vf=0.45V@10mA,VMD2封装,1.4*0.2肖特基二极管,Vr=20V,Io=500mA,Vf=0.36V@100mA,UMD2封装,2.5*11稳压二极管VZ=5.6V 2%精度,200mW, SOD-523 ,1.2*0.8*0.6(H)2Zener diode VZ=5.1V,500mW, SOD323兼容0805 ,2.7*1.45* 150V，150mA，NPN 三极管，EMT3，1.6*1.6*0.7（H）8NPN数字晶体管1P_Channel 1.8V(G-S)MOSFET With Schottky Diode Lead12.5V Drive Nch MOSFET, ID=100mA; Decal ：EMT3/SOT-1磁珠电感，0603,1000R@100mHz,RoHs2IND-0402,8.2NH±5%,450mΩ,250mA5IND-0402 15nH±5% 440mΩ 350mA,RoHs2IND-0402,2.2NH±0.3NH,220mΩ,300mA5IND-0402 4.7nH±0.3NH 190mΩ 400mA,RoHs1IND-0402 18nH±5% 530mΩ 250mA,RoHs1IND-0402,3.3nH±0.3NH,160mΩ,400mA,RoHs2IND-0402,27NH±5%,,700mΩ,300m1IND-0402 150nH±5%2IND-0402,39NH±5%,500mΩ,300mA1IND-0402,33NH±5%,,630mΩ,260mA1IND-0402,7.5nH±0.5%,330mΩ,300mA,RoHs2IND-0603,330nH±5%,2.5Ω,,RoHs5IND-0806，4.7UH±20％,300mA,0.8Ω,RoHs1bead-0603,25000hz,100mhz2775Ω@100MHz,直流电阻0.3,额定电流600mA,封装04021QUAL BAND GSM/GPRS RF transceiver IC，5*5mm，RoHs 1Worldwide FM band support: 76~108MHz 2.7 to 3.6 V1GSM/GPRS/EDGE Application Processor，TFBGA 15mm*15m 1PMIC for 2G/3G handsets and smartphones,input rang1GPS芯片 QFN 尺寸：6mm*6mm*0.85mm1闪光灯驱动芯片16路白色LED共阳驱动，带Charge Pump320402-0R±5％-1/16W30402-10R±5％-1/16W1RES,82Ω±5%,50V,1/16W,0402120402-100R±5％-1/16W230402-1K±5％-1/16W30402-1.5K±5％-1/16W1RES,100K±1%,50V,1/16W,0402150402-100K±5％-1/16W10402-10K±5％-1/16W10402-15K±5％-1/16W2RES,24K±1%,50V,1/16W,040290402-47K±5％-1/16W1RES,12.1K±1%,50V,1/16W,04024RES,2.49K±1%,50V,1/16W,04023RES,33R±5%,50V,1/16W,04022RES,5.1K±1%,50V,1/16W,04022RES,150Ω±1%,50V,1/16W,04021RES,3KΩ±1%,50V,1/16W,04028RES,4.7K±5%,50V,1/16W,04023RES,22R±5%,50V,1/16W,04021RES,1.8K±5%,50V,1/16W,04021RES,523R±1％,50V,1/16W,040210402-51R±5％-1/16W50402-2.2K±5％-1/16W10402贴片电阻(24kΩ)10402贴片电阻（4.7Ω）1RES,0Ω±5%,1/8W,06031RES,0.2Ω±1%,50V,1/4W,08052resistor array 330ohm 8pin ±5% 040224Working Voltage Vdc=18V(max)，Varistor Voltage in V2Vrwm=5.3V Vbr=6V,Vclamp=15V,Cj=0.5pF(typ)，兼容0402封装1RF PA Qual-Band GSM850/GSM900/DCS/PCS Transmit Mod 127MHz 晶体 12pf +-10ppm,3.2X2.5X0.7mm126MHz crystal 8.2pF +-10ppm,3.2X2.5X0.7mm126.000MHz Crystal for AD6548116.368M±0.5ppm,3.2*2.5mm,RoHs.供电电压: 2.8v工作温度: -30-1Bluetooth IC 5*5*0.9 QFN support BT3.0 BT2.1+EDR C 1SAW FILTER 850,1.4*1.1*0.6mm,RoHs1SAW FILTER 1900,1.4*1.1*0.6mm,RoHs1GSM/DCS 2 in 1 RX Saw filter for MT6129,1.8*1.4*01MT6611 bluetooth balance filter,2.0*1.25mm,RoHs11.4*1.2*0.55；1573.92 to 1576.92MHz；1.2dB；1 WIFI模块9.0 x 9.0 x 1.6mm (with shielding case）531K524G2GACB-A050SAMSUNGPI5A4684GAEX PericomMMA7455LR1FreescaleCM3623A3OP Capella MicrosystemsMMC3140MR MEMSICMS2V-T1S(32.768kHz12.5 pF+/-20ppm)//Q13MC146100020MICRO CRYSTAL//EPSON//SII AOT-0603W331A-N0-X-3-M//SP0603B-WW//LTW-C193TS5AOT//Solidlite//LITE-ONCM3652C3OZ Capella MicrosystemsAOT-1615RGB43A-Z0-N-3-M AOTESD9X5.0ST5G//UM5059//ESD9X5V-2/TR//DF2S6.8FS ONSEMI//UNION//WILL//TOSHIBADLW21SN371SQ2//ECS21P2-361muRata//ABCOCP64002T.TCT SemtechICVE21184E070R100FR ICTXH311HG IV07E SIITLG1120TelegentBQ24382DSGR TITAIYOYUDEN//TDK//MURATA//SamsungUMK105CH150JW-F(TaiyoYuden)//C1005CH1H150JT（TDK）// UMK105CH100DW-F(TaiyoYuden) //C1005C0G1H100DT ( T TAIYOYUDEN//TDK//MURATA//Samsung UMK105CH220JW-F(TaiyoYuden) //C1005C0G1H220JT (TD TAIYOYUDEN//TDK//MURATA//Samsung UMK105CG270JW-F(TaiyoYuden)//C1005C0G1H270JT ( TD TAIYOYUDEN//TDK//MURATA//Samsung UMK105CG330JW-F( TaiyoYuden) //C1005C0G1H330JT(TD TAIYOYUDEN//TDK//MURATA//Samsung C1005C0G1H470JT TDKTDK//SamsungC1005C0G1H2R2CT(TDK)//CL05C2R2CB5ANNC(SAMSUNG TDK//SamsungC1005C0G1H4R7CT(TDK)//CL05C4R7CB5ANNC(SAMSUNG UMK105BJ102KV-F (TaiyoYuden)//C1005X7R1H102KT(TDK TAIYOYUDEN//TDK//MURATA//SamsungTAIYOYUDEN//TDK//MURATA//Samsung EMK105BJ103KV-F(TaiyoYuden) //C1005X7R1C103KT( TDKLMK105BJ333KV-F TAIYOYUDENLMK105BJ104KV-F(TaiyoYuden) //C1005X5R1A104KT ( TD T AIYOYUDEN//TDK//MURATA//Samsung C1005C0G1H5R6DT TDKUMK105SL221JV-F(TaiyoYuden)//C1005X7R1H221JT(TDK)TAIYOYUDEN//TDK//MURATA//Samsu ng LMK105BJ224KV-F(TaiyoYuden)//C1005X5R1A224KT( TDKTAIYOYUDEN//TDK//MURATA//Samsung UMK105CH180JW-F(TaiyoYuden)//C1005C0G1H180JT(TDKTAIYOYUDEN//TDK//MURATA//Samsung JMK105BJ105KV-T(TaiyoYuden) //C1005X5R0J105KT(TD TAIYOYUDEN//TDK//MURATA//SamsungTAIYOYUDEN//TDK//MURATA//SamsungUMK105CG101JW-F(TaiyoYuden)//C1005C0G1H101JT(TDK TDK//MURATA//SamsungC1005C0G1H390JT// GRM1555C1H390JZ01D//CL05C390JB GRM1555C1H560JZ01D//C1005C0G1H560J muRataGRM21BR71C105KA01L muRataGRM1555C1H121JA01D//C1005C0G1H121JT//UMK105CG1 Murata //TDK //TAIYOGRM1555C1H820JZ01D//C1005C0G1H820J muRata//tdkGJM1555C1HR75CB01MURATAEMK105BJ153KV-F //C1005X7R1C153KT//GRM155R71C15 TAIYOYUDEN//TDK//MURATA//Samsung JMK107BJ225KA-T （TaiyoYuden)//C1608X5R0J225KT(TDK)TAIYOYUDEN//TDK//MURATA//Samsung JMK107BJ475KA-T （TaiyoYuden） //C1608X5R0J475KT(TDK)EMK212BJ106KG-T//CM21X5R106K16AT TAIYO//KyoceraTMCMA0J476MTRF//F930J476MAA Hitachi //NichiconRB520G-30//RB520G-30ROHM//长电RB551V-30//RB551V-30//BAT54HT1CJ//ROHM//OnsemiNSZ5V6V2T1G//EDZ5.6B//EDZTE615.6B//BZX584C5V6AUNET//高登路//ROHM//长电PZ3D4V2H Prisemi2DC4617R//2SC4617R DIODES//ROHMDTC114EET1G ONSI5853CDC//NTHD4P02FT1//AON4701//AON4703//TPCF8BVISHAY//ONSEMI//AOS//AOS//T oshiba 2SK3019TL//2N7002T Rohm//长电MMZ1608S102AT TDKMLK1005S8N2D TDKMLK1005S15NJT(TDK)//HK1005 15NJ-T(TaiyoYuden) TDK//TaiyoYudenMLK1005S2N2S TDKMLK1005S4N7ST(TDK) // HK1005 4N7S-T(TaiyoYuden)TDK//TaiyoYudenMLK1005S18NJ TDKMLK1005S3N3S TDKMLK1005S27NJT TDKMLG1005SR15JT(TDK)//HK 1005 R15J-T(TAIYO) TDK //T aiyo LQG15HS39NJ02D muRataLQW15AN33NJ00D//0402CS-33NXJLW//0402AS-033J-01muRata//CoilCraft//Fastron LQG15HS7N5J02D Murata HK1608R33J-T//LQM18NNR33K00D Taiyo//muRataLQH2MCN4R7M02MurataBLM18BD252SN1//SZ1608K252T Murata//SunlordSZ1005G750SunlordAD6548ADIAR1010AIROHAMT6516A MTKMT6326A MTKMT3326MTKRT9361APE RICHTEKRP1366GQW Richpower(UNI)0402WGJ0000TCE//(ROHM)MCR01MZPJ000//(Yageo) UNI//ROHM//Yageo(UNI)0402WGJ0100TCE//(ROHM)MCR01MZPJ100//(Yageo)UNI//ROHM//YageoMCR01MZPJ820Rohm(UNI)0402WGJ0101TCE//(ROHM)MCR01MZPJ101//(Yageo) UNI//ROHM//Yageo(UNI)0402WGJ0102TCE//(ROHM)MCR01MZPJ102//(Yageo)UNI// ROHM//Yageo(UNI)0402WGJ0152TCE//(ROHM)MCR01MZPJ152//(Yageo)UNI// ROHM//Yageo(UNI)0402WGF1003TCE//(ROHM)MCR01MZPF1003//(Yage UNI//ROHM//YageoMCR01MZPJ104 ROHMMCR01MZPJ103 ROHMMCR01MZPJ153 ROHM(UNI)0402WGF2402TCE//(ROHM)MCR01MZPF2402//(Yage UNI//ROHM//Yageo(UNI)0402WGJ0473TCE//(ROHM)MCR01MZPJ473//(Yageo)UNI// ROHM//Yageo0402WGF1212TCE UNI-OHM0402WGF2491TCE UNI-OHM(UNI)0402WGJ0330TCE//(ROHM)MCR01MZPJ330UNI//ROH M(UNI)0402WGF5101TCE UNI//Panasonic0402WGF1500TCE Uni(UNI)0402WGF3001TCE//(Yageo)RC0402FR-073KLUNI/Yageo0402WGJ4701TCE优你/UNI-OHM0402WGJ0220TCE优你/UNI-OHMRC0402JR-071K8L//0402WGJ0182TCE Yageo //UNI0402WGF5230TCE UNI0402WGJ0510TCE//RC0402JR-0751RL UNI //YAGEOCR1/16S-222J-V//RC0402JR-072K2//MCR01MZPJ222//0402HDK//YAGEO//ROHM//UNIRC0402JR-0724KL//RMC1/16S-243J-TH//CR1/16S-243J-V/y ageo//KAMAYA//HDK//UNI RK73B1E4R7J//CR1/16S-4R7-JV//MCR01MZPJ4R7//0402W KOA//HDK//ROHM//UNI 0603WGJ0000T5E UNI-OHM(UNI)0805S8F200LT5E//(ROHM)MCR10EZHFLR200UNI//ROHMYC124-JR-07330R//4D02WGJ0331TCE YAGEO//UNIAVLC18S02015//VS10-180A-100AMOTECH//CTCESD9L5.0ST5G//ESD9X5VU-2/TR ONSEMI//WILLRF7161RFMDNX3225DA//TZ0462A//E3SB27.0000F12E13ST//E3SB27.000 NDK//TAI-SAW//鸿讯企业//鸿星NDK//TAI-SAW//TXC//KDSNX3225SA（W-211-133）//TZ0928A//7M26000314//1C3260007M26000018//FXS32-26.000-10CE11P TXC//菲卡电子1XTW16368CAB KDSMT6612N-L MTKSAFBA942MFL0F00muRataSAFEA1G96FA0F00R14MurataSAWEN942MCN0F00R14//B9500muRata //EPCOSBBF-2012-2G4H6-B4//FB2012-06N2R4MT/LFMaglayer//ACXSAFEB1G57KE0F00MURATAWG2250-00WDIVCNL4000TR6020A//SamsungA//Samsung A//Samsung A//Samsung A//Samsung A//Samsung A//Samsung A//Samsung A//Samsung A//Samsung A//Samsung A//Samsung A//Samsung A//Samsung A//Samsung。

【最新】博瑞,说明书-范文word版 (7页)

本文部分内容来自网络整理，本司不为其真实性负责，如有异议或侵权请及时联系，本司将立即删除！== 本文为word格式，下载后可方便编辑和修改！ ==博瑞,说明书篇一：吉利博瑞新浪汽车讯 201X年12月15日，吉利汽车全新旗舰车型GC9在水立方完成首秀并发布中文名：吉利博瑞。

据透露，新车将于明年上半年上市。

作为吉利汽车标志性的产品，GC9由吉利集团造型设计高级副总裁彼得?霍布里领衔的国际化造型团队担纲设计工作，吉利产品未来全新的造型设计语言和趋势也由此体现。

新车亮点： A.多种动力组合，3.5L V6发动机受人瞩目；B.配置豪华，性价比高；C.外观设计大气美观。

现场直击：“吉利汽车品牌之夜”在北京水立方举行，当晚吉利全新旗舰车型GC9完成首秀并公布中文名字“博瑞”。

吉利集团总裁安聪慧介绍了博瑞的背景与相关研发情况，随后沃尔沃总裁萨缪尔森也上台致辞。

此外，吉利还邀请了法雷奥、德国大陆、博世等世界领先汽车零部件供应商的中国区代表上台发言。

最后，吉利宣布与中国游泳队达成战略合作伙伴协议。

外观方面，吉利博瑞由原沃尔沃汽车副总裁霍布里担纲设计，整车保留了许多“KC Concept”概念车元素。

夸张的车头环状格栅造型取材于水波纹，而下格栅网格则与中国传统的回纹图案神似。

后部采用“快背式”设计风格，使整车更接近轿跑的感觉，营造出强烈的运动感。

内饰方面，博瑞定位于中级轿车，内饰也不遗余力地营造出越级的豪华感。

全彩3D立体表盘组合仪表、HUD抬头显示系统、8向电动调节真皮座椅、副驾驶座椅老板键、360全景倒车影像系统等等，都是博瑞的亮点，对于用户来说提供了舒适与便利。

动力方面，博瑞提供2.4L、1.8T和3.5L V6发动机可供选择。

其中，入门级车型配置的2.4L发动机在帝豪EC8车型上已经配置，这款4G24型号发动机的最大功率为119kW，最大扭矩210Nm，自主研发的1.8T涡轮增压发动机，最大功率可达135Kw，峰值扭矩则达到了285Nm。