8I848P-G Rev.2.02

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Product_Overview_by_Linglin

NEXUS
Target voltage 1.8 .. 3.6 V 600 MHz effective sample rate Supports Embedded Trace
Macrocell (ETM)
Supports Program Trace Macrocell
(PTM)
Support of High-Speed Serial Trace Port Compatible to Xilinx Aurora protocol Support of up to four differential lanes Maximum 6,25Gbit/s lane speed Up to 24 Giga CPU cycles

Support for ARM/CORTEX, PIC32, X-GOLD110, X-GOLD102 ACTEL, ARM, ATMEL, CYPRESS, ENERGYMICRO, FREESCALE, FUJITSU, INFINEON, LUMINARYMICRO, MICROCHIP, MIPS, NXP, SAMSUNG, STM, TI, TOSHIBA
Export Form 2011▪ Linglin He ▪ 2011/ August / 18
▪ 5
Products
Power Debugger
Debug Cable
Processor specific adaption Contains software license Supported Processor Families: ARM/XSCALE Power Architecture MIPS32/MIPS64 Intel Atom™/x86 78K0R/RL78 APS AVR32 C166CBC CPU32 ColdFire H8S/23x9 M32R M-Core MCS08 MSP430 RX S12X SH TriCore V850 VR XC2000/C166SV2 XC800 DSPs Softcores Configurable Cores Auxiliary Processors

NI-488.2

Additiona you already have installed NI-488.2 for macOS, you can access the online NI-488.2 help by launching GPIB Explorer and clicking Help»NI-488.2 on the menu bar. Visit /macdrivers to find the latest macOS drivers for your NI products.
© 2002–2019 National Instruments. All rights reserved.
371333F-01
May19
4 | | NI-488.2™ for macOS Getting Started Guide
NI corporate headquarters is located at 11500 North Mopac Expressway, Austin, Texas, 78759-3504. NI also has offices located around the world. For telephone support in the United States, create your service request at /support or dial 1 866 ASK MYNI (275 6964). For telephone support outside the United States, visit the Worldwide Offices section of / niglobal to access the branch office websites, which provide up-to-date contact information, support phone numbers, email addresses, and current events.

865PE(IS8)说明书

在您安装主板以及加入硬件设备之前，请仔细阅读本手册提供的相关信息。

在使用本产品前，请确定所有的排线、电源线都已正确连接好。

若您发现有任何重大瑕疵，请尽快联络您的经销商。

为避免发生电气短路情形，请务必将所有没用到的螺丝、回形针及其他零件收好，不要遗留在主板上或电脑主机中。

灰尘、湿气以及剧烈的温度变化都会影响主板的使用寿命，因此请尽量避免放置在这些地方。

请勿将电脑主机放置在容易摇晃的地方。

若在本产品的使用上有任何的技术问题，请和经过检定或有经验的技术人员联络。

为避免可能的电击造成严重损害，在搬运电脑主机前，请先将电脑电源线暂时从电源插座中拔掉。

当您要加入硬件设备到系统中或者要去除系统中的硬件设备时，请务必先连接该设备的信号线，然后再连接电源线。

可能的话，在安装硬件设备前先拔掉电脑的电源供应器电源线。

当您要从主板连接或拔除任何的信号线前，请确定所有的电源线已事先拔掉。

如果电源供应器已损坏，请不要尝试自行修复。

请将之交给专业技术服务人员或经销商来处理。

请确认您所购买的昂达865PEN主板包装盒是否完整，如果有包装损坏或是有任何配件短缺的情形，请尽快与您的经销商联系。

☞昂达865PEN主板一块☞Ultra DMA66/100 IDE排线一根☞Serial ATA排线一根(可选)☞软驱排线一根☞驱动程序光盘一张☞本用户手册一本☞保修卡一张2.1 产品概述昂达865PEN主板采用了Intel 82865PE和82801EB芯片组，为用户提供了一个集成度高、兼容性强、性价比出众的ATX 系统平台，性能稳定，价格合理，适合于高档商业用机、家庭娱乐用。

2.2 特点介绍—板型结构ATX结构，主板尺寸为305mmX218mm—中央处理器支持478 Socket Intel Pentium 4处理器支持400/533/800MHz FSB Intel P4 478结构CPU仅支持Northwood核心的P4和Celeron4，Prescott CPU及Intel Hyper-threading(超线程技术) Pentium 4 CPU—芯片组北桥：Intel 865PE南桥：Intel 82801EB—系统存贮器4个184-PIN 的DDR内存插槽支持DDR266/333/400MHz内存支持双通道DDR内存（两个同类型内存条分别插入DIMM1&3或DIMM2&4可组成双通道，可提高内存性能）—IDE接口功能支持主从两个IDE通道和两个Serial ATA通道可连接四个独立的驱动器支持Ultra DMA 33/66/100/Serial ATA 多种硬盘传输模式—扩展槽5个32位PCI扩展卡扩充插槽—音频6 声道软声卡解码遵循AC97 v2.2规格符合PC2001 音频性能要求可以通过S-Bracket支持SPDIF输出—AGP插槽1个AGP 8X插槽支持AGP 4X/8X数据读写或传输，最高速度可达2GBps—主板I/O接口功能主芯片之间采用中心加速结构连接技术，提供了更高的数据交换带宽两个串行端口，兼容高速16550 UART模式1个并行端口，支持ECP和EPP模式2个PS/2端口（一个键盘和一个鼠标）1个红外端口1个RJ-45 LAN插孔(可选)1个软驱接口，可支持两个软盘驱动器音频插孔（Microphone, Line-in和Line-out）—8 USB2.0接口功能符合USB2.0规范，最高速度为480Mbit/sec—BIOS支持对于周边设备和扩展卡支持即插即用—板载LAN（可选）板上自带10/100M LAN接口支持10Mb/s和100Mb/s自动交换模式兼容PCI v2.2，mini PCI 1.0和板载标准—电源供电和电源管理ATX电源接口，符合ACPI 1.0b和APM 1.2规范支持Modem唤醒，网络唤醒等各种电源管理功能备注：以上位置图与您的主板布局可能存在不同，仅供参考。

ARIES ARIES-P -Ver.04- 8 0 2 7 9 0 8 1 1 3 7 4 0 产

ISTRUZIONI D'USO E DI INSTALLAZIONE INSTALLATION AND USER'S MANUALINSTRUCTIONS D'UTILISATION ET D'INSTALLATION INSTALLATIONS-UND GEBRAUCHSANLEITUNG INSTRUCCIONES DE USO Y DE INSTALACION INSTRUÇÕES DE USO E DE INSTALAÇÃOCENTRALINA DI COMANDO D811184A ver. 04 08-02-02I CONTROL UNIT GB UNITÉ DE COMMANDE F STEUERZENTRALE D CENTRAL DE MANDO E CENTRAL DO MANDOP ARIES - ARIES P8027908113740a“WARNINGS” leaflet and an “INSTRUCTION MANUAL”.These should both be read carefully as they provide important information about safety, installation, operation and maintenance. This product complies with the recognised technical standards and safety regulations. We declare that this product is in conformity with the following European Directives: 89/336/EEC and 73/23/EEC (and subsequent amendments).1) GENERAL OUTLINEThe ARIES control unit has been designed for swing gates. It can be used for one or two gate controllers.The control unit mod. ARIES P can also be used to perform opening of a single actuator while keeping the other one closed (pedestrian access).2) FUNCTIONSSTOP: In all cases: it stops the gate until a new start command is given.PHOT:Functions can be set with Dip-Switch.Activated during closing.Activated during opening and closing.Rapid closingON: When the position of the gate photocells is exceeded, during both opening and closing, the gate automatically starts to close even if TCA is activated. We recommend setting DIP3 to ON (photocells only activated during closing).Blocks impulsesON: During opening, START commands are not accepted.OFF: During opening, START commands are accepted.PhotocellsON: Photocells only activated during closing.OFF: Photocells activated during opening and closing.Automatic closing time (TCA)ON: Automatic closing activated (can be adjusted from 0 to 90s)Preallarm (mod. ARIES P only)ON: The flashing light turns on abt 3 seconds before the motors start.FOR THE INSTALLER: check the boxes you are interested in.START:four-step logic Gate closedGate openDuring openingDuring closingAfter stop START: two-step logic SCA: Gate open indicating lightit opens it opensit stops and activates TCAit closesit stops and does not activate TCAit starts opening it stops and activats TCA (if activated)it closesit opensit opensoffononflashingATTENTION:Dip non used in mod. ARIES (always in OFF set).3) MAINTENANCE AND DEMOLITIONThe maintenance of the system should only be carried out by qualified personnel regularly. The materials making up the set and its packing must be disposed of according to the regulations in force.Batteries must be properly disposed of.WARNINGSCorrect controller operation is only ensured when the data contained in the present manual are observed. The company is not to be held responsible for any damage resulting from failure to observe the installation standards and the instructions contained in the present manual.The descriptions and illustrations contained in the present manual are not binding. The Company reserves the right to make any alterations deemed appropriate for the technical, manufacturing and commercial improvement of the product, while leaving the essential product features unchanged, at any time and without undertaking to update the present publication.D 811184A _04Thank you for buying this product, our company is sure that you will be more than satisfied with the product ’s performance. The product is supplied with a “WARNINGS ” leaflet and an “INSTRUCTION MANUAL ”.These should both be read carefully as they provide important information about safety, installation, operation and maintenance.This product complies with the recognised technical standards and safety regulations. We declare that this product is in conformity with the following European Directives: 89/336/EEC and 73/23/EEC (and subsequent amendments).1) GENERAL OUTLINEThe ARIES control unit has been designed for swing gates. It can be used for one or two gate controllers.The control unit mod. ARIES P can also be used to perform opening of a single actuator while keeping the other one closed (pedestrian access).2) GENERAL SAFETYWARNING! An incorrect installation or improper use of the product can cause damage to persons, animals or things.•The “Warnings ” leaflet and “Instruction booklet ” supplied with this product should be read carefully as they provide important information about safety, installation, use and maintenance.•Scrap packing materials (plastic, cardboard, polystyrene etc) according to the provisions set out by current standards. Keep nylon or polystyrene bags out of children ’s reach.•Keep the instructions together with the technical brochure for future reference.•This product was exclusively designed and manufactured for the use specified in the present documentation. Any other use not specified in this documentation could damage the product and be dangerous.•The Company declines all responsibility for any consequences resulting from improper use of the product, or use which is different from that expected and specified in the present documentation.•Do not install the product in explosive atmosphere.•The Company declines all responsibility for any consequences resulting from failure to observe Good Technical Practice when constructing closing structures (door, gates etc.), as well as from any deformation which might occur during use.•The installation must comply with the provisions set out by the following European Directives: 89/336/EEC, 73/23/EEC, 98/37/ECC and subsequent amendments.•Disconnect the electrical power supply before carrying out any work on the installation. Also disconnect any buffer batteries, if fitted.•Fit an omnipolar or magnetothermal switch on the mains power supply,having a contact opening distance equal to or greater than 3mm.•Check that a differential switch with a 0.03A threshold is fitted just before the power supply mains.•Check that earthing is carried out correctly: connect all metal parts for closure (doors, gates etc.) and all system components provided with an earth terminal.•The Company declines all responsibility with respect to the automation safety and correct operation when other manufacturers ’ components are used.•Only use original parts for any maintenance or repair operation.•Do not modify the automation components, unless explicitly authorised by the company.•Instruct the product user about the control systems provided and the manual opening operation in case of emergency.•Do not allow persons or children to remain in the automation operation area.•Keep radio control or other control devices out of children ’s reach, in order to avoid unintentional automation activation.•The user must avoid any attempt to carry out work or repair on the automation system, and always request the assistance of qualified personnel.•Anything which is not expressly provided for in the present instructions,is not allowed.3) TECHNICAL SPECIFICATIONSPower supply:...............................................................230V ±10% 50Hz Absorption on empty:.................................................................0.5A max Output power for accessories:..........................................24V~ 6VA max Max relay current:................................................................................8A Max power of motors:...............................................................300 W x 2Torque limiter:.................................................Self-transformer with 4 pos Limit switch:................................................................Adjustable run timePanel dimensions:.........................................................................See fig.1Cabinet protection:............................................................................IP55Working temperature:...............................................................-20 +55°C 4) TERMINAL BOARD CONNECTIONS(Fig.2)CAUTION: Keep the low voltage connections completely separated from the power supply connections.Fig.3 shows the fixing and connection method of the drive condensers whenever they are not fitted to the motor.JP51-2 Single-phase power supply 230V ±10%, 50 Hz (1=L/2=N).For connection to the mains use a multiple-pole cable with a minimum cross section of 3x1.5mm 2 of the type indicated in the above-mentioned standard (by way of example, if the cable is not shielded it must be at least equivalent to H07 RN-F while, if shielded, it must be at least equivalent to H05 VV-F with a cross section of 3x1.5mm 2).JP33-4 (mod.ARIES-P) 230V 40W max. blinker connection.5-6 (mod.ARIES) 230V 40W max. blinker connection.7-8-9 Motor M1 connection - 8 common, 7-9 start.10-11-12 Motor M2(r) connection - 11 common, 10-12 start.JP413-14 Open-close button and key switch (N.O.).13-15 Stop button (N.C.). If unused, leave bridged.13-16 Photocell or pneumatic edge input (N.C.). If unused, leave bridged.17-18 24V 3W max. gate open warning light.18-19 24V~ 0.25A max. (6VA) output (for supplying photocell or other device).20-21 Antenna input for radio-receiver board (20 signal - 21 braid).22 Common terminal (equivalent to terminal 13).23 Terminal for pedestrian control. It moves the leaf of motor M2 connected to terminal 10-11-12. This terminal is available only in ARIES-P control unit.JP225-26 2nd radio channel output of the double-channel receiver board (terminals not fitted on ARIES but fitted on ARIES-P) contact N.O.JP1 Radio-receiver board connector 1-2 channels.5) FUNCTIONSDL1:Power-on LedIt is switched on when the board is electrically powered.START: four-step logic: (DIP5 OFF)gate closed:..................................................................................it opens during opening:............................................... it stops and activates TCA gate open:................................................................................... it closes during closing:.................................... it stops and does not activate TCA after stop:.........................................................................it starts opening START: two-step logic: (DIP5 ON)gate closed:..................................................................................it opens during opening:................................it stops and activats TCA (if activated)gate open:....................................................................................it closes during closing:..............................................................................it opens after stop:.....................................................................................it opens STOP: In all cases: it stops the gate until a new start command is given.PHOT:Functions can be set with DIP-SWITCH.Activated during closing if DIP3-ON.Activated during opening and closing if DIP3-OFF.SCA: Gate open indicating light.with gate closed:...................................................................................off when gate is opening:...........................................................................on with gate open:.......................................................................................on when gate is closing:.....................................................................flashing 6) DIP-SWITCH SELECTION DIP1 Rapid closingON: When the position of the gate photocells is exceeded, during both opening and closing, the gate automatically starts to close even if TCA is activated. We recommend setting DIP3 to ON (photocells only activated during closing).OFF: Function not activated.DIP2 Blocks impulsesON: During opening, START commands are not accepted.OFF: During opening, START commands are accepted.DIP3 PhotocellsON: Photocells only activated during closing.OFF: Photocells activated during opening and closing.D 811184A _04DIP4 Automatic closing time (TCA)ON: Automatic closing activated (can be adjusted from 0 to 90s).OFF: Automatic closing not activated.DIP5 Control logicON: 2-step logic is activated (see start paragraph).OFF: 4-step logic is activated (see start paragraph).DIP6: Preallarm (mod.ARIES P only)ON: The flashing light turns on abt 3 seconds before the motors start.OFF The flashing light turns on simultaneously with the start of the motors.ATTENTION:Dip non used in mod. ARIES (always in OFF set).7) TRIMMER ADJUSTMENTTCA This adjusts the automatic closing time, after which time the gate automatically closes (can be adjusted from 0 to 90s).TW This adjusts the motor working time, after which time the motor stops (can be adjusted from 0 to 40s).TDELAY This adjusts the closing delay time of the second motor (M2).8) MOTOR TORQUE ADJUSTMENTThe ARIES control unit has electric torque adjustment which allows the motor force to be adjusted.The adjustment should be set for the minimum force required to carry out the opening and closing strokes completely.Adjustment is carried out by moving the connection 55 (fig.3) on the tran-sformer sockets as described below:Pos.T1 1st TORQUE (MINIMUM TORQUE)Pos.T2 2nd TORQUE Pos.T3 3rd TORQUEPos.T4 4th TORQUE (MAXIMUM TORQUE)4 motor torque values can be obtained.To gain access to the torque adjustment sockets, disconnect the mains supply and remove the protective case “P ” of the transfomer.CAUTION: Excessive torque adjustment may jeopardise the anti-squash safety function. On the other hand insufficient torque adjustment may not guarantee correct opening or closing strokes.9) MAINTENANCE AND DEMOLITIONThe maintenance of the system should only be carried out by qualified personnel regularly. The materials making up the set and its packing must be disposed of according to the regulations in force.Batteries must be properly disposed of.WARNINGSCorrect controller operation is only ensured when the data contained in the present manual are observed. The company is not to be held responsible for any damage resulting from failure to observe the installation standards and the instructions contained in the present manual.The descriptions and illustrations contained in the present manual are not binding. The Company reserves the right to make any alterations deemed appropriate for the technical, manufacturing and commercial improvement of the product, while leaving the essential product features unchanged, at any time and without undertaking to update the present publication.D811184A_04ARIES/ARIES-P - Ver. 04 -23。

SN8P2722中文规格书

2.3.1 概述 ............................................................................................................................................................................. 24
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SONiX TECHNOLOGY CO., LTD
Page 1
Version 1.1
版本 VER 1.0 VER 1.1
修正记录
日期 2008 年 3 月 2008 年 5 月 2009 年 6 月
修改记录初版。修改烧录信息章节内容。在 T0M 寄存器中增加 TC0CKS2 和 TC0CKS1 位。
3.1
概述.................................................................................................................................................................................. 27
222 中央处理器(CPU)......................................................................................................................................................................... 9
2.1.2 编译选项 ...................................................................................................................................................................... 15

Si534x 8x 更新说明 - 修正版 B 与修正版 D 之间的差异说明书

AN1006: Differences Between Si534x/8x Revision B and Revision D SiliconThis document highlights differences between Revision B and Revision D silicon forthe following part numbers:•Si5340•Si5341•Si5342•Si5344•Si5345•Si5346•Si5347•Si5348•Si5380SUMMARYCompared to Revision B, Revision D silicon for Si534x/8x fixes several errata, supports higher maximum output frequency ranges, and offers several new features. This document outlines those differences.1. Migration from Si534x/8x Revision B to Revision DApplies to Si5380/48/47/46/45/44/42/41/40With the release of Revision D for Si534x/8x, the Revision B devices are now classified as "Not Recommended for New Designs" (NRND). As of the Revision D release date, Silicon Labs has no plans to EOL the Si5348/47/46/45/44/42/41/40 Revision B devices and will continue production of both the Revision B devices and the newer Revision D devices. As of the Revision D release date, Silicon Labs does not plan to continue production of Si5380 Revision B devices. Customers using Si5380 must follow the instructions below to migrate their existing Revision B designs to Revision D.Revision D devices are pin-compatible and footprint-compatible with Revision B devices. However, Revision D devices are not intended to be drop-in replacements for Revision B devices. As a result of changes to the circuitry in Revision D devices, their performance and behavior will not completely match that of Revision B.•Customers currently using Si5348/47/46/45/44/42/41/40 Revision B in production may continue to do so. Silicon Labs will maintain production of both Revision B and Revision D concurrently.•Customers who wish to migrate a design from Revision B to Revision D should download the latest version of ClockBuilder Pro and create a new custom OPN for Revision D with their desired configuration. Once a new Revision D OPN has been created, customers should verify functionality of the device in their system prior to starting production with Revision D.•Silicon Labs does not recommend writing a register file, settings file, or regmap that was created for Revision B to a RevisionD device. When migrating an existing design from Revision B to Revision D, customers should download the latest version ofClockBuilder Pro and create new register files, settings files, or regmap exports to be used with Revision D.1.1 Device Ordering and IdentificationApplies to Si5380/48/47/46/45/44/42/41/40The revision letter which is the 9th digit of the ordering part number indicates "D" for product Revision D. For example: Si5345A-D-GM or Si5345-Dxxxxx-GM, where xxxxx is the custom OPN ID, and D refers to the product revision.1.2 Evaluation Boards Ordering and IdentificationApplies to Si5380/48/47/46/45/44/42/41/40New evaluation boards are available for all Revision D devices. The Revision D evaluation boards are identified with "-D" in the 7th and 8th characters of the OPN. For example, the Si5345 Revision D OPN is Si5345-D-EVB.1.3 Handling Revisions in ClockBuilder ProClockBuilder Pro (CBPro) version 2.9 or later supports both Revision B and Revision D of Si534x/8x. Selection of the target device revision is done in Step 2 of the configuration Wizard:Figure 1.1. Device Revision DThe default revision is "D" for all newly created designs.CBPro stores the target device revision for each project in the .slabtimeproj project file. When an existing project file is opened, CBPro will set the target device revision according to the data stored in the project file.With the NRND classification of Si534x/8x Revision D, CBPro will no longer support creation of new custom ordering part numbers (OPNs) for Revision B. Customers with an ongoing Revision B design who still wish to create custom OPNs for Revision B should contact Silicon Labs.1.4 Changing the Target Device Revision for an Existing CBPro ProjectAt any time the target device revision for a project can be changed in CBPro by choosing Step 2 "Revision" and then selecting the new target revision from the drop-down box at the top of the screen. Customers who have created projects for Revision B in an earlier version of CBPro can migrate their projects to Revision D using the following steps:•Open the original project file in CBPro (CBPro will default to Revision B after opening the file.).•Choose Step 2: "Revision" and select device revision D.•Click the "Finish" button on the lower right side of the screen.When changing a project from Revision B to Revision D in CBPro, note the following:•CBPro will select the default values for any new registers and features that are present in Revision D but were not present in Revision B. This will enable the new Revision D features described below.•CBPro will recalculate the frequency plan using the latest algorithm for Revision D. As a result, the internal frequency plan for Revision D may differ from the plan used on a Revision B project file.Although CBPro will allow the device revision to be changed backwards to Revision D from Revision B, this is not recommended, as Revision D contains several enhancements that are not present on Revision B.AN1006: Differences Between Si534x/8x Revision B and Revision D Silicon • Errata Fixes2. Errata Fixes2.1 Revision B Errata Fixed on Revision D2.2 Revision B Errata Not Fixed on Revision D2.3 Crystal Drive LevelApplies to: Si5380In data sheet rev 0.96 for Si5380 Revision B, the maximum crystal drive level was incorrectly specified as 200 μW. This has been updated to 300 μW for the Si5380 Revision D data sheet and will be corrected in a future release of the Si5380 Revision B data sheet. In addition, the list of approved crystals in the Si5380 reference manual has been updated to reflect this change.AN1006: Differences Between Si534x/8x Revision B and Revision D Silicon • Extended Output Frequency Ranges3. Extended Output Frequency RangesRevision D of Si5345/44/42/41/40 offers higher maximum output frequencies than Revision B. The maximum output frequency for eachNote: Certain limitations apply when output frequencies above 720 MHz are selected. Refer to to the Reference Manual for more information.AN1006: Differences Between Si534x/8x Revision B and Revision D Silicon • New Features and Capabilities4. New Features and CapabilitiesA variety of new features and capabilities are available on Si534x/8x Revision D. These are described in the following sections.4.1 Frequency Ramping on Holdover ExitApplies to Si5380/48/47/46/45/44/42When coming out of holdover, Revision D allows for the adjustment of frequency ramp rate. This greatly minimizes phase transients due to frequency drift while in holdover. The frequency ramp rate adjustment occurs regardless of whether the output frequencies are using fractional or integer synthesis. This feature may be enabledd or disabled in CBPro, and a variety of ramp rates are selectable from 0.2 ppm/s to 40,000 ppm/s.•On Si5380/45/44/42, all outputs will ramp in frequency when the DSPLL is coming out of holdover.•On a Si5348/47/46, only the outputs that connect to the DSPLL that is coming out of holdover will have a ramp in frequency.4.2 Frequency Ramping on an Input Clock SwitchApplies to: Si5380/48/47/46/45/44/42When switching between clock inputs that are not synchronous, Revision D allows for the adjustment of the frequency ramp rate. This greatly minimizes phase transients on the output clocks during the input switching. The frequency ramp rate adjustment occurs regardless of whether the output frequencies are using fractional or integer synthesis. This feature may be enabled or disabled in CBPro, and a variety of ramp rates are selectable from 0.2 ppm/s to 40,000 ppm/s.•On Si5380/45/44/42, all outputs will ramp in frequency when the input clock is switched.•On a Si5348/47/46, when a DSPLL input switch occurs, only the outputs that connect to that DSPLL will have a ramp in frequency. 4.3 Holdover Exit Bandwidth SelectionApplies to: Si5380/48/47/46/45/44/42In Revision D, it is possible to select a PLL bandwidth to be used upon Holdover and Free Run exit. This bandwidth cannot be set to less than the normal bandwidth. The device returns to the normal bandwidth after the PLL has locked.4.4 Loss of Lock Detector ImprovementsApplies to: Si5380/48/47/46/45/44/42/41/40In Revision D, the Si534x/8x LOL detector has been improved to quickly assert LOL on large changes in ppm. Previously on Revision B, a large input frequency change took much longer to assert LOL. The threshold at which LOL is asserted for large ppm changes is set automatically by CBPro based on the frequency plan, and will range from 100 ppm to 1,000,000 ppm.The Si534x/8x Revision D LOL detector has also been improved to detect loss of an input clock signal. On Revision D, if an input clock edge is not detected within 417 μs, LOL will be asserted. Previously on Revision B, loss of an input clock would only trigger LOS and not LOL.4.5 Out of Frequency Detector ImprovementsApplies to: Si5380/48/47/46/45/44/42In Si534x/8x Revision D, the OOF detector has been improved so that OOF is asserted when a loss of signal occurs. Previously on Revision B, the OOF detector would not assert when a loss of signal occurs.Previously on Revision B, either the fast OOF threshold or the precision OOF threshold could be used to both assert and deassert the OOF signal. With Revision D, if the input frequency exceeds either the fast OOF threshold or the precision OOF threshold, OOF will be asserted. However, the input frequency must fall below both OOF thresholds in order for the OOF detector to be deasserted.4.6 Reductions in Output Clock Phase TransientsApplies to: Si5380/48/47/46/45/44/42When performing hitless switching, the output clock phase transient has been reduced in Si534x/8x revision D. New values for this can be found in the data sheet.Additional circuitry optimizes the switching time between Fastlock and normal bandwidth. This reduces output clock phase transients when changing bandwidths.AN1006: Differences Between Si534x/8x Revision B and Revision D Silicon • Changes to Registers from Revision B to Revision D5. Changes to Registers from Revision B to Revision DThe majority of registers present in Si534x/8x Revision B have been left unchanged in Revision D. The exceptions to this are documented below.5.1 Device RevisionApplies to: Si5380/48/47/46/45/44/42/41/40In Si534x/8x the DEVICE_REV register will now read back 0x03 to indicate Revision D. Previously this read back as 0x01 to indicate Revision B.5.2 Preamble and PostambleApplies to: Si5380/48/47/46/45/44/42/41/40In order to change certain registers that affect PLL lock status it is necessary to write a preamble and postamble sequence to the device. The values for the preamble and postamble sequences have changed for Revision D as shown below.Table 5.1. Preamble Sequence for Si5380/47/46/45/44/42/41/40Table 5.2. Postamble Sequence for Si5380/47/46/45/44/42/41/40Table 5.3. Preamble Sequence for Si5348Table 5.4. Postamble Sequence for Si5348Note that on a Revision D device, either the Revision B values or the Revision D values can be written for the preamble/postamble sequence and the device will function the same in either case. However only the Revision D values can be read back from the device.5.3 New Registers Present on Revision DApplies to Si5380/48/47/46/45/44/42/41/40Several new registers have been added to the Si534x/8x Revision D devices to support the new features described above. Details about these new features can be found in the reference manual for each device.Copyright © 2021 Skyworks Solutions, Inc. All Rights Reserved.Information in this document is provided in connection with Skyworks Solutions, Inc. (“Skyworks”) products or services. These materials, including the information contained herein, are provided by Skyworks as a service to its customers and may be used for informational purposes only by the customer. Skyworks assumes no responsibility for errors or omissions in these materials or the information contained herein. Skyworks may change its documentation, products, services, speciﬁcations or product descriptions at any time, without notice. Skyworks makes no commitment to update the materials or information and shall have no responsibility whatsoever for conﬂicts, incompatibilities, or other diﬃculties arising from any future changes.No license, whether express, implied, by estoppel or otherwise, is granted to any intellectual property rights by this document. Skyworks assumes no liability for any materials, products or information provided hereunder, including the sale, distribution, reproduction or use of Skyworks products, information or materials, except as may be provided in Skyworks’ Terms and Conditions of Sale.THE MATERIALS, PRODUCTS AND INFORMATION ARE PROVIDED “AS IS” WITHOUT WARRANTY OF ANY KIND, WHETHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, INCLUDING FITNESS FOR A PARTICULAR PURPOSE OR USE, MERCHANTABILITY, PERFORMANCE, QUALITY OR NON-INFRINGEMENT OF ANY INTELLECTUAL PROPERTY RIGHT; ALL SUCH WARRANTIES ARE HEREBY EXPRESSLY DISCLAIMED. SKYWORKS DOES NOT WARRANT THE ACCURACY OR COMPLETENESS OF THE INFORMATION, TEXT, GRAPHICS OR OTHER ITEMS CONTAINED WITHIN THESE MATERIALS. SKYWORKS SHALL NOT BE LIABLE FOR ANY DAMAGES, INCLUDING BUT NOT LIMITED TO ANY SPECIAL, INDIRECT, INCIDENTAL, STATUTORY, OR CONSEQUENTIAL DAMAGES, INCLUDING WITHOUT LIMITATION, LOST REVENUES OR LOST PROFITS THAT MAY RESULT FROM THE USE OF THE MATERIALS OR INFORMATION, WHETHER OR NOT THE RECIPIENT OF MATERIALS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.Skyworks products are not intended for use in medical, lifesaving or life-sustaining applications, or other equipment in which the failure of the Skyworks products could lead to personal injury, death, physical or environmental damage. Skyworks customers using or selling Skyworks products for use in such applications do so at their own risk and agree to fully indemnify Skyworks for any damages resulting from such improper use or sale.Customers are responsible for their products and applications using Skyworks products, which may deviate from published speciﬁcations as a result of design defects, errors, or operation of products outside of published parameters or design speciﬁcations. Customers should include design and operating safeguards to minimize these and other risks. Skyworks assumes no liability for applications assistance, customer product design, or damage to any equipment resulting from the use of Skyworks products outside of Skyworks’ published speciﬁcations or parameters.Skyworks, the Skyworks symbol, Sky5®, SkyOne ®, SkyBlue™, Skyworks Green™, Clockbuilder ®, DSPLL ®, ISOmodem ®, ProSLIC ®, and SiPHY ® are trademarks or registered trademarks of Skyworks Solutions, Inc. or its subsidiaries in the United States and other countries. Third-party brands and names are for identiﬁcation purposes only and are the property of their respective owners. Additional information, including relevant terms and conditions, posted at , are incorporated by reference.Portfolio/ia/timingSW/HW/CBProQuality/qualitySupport & Resources/supportClockBuilder ProCustomize Skyworks clock generators, jitter attenuators and networksynchronizers with a single tool. With CBPro you can control evaluationboards, access documentation, request a custom part number, export for in-system programming and more!/CBPro。

NXP i.MX 8M Plus Applications Processor Reference

Preview of i.MX 8M Plus Applications Processor Reference ManualGet entire reference manual (7406 pages, PDF)Document Number: IMX8MPRMRev. 1, 06/2021ContentsSection number Title PageChapter 1Introduction1.1Product Overview (9)1.2Target Applications (9)1.3Acronyms and Abbreviations (9)1.4Architectural Overview (12)Chapter 2Memory Map2.1Memory system overview (23)2.2Cortex-A53 Memory Map (24)2.3Cortex-M7 Memory Map (26)2.4DMA memory maps (29)2.5AIPS Memory Maps (30)2.6DAP Memory Map (36)2.7Audio Processor Memory Map (38)2.8HDMI_TX Subsystem Memory Map (38)Chapter 3Security3.1System Security (41)3.2Resource Domain Controller (RDC) (44)Chapter 4Arm Platform and Debug4.1Arm Cortex A53 Platform (A53) (91)4.2Arm Cortex M7 Platform (CM7) (97)4.3Messaging Unit (MU) (99)4.4Semaphore (SEMA4) (143)4.5On-Chip RAM Memory Controller (OCRAM) (161)4.6Network Interconnect Bus System (NIC) (164)4.7AHB to IP Bridge (AIPSTZ) (165)4.8Shared Peripheral Bus Arbiter (SPBA) (188)4.9TrustZone Address Space Controller (TZASC) (201)4.10System Debug (203)4.11System Counter (SYS_CTR) (207)Chapter 5Clocks and Power Management5.1Clock Control Module (CCM) (227)5.2General Power Controller (GPC) (566)5.3Crystal Oscillator (XTALOSC) (718)5.4Thermal Monitoring Unit (TMU) (722)Chapter 6SNVS, Reset, Fuse, and Boot6.1System Boot (741)6.2Fusemap (808)6.3On-Chip OTP Controller (OCOTP_CTRL) (824)6.4Secure Non-Volatile Storage (SNVS) (868)6.5System Reset Controller (SRC) (897)6.6Watchdog Timer (WDOG) (968)Chapter 7Interrupts and DMA7.1Interrupts and DMA Events (987)7.2Smart Direct Memory Access Controller (SDMA) (1008)7.3Enhanced Direct Memory Access (eDMA) (1256)7.4Interrupt Request Steering (IRQ_STEER) (1318)Chapter 8Chip IO and Pinmux8.1External Signals and Pin Multiplexing (1329)8.2IOMUX Controller (IOMUXC) (1352)8.3General Purpose Input/Output (GPIO) (1982)Chapter 9External Memory9.1External Memory Overview (2001)9.2DDR Controller (DDRC) (2003)9.3DDR BLK_CTRL (2164)9.4DDR PHY (DDR_PHY) (2166)9.5AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA) (2177)9.662BIT Correcting ECC Accelerator (BCH) (2217)9.7General Purpose Media Interface (GPMI) (2280)Chapter 10Mass Storage10.1Enhanced Configurable SPI (ECSPI) (2339)10.2FlexSPI Controller (FlexSPI) (2369)10.3Ultra Secured Digital Host Controller (uSDHC) (2500)Chapter 11Connectivity11.1HSIO BLK_CTRL (2659)11.2Universal Serial Bus Controller (USB) (2680)11.3Universal Serial Bus PHY (USB_PHY) (2993)11.4PCI Express (PCIe) (2997)11.5PCI Express PHY (PCIe_PHY) (3369)11.6Ethernet MAC (ENET) (3754)11.7Ethernet Quality Of Service (ENET_QOS) (3957)11.8FlexCAN (4980)Chapter 12Timers12.1General Purpose Timer (GPT) (5123)12.2Pulse Width Modulation (PWM) (5142)Chapter 13Display, Imaging, and Camera13.1Display, Imaging, and Camera Overview (5155)13.2MEDIA BLK_CTRL (5163)13.3LCD Interface (LCDIF) (5233)13.4Image Sensing Interface (ISI) (5265)13.5MIPI CSI Host Controller (MIPI_CSI) (5347)13.6MIPI DSI Host Controller (MIPI_DSI) (5396)13.7MIPI D-PHY (MIPI_DPHY) (5469)13.8LVDS Display Bridge (LDB) (5493)13.9HDMI TX Controller (5496)13.10HDMI TX PHY (5779)13.11HDMI TX BLK_CTRL (5828)13.12HDMI TX Parallel Audio Interface (HTX_PAI) (5859)13.13HDMI TX Parallel Video Interface (HTX_PVI) (5871)13.14Image Signal Processor (ISP) (5895)13.15DeWarp (5901)13.16Machine Learning Neural Processing Unit (NPU) (5907)Chapter 14Audio14.1Audio Overview (5943)14.2AUDIO BLK_CTRL (5947)14.3PDM Microphone Interface (MICFIL) (5977)14.4Synchronous Audio Interface (SAI) (6023)14.5Asynchronous Sample Rate Converter (ASRC) (6077)14.6Enhanced Audio Return Channel (eARC) (6162)14.7Audio DSP (HiFi 4 DSP) (6231)Chapter 15Graphics Processing Unit (GPU)15.1GPU Overview (6239)15.22D Graphics Processing Unit (GPU2D) (6240)15.33D Graphics Processing Unit (GPU3D) (6254)Chapter 16Video Processing Unit (VPU)16.1VPU G1 Decoder (6263)16.2VPU G2 Decoder (6429)16.3VPU VC8000E Encoder (6665)16.4VPU BLK_CTRL (7256)Chapter 17Low Speed Communication and Interconnects17.1I2C Controller (I2C) (7269)17.2Universal Asynchronous Receiver/Transmitter (UART) (7293)Chapter 1Introduction1.1Product OverviewThis chapter introduces the architecture of the i.MX 8M Plus Applications Processor. The i.MX 8M Plus family is a set of NXP products focused on machine learning applications, combining state-of-art multimedia features with high-performance processing optimized for low-power consumption.The i.MX 8M Plus Applications Processor relies on a powerful fully coherent core complex based on a quad Cortex-A53 cluster, a Cortex-M7 coprocessor, audio digital signal processor, machine learning and graphics accelerators.The i.MX 8M Plus provides additional computing resources and peripherals:•Advanced security modules for secure boot, cipher acceleration and DRM support •A wide range of audio interfaces•Large set of peripherals that are commonly used in consumer/industrial markets including USB , PCIe, Ethernet, and CAN1.2Target ApplicationsThe i.MX 8M Plus Media Applications Processor targets applications on:•Smart Homes, Buildings and Cities•Machine Learning and Industrial Automation•Consumer and Pro Audio/Voice Systems1.3Acronyms and AbbreviationsThe table below contains acronyms and abbreviations used in this document.Acronyms and AbbreviationsAcronyms and Abbreviated TermsTerm Meaning ADC Analog-to-Digital ConverterAHB Advanced High-performance BusAIPS Arm IP BusALU Arithmetic Logic UnitAMBA Advanced Microcontroller Bus ArchitectureAPB Advanced Peripheral BusASRC Asynchronous Sample Rate ConverterAXI Advanced eXtensible InterfaceCA/CM Arm Cortex-A/Cortex-MCAAM Cryptographic Acceleration and Assurance Module CA53Arm Cortex A53 CoreCAN Controller Area NetworkCM7Arm Cortex M7 CoreCPU Central Processing UnitCSI CMOS Sensor InterfaceCSU Central Security UnitCTI Cross Trigger InterfaceD-cache Data cacheDAP Debug Access PortDDR Double data rateDMA Direct memory accessDPLL Digital phase-locked loopDRAM Dynamic random access memoryECC Error correcting codesECSPI Enhanced Configurable SPILPSPI Low-power SPIEDMA Enhanced Direct Memory AccessEIM External Interface ModuleENET EthernetEPIT Enhanced Periodic Interrupt TimerEPROM Erasable Programmable Read-Only MemoryETF Embedded Trace FIFOETM Embedded Trace MacrocellFIFO First-In-First-OutGIC General Interrupt ControllerGPC General Power ControllerGPIO General-Purpose I/OGPR General-Purpose RegisterGPS Global Positioning SystemTable continues on the next page...Continue Reading This Reference ManualGet entire reference manual (7406 pages, PDF)Stay informed when design resources related to this product are updated.Go to i.MX 8M Plusi.MX 8M Plus Applications Processor Reference Manual, Rev. 1, 06/202111NXP Semiconductors。

SuperSting R8 IP

SuperSting R8 IP8 channel Memory Earth Resistivity and IP MeterThe SuperSting R8 IP is a state-of-the-art multi-channel portable memory earth resistsivity meter with memory storage of readings and user defined measure cycles. It provides the highest accuracy and lowest noise levels in the industry.This new instrument revolutionizes the field of resistivity imaging surveys by its capability to simultaneously measure up to 8 channels using a high power transmitter so that field data production can reach previously unheard of speeds.With the high power transmitter good data can be recorded in difficult locations wheretime-consuming stacking was the only alternative before.SuperSting R8 IP uses the new Multi-channel Swift Dual Mode Automatic Multi-electrode cable (patent 6,404,203) based on the successful design used in our single-channel cables. With this new cable it is now possible to efficiently record 3D data and use a virtually unlimited quantity of electrodes in a single layout. The electrode address is now a 16 bit number which sets range at about 65000 electrodes!The controller for this new cable is completely built into the SuperSting R8 IP main instrument so there are no extra boxes to carry and connect in the field.Key Benefits∙8 channel simultaneous measure capability, cuts field time dramatically!∙High power transmitter. Can use both 12V and 24V batteries for added power.∙Field adapted rugged construction. Built to last in real conditions.∙Easy to use menu driven system.∙The best accuracy and noise performance in the industry!∙Large capacity internal memory for storage of measurement results.∙User programmed measure cycles can be loaded into memory from a PC and later executed in the field.∙Directly controls the Multi-Channel Swift Dual Mode Automatic Multi-electrode system (patent 6,404,203)!∙Induced Polarization mode records 6 individual IP chargeability windows.∙Manual measurements are available via four banana pole screws on the top of the instrument for connecting current and potential electrodes. Manual measurementarray types include: Resistance, Schlumberger, Wenner, Dipole-dipole, Pole-dipole,and Pole-pole.TECHNICAL SPECIFICATION:Pricing(Please contact our sales department for a price quotation.)。

Program Protection Manual for the C-64 Volume II说明

they use phosphorus or
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VAR-SOM-MX8M-PLUS based on NXP i.MX 8M Plus Evalua

VAR-SOM-MX8M-PLUS based on NXP i.MX 8M PlusEvaluation Kit Quick Start GuideFeatures:1. Power ON Switch (SW7)2. 12V DC In Jack (J24)3. USB Debug (J29)4. micro SD Card slot (J28)5. USB 3.0 OTG (J26)6. USB 2.0 Host (J23)7. Gigabit Ethernet #0 (J21) 8. Gigabit Ethernet #1 (J20)9. MIPI-CSI #1 Camera connector [optional] (J19) 10. Miscellaneous Header #1 (J17)11. HDMI/ MIPI-CSI #2 Camera connector[optional] (J13)12. Mini PCI Express Connector (J15) 13. Miscellaneous Header #2 (J3) 14. SOM Connector (J1) 15. LVDS#B Header (J5)16. LVDS#A/ DSI Header (J7) 17. Fan Power Connector (J9) 18. Digital Microphone (U1) 19. Resistive Touch (J10) 20. Capacitive Touch (J11)21. User Buttons (SW1, SW2, SW4) 22. Line-In Connector (J12)23. Headphones Connector (J14) 24. Boot Select Switch (SW3)25. SAI/I2C/SPI/CAN Header (J16) 26. Reset Button (SW5)27. PWR Select Switch (SW6) 28. UART/PWM Header (J18) 29. RTC Battery Holder (JBT1)Evaluation kit initial Setup1. Carefully remove the 7” LCD and Symphony-Board from the package.2. Connect the 7” LCD Display and Touch cablesto the Evaluation Kit connectors J7, J11 respectively.Note:connect the display cable with the red wire on pin 1. Connect the touch cable with the metal contacts facing down.3. Plug the USB type A to micro B cable betweenthe USB debug connector (J29) and a PC USB port.4. For heatsink assembly instructions, pleasefollow the VHP-VS8M documentation .Please note that the heatsink is mainly used for CPU/GPU intensive applications and may be required per your specific use case.P/N VSS0177AVAR-SOM-MX8M-PLUS based on NXP i.MX 8M PlusEvaluation Kit Quick Start GuideSetting the host PC for debug1. Download any PC terminal software (e.g. Putty ).2. Set the PC terminal software parameters as follows:- Baud Rate: 115200 - Data bits: 8 - Stop bits: 1 - Parity: None- Flow Control: NoneBooting from eMMC1. Set Boot select switch (SW3) to “Internal” position to boot from the VAR-SOM-MX8M-PLUS internal storage.2. Plug the wall adapter into the 12V power jack (J24) and to a 120VAC~240VAC power source.3. Set Power ON switch (SW7) to ON state.4. Boot messages are printed within the PC terminal window.Booting from a micro SD cardThe microSD card is supplied within the package. Updated SD card images can also be downloaded from the Variscite FTP server.See more details in the recovery SD card section in the Variscite Wiki pages.1. Set Power ON switch (SW7) to off state.2. Set Boot select switch (SW3) to “SD ” positionin order to boot from SD Card.3. Push microSD card into the microSD cardslot (J28) of the Symphony-Board.4. Set Power ON switch (SW7) to ON state.5. Boot messages are print ed within PC’sterminal window.(Re-)Installing the file system to eMMCPlease refer to the recovery SD card section in the Variscite Wiki pages.Linkso Wiki page:https:///index.php?title=VAR-SOM-MX8M-PLUSo VAR-SOM-MX8M-PLUS Evaluation kits:https:///product/evaluation-kits/var-som-mx8m-plus-evaluation-kits/o VAR-SOM-MX8M-PLUS System on Module:https:///product/system-on-module-som/cortex-a53-krait/var-som-mx8m-plus-nxp-i-mx-8m-plus/o Symphony carrier board:https:///product/single-board-computers/symphony-board/o Customer portal:https:///loginThank you for purchasing Variscite’s product.For additional assistance please contact: *******************。

国家仪器PXI-7841R 42R、PXI-7851R 52R产品说明书

Manufacturer: National InstrumentsBoard Assembly Part Numbers (Refer to Procedure 1 for identification procedure): Part Number and Revision Description198219B-04L or later PXI-7841R198219B-05L or later PXI-7842R198219B-02L or later PXI-7851R198219B-01L or later PXI-7852RVolatile MemoryTarget Data Type Size BatteryBackupUser1AccessibleSystemAccessibleSanitizationProcedureData storage during VI execution FPGABlockRAM32 x 36 Kbits (-02, -04)48 x 36 Kbits (-01, -05)No Yes Yes Cycle PowerNon-Volatile Memory (incl. Media Storage)Target Data Type Size BatteryBackupUserAccessibleSystemAccessibleSanitizationProcedureDevice configuration •Device information •FPGA bitstream •Calibration metadata •Calibration data2Flash 2M x 8 bits NoNoYesYesNoYesYesYesYesNoneProcedure 2Procedure 3None1 Refer to Terms and Definitions section for clarification of User and System Accessible1 Calibration constants that are stored on the device include information for the device’s full operating range. Any implications resulting from partial self-calibration can be eliminated by running the full self-calibration procedure.ProceduresProcedure 1 –Board Assembly Part Number Identification:To determine the Board Assembly Part Number and Revision, refer to the label applied to the surface of your product. The Assembly Part Number should be formatted as “P/N: #####a-##LProcedure 2 - Device Configuration Flash (FPGA bitstream):You can use the NI-RIO Device Setup utility to erase the FPGA bitstream data. For more details, visit/info and enter the infocode fpgaflashclr.Procedure 3 - Device Configuration Flash (Calibration Metadata):The user-accessible areas of the Device Configuration Flash are exposed through a calibration Applications Programming Interface (API) in LabVIEW. For more details, visit /info and enter the infocode rseriescalclr.Terms and DefinitionsCycle Power:The process of completely removing power from the device and its components and allowing for adequate discharge. This process includes a complete shutdown of the PC and/or chassis containing the device; a reboot is not sufficient for the completion of this process.Volatile Memory:Requires power to maintain the stored information. When power is removed from this memory, its contents are lost. This type of memory typically contains application specific data such as capture waveforms.Non-Volatile Memory:Power is not required to maintain the stored information. Device retains its contents when power is removed.This type of memory typically contains information necessary to boot, configure, or calibrate the product or may include device power up states.User Accessible:The component is read and/or write addressable such that a user can store arbitrary information to the component from the host using a publicly distributed NI tool, such as a Driver API, the System Configuration API, or MAX. System Accessible:The component is read and/or write addressable from the host without the need to physically alter the product. Clearing:Per NIST Special Publication 800-88 Revision 1, “clearing” is a logical technique to sanitize data in all User Accessible storage locations for protection against simple non-invasive data recovery techniques using the same interface available to the user; typically applied through the standard read and write commands to the storage device.Sanitization:Per NIST Special Publication 800-88 Revision 1, “sanitization” is a process to render access to “Target Data” on the media infeasible for a given level of effort. In this document, clearing is the degree of sanitization described.。

DP83848C中文资料

The DP83848C features integrated sublayers to support both 10BASE-T and 100BASE-TX Ethernet protocols, which ensures compatibility and interoperability with all other standards based Ethernet solutions.
The DP83848C easily interfaces to twisted pair media via an external transformer. Both MII and RMII are supported ensuring ease and flexibility of design.
The DP83848C includes a 25MHz clock out. This means that the application can be designed with a
• Energy Detection Mode • 25 MHz clock out • SNI Interface (configurable) • RMII Rev. 1.2 Interface (configurable)
2.0 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.1 Auto-Negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 2.1.1 Auto-Negotiation Pin Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.1.2 Auto-Negotiation Register Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.1.3 Auto-Negotiation Parallel Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.1.4 Auto-Negotiation Restart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.1.5 Enabling Auto-Negotiation via Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.1.6 Auto-Negotiation Complete Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Duo v2 NV+ v2 Ultra 2 Ultra 2 Plus Ultra 4 Ultra 4

ReadyNAS
Home/Prosumer Product Line Comparison
Hardware
- CPU - Memory - Embedded flash memory for firmware - Form factor - Serial ATA channels - Hot-swappable disk trays - 10/100/1000 Ethernet ports - USB 2.0 ports - USB 3.0 ports - LCD/OLED display - Compatible with SATA I & II HDD - Native SATA II support - Kensington latch
Volumes
- Volume management
- Volume monitoring and resource view
√
√
- Single-volume auto-expansion (X-RAID/X-RAID2)
√
√
- Journaled file system
√
√
- User and group-level quotas
√ √ √ √ √ √ √ √ √ √ √ √ Optional
√
√ √ √
√ √ √ √
√
√
√ √ √ √ √ √ √
Optional
Ultra 6 Plus
√ √ √ √ √ √ √ √ √ √
√ √ √ √ √ √ √ √ √ √ √ √ Optional
√
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NI4882-Readme

Power Management - NI-488.2 for Windows, Version 2.2, adds the EPWR
error code. This error indicates that the interface lost power.
This may occur when the system goes to standby or hibernate mode.
Controller/Analyzer board. Support for the obsolete GPIB-USB-A
interface has been dropped in this release.
Driver version 2.3 performance during IBCMD and serial poll calls was
lower than version 2.2. This has been fixed and improved over
version 2.2.
Documentation has been updated for various features.
Enhancements and Bugfixes in Version 2.3
to English and Japanese languages supported by the previous versions
of NI-488.2 for Windows. All Components of this release have been
localized with the exception of:
This driver version has been tested with the following software.

飞思卡尔推出全新系列8位微处理

工艺，该工艺已经在大量出货的汽车片。其它诸如６路３相互补带死区控飞思卡尔的ＣｄＷａｒｒ件开发平ｏｅｒｏ软ｉ
电子产品上得到广泛验证；对芯片内制的ＰＷＭ模块可以方便实现电机控台将全方位支持Ｓ８０Ｐ系列的开发，
开发简易和扩展灵活等关键特性，广晶体电路并节约印板空间；２位分辨１
泛适用于诸如家用电器、电源和电机率的高精度ＡＣ模块在保证模数转个Ｓ８Ｄ０Ｐ系列的开发调试可以重复利
Hale Waihona Puke 控制、消费和工业方面的各种应用场合。换精度的前提下可以大大简化外围信用现有针对Ｓ８系列的所有软硬件工０该系列继续沿用已经在业界被广号调理电路；触摸传感接口（ＳＩＴ）
时钟譬毽
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飞思卡尔推出全新系列８位微处理
■ 飞思卡尔公司
延续着推出基于ＡＭｏｔｘ－ＲＣｒｔｅ
在利用新工艺以降低芯片本身的个定时器资源方便了软件设计时的
Ｍ４内核的高端３２微处理器Ｋｎｔ制造成本的同时，Ｓ８ｉｅｉｓ０Ｐ系列还集成任务定时控制，其中ＲＴＣ模块可在系列后强劲的势头，飞思卡尔半导体了丰富的外设模块来帮助客户最大可芯片进入低功耗休眠模式下维持工在今年８月３日又正式宣布将向全能地降低系统设计成本。高精度的内作并周期性地唤醒微处理器，在少０球市场推出全新的８位Ｓ８０Ｐ系列微部时钟源（温度全电压范围误差小量软件的配合下也可实现实时时钟全处理器，具备可靠性高、系统成本低、于１５）在很多场合都可以省却外部的功能。．％由于沿用了Ｓ８内核架构，整０

LV8548MC(简易2相步进)

Absolute Maximum Ratings at Ta = 25°C
Parameter
Symbol
Conditions
Ratings
Unit
Maximum power supply voltage Output impression voltage
VCC max VOUT
-0.3 to +20
high voltage, or drastic temperature change, the reliability of the IC may be degraded. Please contact us for the further details.
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
Pin function Power-supply voltage pin. VCC voltage is impressed. The permissible operation voltage is from 4.0 to 16.0(V). The capacitor is connected for stabilization for GND pin (6pin). Motor drive control input pin. Driving control input pin of OUT1 (10pin) and OUT2 (9pin). It combines with IN2 pin (3pin) and it fights desperately. The digital input it, range of the "L" level input is 0 to 0.7(V), range of the "H" level input is from 1.8 to 5.5(V). PWM can be input. Pull-down resistance 100(kΩ) is built into in the pin. It becomes a standby mode because all IN1, IN2, IN3, and IN4 pins are made "L", and the circuit current can be adjusted to 0. Motor drive control input pin. Driving control input pin of OUT1 (10pin) and OUT2 (9pin). It combines with IN1 pin (2pin) and it uses it. PWM can be input. With built-in pull-down resistance. Motor drive control input pin. Driving control input pin of OUT3 (8pin) and OUT4 (7pin). It combines with IN4 pin (5pin) and it uses it. PWM can be input. With built-in pull-down resistance. Motor drive control input pin. Driving control input pin of OUT3 (8pin) and OUT4 (7pin). It combines with IN3 pin (4pin) and it uses it. PWM can be input. With built-in pull-down resistance. Ground pin. Driving output pin. The motor coil is connected between terminal OUT3 (8pin).

恩智浦半导体 i.MX 8M Dual 8M QuadLite 8M Quad 应用处理器数

恩智浦半导体数据手册：技术数据文件编号：IMX8MDQLQIEC 第1版，2018年10月恩智浦保留根据需要更改生产规格细节的权利，以改进其产品设计。

MIMX8MQ7CVAHZAAMIMX8MQ6CVAHZAAMIMX8MD7CVAHZAAMIMX8MD6CVAHZAAMIMX8MQ5CVAHZAAMIMX8MQ7CVAHZABMIMX8MQ6CVAHZABMIMX8MD7CVAHZABMIMX8MD6CVAHZABMIMX8MQ5CVAHZAB面向工业产品的i.MX 8MDual / 8M QuadLite / 8MQuad应用处理器数据手册封装信息塑料封装FBGA 17 x 17 mm，0.65 mm间距订购信息参见第6页的表21 i.MX 8M Dual / 8M QuadLite /8MQuad简介i.MX 8M Dual / 8M QuadLite / 8M Quad处理器是恩智浦面向联网音频流/视频流设备、接缝/成像设备以及要求高性能、低功耗处理器的各种设备市场推出的最新产品。

i.MX 8M Dual / 8M QuadLite/8M Quad处理器采用先进的四核Arm® Cortex®-A53内核，运行速度高达1.3 GHz。

通用Cortex®-M4内核处理器用于低功耗处理。

DRAM控制器支持32位/16位LPDDR4、DDR4和DDR3L存储器。

还有许多其他接口可用于连接各种外围设备，如WLAN、蓝牙、GPS、显示器和摄像头传感器等。

i.MX 8M Quad和i.MX 8M Dual处理器具有硬件加速功能，可实现高达4K的视频播放，并可驱动高达60 fps的视频输出。

虽然i.MX 8M QuadLite处理器并未搭载用于视频解码的硬件加速功能，但允许在需要之时使用软件解码器进行视频播放。

1. i.MX 8M Dual / 8M QuadLite /8M Quad简介 (1)1.1. 功能框图 (5)1.2. 订购信息 (6)i.MX 8M Dual / 8M QuadLite /8M Quad简介表1. 特性面向工业产品的i.MX 8M Dual / 8M QuadLite / 8M Quad应用处理器数据手册，第1版，2018年10月i.MX 8M Dual / 8M QuadLite /8M Quad简介表1. 特性（续）面向工业产品的i.MX 8M Dual / 8M QuadLite / 8M Quad应用处理器数据手册，第1版，2018年10月i.MX 8M Dual / 8M QuadLite /8M Quad简介表1. 特性（续）注意实际功能集取决于产品型号(如表2所述)。

Vishay Siliconix Si7848DP N-Channel 40V MOSFET 说明书

SI7848DPVishay SiliconixSi7848DPDocument Number: N-Channel 40-V (D-S) MOSFETFEATURES•TrenchFET ® Power MOSFETS •New Low Thermal ResistancePowerPAK ® Package with Low 1.07-mm Profile•PWM Optimized for Fast Switching •100 % R g TestedAPPLICATIONS•DC/DC Converters- Synchronous Buck - Synchronous RectifierPRODUCT SUMMARYV DS (V)r DS(on) (Ω)I D (A)400.009 at VGS = 10 V 170.012 at V GS = 4.5 V15Notesa. Surface Mounted on 1" x 1" FR4 Board.b. See Solder Profile (/ppg?73257). The PowerPAK SO-8 is a leadless package. The end of the lead terminal is exposedcopper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not required to ensure adequate bottom side solder interconnection.c. Rework Conditions: manual soldering with a soldering iron is not recommended for leadless components. * Pb containing terminations are not RoHS compliant, exemptions may apply. ABSOLUTE MAXIMUM RATINGS T A = 25°C, unless otherwise notedParameterSymbol 10 secs Steady State Unit Drain-Source Voltage V DS 40VGate-Source VoltageV GS± 20Continuous Drain Current (T J = 150 °C)a T A = 25 °C I D 1710.4AT A = 70 °C 13.78.3Pulsed Drain CurrentI DM 50Avalanche CurrentL = 0.1 mH I AS 30Continuous Source Current (Diode Conduction)a I S 4.5 1.67Maximum Power Dissipation aT A = 25 °C P D 5 1.83W T A = 70 °C3.21.2Operating Junction and Storage T emperature Range T J , T stg– 55 to 150°CSoldering Recommendations (Peak Temperature)b,c260THERMAL RESISTANCE RATINGSParameter Sym b ol Typical MaximumUnit Maximum Junction-to-Ambient at ≤ 10 sec R thJA 2025°C/WSteady State 5568Maximum Junction-to-Case (Drain)Steady State R thJC1.82.2 Document Number: 71450Vishay SiliconixSi7848DPNotesa. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %.b. Guaranteed by design, not subject to production testing.Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.SPECIFICATIONS T J = 25°C, unless otherwise notedParameter Sym b ol Test Condition Min TypMaxUnitStaticGate Threshold Voltage V GS(th) V DS = V GS , I D = 250 µA 1.0 3.0V Gate-Body LeakageI GSS V DS = 0 V , V GS = ± 20 V± 100 nA Zero Gate Voltage Drain Current I DSS V DS = 40 V, V GS = 0 V 1µA V DS = 40 V , V GS = 0 V, T J = 55 °C5On-State Drain Current aI D(on) V DS ≥ 5 V , V GS = 10 V 50A Drain-Source On-State Resistance a r DS(on) V GS = 10 V , I D = 14 A 0.00750.009ΩV GS = 4.5 V , I D = 12 A 0.00950.012Forward T ransconductance a g fs V DS = 15 V, I D = 14 A 50S Diode Forward Voltage a V SDI S = 2.8 A, V GS = 0 V0.751.1VDynamic bTotal Gate Charge Q g V DS = 20 V , V GS = 5 V , I D = 14 A18.528nC Gate-Source Charge Q gs 6Gate-Drain Charge Q gd 7.5Gate Resistance R g 0.10.8 1.1ΩTurn-On Delay Time t d(on) V DD = 20 V , R L = 20 ΩI D ≅ 1 A, V GEN = 10 V , R G = 6 Ω1530nsRise Timet r 1020Turn-Off Delay Time t d(off) 50100Fall Timet f 2040Source-Drain Reverse Recovery Timet rrI F = 2.8 A, di/dt = 100 A/µs 3060Output CharacteristicsDocument Number: Vishay SiliconixSi7848DPTYPICAL CHARACTERISTICS 25°C, unless notedSource-Drain Diode Forward Voltage Document Number: 71450Vishay SiliconixSi7848DPTYPICAL CHARACTERISTICS 25°C, unless notedVishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Tech-nology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see /ppg?71450.Legal Disclaimer NoticeVishay Document Number: NoticeSpecifications of the products displayed herein are subject to change without notice. Vishay Intertechnology, Inc., or anyone on its behalf, assumes no responsibility or liability for any errors or inaccuracies.Information contained herein is intended to provide a product description only. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Vishay's terms and conditions of sale for such products, Vishay assumes no liability whatsoever, and disclaims any express or implied warranty, relating to sale and/or use of Vishay products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright, or other intellectual property right. The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications. Customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Vishay for any damages resulting from such improper use or sale.SI7848DP。

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C
PCB統盟,替料移除 R828 150K/6 -> 187K/6/1 , R829 2K/6 -> 7.5K/1 R828 150K/6 -> 187K/6/1 , R829 2K/6 -> 7.5K/1 R1085 931->806; R1171,R1172 62->1K,R1200 1K->0,R1197 1K,R1201 8.2K,Q206 MMBT222A REMOVE FOR CKD BOM PCB統盟,增加替料 PCB鴻達,增加替料
AD11 AD9 AD7 AD19 AE18 AE16 AE14 AE12 AE10 AE8 AE6 AE20 AB15 AB13 AB11 AB9 AB7 AB19 AC18 AC16 AC14 AC12 AC10 AC8 AD17 AD15 AD13 E14 E12 E10 E8 E20
VCORE1 VCORE2 VCORE3 VCORE4 VCORE5 VCORE6 VCORE7 VCORE8 VCORE9 VCORE10 VCORE11 VCORE12 VCORE13 VCORE14 VCORE15 VCORE16 VCORE17 VCORE18 VCORE19 VCORE20 VCORE21 VCORE22 VCORE23 VCORE24 VCORE25 VCORE26 VCORE27 VCORE28 VCORE29 VCORE30 VCORE31 VCORE32
2.02
5
4
3Leabharlann 21DD
VCORE
SOCKET_478A (7) HA[3..16] HA[3..16] HA16 HA15 HA14 HA13 HA12 HA11 HA10 HA9 HA8 HA7 HA6 HA5 HA4 HA3 -HADSTB0 -HREQ4 -HREQ3 -HREQ2 -HREQ1 -HREQ0 N5 N4 N2 M1 N1 M4 M3 L2 M6 L3 K1 L6 K4 K2 L5 H3 J3 J4 K5 J1 AB1 Y1 W2 V3 U4 T5 W1 R6 V2 T4 U3 P6 U1 T2 R3 P4 P3 R2 T1 R5 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 ADSTB0 REQ4 REQ3 REQ2 REQ1 REQ0 A35 A34 A33 A32 A31 A30 A29 A28 A27 A26 A25 A24 A23 A22 A21 A20 A19 A18 A17 ADSTB1
5
4
3
2
1
GIGABYTE GA-8I848P-G
SHEET
D
Schematics
SHEET 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 TITLE CODEC AUDIO JACK, ITE 8712 COM_LPT IDE FAN/HWMO KB_PS2 FPANEL USB CONN DDR POWER VCORE POWER ATX, OTHERS KINNERETH-R KINNERETH-R KINNERETH-R
ADD FLASH ROM 2M:SST 49LF002 REV.B & PMC 2M REV.E FDD 修改成PBT材質 FDD,IDE1,IDE2 修改成PBT材質 ADD 12CF1-2SERPW-01 CABLE RTCRST# R572 200K/6 --> 20K/6 Q117,Q200,Q123,Q204,Q205,Q202 加替料10IF4-501703-01 LU1 MARVELL Rev.A3-->A4 Q117,Q200,Q123,Q204,Q205,Q202 加替料AOD420:10IF4-250420-01 1. PCB 8I848P-G REV2.01 --> REV2.02 2. ADD 5VSB & USB PROTECT DIODE & PCI +12V UNSHORT
PAGE 11,12,13
C
ICH5 USB PORTS 0~7
VCC = 5V 5VSB = 5V 5VUSB = 5V
KINNERETH-R & USB CONN
PAGE 35
IDE Primary and Secondary
VCC25 = 2.5V(I/O,MEMORY/I,VLINK/I) 3VDUAL = 3.3V(SUSPEND POWER) VCC3 = 3.3V RTCVDD = 3.3V VCC = 5V
GMCH
SPRINGDALE
AGP BUS
VCORE = 1.75V / SLEEP : 1.3V 2_5VSTR = 2.5V(MEMORY) VDDQ = 1.5V (AGP POWER 4X, HUBLINK)
DCLKA0~5 -DCLKA0~5 MAAA0~12 MABA1~5 MDA0~63 -DQSA0~7 DMA0~7
PAGE 18
AC97 CODEC ALC650
+12V = 12V VCC3 = 3.3V VCC = 5V AVDD = 5V
FRONT PANEL
AC97 LINK
PAGE 29
PVCC = 5V VCC = 5V 5VSB = 5V +12 = 12V P_5VSB = 5V
LPC BUS
LPC I/O ITE8712
FOR D-STEPING CELERON CPU Modify Prescott CPU BOOTSEL Control Circuit
C
PCB 統盟,祥裕,信豐利 PCB 統盟,祥裕,信豐利 8I848PG-00-20B PCB REV2.01 統盟,祥裕 20B-0205 ADD 替料 LU2 AT24C08AN 20C-0213 R1188 33K -> 36K , R1189 910 -> 1.2K 8I848PG-00-20A NB-20C-0213 9M8I848PG-00-20C --> 9M8I848PG-NB-20C ECN-20C-0216 20D-0301 9MD-NB-20D 20E-0317 9MD-NB-20E 9MD-00-20E ECN-20E-0519 9MD-NB-20E 9MD-00-20E ECN-20E-0716 9MD-NB-20E 9MD-00-20E 9MD-NB-20E 9MD-20E-0812 20F-0730 9MD-20F-0831 20G-1007 NB-20G-1007 9MD-00-20F 20H-1028 NB-20H-1028 9MD-00-20G 20I-1224 NB-20I-1224 9MD-00-20H
PAGE 28
VCC = 5V 5VSB = 5V VBAT = 3V
PAGE 22
A
AUDIO PORTS :
LIN_ OUT CD_IN LINE_IN
FRONT AUDIO MIC
PAGE 30,31
FANS / HWMO
VCC = 5V 5VSB = 5V +12 = 12V
I/O PORTS :
D
C
B
A
01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22
L_OUT, F_AUDIO
C
POWER LNA(CSA-1) LNA(CSA-2) LNA(CSA-3)
B
COMPONENT SIDE (1 oz. Copper) VCC SIDE (1 oz. Copper) GND SIDE (1 oz. Copper) SOLDER SIDE (1 oz. Copper)
COMA COMB LPT PS2 FDD
PAGE 23 PAGE 25,26
A
GIGABYTE CORP.
Title
BOM & PCB MODIFY HISTORY
Rev
Size Document Number Custom Date:
5 4 3 2 1
GA-8I848P-G
Sheet 3 of 38
B
B
A
A
GIGABYTE CORP.
Title
BOM & PCB MODIFY HISTORY
Rev
Size Document Number Custom Date:
5 4 3 2
GA-8I848P-G
Sheet
1
2.02
2 of 38
5
4
3
2
1
BLOCK DIAGRAM
INTEL Pentium4 (478)
PAGE 4, 5, 6
PAGE 32,33,34
AGP SLOT 8X
VDDQ = 1.5V (AGP POWER 4X) VCC3 = 3.3V +12V = 12V 3VDUAL = 3.3V VCC = 5V
GDBI_LO, GDBI_HI GAD0~31 ADSTB0,ADSTB0ADSTB1,ADSTB1SBA0~7 SBSTB,SBSTBGCBE0~3ST0~2
Revision 2.02
TITLE COVER SHEET BOM & PCB MODIFY HISTORY BLOCK DIAGRAM P4_478A P4_478B P4_478C SPRINGDALE HOST SPRINGDALE DDR SPRINGDALE AGP, HUB, CSA, VGA SPRINGDALE PWR DDR1,2 CHANNEL A DDR3 CHANNEL A DDR TERMINATION AGP ICH5 PCI, USB, HUB, LAN ICH5 IDE, GPIO, SATA, CTRL ICH5 VCC, GND FWH ICS952603 CLOCK GEN PCI1_2 PCI3_4 PCI5_6