vhdl编程试题
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4-16译码器的VHDL程序：
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity CONNCET is
port(sel : in STD_LOGIC;
a : in STD_LOGIC_VECTOR(3 downto 0);
b : out STD_LOGIC_VECTOR(15 downto 0));
end CONNCET;
architecture LOGIC of CO NNCET is
begin
process(sel,a)
begin
ifsel='1' then
case a(3 downto 0) is
when "0000"=> b(15 downto 0)<="1111111111111110";
when "0001"=> b(15 downto 0)<="1111111111111101";
when "0010"=> b(15 downto 0)<="1111111111111011";
when "0011"=> b(15 downto 0)<="1111111111110111";
when "0100"=> b(15 downto 0)<="1111111111101111";
when "0101"=> b(15 downto 0)<="1111111111011111";
when "0110"=> b(15 downto 0)<="1111111110111111";
when "0111"=> b(15 downto 0)<="1111111101111111";
when "1000"=> b(15 downto 0)<="1111111011111111";
when "1001"=> b(15 downto 0)<="1111110111111111";
when "1010"=> b(15 downto 0)<="1111101111111111";
when "1011"=> b(15 downto 0)<="1111011111111111";
when "1100"=> b(15 downto 0)<="1110111111111111";
when "1101"=> b(15 downto 0)<="1101111111111111";
when "1110"=> b(15 downto 0)<="1011111111111111";
when "1111"=> b(15 downto 0)<="0111111111111111";
when others=> b(15 downto 0)<="1111111111111111";
end case;
end if;
end process;
end LOGIC;
相应的波形：
与门非门组成的与非门程序：
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity and2_gate is
generic (delay: TIME);
port (in1,in2: in STD_LOGIC;
out1:out STD_LOGIC);
end and2_gate;
architecturebeh of and2_gate is
begin
out1<=in1 and in2 after delay;
endbeh;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity nand2 is
port(a : in STD_LOGIC;
b : in STD_LOGIC;
q : out STD_LOGIC);
end nand2;
architecture view of nand2 is
component and2_gate
generic (delay: TIME);
port(in1,in2:in STD_LOGIC;
out1: out STD_LOGIC);
end component;
signal pass: STD_LOGIC;
begin
q<=NOT pass;
and_phase:and2_gate generic map(5ns)
port map(a,b,pass);
end view;
相应波形：。