bypass_capacitors_decoupling_KCP

Yet More On Decoupling...Kendall Castor-Perry A collection of articles first publishedin 2008, reproduced with kindpermission of the author.Yet More On Decoupling, Part 1: The Regulator’s Interaction with capacitors Kendall Castor-PerryIn “Know the sometimes-surprising interactions in modelling a capacitor-bypass network” (/showArticle.jhtml?articleID=202402836, abbreviated to “Know the...” when referred to here), Tamara Schmitz of Intersil and I provided some simulation background behind the interaction between multiple decoupling capacitors used in parallel. The series inductances inherent in the capacitors cause several resonant peaks and dips in the impedance response, sometimes at frequencies that might be critical for circuit operation. We advised that, if you intend to use decoupling capacitors of different values in parallel (there’s almost always more than one capacitor attached to the power rail), you’d better be sure that the location of the resonant peak won’t cause trouble in your circuit. But we didn’t say what kind of trouble that might be.So this series of articles is an attempt to quantify what’s happening on the supply line of a representative analog circuit with regulated supply rails and decoupling capacitors. We’ll do this entirely in simulation – mainly to show that this is both possible and revealing – and the path to interesting results will prove a somewhat bumpy one. Over the course of the six articles we will:•look at the overall supply impedance seen by a component when we include the decoupling caps, the voltage regulator and the board traces providing thecomponent’s power. In passing, we’ll discover just how supply voltageaffects the value of some ceramic capacitors;•see how such an impedance responds with a characteristic voltage transient when you ‘ping’ it with a small test current step such as an IC might demandfrom the power rail. Choice of capacitor dielectric turns out to have asignificant effect;•see how these supply variations punch through to the output of an op-amp running on these supplies;•discover that many op-amp simulation models, used for this purpose, are so inaccurate that they can produce seriously misleading and even physicallyimpossible results;•run a signal through the attached op-amp, drive a load, and see how the actual load current interacts with the modelled supply, and how this affects theamplifier output;•see that simulations provide an objective approach to selecting decoupling capacitors in order to alleviate a previously poorly documented effect on theprecision of op-amp circuits. And discover another way in which many op-amp simulation models are so inaccurate they are useless for this work! Paralleled decoupling capacitors – the story so farIf you didn’t catch them first time round, why not first review the article linked to above. The graphs in that article show the dramatic impedance excursions possible withparalleled decoupling capacitors of different values. A valid criticism of these plots is that they just refer to the capacitance that the device sees. They don’t include the impedance actually already present on the power supply rail, determined by the voltage regulator (which usually also has its own output capacitor), and the tracks or power planes that connect them all up. They don’t reflect any loss mechanisms that might lessen the severity of these effects. First step, therefore, is to rectify these omissions. Now, instead of just looking at just the theoretical impedance of the decoupling capacitors themselves, we’ll connect up a ‘real’ regulator IC to ‘real’ capacitors and connect all of this to a ‘real’ amplifier which is handling a ‘real’ signal. All in our virtual world, of course.For all the simulation work in these articles I’ve used SwitcherCad 3, which uses their LTspice simulation engine, and is available free from the Linear Technology website (/designtools/software/switchercad.jsp). If anyone is interested in experimenting further with the material presented here, I’ll be uploading the test files to the LTSpice Users Group (/group/LTspice/), so that you can reproduce this work and adapt the fixtures to your own needs. I had loaded SwitcherCad up as part of another project to fearlessly evaluate, on your behalf, some of the free software out there for circuit simulation, and for filter design (something close to my heart). The LTspice engine seems to be admirably robust, accurate and speedy, and SwitcherCad comes with a large library of Linear Technology op-amps, regulators and other devices, which I used here as typical of the parts that would be used on a quality, precision analog design.After some browsing through the SwitcherCad library I chose the LT1761-5 and LT1964-5 as the +5V and -5V regulators for the dual supplies on this virtual project, on the assumption that it will be handling bipolar analog signals. These are low-dropout regulators (LDOs); this type of regulator is commonly used for local regulation of power on analog subsystems.The regulator’s output capacitorThe LT data sheets indicates that output capacitors with low ESR value can be used with these parts, which is not always the case with low dropout regulators. The regulators were each operated with a 2.2uF output capacitor, and the common choices for that part would be a ceramic or a tantalum device. On cost grounds, my initial choice was a ceramic component, and additional help on capacitor parameters was taken from the program SpiCap3 which can be downloaded for free from AVX’s website(/SpiApps/default.asp).SpiCap3 provides an LCR capacitor model for any AVX ceramic capacitor, given operating conditions such as temperature and voltage, which change the capacitance of high value ceramic caps in a big way. The program was used to check parasitic inductance and ESR, and it provided some eye-opening insight into voltage dependency.I initially chose Y5V dielectric for the 2.2uF ceramic alternative, on the basis that temperature and voltage performance weren’t likely to be significant, while small sizeand low cost was. But when you dial in the voltage across the capacitor you find that at 31% of rated voltage – 5V used on a 16V part – the capacitance is down to one quarter of the rated value! In other words, my chosen Y5V 2.2uF part was only a 0.55uF capacitor. Note that while 2.2uF is above the specified minimum output capacitor value for these regulators, 0.55uF is below it, so you’d be violating LT’s guidelines without realising it. Note to AVX: why not make setting working voltage easier to do in the program? Each time you change the rated voltage you have to reset the percent of rated voltage slider, why not have the user enter an operating voltage and get the program to scale it?As designers, we all know that voltage dependency in high-k ceramics is an issue. But when the information is right there in front of you, it becomes much more real, and a huge red flag for all users of high value ceramic capacitors. The final ceramic choice was a 16V 1206 part with ESR of 8 milliohms, and an X5R dielectric to ensure that the actual value under 5V bias is 2.1uF, pretty close to nominal. Another note to AVX: how about having the program tell you the part number of the component you just selected? Getting on trackPrinted board construction varies greatly, and this affects the impedance of the power supply connections at low and high frequencies. I couldn’t find comprehensive models for typical printed circuit traces and started out with standard microstrip models, using the formulas in /pcbtlc2/microstrip.html to estimate inductance and capacitance (the latter is entirely negligible here), and straightforward physics to get the resistance. Nevertheless, a referee of an early draft of this paper felt sure that some acknowledgement of skin depth loss in the PCB traces would be needed, to produce simulations which better reflected physical reality. Accordingly, I adapted some published work on the losses that skin effect introduces into high speed cables.The specific dimension I’ve taken for my copper power trace is: length 50mm (one-tenth of a wavelength long at 600MHz, I’m only planning on analyzing up to 100MHz), width 1.27mm, thickness 35um (1oz copper, though sometimes inner layers are thinner than this), on a 4-layer board with the ground plane on an adjacent layer.only ground this morningWhatever you like to call it – ground, GND, 0V, Vdd, common – this connection causes just as much trouble in simulation as it does in the real world. Ironically, it’s because the ground net in SPICE is perfect, ubiquitous and available anywhere in your circuit at a mouse-click that it yields physically unrealistic results. The makers’ device models also have a rather unhealthy relationship with GND, as we’ll see. As far as the project layout goes, I’ve referred all the inductance impeding the flow of supply current to the supply connections – it’s the total voltage variation at the amplifier under test that I’ll be interested in, and I won’t be asking tough questions about ground voltage variation across my ‘circuit board’.Before we actually fit an amplifier, we’ll just look at the decoupling. We’ll consider a single capacitor per rail (this is in addition to the output capacitor of the regulator), and step its value from 22nF to 470nF, a pretty common spread for single decouplingcapacitors. The SpiCap3 program gave ESR values for each cap choice once I’d decided size and voltage (X7R dielectric used in all cases), but the spread was not that dramatic so an average value of 33milliohms was used. Another parameter I’ve made constant is the parasitic inductance of the capacitor. This is determined by capacitor body size and mounting details, as discussed in “Know the...”. As the capacitor value gets larger, the chosen size of the capacitor rises from 0402 to 0603; for simplicity I have included aconstant 0.7nH for the parasitic inductance and have ignored the ~0.2nH difference you’d get between the two case sizes. This doesn’t have significant effect on the results here.All together now...Figure 1.1 shows the test circuit so far: regulators with their ceramic output capacitors, with 20mA of (constant) load current taken out of them; power supply traces with some skin effect modelling, and a capacitor which we’ll be using as a decoupling device for some subsequent electronics. Figure 1.2 is a busy graph showing various impedances calculated as the AC voltage response on the supply rail divided by the value of the test current source, plotted in dB referred to 1 Ohm. Because the test current has a value of 1, just plotting the voltage also gives the impedance. Don’t worry, this is a linear, level-independent analysis, it doesn’t mean I’m using a test current of 1 Amp!100Hz1KHz 10KHz 100KHz 1MHz 10MHz 100MHz-30dB-20dB -10dB 0dB 10dB 20dB 30dB 40dB50dB 60dB 70dB 80dB 90dB100dBV(n012)/i(r4)V(n006)/i(c7)V(n006)Figure 1.1(L):basic supply impedance test circuit, see text Figure 1.2(R): basic supply impedance test results, see textThere’s a lot going on here. The red traces show the change in impedance of the decoupling capacitor as it is swept; no surprises there. As the value falls, the mow frequency impedance rises, as does the notch frequency where it’s resonating with its self-inductance. At very high frequencies the impedance is rising and isn’t dependent on capacitor value.The blue trace, shown just for the negative rail, is the apparent impedance of everything else connected to the decoupling capacitor. At very low frequencies the impedance is low, as you’d expect for a regulator. As the frequency increases, the impedance rises – why, we’ll come to in a moment. Then above about 10kHz it starts to fall again, and it reaches a minimum just below 1MHz. This is the frequency at which the regulator’soutput capacitor resonates with the layout inductance. After that the impedance rises – we are just seeing the impedance of the power trace.The green traces show the combined effect, shown this time for the +ve rail, primarily to illustrate that the ‘bump at 10kHz is there as well, and it has a pretty similar shape. As expected from “Know the...” there’s now an impedance peak in between the notches; its height (i.e. the ‘Q’ of the resonance) and frequency increase as the decoupling capacitor value is reduced. Shortly we’ll start to look at what happens when some current is demanded from this strange, peaky impedance.But what about the impedance bump around 10kHz – what component is causing this resonance – looks like it must be a very large inductor? Well, it’s the regulator itself , and here’s why. An LDO’s output stage is basically a buffer amplifier with high-ish output impedance and feedback around it to bring that down. The internal amplifier has only moderate bandwidth and approximates an integrator, as indeed the vast majority of op-amps do (hold that thought for the next part). This helps the regulator to be stable with a variety of reactive loads. So the effectiveness of the feedback in reducing the output impedance lessens at higher frequencies, and so the output impedance rises with increasing frequency. The regulator thus acquires an inductive output impedance.Feeling a little ‘peaky’The ‘bump’ at 10kHz is the result of this inductive output impedance resonating with the 2.2uF output capacitor. And it changes with the load current; figure 1.3 shows a load current sweep from 1mA to 50mA. At lower currents the height of the impedance peak can rise dramatically. Some LDO regulator data sheets do tell you this in the graphical small print at the back, but often don’t dwell on the consequences. We can also see that the two regulators don’t behave in the same way as current is changed. Green trace is the composite for the decoupled +ve rail; both rails look the same at high frequencies. Blue trace is the –ve regulator and traces at low frequencies, and represents either regulator at higher frequencies. In the figures, the decoupling capacitor is held at 100nF (red trace).100Hz1KHz 10KHz 100KHz 1MHz 10MHz 100MHz -40dB-30dB -20dB -10dB 0dB 10dB 20dB 30dB 40dB 50dB 60dB 70dB 80dB 90dB V(n012)/i(r4)V(n006)/i(c7)V(n006)100Hz1KHz 10KHz 100KHz 1MHz 10MHz 100MHz-40dB-30dB -20dB -10dB 0dB 10dB 20dB 30dB 40dB 50dB 60dB 70dB 80dB 90dB V(n006)/i(r1)V(n006)/i(c7)V(n016)Figure 1.3(L): variation of theregulator’s effective inductance with load current Figure 1.4(R): as figure 1.3 but with ‘noise bypass’ caps fittedThe maker of these particular regulators has thoughtfully provided an extra pin, which can be connected back to the output with a capacitor (the noise bypass capacitor confusingly also called a ‘bypass’ capacitor). This reduces the high frequency gain, with the main intention of reducing the output noise of the regulator. Does it also have an effect on the output impedance? It sure does, figure 1.4 shows how the peaks can be managed by attaching a suitable capacitor (not the same for each regulator; I used 2200pF on the +ve regulator and 150pF on the –ve regulator). The tracking and matching is not perfect but it looks to me like a worthwhile improvement, because not all circuits attached to these supplies can be assumed to have perfect power supply rejection performance. To be continued...Takeaways from this part:•If you are using Y5V capacitors with DC bias across them – as you always do in a supply decoupling application – carefully calculate the effectivecapacitance value. You could be ‘out’ by enough to seriously impair circuitperformance and reliability.•LDOs have an effective output inductance; it varies with output current (goes higher as the current falls) and causes an output impedance peak with theoutput capacitor. Use an LDO with a “noise bypass” capacitor connection toflatten out the impedance.Yet More On Decoupling, Part 2: ring the changes, change the ringsKendall Castor-PerryPreviously on “Yet more...” we built up a pair of regulators with output capacitors, and connected them to some decoupling caps with a short length of copper trace. We looked at the impedance at these decoupling caps, and saw some peaks. What happens when we start taking some current from these imperfect supplies?Figures 2.1 and 2.2 show what happens in the time domain when we take a squarewave current switching between 0 and +10mA at 100kHz from the positive regulator, and one switching between -10mA and 0 on the negative regulator. The rationale is that later on, we’ll either be taking current from the +ve rail, or dumping it into the –ve rail. Remember that the regulators have a static load of 20mA as well, so we are not taking regulator current down to zero. The swept parameter is once again the value of the local decoupling capacitor, 22nF (top trace, blue) to 470nF (bottom trace, pink), and the traces are offset from the top down by 10mV each time.Figure 2.1(L): pinging the positive rail with 100kHz 0 to +10mA square wave, 5mV/div, traces spread by 10mV Figure 2.2(R): pinging the negative rail with 100kHz 0-10mA square wave,5mV/div, traces spread by 10mVAs expected, the smallest capacitor shows the highest amplitude of additional ringing, occurring at the highest frequency. As the capacitor value goes up, the magnitude of the ringing falls. Constant in all this is the effective impedance at the 100kHz fundamental, which seems to be about 0.7ohms for either supply. Note that these voltages are in phase. The frequent assumption about the supply variations being symmetrical around ground is not true in this case; indeed, hardly ever true.The high frequency ringing looks unsightly and may well impact our circuits – what could we do about that? We need some damping somewhere, perhaps by adding some series resistance to one of the capacitors. This will help to dissipate stored energy in the resonant circuits more rapidly, reducing the ‘Q’. Now, with other regulator designs we might have been forced to have this extra series resistance, because some LDO designs are not stable when the main output capacitor has too low an ESR. Often in those designs a tantalum capacitor is used, so let’s pick one.AVX have another useful utility on their download page, SpiTanII, which assists with the selection of tantalum capacitors, and the associated SPICE library contains models which accurately portray the frequency-dependent loss of that type of cap. This should lead to much more accurate simulation than just guessing a resistive ESR value. A 2.2uF 1206-sized part (TPSA225K016R1800, same footprint as the ceramic previously deployed, and with 16V working voltage) was chosen; it has a rated maximum ESR of 1.8ohms at 100kHz, which is about as good as it gets for a small tantalum. Important tip: fit this capacitor the right way round in your simulations. In the simulation world as well as in the real world, the tantalum capacitor doesn’t work properly under reverse polarity!100Hz1KHz 10KHz 100KHz 1MHz 10MHz 100MHz-40dB-30dB -20dB -10dB 0dB 10dB 20dB 30dB 40dB 50dB 60dB 70dB 80dB 90dB V(plus)V(minus)v(plus)/i(c7)Figure 2.3(L):same as fig 2.1 but using a 2.2uF tantalum output cap on the +ve regulator Figure 2.4(R): impedance plots of the supply rails with tantalum capacitors. Contrast with figure 1.2 in part 1What a difference; a lot less high frequency rubbish (especially on the –ve rail which is not shown). The impedance curves show why; with the tantalum capacitor, the +veregulator particularly is still showing some peaking just below 1MHz. Still, looks like an improvement, but we will keep testing this choice in the work to come, to see what consequences the ringing has.Can you hear me?Most of this work is concerned with effects in the MHz region, but in passing, let’s look at what happens with lower frequency stimulation of the rails. This may be interesting for people working on audio applications.Figure 2.5 shows the rail impedances as we step up the regulator output capacitor from our current 2.2uF up to a whopping 2200uF (ESR was set at 0.1ohm for all of them, as might come from a physically large aluminium electrolytic used in audio circuits). The decoupling capacitor was fixed at 100nF; none of the high frequency effects pointed out earlier are relevant at this timescale. As the capacitance value increases, the audio band impedance becomes flatter, then finally rather less flat as the very largest capacitor does a better job than the regulator does. Figure 2.6 shows the voltage response of the +ve rail to a test current of 0-10mA at 333Hz.100Hz1KHz 10KHz 100KHz 1MHz 10MHz 100MHz-40dB-30dB -20dB -10dB 0dB 10dB 20dB 30dB 40dB 50dB 60dB 70dB 80dB 90dB V(plus)V(minus)v(plus)/i(c7)Figure 2.5(L): rail impedance as we increase the regulator output cap from 2.2uF up to 2200uF, decade steps. This is with the noise bypass caps. Figure 2.6(R): voltage on the rails when 0-10mA squarewave at 333Hz is applied. 2.2uF top, 2200uF bottom.As the output capacitor increases, it provides progressively more ‘support’ for theregulator. Going only on the traces in figure 2.6, it looks like a 220uF capacitor would do a good job of delivering an ‘uncoloured’, frequency-independent output impedance in the audio band. The square-wave response for the 2200uF is actually less accurate, though judgements like these will depend on the actual test frequency and there’s no one “right answer”.Remember that we suppressed some impedance peaking at 10kHz in part 1 by adding the noise bypass capacitors. What happens if we lift these off and run this test again?: The resulting rail impedance is shown in figure 2.7; the location of the peak falls as the output capacitor is increased, but even with an enormous 2200uF capacitor it’s still well into the audible band. The consequences of this peak are clear in the current transient test. Perhaps it’s not surprising that advocates of ultimate audio quality insist that capacitor selection can have an effect on a system’s sonic performance even where you’d think it couldn’t, like on the output of a regulator. Fit those noise bypass caps!100Hz1KHz 10KHz 100KHz 1MHz 10MHz 100MHz-40dB-30dB -20dB -10dB 0dB 10dB 20dB 30dB 40dB 50dB 60dB 70dB 80dB 90dB V(plus)V(minus)v(plus)/i(c7)Figure 2.7(L): as figure 2.5 but with the noise bypass capacitors removed. Note the resonant peak in the audio band Figure 2.8(R): the response of figure 2.7 to the 0-10mA 333Hz square wave. Talk about ringing!Still to come: we’ll look at ‘real’ operational amplifiers (well, models of them, anyway) and see what actually happens at their output when their supply pins are waved around.And then we’ll bring those amplifiers and the power supply from this part together. It won’t be pretty! To be continued...Takeaways from this part:•Whatever the LDO datasheet says, high-ESR output capacitors give better control of high frequency supply resonances•The smaller you make the main ceramic decoupling capacitor, the faster and larger will be the ringing that occurs on a load current step – this is a small-signal effect and occurs for any current change, not just large ones.•If you are designing audio circuits which don’t have impeccable power supply rejection, the LDO regulator impedance bump could cause coloration as itusually occurs within the audio band. Huge output capacitors don’t cure it, infact they could make it worse. Use that noise bypass connection.Yet More On Decoupling, Part 3 – Some gain, some painKendall Castor-PerryPreviously on “Yet More...” we looked at the impedance of a typical regulator and decoupling capacitor combination, and showed what happened when you ‘shock’ it with some dynamic current consumption. Now we’re going to look at whether we should be concerned about the wobbling supply voltage that analog components will experience when connected. We’ll focus on a staple ingredient of the analog designer’s toolbox: the op-amp.“Bah, Humbug!”, I hear from somewhere in the audience. “Modern precision op-amps are so fantastic that their enormous power supply rejection will extinguish any possible effect that varying supplies could have on a circuit! My dear boy, decoupling capacitors are only there to quell the evil spirits of oscillation, they don’t actually affect the performance of the circuit! Simulate the power supply rail? Haven’t you got anything better to do with that new-fangled slide rule of yours?”Well, we’ll see. By now, most analog engineers are (or should be) wise to the myth that ‘op-amps have almost infinite gain and everything is sorted out by the negative feedback loop, whose properties completely dominate the closed-loop performance’. However, despite huge advertised ‘open loop gains’, it is the destiny of any op-amp’s gain curve to trend downwards at roughly 6dB per octave until at some frequency (the unity-gain frequency, numerically equal to gain bandwidth product in simple cases, though the terms don’t mean the same thing), there’s none left, it’s just unity, or 0dB. As frequency rises, falling loop gain means a falling amount of feedback to correct errors inside the loop. What’s more, some amplifiers don’t even have very high low frequency open loop gain either. This is particularly true either of very fast amplifiers or very cheap amplifiers. OK, so we may not have that much loop gain, but why does it matter – surely a competent designer can suppress the sensitivity to supply rail variations just through architecture choices. Not so! Here’s a blunt assertion you may not have seen before: it is not possible to build a conventional op-amp (a pair of differential inputs, two power pins, one single-ended output pin) which is insensitive to voltage variations on one or other of its power pins. The device converts the voltage difference between the signal inputs into a single-ended output – but that output has to be referenced to something other than ground, because the op-amp doesn’t have a ground pin! Depending on the design, the output voltage will be referenced either to one or other supply pin, or to a voltage somewhere along a potential divider between those two pins (think of it as produced by the ratio of output conductances of the current paths in the main gain stage to the two supply pins).So, you can’t build a precision op-amp which behaves like it had its own private voltage regulators inside to prevent the output voltage from moving when the supplies do. That kind of device would require a ground connection to reference those private regulators to, which our standard pinout does not give us. And indeed this is borne out by the PSRR plots in amplifier data sheets, which usually show curves with the same general shape asthe open-loop gain. Figure 3.1 shows the open loop gain of LT’s LT1723 and figure 3.2 shows the PSRR of the amplifier when connected as a unity gain buffer. The curves for rejection from the +ve and –ve supplies deviate at low frequencies but are very similar above 1MHz.Figure 3.1(L): the open-loop gain response of the LT1723 to signals applied at its input pins Figure 3.2(R): the closed-loop gain response of the LT1723 to signals applied at its power pinsThe question of common-mode performance effects on the input stage is a complicating factor and I want to skirt round that for this article. Of course the input stage is attached to the power supplies, and the apparent input voltage at the device can be distorted by the input stage’s reaction to supply variations. But, unlike the power supply rejection problem, this one is amenable to design, layout and processing fixes. Also, the common mode rejection capabilities of current-feedback amplifiers often fall short of good voltage mode op-amps. For clarity of purpose, I’ll use voltage-feedback op-amps in an inverting amplifier configuration as my circuit under test. This means that the input stage only has to reject the (hopefully small) supply variations, and not any applied input signal as well. Figure 3.3 shows a basic test fixture for measuring the power supply gain (PSG) of a simulation model. The PSG is just the ratio between the small-signal voltage response at the output pin (with respect to ground) to the voltage variation applied to the supply pin (again with respect to ground). The component values depend on whether we’re testing the open-loop (OLPSG) or closed-loop PSG. For the open-loop measurement, we ensure that a good operating point is set by a feedback loop with such a large time constant that it doesn’t allow AC feedback at any frequency we’re simulating over. For the closed-loop test, we just run the amplifier at a gain of -1, by editing the capacitor’s value down from very large (an AC short circuit at all frequencies) to very small (an AC open circuit at all frequencies).。