FPGA可编程逻辑器件芯片5SGSMD5K3F40C3WN中文规格书

Introduction The core clock (CCLK) and system peripheral clock (SCLK) are derived from the input clock (CLKIN) signal. An on-chip phase-locked loop (PLL) is capable of multiplying the CLKIN signal by a user-programmable (0.5x to 64x) multiplication factor (bounded by specified minimum and maximum VCO frequencies). The default multiplier is 8x, but it can be modified by
a software instruction sequence. On-the-fly frequency changes can be
made by simply writing to the PLL_DIV register.
All on-chip peripherals are clocked by the system clock (SCLK). The system clock frequency is programmable by means of the SSEL[3:0] bits of the PLL_DIV register.
Dynamic Power Management
The processor provides four operating modes, each with a different perfor-mance/power profile. In addition, dynamic power management provides the control functions to dynamically alter the processor core supply volt-age to further reduce power dissipation. Control of clocking to each of the peripherals also reduces power consumption.
Full On Mode (Maximum Performance)
In the full on mode, the PLL is enabled, not bypassed, providing the max-imum operational frequency. This is the normal execution state in which maximum performance can be achieved. The processor core and all
enabled peripherals run at full speed.
Active Mode (Moderate Dynamic Power Savings) In the active mode, the PLL is enabled, but bypassed. Because the PLL is bypassed, the processor’s core clock (CCLK) and system clock (SCLK) run at the input clock (CLKIN) frequency. DMA access is available to appropri-ately configured L1 and L2 memories.
ADSP-BF54x Blackfin Processor Hardware Reference
One-Time Programmable Memory
4.The developer is responsible for locking both the data page(s) and
the ECC page(s) after all programming is complete.
5.Pages 0x04 to 0x0F are reserved for factory use. Therefore, pages
0x004 to 0x00F, 0x0E0, and 0x0E1 are locked when devices leave
the Analog Devices Inc. factory.
Table 4-2. Mapping for Storage of Error Correction Codes for Unsecured OTP Space
Page Byte
15141312111098 0x0E00x007U0x007L0x006U0x006L0x005U0x005L0x004U0x004L 0x0E10x00FU0x00FL0x00EU0x00EL0x00DU0x00DL0x00CU0x00CL 0x0E20x017U0x017L0x016U0x016L0x015U0x015L0x014U0x014L ....
0x0FB0x0DFU0x0DFL0x0DEU0x0DEL0x0DDU0x0DDL0x0DCU0x0DCL
Page76543210
0x0E0Unused Unused Unused Unused Unused Unused Unused Unused 0x0E10x00BU0x00BL0x00AU0x00AL0x009U0x009L0x008U0x008L 0x0E20x013U0x013L0x012U0x012L0x011U0x011L0x010U0x010L ....
0x0FB0x0DBU0x0DBL0x0DAU0x0DAL0x0D9U0x0D9L0x0D8U0x0D8L ADSP-BF54x Blackfin Processor Hardware Reference。