AD401M324RQA-5中文资料

ASCEND Semiconductor 4Mx4 EDO Data sheet
Description
The device CMOS Dynamic RAM organized as 4,194,304 words x 4 bits with extended data out access mode. It is fabricated with an advanced submicron CMOS technology and designed to operate from a single 3.3V oniy power supply. Low voltage operation is more suitable to be used on battery backup, portable elec-tronic application. lt is packaged in JEDEC standard 26/24-pin plastic SOJ or TSOP(II).Features
• Single 3.3V(%) only power supply • High speed t RAC acess time: 50/60ns • Low power dissipation
- Active mode : 432/396 mW (Mas) - Standby mode: 0.54 mW (Mas)
• Extended - data - out(EDO) page mode access • I/O level: CMOS level (Vcc = 3.3V)
• 2048 refresh cycle in 32 ms(Std.) or 128 ms(S-version)• 4 refresh modesh: - RAS only refresh
- CAS - before - RAS refresh - Hidden refresh - Self-refresh(S-version)
10±
Pin Name Function
A0-A10
Address inputs
- Row address - Column address - Refresh address DQ1~DQ4Data-in / data-out RAS Row address strobe CAS Column address strobe WE Write enable OE Output enable Vcc Power (+ 3.3V)Vss
Ground
VCC 1DQ12DQ23DQ34DQ45VCC
6891011 NC 12 WE 13
A0 A117 A218 A319VSS RAS CAS OE A8A7A6A5A4VSS
AD404M42VS
Pin Description Pin Configuration
21222324 25
261514
16 A1026/24-PIN 300mil Plastic SOJ
A9VCC 1DQ12DQ23DQ34DQ45VCC
6891011 NC 12 WE 13
A0 A117 A218 A319VSS RAS CAS OE A8A7 A6A5 A4VSS
AD404M42VT
2122232425261514
16 A1026/24-PIN 300mil Plastic TSOP (ll)
A9A0-A10A0-A10A0-A10
WE
CAS
NO. 2 CLOCK GENERATOR
COLUMN ADDRESS BUFFERS (11)
REFRESH CONTROLLER
REFRESH COUNTER
BUFFERS (11)
ADDRESS ROW NO. 1 CLOCK GENERATOR
A0RAS
A1A2A3A4A5A6A7A8CONTROL
LOGIC
DATA-IN BUFFER
DATA-OUT BUFFER
OE
DQ1.DQ4
.COLUMN DECODER
2048
SENSE AMPLIFIERS
I/O GATING
2048x4
2048x2048x4MEMORY ARRAY
2048
R O W D E C O D E R
Vcc Vss
Block Diagram
A9
A10
TRUTH TABLE
Notes: 1. EARLY WRITE only.
FUNCTION
RAS
CAS WE OE ADDRESSES
DQ S
Notes
ROW COL STANDBY H X X X X High-Z READ
L L H L ROW COL Data-Out WRITE: (EARLY WRITE )L L L X ROW COL Data-ln
READ WRITE L L ROW COL Data-Out,Data-ln EDO-PAGE-MODE READ
1st Cycle L H L ROW COL Data-Out 2nd Cycle
L H L n/a COL Data-Out EDO-PAGE MODE WRITE
1st Cycle
L L X ROW COL Data-In 2nd Cycle L L X
n/a COL Data-In
EDO-
PAGE-MODE
READ-WRITE 1st Cycle L ROW COL Data-Out, Data-In 2nd Cycle L n/a COL Data-Out, Data-In HIDDEN REFRESH
READ L H L ROW COL Data-Out WRITE
L L X ROW COL Data-In 1
RAS-ONLY REFRESH L H X X ROW n/a High-Z CBR REFRESH
L
H
X
X
X
High-Z
H X →H L →L H →H L →H L →H L →H L →H L →H L →L H →H L →H L →L H
→L H L →→L H L
→→H L
→
Absolute Maximum Ratings
Recommended DC Operating Conditions
Capacitance
Ta = 25°C, V CC = 3.3V
%, f = 1MHz Note: 1. Capacitance measured with effective capacitance measuring method. 2. RAS, CAS = V IH to disable Dout.
Parameter
Symbol Value Unit Voltage on any pin relative to Vss V T -0.5 to + 4.6V Supply voltage relative to Vss V CC -0.5 to + 4.6
V Short circuit output current I OUT 50mA Power dissipation P D 1.0W
Operating temperature T OPT 0 to + 70°C Storage temperature
T STG
-55 to + 125
°C
Parameter/Condition Symbol
3.3 Volt Version
Unit
Min
Typ Max
Supply Voltage
V CC 3.0 3.3
3.6
V Input High Voltage, all inputs V IH 2.0-V CC + 0.3V Input Low Voltage, all inputs
V IL
-0.3
-0.8
V
Parameter
Symbol Typ Max Unit Note Input capacitance (Address)
C I1 -5pF 1Input capacitance (RAS, CAS, OE, WE)C I2-7pF 1Output capacitance
(Data-in, Data-out)
C I/O
-
7
pF
1, 2
10±
DC Characteristics :
(T a = 0 to 70°C, V CC = + 3.3V%, V SS = 0V)
Parameter Symbol Test Conditions AD404M42V Unit Notes
-5-6
Min Max Min Max
Operating current I CC1RAS cycling
CAS, cycling
t RC = min
-120-110mA1, 2
Standby Current Low
power
S-version
I CC2LVTTL interface
RAS, CAS = V IH
Dout = High-Z
-0.5-0.5mA
CMOS interface
RAS, -0.2V
Dout = High-Z
-0.15-0.15mA
Standard
power
version
LVTTL interface
RAS, CAS = V IH
Dout = High-Z
-2-2mA
CMOS interface
RAS,-0.2V
Dout = High-Z
-0.5-0.5mA
RAS- only refresh current I CC3RAS cycling, CAS = V IH
t RC = min
-120-110mA1, 2 EDO page mode current I CC4t PC = min-90-80mA1, 3
CAS- before- RAS refresh current I CC5t RC = min
RAS, CAS cycling
-120-110mA1, 2
Self- refresh current (S-Version)
I CC8 - 550 - 550
10
±
CAS V CC
≥
CAS V CC
≥
t RASS100µs
≥µA
DC Characteristics :
(T a = 0 to 70°C , V CC = +3.3V %, V SS = 0V)
Notes:
1. I CC is specified as an average current. It depends on output loading condition and cycle rate when the device is selected. I CC max is specified at the output open condition.
2. Address can be changed once or less while RAS = V IL .
3. For I CC4, address can be changed once or less within one EDO page mode cycle time.
Parameter Symbol Test Conditions AD404M42V
Unit
Notes
-5
-6Min Max
Min Max
Input leakage current I LI + 0.3V -55-55Output leakage current I LO + 0.3V Dout = Disable -5
5
-55
Output high Voltage V OH I OH = -2mA 2.4- 2.4-V Output low voltage V OL
I OL = +2mA
-0.4
-0.4
V
10±0V Vin V CC ≤≤µA 0V Vout V CC ≤≤µA
AC Characteristics
(T a = 0 to + 70°C , V cc = 3.3V %, V ss = 0V) *1, *2, *3, *4
Test conditions
• Output load: one TTL Load and 100pF (V CC = 3.3V %)• Input timing reference levels:
V IH = 2.0V, V IL = 0.8V (V CC = 3.3V %)• Output timing reference levels:V OH = 2.0V, V OL = 0.8V
10±10±10±Read, Write, Read- Modify- Write and Refresh Cycles (Common Parameters)
Parameter
Symbol AD404M42V Unit
Notes
-5
-6Min Max
Min Max
Random read or write cycle time t RC 84-104-ns RAS precharge time
t RP 30-40-ns CAS precharge time in normal mode t CPN 10-10-ns RAS pulse width t RAS 50100006010000ns 5CAS pulse width t CAS 810000
1010000
ns 6
Row address setup time t ASR 0-0-ns Row address hold time t RAH 8-10-ns Column address setup time t ASC 0-0-ns 7Column address hold time t CAH 8-10-ns RAS to CAS delay time
t RCD 12371445ns 8RAS to column address delay time t RAD 10251230ns 9Column address to RAS lead time t RAL 25-30-ns RAS hold time t RSH 8-10-ns CAS hold time
t CSH 38-40-ns CAS to RAS precharge time t CRP 5-5-ns 10OE to Din delay time t OED 12-15-ns Transition time (rise and fall)t T 150150ns 11Refresh period
t REF -32-32ms Refresh period (S- Version)t REF -128-128ms CAS to output in Low- Z t CLZ 0-0-ns CAS delay time from Din t DZC 0-0-ns OE delay time from Din
t DZO
-0-ns
Read Cycle
Write Cycle Parameter Symbol
AD404M42V Unit Notes
-5-6
Min Max Min Max
Access time from RAS t RAC-50-60ns12 Access time from CAS t CAC-14-15ns13, 14 Access time from column address t AA-25-30ns14, 15 Access time from OE t OEA-12-15ns
Read command setup time t RCS0-0-ns7 Read command hold time to CAS t RCH0-0-ns10, 16 Read command hold time to RAS t RRH0-0-ns16 Output buffer turn-off time t OFF012015ns17 Output buffer turn-off time from OE t OEZ012015ns17
Parameter Symbol
AD404M42V Unit Notes -5-6
Min Max Min Max
Write command setup time t WCS0-0-ns7, 18 Write command hold time t WCH8-10-ns
Write command pulse width t WP8-10-ns
Write command to RAS lead time t RWL13-15-ns
Write command to CAS lead time t CWL8-10-ns
Data-in setup time t DS0-0-ns19 Data-in hold time t DH8-10-ns19 WE to Data-in delay t WED10-10-ns
Read- Modify- Write Cycle
Refresh Cycle Parameter Symbol
AD404M42V Unit Notes
-5-6
Min Max Min Max
Read-modify- write cycle time t RWC108-133-ns
RAS to WE delay time t RWD64-77-ns18 CAS to WE dealy time t CWD26-32-ns18 Column address to WE delay time t AWD39-47-ns18 OE hold time from WE t OEH8-10-ns
Parameter Symbol
AD404M42V
Unit Notes -5-6
Min Max Min Max
CAS setup time (CBR refresh) t CSR5-5-ns
CAS hold time (CBR refresh)t CHR8-10-ns10 RAS precharge to CAS hold time t RPC5-5-ns7 RAS pulse width (self refresh)t RASS100-100-
RAS precharge time (self refresh)t RPS90-110-ns
CAS hold time (CBR self refresh)t CHS-50--50-ns
WE setup time t WSR0-0-ns
WE hold time t WHR10-10-ns
µs
EDO Page Mode Cycle
EDO Page Mode Read Modify Write Cycle
Parameter
Symbol AD404M42V
Unit Notes
-5
-6Min Max
Min Max
EDO page mode cycle time
t PC 20-25-ns EDO page mode CAS precharge time t CP 10-10-ns EDO page mode RAS pulse width t RASP 5010560105ns 20Access time from CAS precharge t CPA -30-35ns 10, 14RAS hold time from CAS precharge t CPRH 30-35-ns OE high hold time from CAS high t OEHC 5-5-ns OE high pulse width
t OEP 10-10-ns Data output hold time after CAS low t COH 5-5-ns Output disable delay from WE
t WHZ 310310ns WE pulse width for output disable when
CAS high
t WPZ
7
-7-ns
Parameter
Symbol AD404M42V Unit Notes -5
-6Min Max
Min Max
EDO page mode read- modify- write cycle CAS precharge to WE delay time
t CPW 45-55-ns 10
EDO page mode read- modify- write cycle time
t PRWC
56
-68-ns
Notes :
1. AC measurements assume t T = 2ns.
2. An initial pause of 100 is required after power up, and it followed by a minimum of eight
initialization cycles (RAS - only refresh cycle or CAS - before - RAS refresh cycle). If the internal refresh counter is used, a minimun of eight CAS - before - RAS refresh cycles are required.
3. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device.
4. All the V CC and V SS pins shall be supplied with the same voltages.
5. t RAS (min) = t RWD (min)+t RWL (min)+t T in read-modify-write cycle.
6. t CAS (min) = t CWD (min)+t CWL (min)+t T in read-modify-write cycle.
7. t ASC (min), t RCS (min), t WCS (min), and t RPC are determined by the falling edge of CAS .
8. t RCD (max) is specified as a reference point only, and t RAC (max) can be met with the t RCD (max) limit.Otherwise, t RAC is controlled exclusively by t CAC if t RCD is greater than the specified t RCD (max) limit. 9. t RAD (max) is specified as a reference point only, and t RAC (max) can be met with the t RAD (max) limit.Otherwise, t RAC is controlled exclusively by t AA if t RAD is greater than the specified t RAD (max) limit. 10. t CRP , t CHR , t RCH , t CPA and t CPW are determined by the rising edge of CAS .
11. V IH (min) and V IL (max) are reference levels for measuring timing or input signals. Therefore, transition
time is measured between V IH and V IL .
12. Assumes that t RCD t
RCD (max) and t RAD t RAD (max). If t RCD or t RAD is greater than the maximum recommended value shown in this table, t RAC exceeds the value shown. 13. Assumes that (max) and (max).
14. Access time is determined by the maximum of t AA , t CAC , t CPA . 15. Assumes that (max) and (max). 16. Either t RCH or t RRH must be satisfied for a read cycle.
17. t OFF (max) and t OEZ (max) define the time at which the output achieves the open circuit condition (high
impedance). t OFF is determined by the later rising edge of RAS or CAS.
18. t WCS , t RWD , t CWD , and t AWD are not restrictive operating parameters. They are included in the data
sheet as electrical characteristics only. If (min), the cycle is an early write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. If (min),(min), (min) and (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell. If neither of the above sets of conditions is satisfied, the condition of the data output (at access time) is indeterminate.
19. These parameters are referenced to CAS separately in an early write cycle and to WE edge in a
delayed write or a read-modify-write cycle.
20. t RASP defines RAS pulse width in EDO page mode cycles.
µs ≤≤t RCD t RCD ≥t RAD
t RAD ≤t RCD t RCD ≤t RAD t RAD ≥t WCS t WCS ≥t RWD t RWD ≥t CWD
t CWD ≥t AWD t AWD ≥t CPW t CPW
≥
Timing Waveforms
• Read Cycle
t RC t RAS
t RP
t
CRP
t
CPN
t
RRH
t
RCH
t OEZ t OFF t
OEA t
CAC
t AA
t
RAC
t CLZ
D OUT
t
RCS t ASR t
RAH t
ASC t
CAH t
RAD t RAL
t
CAS
t
RSH t
RCD
t T
t
CSH
RAS
CAS
ADDRESS
WE
DQ1~DQ4
Note : = don’t care OE
t OFF
Row
Column
= Invalid Dout
•Early Write Cycle
t
RC t RAS
t RP
t WCH
t DS
t DH
t WCS t RAL
t
CAS
t
RSH t
RCD
t T
t
CSH
RAS
CAS
WE
DQ1~DQ4
t
CRP
t
ASR
t
RAH t
ASC
t
CAH ADDRESS
Column
Row
t
CPN
D IN
t
RAD
t RAL
• Delayed Write Cycle
t
RC t RAS
t RP
t RWL t RCS
t CAS
t
RSH t
RCD
t T
t
CSH
RAS
CAS
t
ASR t
RAH t
CAH
ADDRESS
Column
Row t
ASC D IN
DQ1~DQ4
WE
t
CRP
t
CPN
t DH
t DS
t OEH
t OED
OE
t DS
OPEN
t WP
t CWL
• Read - Modify - Write Cycle
t
RWC t RAS
t RP
t
RWD
t WP
t
RAD
t
RWL t
CAS
t
CWL t
RCD
t T
t
CPN
RAS
CAS
WE
t
CRP t ASR
t
RAH
t
ASC
t
CAH
ADDRESS Column Row
DQ1~DQ4
t DH
t DS
OE
t
RCS
t
AWD t
CWD D IN
t OED
t OEH
t OEZ
t OEA t CAC t RAC
t AA
DQ1~DQ4
D OUT
OPEN
t
DZC
t
DZO
• EDO Page Mode Read Cycle
t
RASP
t
CPRH
t RCS
t
CAS
t
RSH t
RCD
t OEA
t
CSH
RAS
CAS
t
ASR
t
RAH
t
CAH
ADDRESS
t
CAS
WE
t
CRP
t CP
OE
DQ1~DQ4
OPEN
t
OEP
D OUT 1
t PC
t CP
t
CAS
t
CPN
t
CRP
t
RAD
t
CAH
t
ASC
t ASC
t
CAH
t ASC
t RAL Row Column 1t OEA
t OEHC
t
RRH t
RCH
t RAC
t AA
t AA
t AA t CPA t CPA t OEZ
t OFF
t OFF
t CAC
t OEZ
t CAC t CAC
t COH
D OUT N
WE OE Column 2Column N Row
t RP
D OUT 2
• EDO Page Mode Early Write Cycle
t
RASP
t
RP
t WCS
t CAS
t
RSH t
RCD
RAS
CAS
t
ASR
t
RAH
t
CAH
ADDRESS
t
CAS
WE
t CP
DQ1~DQ4
t PC
t CP
t CAS
t
CPN
t
CRP t
CAH t
ASC
t
ASC t
CAH t
ASC Row Column 1t DS WE Column 2Column N
t WCH t WCS t WCH t WCS t WCH
t DH t DS t DH t DS t DH
D IN 1D IN 2D IN N
t T
t
CSH
• EDO Page Mode Read-Early-Write Cycle
t RASP
t
CPRH
t RCS
t
CAS
t
RSH t
RCD
t OEA
t
CSH
RAS
CAS
t
ASR
t
RAH
t
CAH
ADDRESS
t
CAS
WE
t
CRP
t CP
OE
DQ1~DQ4
OPEN
t
WED
t PC
t CP
t
CAS
t
CPN
t
CRP
t
RAD
t
RAH
t
ASC
t ASC
t
CAH
t ASC
t RAL Row Column 1t
WCS
t
RCH
t RAC
t AA
t AA
t CPA t DH
t WHZ
t CAC
t CAC
t COH
WE OE Column 2Column N Row
t RP
t CAL t
WCH
Data
Doutput 2
Data Input N
Data
Doutput 1
t DS
t
CSH
• EDO Page Mode Read-Modify-Write Cycle
t RASP
t CPRH
t RCS
t
CAS
t WP RAS
CAS
t ASR
t
RAH
t
CAH
ADDRESS
t CAS
WE
t
RCD
CP
DQ1~DQ4
t
PRWC
t CP
t
CAS
t
CRP
t
RAD
t
CAH
t
ASC
t ASC
t
CAH t
ASC Row Column 1
t
RWL
t
RCS
t OED
t DZO
t CAC WE OE
t RP
t RAL D OUT 2
D OUT N
D OUT 1
t
T
t Column N
Column 2
Column 1t
RWD t
AWD t
CWD
t
CWL
t
RCS
t
CWD
t
AWD t
CPW t
CWL t
CPW t
AWD t
CWD
t
CWL t OED
t OED
t OEH
t OEH
t OEH
t CAC t CAC t OEA t AA
t RAC
t OEZ
t OEA
t AA t CPA
t OEZ
t OEA
t AA t CPA
t OEZ t DS
t DH
t WP t DS
t DH
t WP t DS
t DH
OPEN
OPEN
OPEN D IN 1D IN N
D IN 2DQ1~DQ4
t DZC
t DZO
t DZC
t DZC
t DZO
• Read Cycle with WE Controlled Disable
t WPZ
t RCS
t
CAS
t
RCD
t T
t
CSH
RAS
CAS
t ASR
t
RAH
t
CAH
ADDRESS
Column
Row t
ASC
D DQ1~DQ4
WE
t OEZ
t DS
t WHZ
OE
t RCH t OEA t CAC
t AA
t RAC
t CLZ
OUT
t
RAD
RAS
ADDRESS
t RC t CRP
t ASR
t RAH
t T
t RPC
ROW
t OFF
CAS t RAS
t RP
OPEN
t CRP
DQ1~DQ4
RAS
t CSR
t WSR
t RP
t T t RPC
t OFF
CAS t RAS
t RP
OPEN
t CRP
DQ1~DQ4
t RPC
t CHR
t RAS
t RP
t RC
t RC
t CHR
t CSR
t WHR
t WSR
t WHR
WE
CAS-Before-RAS Refresh Cycle
RAS
WE
t RPC
t OFF
t CSR
t CHS
t WSR
CAS
t RASS t RPS
OPEN
DQ1~DQ4
t WHR
High lmpedance
• Hidden Refresh Cycle
t RP
t RAS
RAS
t RCD
t CRP
ADDRESS
WE
t CHR
t CAS
t RSH
t RAH
t ASR
t ASC
t CAH
t RAL ROW t RCH
t OEZ
CAS
DQ1~DQ4
t T
t RCS
D t RAS
t RAS
t RP
t RP
t RC t RC
t RC
t RAD
t RRH
t OFF t OFF
t OEA t CAC
t AA
t RAC
COlumn
OUT
OE
(READ)
(REFRESH)
(REFRESH)
Ordering information
AD404M42VSA-5
• AD
• Ascend Memory Product • 40 • Device Type
• 4M4 • Density and Organization • 2
• Refresh Rate, 2: 2K Refresh • V
• T: 5V, V: 3.3V
• S • Package Type (S : SOJ, T : TSOP II)• A
• Version
• 5
• Speed (5: 50 ns, 6: 60 ns)
Part Number Access time Package
AD404M42VSA-5AD404M42VSA-6AD404M42VTA-5AD404M42VTA-6
50 ns 60 ns 50 ns 60 ns
300mil 26/24-Pin Plastic SOJ
TSOP II
Packaging information • 300 mil, 26/24-Pin Plastic SOJ
• 300 mil, 26/24-Pin TSOP II。