AT90SC25672R中文资料

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AT90SC6464C中文资料

Note:This is a summary document.A complete document is available under NDA.For more information,please contactyour local Atmel sales office.Features•Accurate Real-time Emulation of AT91SC,AT90SC and AT05SC Secure Microcontroller Products•Non-intrusive Emulation•Breakpoint Capability on any Hardware Instruction or Address •Emulation Allows Multiple Resets •Real-time Variables •Code Coverage•128-bit by 64K Deep Bus Trace •Watch Points and Breakpoints •Complex Triggering Capability •External Triggering Ability•Fast System Context Save and Retrieval •Integrated User Help•Hardware I/O Capability (USB,ISO,SPI &Contactless All Supported)•Advanced Scripting SupportNote:Not all features are available on the first release of the system.System Requirements•A PC Running Windows ®95/98/2000or Windows NT®•C-Spy ®Debugger from IAR Systems Installed (May be Obtained Directly from IARSystems)OverviewThe ATV1(Voyager),designed and manufactured by Atmel,provides a flexible emula-tion platform to support current and future Smart Card products.This platform has the intrinsic ability to support ARM ®(AT91SC),AVR ®(AT90SC)and HC05(AT05SC)based smart card products,and has been designed to be both flexible and easy to use.For maximum flexibility,the system has been designed to be upgraded easily.It has been engineered to support future device architectures.Switching to support other devices within a given core family is done simply by running a software utility that guides the user through the device update process –there is no need to change PCBs or jumper settings.For maximum usability,the system provides support for the IAR Systems C-Spy front-end.It also uses a proprietary configuration control application,which allows the developer not only to configure the hardware setup,but also to perform a variety of functions such as bus state analysis and code coverage.©Atmel Corporation 2002.Atmel Corporation makes no warranty for the use of its products,other than those expressly contained in the Com-pany’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site.The Company assumes no responsibility for any errors which may appear in this document,reserves the right to change devices or specifications detailed herein at any time without notice,and does not make any commitment to update the information contained herein.No licenses to patents or other intellectual property of Atmel are granted by the Com-pany in connection with the sale of Atmel products,expressly or by implication.Atmel’s products are not authorized for use as critical compo-nents in life support devices or systems.Corporate Headquarters,2325Orchard Parkway,San Jose,CA 95131,TEL (408)441-0311,FAX (408)487-2600Atmel Colorado Springs,1150E.Cheyenne Mtn.Blvd.,Colorado Springs,CO 80906,TEL (719)576-3300,FAX (719)540-1759Atmel Grenoble,Avenue de Rochepleine,BP 123,38521Saint-Egreve Cedex,France,TEL (33)4-7658-3000,FAX (33)4-7658-3480Atmel Heilbronn,Theresienstrasse 2,POB 3535,D-74025Heilbronn,Germany,TEL (49)7131672594,FAX (49)7131672423Atmel Nantes,La Chantrerie,BP 70602,44306Nantes Cedex 3,France,TEL (33)024*******,FAX (33)024*******Atmel Rousset,Zone Industrielle,13106Rousset Cedex,France,TEL (33)4-4253-6000,FAX (33)4-4253-6001Atmel Smart Card ICs,Scottish Enterprise Technology Park,East Kilbride,Scotland G750QR,TEL (44)1355-803-000,FAX (44)1355-242-743on recycled paper.Figure 1.The ATV1Development SystemOrdering InformationOrder the ATV1using the following Atmel product name and part number.Contact DetailsContact your local Atmel sales office to order the Voyager Emulation Platform.Contact IAR’s Regional offices and distributors at or email info@ to order C-Spy Debugger.Power Switch SCADPT5and SPI Port (ISO7816Compatible)USB PortReset SwitchStatus Indicators1553BS–SMIC–03/02ATMEL ®and AVR ®are the registered trademarks of Atmel.ARM ®is the registered trademark of ARM Ltd.;Windows ®95/98/2000and Windows NT ®are the registered trademarks of Microsoft Corporation;C-Spy ®is the registered trademark of IAR Systems AB.Other terms and product names may be the trademarks of others.This datasheet has been download from: Datasheets for electronics components.。

AT91SAM7X256中文版

• 片内高速 SRAM, 最高速度下单时钟周期存取
– 64K 字节 (AT91SAM7X256) – 32K 字节 (AT91SAM7X128)
• 内存控制器 (MC)
– 嵌入式 Flash 控制器, 中止状态和未对齐检测
• 复位控制器 (RSTC)
– 基于上电复位单元和经过工厂标定的低功耗掉电检测 – 提供外部信号整形和复位源状态
2. AT91SAM7X256 和 AT91SAM7X128 的配置比较
AT91SAM7X256 和 AT91SAM7X128 仅在存储器大小上有所差别。Table 2-1 是这两个设备的主要配置差别。
Table 2-1. 配置差别
设备 AT91SAM7X256 AT91SAM7X128
Flash 256K 字节 128K 字节
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本资料英文版本来源于互联网，将其译成中文版本以便于中国广大ARM爱好者交流、学习，请勿用于任何商业目的。
本文件为英文原本之非正式翻译，不保证翻译的真实性和准确性，同时声明文件以英文版本为准。
由于嵌入式领域我国并无统一名称规范，大部分术语均直译，另有部分术语参考了 ATMEL 公司的 AT91SAM7S64 中文资料，由于译者对嵌入式领域理解的深度有限，难免有疏漏和错误之处，也希望大家指出。
– 8 个完全可编程消息对象邮箱, 16 位时间标志计数器
• 一个同步串行控制器 (SSC)
– 每个接受器和发送器都有独立的时钟和帧同步信号 – 支持I²S 模拟接口, 支持分时复用 – 支持 32 位数据传输的高速连续数据流功能
• 两个通用同步/异步收发器 (USART)
– 独立的波特率发生器, 可以 IrDA 红外调制/解调 – 支持 ISO7816 T0/T1 智能卡, 硬件握手信号以及 RS485 – USART1 口支持全 Modem 线

L7820C中文资料

1/34November 2004s OUTPUT CURRENT TO 1.5AsOUTPUT VOLTAGES OF 5; 5.2; 6; 8; 8.5; 9; 10; 12; 15; 18; 24Vs THERMAL OVERLOAD PROTECTION s SHORT CIRCUIT PROTECTIONsOUTPUT TRANSITION SOA PROTECTIONDESCRIPTIONThe L7800 series of three-terminal positive regulators is available in TO-220, TO-220FP,TO-220FM, TO-3 and D 2PAK packages and several fixed output voltages, making it useful in a wide range of applications. These regulators can provide local on-card regulation, eliminating the distribution problems associated with single point regulation. Each type employs internal current limiting, thermal shut-down and safe area protection, making it essentially indestructible. If adequate heat sinking is provided, they can deliver over 1A output current. Although designed primarily as fixed voltage regulators, these devices can be used with external components to obtain adjustable voltage and currents.L7800SERIESPOSITIVE VOLTAGE REGULATORSL7800 SERIESTable 1: Absolute Maximum RatingsAbsolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied.Table 2: Thermal DataFigure 2: Schematic DiagramSymbol ParameterValue Unit V I DC Input Voltage for V O = 5 to 18V 35Vfor V O = 20, 24V40I O Output Current Internally Limited P tot Power DissipationInternally LimitedT stg Storage Temperature Range-65 to 150°C T opOperating Junction Temperature Range for L7800-55 to 150°C for L7800C0 to 150SymbolParameterD 2PAK TO-220TO-220FP TO-220FMTO-3Unit R thj-case Thermal Resistance Junction-case Max 35554°C/W R thj-ambThermal Resistance Junction-ambient Max62.550606035°C/WL7800 SERIES3/34Figure 3: Connection Diagram (top view)Table 3: Order Codes(*) Available in Tape & Reel with the suffix "-TR".TYPE TO-220(A Type)TO-220(C Type)TO-220(E Type)D 2PAK (A Type) (*)D 2PAK (C Type)(T & R)TO-220FPTO-220FMTO-3L7805L7805T L7805C L7805CV L7805C-V L7805CV1L7805CD2T L7805C-D2TRL7805CP L7805CF L7805CT L7852C L7852CV L7852CD2T L7852CP L7852CF L7852CT L7806L7806T L7806C L7806CV L7806C-V L7806CD2T L7806CP L7806CF L7806CT L7808L7808T L7808C L7808CV L7808C-V L7808CD2T L7808CP L7808CF L7808CT L7885C L7885CV L7885CD2T L7885CP L7885CF L7885CT L7809C L7809CV L7809C-VL7809CD2T L7809CP L7809CFL7809CT L7810C L7810CV L7810CD2T L7810CP L7812L7812T L7812C L7812CV L7812C-V L7812CD2T L7812CP L7812CF L7812CT L7815L7815T L7815C L7815CV L7815C-VL7815CD2T L7815CP L7815CF L7815CT L7818L7818T L7818C L7818CV L7818CD2T L7818CP L7818CF L7818CT L7820L7820T L7820C L7820CV L7820CD2T L7820CP L7820CF L7820CT L7824L7824T L7824CL7824CVL7824CD2TL7824CPL7824CFL7824CTL7800 SERIESFigure 4: Application CircuitsTEST CIRCUITSFigure 5: DC ParameterFigure 6: Load Regulation4/34L7800 SERIES5/34Figure 7: Ripple RejectionTable 4: Electrical Characteristics Of L7805 (refer to the test circuits, T J = -55 to 150°C, V I = 10V,I O = 500 mA, C I = 0.33 µF, C O = 0.1 µF unless otherwise specified).(*) Load and line regulation are specified at constant junction temperature. Changes in V O due to heating effects must be taken into account separately. Pulse testing with low duty cycle is used.Symbol ParameterTest ConditionsMin.Typ.Max.Unit V O Output Voltage T J = 25°C 4.85 5.2V V O Output Voltage I O = 5 mA to 1 A P O ≤ 15WV I = 8 to 20 V 4.655 5.35V ∆V O (*)Line Regulation V I = 7 to 25 V T J = 25°C 350mVV I = 8 to 12 V T J = 25°C 125∆V O (*)Load Regulation I O = 5 mA to 1.5 A T J = 25°C 100mV I O = 250 to 750 mA T J = 25°C25I d Quiescent Current T J = 25°C 6mA ∆I dQuiescent Current ChangeI O = 5 mA to 1 A 0.5mA V I = 8 to 25 V0.8∆V O /∆T Output Voltage Drift I O = 5 mA0.6mV/°C eN Output Noise Voltage B =10Hz to 100KHz T J = 25°C40µV/V O SVR Supply Voltage Rejection V I = 8 to 18 V f = 120Hz68dB V d Dropout Voltage I O = 1 A T J = 25°C2 2.5V R O Output Resistance f = 1 KHz 17m ΩI sc Short Circuit Current V I = 35 V T J = 25°C0.75 1.2A I scpShort Circuit Peak CurrentT J = 25°C1.32.23.3AL7800 SERIES6/34Table 5: Electrical Characteristics Of L7806 (refer to the test circuits, T J = -55 to 150°C, V I = 11V,I O = 500 mA, C I = 0.33 µF, C O = 0.1 µF unless otherwise specified).(*) Load and line regulation are specified at constant junction temperature. Changes in V O due to heating effects must be taken into account separately. Pulse testing with low duty cycle is used.Table 6: Electrical Characteristics Of L7808 (refer to the test circuits, T J = -55 to 150°C, V I = 14V,I O = 500 mA, C I = 0.33 µF, C O = 0.1 µF unless otherwise specified).(*) Load and line regulation are specified at constant junction temperature. Changes in V O due to heating effects must be taken into account separately. Pulse testing with low duty cycle is used.Symbol ParameterTest ConditionsMin.Typ.Max.Unit V O Output Voltage T J = 25°C 5.756 6.25V V O Output Voltage I O = 5 mA to 1 A P O ≤ 15WV I = 9 to 21 V 5.6566.35V ∆V O (*)Line Regulation V I = 8 to 25 V T J = 25°C 60mVV I = 9 to 13 V T J = 25°C 30∆V O (*)Load Regulation I O = 5 mA to 1.5 A T J = 25°C 100mV I O = 250 to 750 mA T J = 25°C30I d Quiescent Current T J = 25°C 6mA ∆I dQuiescent Current ChangeI O = 5 mA to 1 A 0.5mA V I = 9 to 25 V0.8∆V O /∆T Output Voltage Drift I O = 5 mA0.7mV/°C eN Output Noise Voltage B =10Hz to 100KHz T J = 25°C40µV/V O SVR Supply Voltage Rejection V I = 9 to 19 V f = 120Hz65dB V d Dropout Voltage I O = 1 A T J = 25°C2 2.5V R O Output Resistance f = 1 KHz 19m ΩI sc Short Circuit Current V I = 35 V T J = 25°C0.75 1.2A I scpShort Circuit Peak CurrentT J = 25°C1.32.23.3A Symbol ParameterTest ConditionsMin.Typ.Max.Unit V O Output Voltage T J = 25°C 7.788.3V V O Output Voltage I O = 5 mA to 1 A P O ≤ 15WV I = 11.5 to 23 V 7.688.4V ∆V O (*)Line Regulation V I = 10.5 to 25 V T J = 25°C 80mVV I = 11 to 17 V T J = 25°C 40∆V O (*)Load Regulation I O = 5 mA to 1.5 A T J = 25°C 100mV I O = 250 to 750 mA T J = 25°C40I d Quiescent Current T J = 25°C 6mA ∆I dQuiescent Current ChangeI O = 5 mA to 1 A 0.5mA V I = 11.5 to 25 V0.8∆V O /∆T Output Voltage Drift I O = 5 mA1mV/°C eN Output Noise Voltage B =10Hz to 100KHz T J = 25°C 40µV/V O SVR Supply Voltage Rejection V I = 11.5 to 21.5 V f = 120Hz62dB V d Dropout Voltage I O = 1 A T J = 25°C2 2.5V R O Output Resistance f = 1 KHz 16m ΩI sc Short Circuit Current V I = 35 V T J = 25°C0.75 1.2A I scpShort Circuit Peak CurrentT J = 25°C1.32.23.3AL7800 SERIES7/34Table 7: Electrical Characteristics Of L7812 (refer to the test circuits, T J = -55 to 150°C, V I = 19V,I O = 500 mA, C I = 0.33 µF, C O = 0.1 µF unless otherwise specified).(*) Load and line regulation are specified at constant junction temperature. Changes in V O due to heating effects must be taken into account separately. Pulse testing with low duty cycle is used.Table 8: Electrical Characteristics Of L7815 (refer to the test circuits, T J = -55 to 150°C, V I = 23V,I O = 500 mA, C I = 0.33 µF, C O = 0.1 µF unless otherwise specified).(*) Load and line regulation are specified at constant junction temperature. Changes in V O due to heating effects must be taken into account separately. Pulse testing with low duty cycle is used.Symbol ParameterTest ConditionsMin.Typ.Max.Unit V O Output Voltage T J = 25°C 11.51212.5V V O Output Voltage I O = 5 mA to 1 A P O ≤ 15WV I = 15.5 to 27 V 11.41212.6V ∆V O (*)Line Regulation V I = 14.5 to 30 V T J = 25°C 120mVV I = 16 to 22 V T J = 25°C 60∆V O (*)Load Regulation I O = 5 mA to 1.5 A T J = 25°C 100mV I O = 250 to 750 mA T J = 25°C60I d Quiescent Current T J = 25°C 6mA ∆I dQuiescent Current ChangeI O = 5 mA to 1 A 0.5mA V I = 15 to 30 V0.8∆V O /∆T Output Voltage Drift I O = 5 mA1.5mV/°C eN Output Noise Voltage B =10Hz to 100KHz T J = 25°C 40µV/V O SVR Supply Voltage Rejection V I = 15 to 25 V f = 120Hz61dB V d Dropout Voltage I O = 1 A T J = 25°C2 2.5V R O Output Resistance f = 1 KHz 18m ΩI sc Short Circuit Current V I = 35 V T J = 25°C0.75 1.2A I scpShort Circuit Peak CurrentT J = 25°C1.32.23.3A Symbol ParameterTest ConditionsMin.Typ.Max.Unit V O Output Voltage T J = 25°C 14.41515.6V V O Output Voltage I O = 5 mA to 1 A P O ≤ 15WV I = 18.5 to 30 V 14.251515.75V ∆V O (*)Line Regulation V I = 17.5 to 30 V T J = 25°C 150mVV I = 20 to 26 V T J = 25°C 75∆V O (*)Load Regulation I O = 5 mA to 1.5 A T J = 25°C 150mV I O = 250 to 750 mA T J = 25°C75I d Quiescent Current T J = 25°C 6mA ∆I dQuiescent Current ChangeI O = 5 mA to 1 A 0.5mA V I = 18.5 to 30 V0.8∆V O /∆T Output Voltage Drift I O = 5 mA1.8mV/°C eN Output Noise Voltage B =10Hz to 100KHz T J = 25°C 40µV/V O SVR Supply Voltage Rejection V I = 18.5 to 28.5 V f = 120Hz60dB V d Dropout Voltage I O = 1 A T J = 25°C2 2.5V R O Output Resistance f = 1 KHz 19m ΩI sc Short Circuit Current V I = 35 V T J = 25°C0.75 1.2A I scpShort Circuit Peak CurrentT J = 25°C1.32.23.3AL7800 SERIES8/34Table 9: Electrical Characteristics Of L7818 (refer to the test circuits, T J = -55 to 150°C, V I = 26V,I O = 500 mA, C I = 0.33 µF, C O = 0.1 µF unless otherwise specified).(*) Load and line regulation are specified at constant junction temperature. Changes in V O due to heating effects must be taken into account separately. Pulse testing with low duty cycle is used.Table 10: Electrical Characteristics Of L7820 (refer to the test circuits, T J = -55 to 150°C, V I = 28V,I O = 500 mA, C I = 0.33 µF, C O = 0.1 µF unless otherwise specified).(*) Load and line regulation are specified at constant junction temperature. Changes in V O due to heating effects must be taken into account separately. Pulse testing with low duty cycle is used.Symbol ParameterTest ConditionsMin.Typ.Max.Unit V O Output Voltage T J = 25°C 17.31818.7V V O Output Voltage I O = 5 mA to 1 A P O ≤ 15WV I = 22 to 33 V 17.11818.9V ∆V O (*)Line Regulation V I = 21 to 33 V T J = 25°C 180mVV I = 24 to 30 V T J = 25°C 90∆V O (*)Load Regulation I O = 5 mA to 1.5 A T J = 25°C 180mV I O = 250 to 750 mA T J = 25°C90I d Quiescent Current T J = 25°C 6mA ∆I dQuiescent Current ChangeI O = 5 mA to 1 A 0.5mA V I = 22 to 33 V0.8∆V O /∆T Output Voltage Drift I O = 5 mA2.3mV/°C eN Output Noise Voltage B =10Hz to 100KHz T J = 25°C 40µV/V O SVR Supply Voltage Rejection V I = 22 to 32 V f = 120Hz59dB V d Dropout Voltage I O = 1 A T J = 25°C2 2.5V R O Output Resistance f = 1 KHz 22m ΩI sc Short Circuit Current V I = 35 V T J = 25°C0.75 1.2A I scpShort Circuit Peak CurrentT J = 25°C1.32.23.3A Symbol ParameterTest ConditionsMin.Typ.Max.Unit V O Output Voltage T J = 25°C 19.22020.8V V O Output Voltage I O = 5 mA to 1 A P O ≤ 15WV I = 24 to 35 V 192021V ∆V O (*)Line Regulation V I = 22.5 to 35 V T J = 25°C 200mVV I = 26 to 32 V T J = 25°C 100∆V O (*)Load Regulation I O = 5 mA to 1.5 A T J = 25°C 200mV I O = 250 to 750 mA T J = 25°C100I d Quiescent Current T J = 25°C 6mA ∆I dQuiescent Current ChangeI O = 5 mA to 1 A 0.5mA V I = 24 to 35 V0.8∆V O /∆T Output Voltage Drift I O = 5 mA2.5mV/°C eN Output Noise Voltage B =10Hz to 100KHz T J = 25°C 40µV/V O SVR Supply Voltage Rejection V I = 24 to 35 V f = 120Hz58dB V d Dropout Voltage I O = 1 A T J = 25°C2 2.5V R O Output Resistance f = 1 KHz 24m ΩI sc Short Circuit Current V I = 35 V T J = 25°C0.75 1.2A I scpShort Circuit Peak CurrentT J = 25°C1.32.23.3AL7800 SERIES9/34Table 11: Electrical Characteristics Of L7824 (refer to the test circuits, T J = -55 to 150°C, V I = 33V,I O = 500 mA, C I = 0.33 µF, C O = 0.1 µF unless otherwise specified).(*) Load and line regulation are specified at constant junction temperature. Changes in V O due to heating effects must be taken into account separately. Pulse testing with low duty cycle is used.Table 12: Electrical Characteristics Of L7805C (refer to the test circuits, T J = 0 to 125°C, V I = 10V,I O = 500 mA, C I = 0.33 µF, C O = 0.1 µF unless otherwise specified).(*) Load and line regulation are specified at constant junction temperature. Changes in V O due to heating effects must be taken into account separately. Pulse testing with low duty cycle is used.Symbol ParameterTest ConditionsMin.Typ.Max.Unit V O Output Voltage T J =25°C 232425V V O Output Voltage I O = 5 mA to 1 A P O ≤ 15WV I = 28 to 38 V 22.82425.2V ∆V O (*)Line Regulation V I = 27 to 38 V T J = 25°C 240mVV I = 30 to 36 V T J = 25°C 120∆V O (*)Load Regulation I O = 5 mA to 1.5 A T J = 25°C 240mV I O = 250 to 750 mA T J = 25°C120I d Quiescent Current T J = 25°C 6mA ∆I dQuiescent Current ChangeI O = 5 mA to 1 A 0.5mA V I = 28 to 38 V0.8∆V O /∆T Output Voltage Drift I O = 5 mA3mV/°C eN Output Noise Voltage B =10Hz to 100KHz T J = 25°C 40µV/V O SVR Supply Voltage Rejection V I = 28 to 38 V f = 120Hz56dB V d Dropout Voltage I O = 1 A T J = 25°C2 2.5V R O Output Resistance f = 1 KHz 28m ΩI sc Short Circuit Current V I = 35 V T J = 25°C0.75 1.2A I scpShort Circuit Peak CurrentT J = 25°C1.32.23.3A Symbol ParameterTest ConditionsMin.Typ.Max.Unit V O Output Voltage T J = 25°C 4.85 5.2V V O Output Voltage I O = 5 mA to 1 A P O ≤ 15WV I = 7 to 20 V 4.755 5.25V ∆V O (*)Line Regulation V I = 7 to 25 V T J = 25°C 3100mVV I = 8 to 12 VT J = 25°C 150∆V O (*)Load Regulation I O = 5 mA to 1.5 A T J = 25°C 100mV I O = 250 to 750 mA T J = 25°C50I d Quiescent Current T J = 25°C 8mA ∆I dQuiescent Current ChangeI O = 5 mA to 1 A 0.5mA V I = 7 to 25 V0.8∆V O /∆T Output Voltage Drift I O = 5 mA-1.1mV/°C eN Output Noise Voltage B =10Hz to 100KHz T J = 25°C40µV/V O SVR Supply Voltage Rejection V I = 8 to 18 V f = 120Hz62dB V d Dropout Voltage I O = 1 A T J = 25°C2V R O Output Resistance f = 1 KHz 17m ΩI sc Short Circuit Current V I = 35 V T J = 25°C 0.75A I scpShort Circuit Peak CurrentT J = 25°C2.2AL7800 SERIES10/34Table 13: Electrical Characteristics Of L7852C (refer to the test circuits, T J = 0 to 125°C, V I = 10V,I O = 500 mA, C I = 0.33 µF, C O = 0.1 µF unless otherwise specified).(*) Load and line regulation are specified at constant junction temperature. Changes in V O due to heating effects must be taken into account separately. Pulse testing with low duty cycle is used.Table 14: Electrical Characteristics Of L7806C (refer to the test circuits, T J = 0 to 125°C, V I = 11V,I O = 500 mA, C I = 0.33 µF, C O = 0.1 µF unless otherwise specified).(*) Load and line regulation are specified at constant junction temperature. Changes in V O due to heating effects must be taken into account separately. Pulse testing with low duty cycle is used.Symbol ParameterTest ConditionsMin.Typ.Max.Unit V O Output Voltage T J = 25°C 5.0 5.2 5.4V V O Output Voltage I O = 5 mA to 1 A P O ≤ 15WV I = 8 to 20 V 4.955.2 5.45V ∆V O (*)Line Regulation V I = 7 to 25 V T J = 25°C 3105mVV I = 8 to 12 V T J = 25°C 152∆V O (*)Load Regulation I O = 5 mA to 1.5 A T J = 25°C 105mV I O = 250 to 750 mA T J = 25°C52I d Quiescent Current T J = 25°C 8mA ∆I dQuiescent Current ChangeI O = 5 mA to 1 A 0.5mA V I = 7 to 25 V1.3∆V O /∆T Output Voltage Drift I O = 5 mA-1mV/°C eN Output Noise Voltage B =10Hz to 100KHz T J = 25°C42µV/V O SVR Supply Voltage Rejection V I = 8 to 18 V f = 120Hz61dB V d Dropout Voltage I O = 1 A T J = 25°C2V R O Output Resistance f = 1 KHz 17m ΩI sc Short Circuit Current V I = 35 V T J = 25°C 0.75A I scpShort Circuit Peak CurrentT J = 25°C2.2A Symbol ParameterTest ConditionsMin.Typ.Max.Unit V O Output Voltage T J = 25°C 5.756 6.25V V O Output Voltage I O = 5 mA to 1 A P O ≤ 15WV I = 8 to 21 V 5.766.3V ∆V O (*)Line Regulation V I = 8 to 25 V T J = 25°C 120mVV I = 9 to 13 V T J = 25°C 60∆V O (*)Load Regulation I O = 5 mA to 1.5 A T J = 25°C 120mV I O = 250 to 750 mA T J = 25°C60I d Quiescent Current T J = 25°C 8mA ∆I dQuiescent Current ChangeI O = 5 mA to 1 A 0.5mA V I = 8 to 25 V1.3∆V O /∆T Output Voltage Drift I O = 5 mA-0.8mV/°C eN Output Noise Voltage B =10Hz to 100KHz T J = 25°C45µV/V O SVR Supply Voltage Rejection V I = 9 to 19 V f = 120Hz59dB V d Dropout Voltage I O = 1 A T J = 25°C2V R O Output Resistance f = 1 KHz 19m ΩI sc Short Circuit Current V I = 35 V T J = 25°C 0.55A I scpShort Circuit Peak CurrentT J = 25°C2.2A(*) Load and line regulation are specified at constant junction temperature. Changes in V O due to heating effects must be taken into account separately. Pulse testing with low duty cycle is used.Table 16: Electrical Characteristics Of L7885C (refer to the test circuits, T J = 0 to 125°C, V I = 14.5V,I O = 500 mA, C I = 0.33 µF, C O = 0.1 µF unless otherwise specified).(*) Load and line regulation are specified at constant junction temperature. Changes in V O due to heating effects must be taken into account separately. Pulse testing with low duty cycle is used.Symbol ParameterTest ConditionsMin.Typ.Max.Unit V O Output Voltage T J = 25°C 7.788.3V V O Output Voltage I O = 5 mA to 1 A P O ≤ 15WV I = 10.5 to 25 V 7.688.4V ∆V O (*)Line Regulation V I = 10.5 to 25 V T J = 25°C 160mVV I = 11 to 17 V T J = 25°C 80∆V O (*)Load Regulation I O = 5 mA to 1.5 A T J = 25°C 160mV I O = 250 to 750 mA T J = 25°C80I d Quiescent Current T J = 25°C 8mA ∆I dQuiescent Current ChangeI O = 5 mA to 1 A 0.5mA V I = 10.5 to 25 V1∆V O /∆T Output Voltage Drift I O = 5 mA-0.8mV/°C eN Output Noise Voltage B =10Hz to 100KHz T J = 25°C 52µV/V O SVR Supply Voltage Rejection V I = 11.5 to 21.5 V f = 120Hz56dB V d Dropout Voltage I O = 1 A T J = 25°C2V R O Output Resistance f = 1 KHz 16m ΩI sc Short Circuit Current V I = 35 V T J = 25°C 0.45A I scpShort Circuit Peak CurrentT J = 25°C2.2A Symbol ParameterTest ConditionsMin.Typ.Max.Unit V O Output Voltage T J = 25°C 8.28.58.8V V O Output Voltage I O = 5 mA to 1 A P O ≤ 15WV I = 11 to 26 V 8.18.58.9V ∆V O (*)Line Regulation V I = 11 to 27 V T J = 25°C 160mVV I = 11.5 to 17.5 V T J = 25°C 80∆V O (*)Load Regulation I O = 5 mA to 1.5 A T J = 25°C 160mV I O = 250 to 750 mA T J = 25°C80I d Quiescent Current T J = 25°C 8mA ∆I dQuiescent Current ChangeI O = 5 mA to 1 A 0.5mA V I = 11 to 27 V1∆V O /∆T Output Voltage Drift I O = 5 mA-0.8mV/°C eN Output Noise Voltage B =10Hz to 100KHz T J = 25°C 55µV/V O SVR Supply Voltage Rejection V I = 12 to 22 V f = 120Hz56dB V d Dropout Voltage I O = 1 A T J = 25°C2V R O Output Resistance f = 1 KHz 16m ΩI sc Short Circuit Current V I = 35 V T J = 25°C 0.45A I scpShort Circuit Peak CurrentT J = 25°C2.2A(*) Load and line regulation are specified at constant junction temperature. Changes in V O due to heating effects must be taken into account separately. Pulse testing with low duty cycle is used.Table 18: Electrical Characteristics Of L7810C (refer to the test circuits, T J = 0 to 125°C, V I = 16V,I O = 500 mA, C I = 0.33 µF, C O = 0.1 µF unless otherwise specified).(*) Load and line regulation are specified at constant junction temperature. Changes in V O due to heating effects must be taken into account separately. Pulse testing with low duty cycle is used.Symbol ParameterTest ConditionsMin.Typ.Max.Unit V O Output Voltage T J = 25°C 8.6499.36V V O Output Voltage I O = 5 mA to 1 A P O ≤ 15WV I = 11.5 to 26 V 8.5599.45V ∆V O (*)Line Regulation V I = 11.5 to 26 V T J = 25°C 180mVV I = 12 to 18 V T J = 25°C 90∆V O (*)Load Regulation I O = 5 mA to 1.5 A T J = 25°C 180mV I O = 250 to 750 mA T J = 25°C90I d Quiescent Current T J = 25°C 8mA ∆I dQuiescent Current ChangeI O = 5 mA to 1 A 0.5mA V I = 11.5 to 26 V1∆V O /∆T Output Voltage Drift I O = 5 mA-1mV/°C eN Output Noise Voltage B =10Hz to 100KHz T J = 25°C 70µV/V O SVR Supply Voltage Rejection V I = 12 to 23 V f = 120Hz55dB V d Dropout Voltage I O = 1 A T J = 25°C2V R O Output Resistance f = 1 KHz 17m ΩI sc Short Circuit Current V I = 35 V T J = 25°C 0.40A I scpShort Circuit Peak CurrentT J = 25°C2.2A Symbol ParameterTest ConditionsMin.Typ.Max.Unit V O Output Voltage T J = 25°C 9.61010.4V V O Output Voltage I O = 5 mA to 1 A P O ≤ 15WV I = 12.5 to 26 V 9.51010.5V ∆V O (*)Line Regulation V I = 12.5 to 26 V T J = 25°C 200mVV I = 13.5 to 19 V T J = 25°C 100∆V O (*)Load Regulation I O = 5 mA to 1.5 A T J = 25°C 200mV I O = 250 to 750 mA T J = 25°C100I d Quiescent Current T J = 25°C 8mA ∆I dQuiescent Current ChangeI O = 5 mA to 1 A 0.5mA V I = 12.5 to 26 V1∆V O /∆T Output Voltage Drift I O = 5 mA-1mV/°C eN Output Noise Voltage B =10Hz to 100KHz T J = 25°C 70µV/V O SVR Supply Voltage Rejection V I = 13 to 23 V f = 120Hz55dB V d Dropout Voltage I O = 1 A T J = 25°C2V R O Output Resistance f = 1 KHz 17m ΩI sc Short Circuit Current V I = 35 V T J = 25°C 0.40A I scpShort Circuit Peak CurrentT J = 25°C2.2A(*) Load and line regulation are specified at constant junction temperature. Changes in V O due to heating effects must be taken into account separately. Pulse testing with low duty cycle is used.Table 20: Electrical Characteristics Of L7815C (refer to the test circuits, T J = 0 to 125°C, V I = 23V,I O = 500 mA, C I = 0.33 µF, C O = 0.1 µF unless otherwise specified).(*) Load and line regulation are specified at constant junction temperature. Changes in V O due to heating effects must be taken into account separately. Pulse testing with low duty cycle is used.Symbol ParameterTest ConditionsMin.Typ.Max.Unit V O Output Voltage T J = 25°C 11.51212.5V V O Output Voltage I O = 5 mA to 1 A P O ≤ 15WV I = 14.5 to 27 V 11.41212.6V ∆V O (*)Line Regulation V I = 14.5 to 30 V T J = 25°C 240mVV I = 16 to 22 V T J = 25°C 120∆V O (*)Load Regulation I O = 5 mA to 1.5 A T J = 25°C 240mV I O = 250 to 750 mA T J = 25°C120I d Quiescent Current T J = 25°C 8mA ∆I dQuiescent Current ChangeI O = 5 mA to 1 A 0.5mA V I = 14.5 to 30 V1∆V O /∆T Output Voltage Drift I O = 5 mA-1mV/°C eN Output Noise Voltage B =10Hz to 100KHz T J = 25°C 75µV/V O SVR Supply Voltage Rejection V I = 15 to 25 V f = 120Hz55dB V d Dropout Voltage I O = 1 A T J = 25°C2V R O Output Resistance f = 1 KHz 18m ΩI sc Short Circuit Current V I = 35 V T J = 25°C 0.35A I scpShort Circuit Peak CurrentT J = 25°C2.2A Symbol ParameterTest ConditionsMin.Typ.Max.Unit V O Output Voltage T J = 25°C 14.51515.6V V O Output Voltage I O = 5 mA to 1 A P O ≤ 15WV I = 17.5 to 30 V 14.251515.75V ∆V O (*)Line Regulation V I = 17.5 to 30 V T J = 25°C 300mVV I = 20 to 26 V T J = 25°C 150∆V O (*)Load Regulation I O = 5 mA to 1.5 A T J = 25°C 300mV I O = 250 to 750 mA T J = 25°C150I d Quiescent Current T J = 25°C 8mA ∆I dQuiescent Current ChangeI O = 5 mA to 1 A 0.5mA V I = 17.5 to 30 V1∆V O /∆T Output Voltage Drift I O = 5 mA-1mV/°C eN Output Noise Voltage B =10Hz to 100KHz T J = 25°C 90µV/V O SVR Supply Voltage Rejection V I = 18.5 to 28.5 V f = 120Hz54dB V d Dropout Voltage I O = 1 A T J = 25°C2V R O Output Resistance f = 1 KHz 19m ΩI sc Short Circuit Current V I = 35 V T J = 25°C 0.23A I scpShort Circuit Peak CurrentT J = 25°C2.2A(*) Load and line regulation are specified at constant junction temperature. Changes in V O due to heating effects must be taken into account separately. Pulse testing with low duty cycle is used.Table 22: Electrical Characteristics Of L7820C (refer to the test circuits, T J = 0 to 125°C, V I = 28V,I O = 500 mA, C I = 0.33 µF, C O = 0.1 µF unless otherwise specified).(*) Load and line regulation are specified at constant junction temperature. Changes in V O due to heating effects must be taken into account separately. Pulse testing with low duty cycle is used.Symbol ParameterTest ConditionsMin.Typ.Max.Unit V O Output Voltage T J = 25°C 17.31818.7V V O Output Voltage I O = 5 mA to 1 A P O ≤ 15WV I = 21 to 33 V 17.11818.9V ∆V O (*)Line Regulation V I = 21 to 33 V T J = 25°C 360mVV I = 24 to 30 V T J = 25°C 180∆V O (*)Load Regulation I O = 5 mA to 1.5 A T J = 25°C 360mV I O = 250 to 750 mA T J = 25°C180I d Quiescent Current T J = 25°C 8mA ∆I dQuiescent Current ChangeI O = 5 mA to 1 A 0.5mA V I = 21 to 33 V1∆V O /∆T Output Voltage Drift I O = 5 mA-1mV/°C eN Output Noise Voltage B =10Hz to 100KHz T J = 25°C 110µV/V O SVR Supply Voltage Rejection V I = 22 to 32 V f = 120Hz53dB V d Dropout Voltage I O = 1 A T J = 25°C2V R O Output Resistance f = 1 KHz 22m ΩI sc Short Circuit Current V I = 35 V T J = 25°C 0.20A I scpShort Circuit Peak CurrentT J = 25°C2.1A Symbol ParameterTest ConditionsMin.Typ.Max.Unit V O Output Voltage T J = 25°C 19.22020.8V V O Output Voltage I O = 5 mA to 1 A P O ≤ 15WV I = 23 to 35 V 192021V ∆V O (*)Line Regulation V I = 22.5 to 35 V T J = 25°C 400mVV I = 26 to 32 V T J = 25°C 200∆V O (*)Load Regulation I O = 5 mA to 1.5 A T J = 25°C 400mV I O = 250 to 750 mA T J = 25°C200I d Quiescent Current T J = 25°C 8mA ∆I dQuiescent Current ChangeI O = 5 mA to 1 A 0.5mA V I = 23 to 35 V1∆V O /∆T Output Voltage Drift I O = 5 mA-1mV/°C eN Output Noise Voltage B =10Hz to 100KHz T J = 25°C 150µV/V O SVR Supply Voltage Rejection V I = 24 to 35 V f = 120Hz52dB V d Dropout Voltage I O = 1 A T J = 25°C2V R O Output Resistance f = 1 KHz 24m ΩI sc Short Circuit Current V I = 35 V T J = 25°C 0.18A I scpShort Circuit Peak CurrentT J = 25°C2.1A。

AT90SC资料

1Features•High-performance, Low-power 8-bit AVR ® RISC Architecture –120 Powerful Instructions–Most Single Clock Cycle Execution •Up to 64K Bytes Flash Program Memory –Endurance: 10K Write/Erase Cycles •Up to 64K Bytes EEPROM User Memory –Endurance: 250K Write/Erase Cycles •Up to 2.5K Bytes RAM •Cryptoprocessor–Pre-programmed Functions for Cryptography and Authentication •Supervisor Mode (Memory Management)•One or Two ISO 7816 I/O Ports •Random Number Generator •One or Two 16-bit Timers•2-level, 6-vector Interrupt Controller •Security Features–Power-down Protection–Low-frequency and High-frequency Protection –Logical Scrambling on Program Code •Low-power Idle and Power-down Modes •Bond Pad Locations Conform to ISO 7816•V CC : 3.0V ± 10%, 5.0V ± 10%DescriptionThe AT90SC series is a low-power, high-performance, 8-bit microcontroller with Flash program memory and EEPROM data memory, based on the AVR RISC architecture.By executing powerful instructions in a single clock cycle, the AT90SC achieves throughputs close to 1 MIPS per MHz. Its Harvard architecture includes 32 general-purpose working registers directly connected to the ALU, allowing two independent registers to be accessed in one single instruction executed in one clock cycle.Some products in the AT90SC family feature a cryptoprocessor: a 16-bit crypto engine dedicated to performing fast encryption or authentication functions (see table below). Additional security features include power and frequency protection logic, log-ical scrambling on program data and addresses, and memory accesses controlled by a supervisor mode.The AT90SC family provides up to 128K bytes of Atmel ’s high-density, nonvolatile memory technology. The on-chip downloadable Flash allows the program memory to be reprogrammed in-system. This technology combined with the versatile 8-bit CPU on a monolithic chip provides a highly flexible and cost-effective solution to many smart card applications. Table 1. The AT90SC FamilyDevice Program Memory Flash BytesUser Memory EEPROM BytesRAM BytesCrypto-processorI/O Ports A T90SC1616C 16K 16K 1K Y es 2A T90SC323232K 32K 1.5K No 1A T90SC3232C 32K 32K 1K Y es 1A T90SC6464C64K64K2.5KY es2AT90SC2Block DiagramNote: 1.Only available on products featuring a cryptoprocessor.2.Only available on products not featuring a cryptoprocessor.3.Currently available only on A T90SC1616C and A T90SC6464C.Pin DescriptionVCCSupply voltage.GND Ground.RSTReset input. A low level on this pin for two clock cycles while the AT90SC is running resets the device.This pin includes an internal pull-up resistor.CLKClock input to internal clock operating circuit.This pin includes an internal pull-up resistor.IN/OUTOn products with a single IN/OUT pin, IN/OUT is a single bit open drain bi-directional I/O port. This bi-directional pin includes a pull-up resistor.Products with a second I/O port can be configured as open drain with pull-up or as a true CMOS I/O port.AT90SC38-bit AVR RISC Microcontroller CPUThe AVR uses a Harvard architecture concept with sepa-rate memories and buses for program and data. The program memory is accessed with a two stage pipeline.While one instruction is being executed, the next instruction is prefetched from the program memory. This concept enables instructions to be executed in every clock cycle.The fast-access register file concept contains 32 x 8 gen-eral purpose working registers with a single clock cycle access time. This means that during one single clock cycle,one ALU operation is executed. Two operands are output from the register file, the operation is executed, and the result is stored back in the register file in one clock cycle.The timer and other I/O functions are located in the I/O memory space. The 64 addresses of the I/O memory space can be accessed directly as I/O registers or as memory space.Memory OrganizationThe AT90SC microcontrollers have the following memory organization as shown in Figures 1 and 2.Program memory:•16-bit addressable EEPROM user memory •16-bit addressable Flash program memory Data memory:•8-bit addressable EEPROM user memory •8-bit addressable SRAM shared between AVR and crypto engine •8-bit registers addressable as data memoryThe EEPROM is shared between program memory and data memory depending on the mode. The portion of EEPROM dedicated to each function is flexible and varies according to the application.Program memory is read-only in normal operation mode.Both Flash and EEPROM memory locations are directly addressable. The EEPROM memory locations follow the Flash memory in the program address space.Program MemoryThe AT90SC microcontroller has separate address spaces for program memory and data memory. Up to 64K bytes of Flash program memory are available. Figure 1 shows the program memory.Data MemoryThe AT90SC can directly address up to 64K bytes of data memory. The LOAD and STORE instructions access the whole data memory.The AT90SC family also features 96 bytes of register and I/O space and up to 2.5K bytes of SRAM.The I/O space of the RAM can be accessed by direct addressing.The 128-byte last page of the EEPROM user memory is an OTP memory (64 bytes) and bit addressable memory (64bytes).Figure 1. The AT90SC Program MemoryFigure 2. The AT90SC Data Memory元器件交易网AT90SC4Flash Program Memory•Page size of 128 bytes•Minimum endurance of 10K write/erase cycles •Data retention for a minimum of 40 yearsThe AT90SC contains up to 64K bytes of downloadable Flash memory for program storage. Since all instructions are 16-bit words, the Flash is organized as 32K x 16. The Flash memory is read-only except during the program download mode. This mode is selected by setting a bit in the memory control I/O register.Once the Flash memory is loaded, a security feature dis-ables the download function, making the writing of the Flash impossible.EEPROM User Memory•Erasure and Writing:- Byte-by-byte - Bit mode- Page mode (128 bytes per page)•Minimum endurance of 250K write/erase cycles •Data retention for a minimum of 40 yearsThe user memory is organized as up to 32K x 16. A write mode bit in the memory control register selects byte by byte or page mode. During the write cycle, a bit is set in the memory control register, disabling pending write opera-tions. When the write cycle is finished, this bit is cleared and an interrupt request is generated.In addition, the AT90SC features a pseudo bit mode which allows individual bits to be overwritten (one to zero).Bit Addressable MemoryThe 64 bytes of bit addressable memory are found in the last 128-byte page of the EEPROM address space and represent the first 64 bytes of this page.OTP MemoryThe 64 bytes of OTP (One-Time Programmable) Memory are found in the last 128-byte page of the EEPROM address space and represent the last 64 bytes of this page.CryptoprocessorThe cryptoprocessor is a 16-bit crypto engine dedicated to performing fast encryption or authentication functions. It isbased on a parallel RISC architecture allowing most instructions to be performed in a single clock cycle. The crypto engine can run in parallel with the microcontroller.An internal 16 x 16 multiplier provides 32-bit results within one cycle.The cryptoprocessor runs on its own internal clock.The cryptoprocessor ROM stores the program code which contains the following catalog of functions: •Reset and self test•Random Number Generation•Exponentiation with CRT (241 to 1024)•Exponentiation without CRT (241 to 1024)•DSARAM Memory SharingThe cryptoprocessor and the AVR share the RAM memory as follows: when the cryptoprocessor is inactive, the entire RAM can be accessed by the CPU. When the cryptopro-cessor is active, the shared RAM is not accessible by the CPU.Operational ModesThe AT90SC features two operational modes:• A supervisor mode with a privileged access to data, active when code is executed from the supervisor memory • A user mode with data access restrictions, active when code is executed from EEPROM user memory The supervisor and user locations are programmed in I/O registers.In user mode, direct read and write access to I/O registers and EEPROM is not allowed. Furthermore, a programma-ble zone in the RAM can be reserved for supervisor mode.Any attempt to access the I/O, EEPROM or reserved RAM area generates a maskable interrupt.Also, any jump to the supervisor zone in user mode gener-ates a non-maskable security interrupt. The AT90SC provides a supervisor call instruction to branch at a defined vector address of the supervisor zone.This powerful hardware solution is specially designed to ensure full separation between applications. It provides secure protection against program dumping and secure data access control.元器件交易网AT90SC5Security FeaturesFor security reasons the following list is not exhaustive.•Shipping and Initialization are protected by a Transport Code •Power-down/up protection•Low-frequency protection against static analysis •High-frequency protection against intrusion •Unique serial number •Supervisor mode •Secured test structure •Logical scrambling •Secure layoutISO 7816 I/O PortsThe ISO 7816 I/O pins are controlled by the CPU. They can be configured to generate an interrupt on:- Low level - Positive edge - Negative edge- Positive or negative edgeInterrupt ControllerThe AT90SC has a total of six interrupt vectors: security,I/O pins 0 and 1, timer, EEPROM end of write cycle and a cryptoprocessor interrupt.Each of these interrupt sources can be individually enabled or disabled by setting or clearing a bit in the Interrupt Mask Register located in the I/O memory space. This register also contains a global disable bit which disables all inter-rupts at once.One priority level can be programmed in the Interrupt Prior-ity register. A second priority level is given by the vector number.The interrupt controller is able to memorize interrupts. It sends them to the microcontroller in the correct order according to their priority level.Reduced Power ModeTo exploit the power savings for smart cards available in CMOS circuitry, Atmel ’s microcontrollers have two soft-ware-invoked reduced power modes.Idle ModeDuring Idle Mode, the CPU is disabled while all on-chip peripherals (RAM, I/O registers, timer and serial port)remain active. This mode is invoked by a SLEEP instruc-tion and by an enabled bit in an I/O register. Idle Mode can be terminated by any enabled interrupt or by a hardware reset.If a reset occurs during sleep mode, the CPU awakes and executes from the reset vector.If an interrupt occurs, the CPU awakes and executes the interrupt routine, and resumes execution from the instruc-tion following SLEEP.Power-down ModeDuring Power-down Mode, the clock is frozen. The on-chip RAM and I/O registers retain their values during Power-down Mode. The SLEEP instruction forces this mode. Exit from Power-down can be initiated either by a hardware reset or by the enabled external interrupt. Reset redefines the I/O registers but does not change the on-chip RAM.The I/O registers keep their value if the exit from Power-down is generated by an external interrupt.Download ModeThe AT90SC microcontroller has a special mode which allows the Flash to be written for new software download.The new software is loaded through the ISO port and writ-ten into the Flash memory. This download mode is software controlled, so if the software in use does not con-tain the download facility, no new program can be loaded. If the product contains only Flash for the code, during pro-gram download (OS or application) the code is fetched from the EEPROM.TimersThe AT90SC provides one or two 16-bit general timers with prescalers. The timers can run on a 16-bit counter or on an 8-bit counter with auto-reload mode.元器件交易网AT90SC6The Instruction SetAll members of the AT90SC series execute the same instruction set. The 16-bit instruction set provides a variety of fast addressing modes to facilitate byte and word opera-tions on small data structures. The instruction set supports 32 general-purpose registers for efficient implementation of software.Addressing ModeThe AT90SC AVR RISC microcontroller supports powerful and efficient addressing modes for access to program and data memory:•Direct I/O addressing•Direct Register addressing with one or two registers •Data direct : Operand address is specified by a 16-bit code •Indirect address data: Operand address is a 16-bit register •Indirect data with displacement : Operand address is a 16-bit register with a 6-bit offset •Indirect data with pre-decrement and post-increment: Operand address is a 16-bit register •Access to program memory : Operand address is a 16-bit register for access in byte LPM instruction •Indirect program addressing : Operand address is a 16-bit register for IJMP and ICALL •Relative program addressing : Operand address is a 16-bit PC with an offset of -2048 to +2047•Direct program addressingInstruction type •Data Transfers- From/to internal I/O, RAM, Registers - From/to internal EEPROM - From Flash •Arithmetic and logical Instruction - Manipulation, one or two registers - Manipulation, constant and register •Boolean Instruction- Manipulation and test on bit •Branch instruction - Relative branch - Indirect branch - Conditional skip- Unconditional branch - Conditional branch- Subroutine call and return - Interrupt returnMaster Clock GenerationThe master clock of the CPU is generated by the external ISO 7816 clock.Development ToolsA complete set of AT90SC development tools and a hard-ware emulator are available.© Atmel Corporation 1999.Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company ’s standard war-ranty which is detailed in Atmel ’s Terms and Conditions located on the Company ’s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual prop-erty of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel ’s products are not authorized for use as critical components in life support devices or systems.Atmel HeadquartersAtmel OperationsCorporate Headquarters2325 Orchard Parkway San Jose, CA 95131TEL (408) 441-0311FAX (408) 487-2600EuropeAtmel U.K., Ltd.Coliseum Business Centre Riverside WayCamberley, Surrey GU15 3YL EnglandTEL (44) 1276-686-677FAX (44) 1276-686-697AsiaAtmel Asia, Ltd.Room 1219Chinachem Golden Plaza 77 Mody Road Tsimhatsui East Kowloon Hong KongTEL (852) 2721-9778FAX (852) 2722-1369JapanAtmel Japan K.K.9F, Tonetsu Shinkawa Bldg.1-24-8 ShinkawaChuo-ku, Tokyo 104-0033JapanTEL (81) 3-3523-3551FAX (81) 3-3523-7581Atmel Colorado Springs1150 E. Cheyenne Mtn. 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AT91SAM7S256-AU-001中文资料

Features Array•Incorporates the ARM7TDMI® ARM® Thumb® Processor–High-performance 32-bit RISC Architecture–High-density 16-bit Instruction Set–Leader in MIPS/Watt–Embedded ICE In-circuit Emulation, Debug Communication Channel Support •256 Kbytes of Internal High-speed Flash, Organized in 1024 Pages of 256 Bytes –Single Cycle Access at Up to 30 MHz in Worst Case Conditions–Prefetch Buffer Optimizing Thumb Instruction Execution at Maximum Speed–Page Programming Time: 4 ms, Including Page Auto-erase, Full Erase Time: 10 ms –10,000 Write Cycles, 10-year Data Retention Capability, Sector Lock Capabilities, Flash Security Bit–Fast Flash Programming Interface for High Volume Production•64 Kbytes of Internal High-speed SRAM, Single-cycle Access at Maximum Speed •Memory Controller (MC)–Embedded Flash Controller, Abort Status and Misalignment Detection•Reset Controller (RSTC)–Based on Power-on Reset and Low-power Factory-calibrated Brown-out Detector –Provides External Reset Signal Shaping and Reset Source Status•Clock Generator (CKGR)–Low-power RC Oscillator, 3 to 20 MHz On-chip Oscillator and one PLL•Power Management Controller (PMC)–Software Power Optimization Capabilities, Including Slow Clock Mode (Down to 500 Hz) and Idle Mode–Three Programmable External Clock Signals•Advanced Interrupt Controller (AIC)–Individually Maskable, Eight-level Priority, Vectored Interrupt Sources–Two External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt Protected•Debug Unit (DBGU)–2-wire UART and Support for Debug Communication Channel interrupt,Programmable ICE Access Prevention•Periodic Interval Timer (PIT)–20-bit Programmable Counter plus 12-bit Interval Counter•Windowed Watchdog (WDT)–12-bit key-protected Programmable Counter–Provides Reset or Interrupt Signals to the System–Counter May Be Stopped While the Processor is in Debug State or in Idle Mode •Real-time Timer (RTT)–32-bit Free-running Counter with Alarm–Runs Off the Internal RC Oscillator•One Parallel Input/Output Controller (PIOA)–Thirty-two Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os –Input Change Interrupt Capability on Each I/O Line–Individually Programmable Open-drain, Pull-up resistor and Synchronous Output •Eleven Peripheral DMA Controller (PDC) Channels•One USB 2.0 Full Speed (12 Mbits per second) Device Port–On-chip Transceiver, 328-byte Configurable Integrated FIFOs26117BS–ATARM–07-Apr-05AT91SAM7S256•One Synchronous Serial Controller (SSC)–Independent Clock and Frame Sync Signals for Each Receiver and Transmitter –I²S Analog Interface Support, Time Division Multiplex Support–High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer •Two Universal Synchronous/Asynchronous Receiver Transmitters (USART)–Individual Baud Rate Generator, IrDA Infrared Modulation/Demodulation–Support for ISO7816 T0/T1 Smart Card, Hardware Handshaking, RS485 Support –Manchester Encoder/Decoder–Full Modem Line Support on USART1•One Master/Slave Serial Peripheral Interface (SPI)–8- to 16-bit Programmable Data Length, Four External Peripheral Chip Selects •One Three-channel 16-bit Timer/Counter (TC)–Three External Clock Inputs, Two Multi-purpose I/O Pins per Channel –Double PWM Generation, Capture/Waveform Mode, Up/Down Capability •One Four-channel 16-bit PWM Controller (PWMC)•One Two-wire Interface (TWI)–Master Mode Support Only, All Two-wire Atmel EEPROMs Supported•One 8-channel 10-bit Analog-to-Digital Converter, Four Channels Multiplexed with Digital I/Os •IEEE 1149.1 JTAG Boundary Scan on All Digital Pins•5V-tolerant I/Os, including Four High-current Drive I/O lines, Up to 16 mA Each •Power Supplies–Embedded 1.8V Regulator, Drawing up to 100 mA for the Core and External Components –3.3V VDDIO I/O Lines Power Supply, Independent 3.3V VDDFLASH Flash Power Supply –1.8V VDDCORE Core Power Supply with Brown-out Detector•Fully Static Operation: Up to 55 MHz at 1.65V and 85°C Worst Case Conditions •Available in a 64-lead LQFP Green Package1.DescriptionAtmel’s AT91SAM7S256 is a member of a series of low pincount Flash microcontrollers based on the 32-bit ARM RISC processor. It features a 256 Kbyte high-speed Flash and a 64 Kbyte SRAM, a large set of peripherals, including a USB 2.0 device, and a complete set of system functions minimizing the number of external components. The device is an ideal migration path for 8-bit microcontroller users looking for additional performance and extended memory.The embedded Flash memory can be programmed in-system via the JTAG-ICE interface or via a parallel interface on a production programmer prior to mounting. Built-in lock bits and a security bit protect the firmware from accidental overwrite and preserves its confidentiality.The AT91SAM7S256 system controller includes a reset controller capable of managing the power-on sequence of the microcontroller and the complete system. Correct device operation can be monitored by a built-in brownout detector and a watchdog running off an integrated RC oscillator.The AT91SAM7S256 is a general-purpose microcontroller. Its integrated USB Device port makes it an ideal device for peripheral applications requiring connectivity to a PC or cellular phone. Its aggressive price point and high level of integration pushes its scope of use far into the cost-sensitive, high-volume consumer market.36117BS–ATARM–07-Apr-05AT91SAM7S2562.Block DiagramFigure 2-1.AT91SAM7S256 Block Diagram46117BS–ATARM–07-Apr-05AT91SAM7S2563.Signal DescriptionTable 3-1.Signal Description ListSignal NameFunctionTypeActive LevelCommentsPowerVDDIN Voltage and ADC Regulator Power Supply Input Power 3.0 to 3.6V VDDOUT Voltage Regulator Output Power 1.85V nominal VDDFLASH Flash Power Supply Power 3.0V to 3.6V VDDIO I/O Lines Power Supply Power 3.0V to 3.6V VDDCORE Core Power Supply Power 1.65V to 1.95V VDDPLL PLL Power 1.65V to 1.95VGNDGroundGroundClocks, Oscillators and PLLsXIN Main Oscillator Input Input XOUT Main Oscillator Output Output PLLRC PLL FilterInput PCK0 - PCK2Programmable Clock OutputOutputICE and JTAGTCK Test Clock Input No pull-up resistor TDI Test Data In Input No pull-up resistorTDO Test Data Out Output TMS Test Mode Select Input No pull-up resistor JTAGSELJTAG SelectionInputPull-down resistor Flash MemoryERASEFlash and NVM Configuration Bits Erase CommandInputHighPull-down resistorReset/TestNRST Microcontroller Reset I/O Low Pull-Up resistor TSTTest Mode SelectInputHighPull-down resistorDebug UnitDRXD Debug Receive Data Input DTXDDebug Transmit DataOutput AICIRQ0 - IRQ1External Interrupt Inputs Input FIQFast Interrupt InputInput56117BS–ATARM–07-Apr-05AT91SAM7S256PIOP A0 - P A31Parallel IO Controller A I/OPulled-up input at resetUSB Device PortDDM USB Device Port Data - Analog DDPUSB Device Port Data +AnalogUSARTSCK0 - SCK1Serial Clock I/O TXD0 - TXD1Transmit Data I/O RXD0 - RXD1 Receive Data Input RTS0 - RTS1Request T o Send Output CTS0 - CTS1Clear T o Send Input DCD1Data Carrier Detect Input DTR1Data Terminal Ready Output DSR1Data Set Ready Input RI1Ring IndicatorInputSynchronous Serial ControllerTD Transmit Data Output RD Receive Data Input TK Transmit Clock I/O RK Receive Clock I/O TF Transmit Frame Sync I/O RFReceive Frame SyncI/OTimer/CounterTCLK0 - TCLK2External Clock Inputs Input TIOA0 - TIOA2I/O Line A I/O TIOB0 - TIOB2I/O Line BI/OPWM ControllerPWM0 - PWM3PWM ChannelsOutputSPIMISO Master In Slave Out I/O MOSI Master Out Slave In I/O SPCK SPI Serial ClockI/O NPCS0SPI Peripheral Chip Select 0I/O Low NPCS1-NPCS3SPI Peripheral Chip Select 1 to 3OutputLowTable 3-1.Signal Description List (Continued)Signal NameFunctionTypeActive LevelComments66117BS–ATARM–07-Apr-05AT91SAM7S256Two-Wire InterfaceTWD Two-wire Serial Data I/O TWCKTwo-wire Serial ClockI/OAnalog-to-Digital ConverterAD0-AD3Analog Inputs Analog Digital pulled-up inputs at reset AD4-AD7Analog Inputs Analog Analog InputsADTRG ADC Trigger Input ADVREFADC ReferenceAnalogFast Flash Programming InterfacePGMEN0-PGMEN2Programming Enabling Input PGMM0-PGMM3Programming Mode Input PGMD0-PGMD15Programming Data I/O PGMRDY Programming Ready Output High PGMNVALID Data Direction Output Low PGMNOE Programming Read Input LowPGMCK Programming Clock Input PGMNCMDProgramming CommandInputLow Table 3-1.Signal Description List (Continued)Signal NameFunctionTypeActive LevelComments76117BS–ATARM–07-Apr-05AT91SAM7S2564.Package and PinoutThe AT91SAM7S256 is available in a 64-lead LQFP package.4.164-lead LQFP Mechanical OverviewFigure 4-1 shows the orientation of the 64-lead LQFP package. A detailed mechanical description is given in the section Mechanical Characteristics of the full datasheet.Figure 4-1.64-lead LQFP Package Pinout (Top View)4.2PinoutTable 4-1.AT91SAM7S256 Pinout in 64-lead LQFP Package1ADVREF 17GND 33TDI 49TDO 2GND 18VDDIO 34P A6/PGMNOE 50JTAGSEL 3AD419P A16/PGMD435P A5/PGMRDY 51TMS 4AD520P A15/PGMD336P A4/PGMNCMD 52P A315AD621P A14/PGMD237P A27/PGMD1553TCK 6AD722P A13/PGMD138P A2854VDDCORE 7VDDIN 23P A24/PGMD1239NRST 55ERASE 8VDDOUT 24VDDCORE 40TST 56DDM 9P A17/PGMD5/AD025P A25/PGMD1341P A2957DDP 10P A18/PGMD6/AD126P A26/PGMD1442P A3058VDDIO 11P A21/PGMD927P A12/PGMD043P A359VDDFLASH12VDDCORE 28P A11/PGMM344P A2/PGMEN260GND 13P A19/PGMD7/AD229P A10/PGMM245VDDIO 61XOUT 14P A22/PGMD1030P A9/PGMM146GND 62XIN/PGMCK 15P A23/PGMD1131P A8/PGMM047P A1/PGMEN163PLLRC 16P A20/PGMD8/AD332P A7/PGMNVALID48P A0/PGMEN064VDDPLL86117BS–ATARM–07-Apr-05AT91SAM7S2565.Power Considerations5.1Power SuppliesThe AT91SAM7S256 has six types of power supply pins and integrates a voltage regulator, allowing the device to be supplied with only one voltage. The six power supply pin types are:•VDDIN pin. It powers the voltage regulator and the ADC; voltage ranges from 3.0V to 3.6V , 3.3V nominal. If the voltage regulator is not used, VDDIN should be connected to GND.•VDDOUT pin. It is the output of the 1.8V voltage regulator.•VDDIO pin. It powers the I/O lines and the USB transceivers; dual voltage range issupported. Ranges from 3.0V to 3.6V , 3.3V nominal. Note that supplying less than 3.0V to VDDIO prevents any use of the USB transceivers.•VDDFLASH pin. It powers a part of the Flash and is required for the Flash to operate correctly; voltage ranges from 3.0V to 3.6V, 3.3V nominal.•VDDCORE pins. They power the logic of the device; voltage ranges from 1.65V to 1.95V, 1.8V typical. It can be connected to the VDDOUT pin with decoupling capacitor.VDDCORE is required for the device, including its embedded Flash, to operate correctly.•VDDPLL pin. It powers the oscillator and the PLL. It can be connected directly to the VDDOUT pin.No separate ground pins are provided for the different power supplies. Only GND pins are pro-vided and should be connected as shortly as possible to the system ground plane.5.2Power ConsumptionThe AT91SAM7S256 has a static current of less than 60 µA on VDDCORE at 25°C, including the RC oscillator, the voltage regulator and the power-on reset when the brown-out detector is deactivated. Activating the brown-out detector adds 20 µA static current.The dynamic power consumption on VDDCORE is less than 50 mA at full speed when running out of the Flash. Under the same conditions, the power consumption on VDDFLASH does not exceed 10 mA.5.3Voltage RegulatorThe AT91SAM7S256 embeds a voltage regulator that is managed by the System Controller.In Normal Mode, the voltage regulator consumes less than 100 µA static current and draws 100 mA of output current.The voltage regulator also has a Low-power Mode. In this mode, it consumes less than 25 µA static current and draws 1 mA of output current.Adequate output supply decoupling is mandatory for VDDOUT to reduce ripple and avoid oscillations. The best way to achieve this is to use two capacitors in parallel: one external 470 pF (or 1 nF) NPO capacitor must be connected between VDDOUT and GND as close to the chip as possible. One external 2.2 µF (or 3.3 µF) X7R capacitor must be connected between VDDOUT and GND.Adequate input supply decoupling is mandatory for VDDIN in order to improve startup stability and reduce source voltage drop. The input decoupling capacitor should be placed close to the chip. For example, two capacitors can be used in parallel: 100 nF NPO and 4.7 µF X7R.96117BS–ATARM–07-Apr-05AT91SAM7S2565.4Typical Powering SchematicsThe AT91SAM7S256 supports a 3.3V single supply mode. The internal regulator is connected to the 3.3V source and its output feeds VDDCORE and the VDDPLL. Figure 5-1 shows the power schematics to be used for USB bus-powered systems.Figure 5-1.3.3V System Single Power Supply Schematic106117BS–ATARM–07-Apr-05AT91SAM7S2566.I/O Lines Considerations6.1JTAG Port PinsTMS, TDI and TCK are schmitt trigger inputs. TMS and TCK are 5-V tolerant, TDI is not. TMS, TDI and TCK do not integrate a pull-up resistor.TDO is an output, driven at up to VDDIO, and has no pull-up resistor.The pin JTAGSEL is used to select the JTAG boundary scan when asserted at a high level. The pin JTAGSEL integrates a permanent pull-down resistor of about 15 k Ω to GND, so that it can be left unconnected for normal operations.6.2Test PinThe pin TST is used for manufacturing test or fast programming mode of the AT91SAM7S256 when asserted high. The pin TST integrates a permanent pull-down resistor of about 15 k Ω to GND, so that it can be left unconnected for normal operations.To enter fast programming mode, the pin TST and the pins PA0 and PA1 should be tied hig-hand PA2 tied to low.Driving the pin TST at a high level while PA0 or PA1 is driven at 0 leads to unpredictable results.6.3Reset PinThe pin NRST is bidirectional. It is handled by the on-chip reset controller and can be driven low to provide a reset signal to the external components or asserted low externally to reset the microcontroller. There is no constraint on the length of the reset pulse, and the reset controller can guarantee a minimum pulse length. This allows connection of a simple push-button on the pin NRST as system user reset, and the use of the signal NRST to reset all the components of the system.The pin NRST integrates a permanent pull-up resistor to VDDIO.6.4ERASE PinThe pin ERASE is used to re-initialize the Flash content and some of its NVM bits. It integrates a permanent pull-down resistor of about 15 k Ω to GND, so that it can be left unconnected for normal operations.6.5PIO Controller A LinesAll the I/O lines PA0 to PA31 are 5V-tolerant and all integrate a programmable pull-up resistor. Programming of this pull-up resistor is performed independently for each I/O line through the PIO controllers.5V-tolerant means that the I/O lines can drive voltage level according to VDDIO, but can be driven with a voltage of up to 5.5V. However, driving an I/O line with a voltage over VDDIO while the programmable pull-up resistor is enabled can lead to unpredictable results. Care should be taken, in particular at reset, as all the I/O lines default to input with pull-up resistor enabled at reset.116117BS–ATARM–07-Apr-05 AT91SAM7S2566.6I/O Line Drive LevelsThe PIO lines PA0 to PA3 are high-drive current capable. Each of these I/O lines can drive up to 16 mA permanently.The remaining I/O lines can draw only 8 mA.However, the total current drawn by all the I/O lines cannot exceed 150 mA.126117BS–ATARM–07-Apr-05AT91SAM7S2567.Processor and Architecture7.1ARM7TDMI Processor•RISC processor based on ARMv4T Von Neumann architecture–Runs at up to 55 MHz, providing 0.9 MIPS/MHz•Two instruction sets–ARM ® high-performance 32-bit instruction set–Thumb ® high code density 16-bit instruction set•Three-stage pipeline architecture–Instruction Fetch (F)–Instruction Decode (D)–Execute (E)7.2Debug and Test Features •Integrated embedded in-circuit emulator–Two watchpoint units–Test access port accessible through a JTAG protocol–Debug communication channel•Debug Unit–Two-pinUART–Debug communication channel interrupt handling–Chip ID Register•IEEE1149.1 JT AG Boundary-scan on all digital pins7.3Memory Controller•Bus Arbiter–Handles requests from the ARM7TDMI and the Peripheral DMA Controller•Address decoder provides selection signals for–Three internal 1 Mbyte memory areas–One 256 Mbyte embedded peripheral area•Abort Status Registers–Source, Type and all parameters of the access leading to an abort are saved–Facilitates debug by detection of bad pointers•Misalignment Detector–Alignment checking of all data accesses–Abort generation in case of misalignment•Remap Command–Remaps the SRAM in place of the embedded non-volatile memory–Allows handling of dynamic exception vectors•Embedded Flash Controller–Embedded Flash interface, up to three programmable wait states136117BS–ATARM–07-Apr-05 AT91SAM7S256–Prefetch buffer, bufferizing and anticipating the 16-bit requests, reducing therequired wait states–Key-protected program, erase and lock/unlock sequencer–Single command for erasing, programming and locking operations–Interrupt generation in case of forbidden operation7.4Peripheral DMA Controller•Handles data transfer between peripherals and memories•Eleven channels–Two for each USART–Two for the Debug Unit–Two for the Serial Synchronous Controller–Two for the Serial Peripheral Interface–One for the Analog-to-digital Converter•Low bus arbitration overhead–One Master Clock cycle needed for a transfer from memory to peripheral–Two Master Clock cycles needed for a transfer from peripheral to memory•Next Pointer management for reducing interrupt latency requirements146117BS–ATARM–07-Apr-05AT91SAM7S2568.Memory•256 Kbytes of Flash Memory–1024 pages of 256 bytes–Fast access time, 30 MHz single-cycle access in worst case conditions–Page programming time: 4 ms, including page auto-erase–Page programming without auto-erase: 2 ms–Full chip erase time: 10 ms–10,000 write cycles, 10-year data retention capability–16 lock bits, each protecting 16 sectors of 64 pages–Protection Mode to secure contents of the Flash•64 Kbytes of Fast SRAM–Single-cycle access at full speed8.1Memory Mapping 8.1.1Internal SRAMThe AT91SAM7S256 embeds a high-speed 64-Kbyte SRAM bank. After reset and until the Remap Command is performed, the SRAM is only accessible at address 0x0020 0000. After Remap, the SRAM also becomes available at address 0x0.8.1.2Internal FlashThe AT91SAM77S256 features one bank of 256 Kbytes of Flash. At any time, the Flash is mapped to address 0x0010 0000. It is also accessible at address 0x0 after the reset and before the Remap Command.Figure 8-1.Internal Memory Mapping156117BS–ATARM–07-Apr-05 AT91SAM7S2568.2Embedded Flash 8.2.1Flash OverviewThe Flash of the AT91SAM7S256 is organized in 1024 pages of 256 bytes. The 262,144 bytes are organized in 32-bit words.The Flash contains a 256-byte write buffer, accessible through a 32-bit interface.The Flash benefits from the integration of a power reset cell and from the brownout detector. This prevents code corruption during power supply changes, even in the worst conditions.When Flash is not used (read or write access), it is automatically placed into standby mode.8.2.2Embedded Flash ControllerThe Embedded Flash Controller (EFC) manages accesses performed by the masters of the system. It enables reading the Flash and writing the write buffer. It also contains a User Inter-face, mapped within the Memory Controller on the APB. The User Interface allows:•programming of the access parameters of the Flash (number of wait states, timings, etc.)•starting commands such as full erase, page erase, page program, NVM bit set, NVM bit clear, etc.•getting the end status of the last command•getting error status•programming interrupts on the end of the last commands or on errorsThe Embedded Flash Controller also provides a dual 32-bit Prefetch Buffer that optimizes 16-bit access to the Flash. This is particularly efficient when the processor is running in Thumb mode.8.2.3Lock RegionsThe Embedded Flash Controller manages 16 lock bits to protect 16 regions of the flash against inadvertent flash erasing or programming commands. The AT91SAM7S256 contains 16 lock regions and each lock region contains 64 pages of 256 bytes. Each lock region has a size of 16 Kbytes.If a locked-regions erase or program command occurs, the command is aborted and the EFC trigs an interrupt.The 16 NVM bits are software programmable through the EFC User Interface. The command "Set Lock Bit" enables the protection. The command "Clear Lock Bit" unlocks the lock region.Asserting the ERASE pin clears the lock bits, thus unlocking the entire Flash.8.2.4Security Bit FeatureThe AT91SAM7S256 features a security bit, based on a specific NVM-Bit. When the security is enabled, any access to the Flash, either through the ICE interface or through the Fast Flash Programming Interface, is forbidden. This ensures the confidentiality of the code programmed in the Flash.This security bit can only be enabled, through the Command "Set Security Bit" of the EFC User Interface. Disabling the security bit can only be achieved by asserting the ERASE pin at 1, and after a full flash erase is performed. When the security bit is deactivated, all accesses to the flash are permitted.It is important to note that the assertion of the ERASE pin should always be longer than 50 ms.166117BS–ATARM–07-Apr-05AT91SAM7S256As the ERASE pin integrates a permanent pull-down, it can be left unconnected during normal operation. However, it is safer to connect it directly to GND for the final application.8.2.5Non-volatile Brownout Detector ControlTwo general purpose NVM (GPNVM) bits are used for controlling the brownout detector (BOD), so that even after a power loss, the brownout detector operations remain in their state. These two GPNVM bits can be cleared or set respectively through the commands "Clear Gen-eral-purpose NVM Bit" and "Set General-purpose NVM Bit" of the EFC User Interface.•GPNVM Bit 0 is used as a brownout detector enable bit. Setting the GPNVM Bit 0 enables the BOD, clearing it disables the BOD. Asserting ERASE clears the GPNVM Bit 0 and thus disables the brownout detector by default.•The GPNVM Bit 1 is used as a brownout reset enable signal for the reset controller. Setting the GPNVM Bit 1 enables the brownout reset when a brownout is detected, Clearing the GPNVM Bit 1 disables the brownout reset. Asserting ERASE disables the brownout reset by default.8.2.6Calibration BitsEight NVM bits are used to calibrate the brownout detector and the voltage regulator. These bits are factory configured and cannot be changed by the user. The ERASE pin has no effect on the calibration bits.8.3Fast Flash Programming InterfaceThe Fast Flash Programming Interface allows programming the device through either a serial JTAG interface or through a multiplexed fully-handshaked parallel port. It allows gang-pro-gramming with market-standard industrial programmers.The FFPI supports read, page program, page erase, full erase, lock, unlock and protect commands.The Fast Flash Programming Interface is enabled and the Fast Programming Mode is entered when the TST pin and the PA0 and PA1 pins are all tied high and PA2 is tied low.176117BS–ATARM–07-Apr-05 AT91SAM7S2569.System ControllerThe System Controller manages all vital blocks of the microcontroller: interrupts, clocks, power, time, debug and reset.Figure 9-1.System Controller Block Diagram186117BS–ATARM–07-Apr-05AT91SAM7S2569.1System Controller MappingThe System Controller peripherals are all mapped to the highest 4 Kbytes of address space, between addresses 0xFFFF F000 and 0xFFFF FFFF.Figure 9-2 shows the mapping of the System Controller. Note that the Memory Controller con-figuration user interface is also mapped within this address space.Figure 9-2.System Controller Mapping196117BS–ATARM–07-Apr-05 AT91SAM7S2569.2Reset ControllerThe Reset Controller is based on a power-on reset cell and one brownout detector. It gives the status of the last reset, indicating whether it is a power-up reset, a software reset, a user reset, a watchdog reset or a brownout reset. In addition, it controls the internal resets and the NRST pin output. It allows to shape a signal on the NRST line, guaranteeing that the length of the pulse meets any requirement.Note that if NRST is used as a reset output signal for external devices during power-off, the brownout detector must be activated.9.2.1Brownout Detector and Power-on ResetThe AT91SAM7S256 embeds a brownout detection circuit and a power-on reset cell. Both are supplied with and monitor VDDCORE. Both signals are provided to the Flash to prevent any code corruption during power-up or power-down sequences or if brownouts occur on the VDDCORE power supply.The power-on reset cell has a limited-accuracy threshold at around 1.5V. Its output remains low during power-up until VDDCORE goes over this voltage level. This signal goes to the reset controller and allows a full re-initialization of the device.The brownout detector monitors the VDDCORE level during operation by comparing it to a fixed trigger level. It secures system operations in the most difficult environments and prevents code corruption in case of brownout on the VDDCORE.Only VDDCORE is monitored, as a voltage drop on VDDFLASH or any other power supply of the device cannot affect the Flash.When the brownout detector is enabled and VDDCORE decreases to a value below the trigger level (Vbot-, defined as Vbot - hyst/2), the brownout output is immediately activated.When VDDCORE increases above the trigger level (Vbot+, defined as Vbot + hyst/2), the reset is released. The brownout detector only detects a drop if the voltage on VDDCORE stays below the threshold voltage for longer than about 1µs.The threshold voltage has a hysteresis of about 50 mV, to ensure spike free brownout detec-tion. The typical value of the brownout detector threshold is 1.68V with an accuracy of ± 2% and is factory calibrated.The brownout detector is low-power, as it consumes less than 20 µA static current. However, it can be deactivated to save its static current. In this case, it consumes less than 1µA. The deactivation is configured through the GPNVM bit 0 of the Flash.206117BS–ATARM–07-Apr-05AT91SAM7S2569.3Clock GeneratorThe Clock Generator embeds one low-power RC Oscillator, one Main Oscillator and one PLL with the following characteristics:•RC Oscillator ranges between 22 KHz and 42 KHz•Main Oscillator frequency ranges between 3 and 20 MHz•Main Oscillator can be bypassed•PLL output ranges between 80 and 220 MHzIt provides SLCK, MAINCK and PLLCK.Figure 9-3.Clock Generator Block Diagram。

96SC Crystal 502 2的物质安全数据表说明书

C 502 96SC 5C 0.5MM G 250G C 502 96SC 5C 0.7MM H 500G C 502 96SC 5C 1.0MM H 500GRevision Date: 18/05/2006Issue date:18/05/2006Version:91.CHEMICAL PRODUCT AND COMPANY IDENTIFICATIONProduct name: 96SC Crystal 5022. COMPOSITION/INFORMATION ON INGREDIENTSHazardous componentsCAS No.EINECS-No.%ClassificationTin 7440-31-5231-141-880 - 100Silver 7440-22-4 231-131-3 1 - 5Copper 7440-50-8231-159-60.1 - 1Additional Information:For the explanation of the listed risk phrases refer to Section 16.3. HAZARDS IDENTIFICATIONThis product contains modified rosin. Flux fumes emitted during reflow will irritate the nose and throat and may cause an asthmatic type reaction.4. FIRST AID MEASURESInhalation: Move to fresh air. If symptoms persist, seek medical advice.Eye contact:Flush eyes with plenty of water for at least 15 minutes. If irritation persists seek medical attention.Ingestion:Do not induce vomiting. Seek medical attention immediately.Skin contact:Wash off with soap and plenty of water. Obtain medical attention if irritation persists.1 of 5Item No. :MB1068Product name: 96SC Crystal 502Item No. : MB1068Product type: Solder WireRegion:Europe Company Name & Address Henkel Loctite Adhesives Ltd. Multicore SoldersTechnologies House, Wood Lane End Hemel Hempstead, Herts HP2 4RQ, UK Tel: +44 (0) 1442 278000 Fax: +44 (0) 1442 278071Emergency Tel: +44 (0) 1442 2780005. FIRE-FIGHTING MEASURESExtinguishing media:The product itself does not burn. Use extinguishing meaures appropriate to local circumstances andthe surrounding environment.Special fire fighting procedures:Fire fighters should wear positive pressure breathing apparatus. Do not use water on fires wheremolten metal is present.Unusual fire or explosion hazards:None.Hazardous combustion products:High temperatures may produce heavy metal dust, fumes or vapours. The flux will give rise to irritatingfumes.6. ACCIDENTAL RELEASE MEASURESClean-up methods:Scrape up.7. HANDLING AND STORAGEHandling:Use only in area provided with appropriate exhaust ventilation. Do not eat, drink or smoke whenhandling. Wash hands before breaks and immediately after handling the product.Storage: Store in a cool, dry place. Keep out of reach of children.8. EXPOSURE CONTROLS / PERSONAL PROTECTIONHazardous componentsCAS No.ACGIH TLV Austria Belgium CzechTin 7440-31-52 mg/m³ TWA2 mg/m³ TWA excepttin hydride, as Sn2 mg/m³ MAK4 mg/m³ STEL4 mg/m³ STEL2 mg/m³ VLE2 mg/m³ VLE2 mg/m3 TWASilver 7440-22-4 0.1 mg/m³ TWA0.01 mg/m³ MAK0.1 mg/m³ STEL0.1 mg/m³ VLE0.1 mg/m3 TWACopper 7440-50-8 0.2 mg/m³ TWA fume1 mg/m³ TWA dustand mist, as Cu0.1 mg/m³ MAK0.1 mg/m³ MAK0.4 mg/m³ STEL1 mg/m³ MAK4 mg/m³ STEL0.2 mg/m³ VLE1 mg/m³ VLE0.1 mg/m3 TWA1 mg/m3 TWAHazardous componentsCAS No.Estonia Greece Finland France HungaryTin 7440-31-5 2 mg/m3 TWA 2 mg/m³ TWA2 mg/m³ TWA8 mg/m3 STEL2 mg/m3 TWASilver 7440-22-4 0.1 mg/m3 TWA0.1 mg/m3 TWA0.1 mg/m³ TWA0.1 mg/m³ VME0.4 mg/m3 STEL0.1 mg/m3 TWACopper 7440-50-81 mg/m3 TWA0.2 mg/m3 TWA0.2 mg/m3 TWA2 mg/m3 STEL0.2 mg/m3 TWA1 mg/m3 TWA0.1 mg/m³ TWA1 mg/m³ TWA1 mg/m³ TWA0.2 mg/m³ VME1 mg/m³ VME2 mg/m³ VLE4 mg/m3 STEL0.4 mg/m3 STEL0.1 mg/m3 TWA1 mg/m3 TWA1 mg/m3 TWA2 of 5MB1068Item No. :Product name: 96SC Crystal 502Hazardous componentsCAS No.Germany Ireland Netherlands Norway Portugal Tin 7440-31-52 mg/m³ TWA 4 mg/m³ STEL 4 mg/m³ STEL 2 mg/m³ MAC 2 mg/m³ MAC 2 mg/m³ TWA 2 mg/m³ TWA 2 mg/m³ TWA Silver 7440-22-4 0.01 mg/m³ MAK 0.02 mg/m³ Peak 0.1 mg/m³ MAK 0.8 mg/m³ Peak 0.01 mg/m³ TWA 0.1 mg/m³ TWA 0.1 mg/m³ MAC0.1 mg/m³ TWA0.1 mg/m³ TWACopper 7440-50-80.1 mg/m³ MAK 0.2 mg/m³ Peak0.2 mg/m³ TWA 1 mg/m³ TWA 2 mg/m³ STEL0.2 mg/m³ MAC 1 mg/m³ MAC 0.1 mg/m³ TWA 1 mg/m³ TWA 0.2 mg/m³ TWA 1 mg/m³ TWAHazardous componentsCAS No.Poland Spain Sweden UK EH40 Tin 7440-31-52 mg/m3 NDS 2 mg/m³ VLA-ED 2 mg/m³ VLA-ED 0.1 mg/m 3 LLV 0.2 mg/m 3 STV 2 mg/m 3 TWA4 mg/m 3 STEL Silver 7440-22-4 0.05 mg/m 3 NDS0.1 mg/m³ VLA-ED 0.1 mg/m³ LLV 0.1 mg/m 3 TWA 0.3 mg/m 3 STEL Copper 7440-50-8 0.2 mg/m³ VLA-ED 1 mg/m³ VLA-ED0.2 mg/m³ LLV 1 mg/m³ LLV0.2 mg/m 3 TWA 1 mg/m 3 TWA 0.6 mg/m 3 STEL 2 mg/m 3 STEL Modified rosinRosin flux fume:0.05 mg/m³ MEL TWA (As total resin acids) 0.15 mg/m³ MEL STEL (As total resin acids)Engineering controls:Extraction is necessary to remove fumes evolved during reflow. Where reasonably practicable this should be achieved by the use of local exhaust ventilation and good general extraction.Respiratory protection:In case of insufficient ventilation, wear suitable respiratory equipment.Skin protection:No special protective equipment required.Eye/face protection:Safety glasses should be worn.9. PHYSICAL AND CHEMICAL PROPERTIESPhysical state:pasteColour:greyOdour:none pH:not applicableVapour pressure:not determinedBoiling point/range: not determinedMelting point/range:217°C (423°F) (solder alloy)Specific gravity:7.5Vapour density:not applicableFlash point: not applicableAutoignition temperature:not applicableSolubility in water:insolublePartition coefficient (n-octanol/water):not determined3 of 5MB1068Item No. :Product name: 96SC Crystal 50210. STABILITY AND REACTIVITYStability:Stable under recommended storage conditions.Hazardous polymersation:Will not occur.Hazardous decomposition products:Thermal decomposition can lead to release of irritating gases and vapours.Conditions to avoid:Solder alloy will react with concentrated nitric acid to produce toxic fumes of nitrogen oxides.11. TOXICOLOGICAL INFORMATION12. ECOLOGICAL INFORMATIONMobility:No data available.Bioaccumulation:No data available.Ecotoxicity:No information available.Persistence and degradability:Not inherently biodegradable.WGK Water Classification (VwVwS):Class 113. DISPOSAL CONSIDERATIONSProductDisposal methods:Wherever possible unwanted solder alloy should be recycled for recovery of metal. Otherwise dispose of in accordance with local and national regulations.European Waste Catalogue:06 04 05 - wastes containing other heavy metals.PackagingDisposal Methods:Dispose of in accordance with local and national regulations.14. TRANSPORT INFORMATIONICAO/IATA (Air):Identification number:NoneProper shipping name:Not regulated Hazard class or division:None Packing group:NoneIMO/IMDG (Sea)Identification number:NoneProper shipping name:Not regulated Hazard class or division:None Packing group:NoneADR/RID (Road/Rail)4 of 5Skin:Fumes emitted during soldering may irritate the skin. Inhalation:Eyes:Fumes emitted during soldering may irritate the eyes. Fumes evolved at soldering temperatures will irritate the nose, throat and lungs. Prolonged or repeated exposure to flux fumes may result in sensitisation in sensitive workers. Item No. :MB1068Product name: 96SC Crystal 502Ingestion:This product is considered to be of low toxicity.UN Number NoneProper shipping name:Unrestricted Hazard class or division None Packing group None15. REGULATORY INFORMATIONIndication of danger:None.Risk Phrases:None.Safety Phrases:NoneAdditional Labelling:Avoid breathing fumes given out during soldering. Flux fumes may irritate the nose, throat and lungs and may after prolonged/repeated exposure give an allergic reaction (asthma). After handling solder wash hands with soap and water before eating, drinking or smoking. Keep out of reach of children.UK National regulations:The Health & Safety at Work etc. ActThe Control of Substances Hazardous to Health Regulations 2002 L5: General Approved Code of Practice to the COSHH Regulations HS(G)97: A Step by Step Guide to the COSHH Regulations HS(G)193: COSHH essentials: Easy steps to control chemicalsIND (G)248L: Solder fume and you(G)249L: Controlling health risks from rosin (colophony) based solder fluxes16. OTHER INFORMATIONSupercedes Sheet Dated: 22/11/2005Prepared by:Barry Chase Senior SpecialistProduct Safety & Regulatory Affairs - EuropeMSDS data Revised:18/05/2006The information in this safety data sheet was obtained from reputable sources and to the best of our knowledge is accurate and current at the mentioned date. Neither Loctite nor its subsidiary companies accept any liability arising out of the use of the information provided here or the use, application or processing of the product(s) described herein. Attention of users is drawn to the possible hazards from improper use of the product(s). This safety data sheet was prepared in accordance with Commission Directive 2004/73/EC adapting to technical progress for the 29th time Council Directive 67/548/EEC, and Commission Directive 1999/45/EC.Explanation of Section 2 R - Phrases Not applicable.5 of 5MB1068Item No. :Product name: 96SC Crystal 502C 502 96SC 5C 0.5MM G 250G C 502 96SC 5C 0.7MM H 500G C 502 96SC 5C 1.0MM H 500G。

ATMEL CPU卡及其操作系统

正常芯片在运输过程及初始化时受到 64 位的传输代码的保护 Device NameFlashEEPROMRAMAT89SC16816 K bytes8 K bytes256 bytesAT89SC168A16 K bytes8 K bytes512 bytesAT89SC1616A16 K bytes16 K bytes512 bytes
片处于完全工作状态时电流的 15% • 休眠模式芯片上一切活动均被挂起 RAM 中还保留数据在休眠状态下芯片的
电流通常低于 15µA 最低可达到 0.6µA 同时由于芯片使用静态逻辑设计无须时钟持续工作这就是说在等待一个内部事件的触发时时钟频率可以减缓甚至停止安全特性 AT89SC 系列微处理器提供了下述安全特性 • 低电压保护 • 低频保护防止静态分析 • 高频滤波防止干扰 • 传输代码保护芯片在运输过程中不被盗用 • 唯一系列代码当时钟频率低于 500KHz 或电压低于 4V 时芯片会产生一个安全保护中断当时钟频率高于 10MHz 或电压低于 3V 时芯片处于复位状态直至电压或时钟频率恢复
Select File 功能
此命令使用文件名或应用标示符来选择 IC 卡内 DF 或 EF
格式代码值 CLA‘00’INS‘A4’P1‘00’P2‘00’Lc‘00’ 选择 MF 文件 / ‘02’Data 无 / FID
Get Challenge 功能
此命令请求 IC 卡返回一个用于安全相关过程的随机数
SF 是密码文件各层目录均可有一个存放用户密码 KF 是密钥文件各层目录均可有一个存放发行商密钥 WF 是工作文件数据文件 EF 支持两种标准 EF 文件结构线性定长记录透明二进制本结构支持一卡多用

飞思卡尔MC9S12XET256 SCI串口寄存器说明

串口寄存器说明该模块指南提供了串行通信接口（SCI）模块概述。

SCI的允许与外围设备和其他CPU异步串行通信。

1.1 SCI包括这些特征：•全双工或单线运行•标准标记/空间不归零（NRZ）格式•可选的IrDA1.4返回到零倒置（RZI）与可编程脉冲宽度格式•13位的波特率选择•可编程8位或9位数据格式•分别使能发射机和接收机•可编程极性对发射机和接收机•可编程发送器输出校验•两个接收器唤醒的方法：-唤醒空闲线- 地址标志唤醒•中断驱动的操作有八个标志：-发送器空- 传输完成- 接收器满- 空闲接收器输入- 接收器溢出-噪声误差-帧错误- 奇偶错误- 接收有效边缘唤醒- 发送冲突检测支持LIN-间隔检测支持LIN•接收帧错误检测•硬件奇偶校验•1 / 16位时间噪声检测1.2 操作模式SCI的功能相同在正常、特殊和仿真模式。

它有两种低功耗模式，等待和停止模式。

•运行模式•等待模式•停止模式1.3 寄存器说明1、波特率控制寄存器（SCIBDH、SCIBDL)SCIBDH和SCIBDL一起构成了一个16位的波特率控制寄存器。

SBR12~~SBR0为波特率常数。

IREN:红外调制模式使能位1 使能0 禁止TNP[0..1]:窄脉冲发射位，这些位使能SCI是否能发送一个1 / 16，3 /16，1/ 32或1 / 4的窄脉冲。

见表20-3。

SBR[0..12]:波特率设置位When IREN = 0 then,SCI baud rate = SCI bus clock / (16 x SBR[12:0])When IREN = 1 then,SCI baud rate = SCI bus clock / (32 x SBR[12:1])【说明】波特率发生器在复位后是禁止的，在设置TE、RE(在SCICR2寄存器中)后才会工作。

当(SBR[12:0] = 0 and IREN = 0) 或者(SBR[12:1] = 0 andIREN = 1)，波特率发生器不工作。

AT27C256R-70PU中文资料

Features Array•Fast Read Access Time – 45 ns•Low-Power CMOS Operation–100 µA Max Standby–20 mA Max Active at 5 MHz•JEDEC Standard Packages–28-lead PDIP–32-lead PLCC–28-lead TSOP and SOIC•5V±10% Supply•High Reliability CMOS Technology–2,000V ESD Protection–200 mA Latchup Immunity•Rapid Programming Algorithm – 100 µs/Byte (Typical)•CMOS and TTL Compatible Inputs and Outputs•Integrated Product Identification Code•Industrial and Automotive Temperature Ranges•Green (Pb/Halide-free) Packaging Option1.DescriptionThe AT27C256R is a low-power, high-performance 262,144-bit one-time programma-ble read-only memory (OTP EPROM) organized 32K by 8 bits. It requires only one 5V power supply in normal read mode operation. Any byte can be accessed in less than 45 ns, eliminating the need for speed reducing WAIT states on high-performance microprocessor systems.Atmel’s scaled CMOS technology provides low-active power consumption, and fast programming. Power consumption is typically only 8 mA in Active Mode and less than 10 µA in Standby.The AT27C256R is available in a choice of industry-standard JEDEC-approved one time programmable (OTP) plastic DIP, PLCC, SOIC, and TSOP packages. All devices feature two-line control (CE, OE) to give designers the flexibility to prevent bus contention.With 32K byte storage capability, the AT27C256R allows firmware to be stored reli-ably and to be accessed by the system without the delays of mass storage media. Atmel’s AT27C256R has additional features to ensure high quality and efficient pro-duction use. The Rapid Programming Algorithm reduces the time required to program the part and guarantees reliable programming. Programming time is typically only 100 µs/byte. The Integrated Product Identification Code electronically identifies the device and manufacturer. This feature is used by industry-standard programmingequipment to select the proper programming algorithms and voltages.20014M–EPROM–12/07AT27C256R2.128-lead PDIP/SOIC Top View2.232-lead PLCC Top ViewNote:PLCC Package Pins 1 and 17 are Don’t Connect.2.328-lead TSOP Top View – Type 12.Pin ConfigurationsPin Name Function A0 - A14Addresses O0 - O7Outputs CE Chip Enable OE Output Enable NCNo Connect30014M–EPROM–12/07AT27C256R3.System ConsiderationsSwitching between active and standby conditions via the Chip Enable pin may produce tran-sient voltage excursions. Unless accommodated by the system design, these transients may exceed datasheet limits, resulting in device non-conformance. At a minimum, a 0.1 µF high frequency, low inherent inductance, ceramic capacitor should be utilized for each device. This capacitor should be connected between the V CC and Ground terminals of the device, as close to the device as possible. Additionally, to stabilize the supply voltage level on printed circuit boards with large EPROM arrays, a 4.7 µF bulk electrolytic capacitor should be utilized, again connected between the V CC and Ground terminals. This capacitor should be positioned as close as possible to the point where the power supply is connected to the array.4.Block DiagramNote:1.Minimum voltage is -0.6V DC which may undershoot to -2.0V for pulses of less than 20 ns. M aximum output pin voltage isV CC+ 0.75V dc which may overshoot to +7.0 volts for pulses of less than 20 ns.5.Absolute Maximum Ratings*T emperature Under Bias................................-55°C to +125°C *NOTICE:Stresses beyond those listed under “Absolute Maxi-mum Ratings” may cause permanent damage to the device. This is a stress rating only and func-tional operation of the device at these or any other conditions beyond those indicated in the opera-tional sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.Storage T emperature.....................................-65°C to +150°C Voltage on Any Pin withRespect to Ground .........................................-2.0V to +7.0V (1)Voltage on A9 withRespect to Ground ......................................-2.0V to +14.0V (1)V PP Supply Voltage withRespect to Ground .......................................-2.0V to +14.0V (1)40014M–EPROM–12/07AT27C256RNotes:1.X can be V IL or V IH .2.Refer to Programming Characteristics.3.V H = 12.0 ± 0.5V .4.Two identifier bytes may be selected. All Ai inputs are held low (V IL ), except A9 which is set to V H and A0 which is toggledlow (V IL ) to select the Manufacturer’s Identification byte and high (V IH ) to select the Device Code byte.Notes:1.V CC must be applied simultaneously with or before V PP , and removed simultaneously with or after V PP ..2.V PP may be connected directly to V CC , except during programming. The supply current would then be the sum of I CC and I PP .6.Operating ModesMode/Pin CE OE Ai V PP Outputs ReadV IL V IL Ai V CC D OUT Output Disable V IL V IH X (1)V CC High Z Standby V IH X (1) X (1)V CC High Z Rapid Program (2)V IL V IH Ai V PP D IN PGM Verify (2)X (1)V IL Ai V PP D OUT Optional PGM Verify (2)V IL V IL Ai V CC D OUT PGM Inhibit (2)V IH V IH X (1)V PP High Z Product Identification (4)V ILV ILA9 = V H (3)A0 = V IH or V IL A1 - A14 = V ILV CCIdentification Code7.DC and AC Operating Conditions for Read OperationAT27C256R-45-70Operating T emp. (Case)Ind.-40°C - 85°C-40°C - 85°C Auto.-40°C - 125°C V CC Supply5V ± 10%5V ± 10%8.DC and Operating Characteristics for Read OperationSymbol Parameter Condition MinMax Units I LIInput Load CurrentV IN = 0V to V CCInd.±1µA Auto.±5µA I LO Output Leakage Current V OUT = 0V to V CC Ind.±5µA Auto.±10µA I PP1(2)V PP (1) Read/Standby Current V PP = V CC10µA I SB V CC (1) Standby Current I SB1 (CMOS), CE = V CC ± 0.3V 100µA I SB2 (TTL), CE = 2.0 to V CC + 0.5V 1mA I CC V CC Active Current f = 5 MHz, I OUT = 0 mA, E = V IL20mA V IL Input Low Voltage -0.60.8V V IH Input High Voltage 2.0V CC + 0.5V V OL Output Low Voltage I OL = 2.1 mA 0.4V V OH Output High VoltageI OH = -400 µA2.4V50014M–EPROM–12/07AT27C256RNote:1.See AC Waveforms for Read Operation.10.AC Waveforms for Read Operation (1)Notes:1.Timing measurement reference level is 1.5V for -45 devices. Input AC drive levels are V IL = 0.0V and V IH = 3.0V . Timing mea-surement reference levels for all other speed grades are V OL = 0.8V and V OH =2.0V . Input AC drive levels are V IL = 0.45V and V IH = 2.4V .2.OE may be delayed up to t CE - t OE after the falling edge of CE without impact on t CE .3.ACC - t OE after the address is valid without impact on t ACC .4.This parameter is only sampled and is not 100% tested.5.Output float is defined as the point when data is no longer driven.9.AC Characteristics for Read OperationSymbol ParameterCondition AT27C256R Units -45-70MinMax MinMax t ACC (1)Address to Output Delay CE = OE = V IL 4570ns t CE (1)CE to Output Delay OE = V IL 4570ns t OE (1)OE to Output DelayCE = V IL2030ns t DF (1)OE or CE High to OutputFloat, Whichever Occurred First 2025ns t OH Output Hold from Address, CE or OE, Whichever Occurred First77ns60014M–EPROM–12/07AT27C256R11.Input Test Waveforms and Measurement Levels12.Output Test LoadNote:1.C L = 100 pF including jig capacitance, except for the -45 devices, where C L = 30 pF .Note:1.Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.R F For -45 devices only:R F For -70 devices:13.Pin Capacitancef = 1 MHz, T = 25°C (1)Symbol Typ Max Units Conditions C IN 46pF V IN = 0V C OUT 812pFV OUT = 0V70014M–EPROM–12/07AT27C256R14.Programming Waveforms (1)Notes:1.The Input Timing Reference is 0.8V for V IL and2.0V for V IH .2.t OE and t DFP are characteristics of the device but must be accommodated by the programmer.3.When programming the A T27C256R a 0.1 µF capacitor is required across V PP and ground to suppress spurious voltagetransients.15.DC Programming CharacteristicsT A = 25 ± 5°C, V CC = 6.5 ± 0.25V, V PP = 13.0 ± 0.25VSymbol Parameter Test Conditions LimitsUnits MinMax I LI Input Load Current V IN = V IL ,V IH±10µA V IL Input Low Level -0.60.8V V IH Input High Level 2.0V CC + 1V V OL Output Low Volt I OL = 2.1 mA 0.4V V OH Output High VoltI OH = -400 µA2.4V I CC2V CC Supply Current (Program and Verify)25mA I PP2V PP CurrentCE = V IL25mA V IDA9 Product Identification Voltage11.512.5V80014M–EPROM–12/07AT27C256RNotes:1.V CC must be applied simultaneously or before V PP and removed simultaneously or after V PP .2.This parameter is only sampled and is not 100% tested. Output Float is defined as the point where data is no longerdriven – see timing diagram.3.Program Pulse width tolerance is 100 µsec ± 5%.16.AC Programming CharacteristicsT A = 25 ± 5°C, V CC = 6.5 ± 0.25V, V PP = 13.0 ± 0.25VSymbol ParameterTest Conditions (1)LimitsUnits Min Maxt AS Address Setup Time Input Rise and Fall Times(10% to 90%) 20 ns Input Pulse Levels0.45V to 2.4VInput Timing Reference Level0.8V to 2.0V Output Timing Reference Level0.8V to 2.0V 2µs t OES OE Setup Time 2µs t DSData Setup Time 2µs t AHAddress Hold Time 0µs t DH Data Hold Time2µst DFPOE High to Output Float Delay (2)0130ns t VPS V PP Setup Time 2µs t VCS V CC Setup Time2µs t PW CE Program Pulse Width (3)95105µs t OE Data Valid from OE (2)150ns t PRT V PP Pulse Rise Time During Programming50ns17.Atmel’s AT27C256R Integrated Product Identification CodeCodes PinsHex Data A0O7O6O5O4O3O2O1O0Manufacturer 0000111101E Device Type11118C90014M–EPROM–12/07AT27C256R18.RapidProgramming AlgorithmA 100 µs CE pulse width is used to program. The address is set to the first location. V CC is raised to 6.5V and V PP is raised to 13.0V. Each address is first programmed with one 100 µs CE pulse without verification. Then a verification/reprogramming loop is executed for each address. In the event a byte fails to pass verification, up to 10 successive 100 µs pulses are applied with a verification after each pulse. If the byte fails to verify after 10 pulses have been applied, the part is considered failed. After the byte verifies properly, the next address is selected until all have been checked. V PP is then lowered to 5.0V and V CC to 5.0V. All bytesare read again and compared with the original data to determine if the device passes or fails.100014M–EPROM–12/07AT27C256R19.Ordering InformationNote: 1.The 28-pin SOIC package is not recommended for new designs.19.1Standard Packaget ACC (ns)I CC (mA)Ordering Code Package Operation Range Active Standby 45200.1A T27C256R-45JI A T27C256R-45PI A T27C256R-45RI A T27C256R-45TI 32J 28P628R (1)28T Industrial (-40°C to 85°C)70200.1A T27C256R-70JI A T27C256R-70PI A T27C256R-70RI A T27C256R-70TI 32J 28P628R (1)28T Industrial (-40°C to 85°C)200.1A T27C256R-70JA A T27C256R-70P A A T27C256R-70RA32J 28P628R (1)Automotive (-40°C to 125°C)Note:Not recommended for new designs. Use Green package option.19.2Green Package (Pb/Halide-free)t ACC (ns)I CC (mA)Ordering Code Package Operation Range Active Standby 45200.1A T27C256R-45JU A T27C256R-45PU A T27C256R-45RU A T27C256R-45TU 32J 28P628R (1)28T Industrial (-40°C to 85°C)70200.1A T27C256R-70JU A T27C256R-70PU A T27C256R-70RU A T27C256R-70TU32J 28P628R (1)28TIndustrial (-40°C to 85°C)Package Type32J 32-lead, Plastic J-Leaded Chip Carrier (PLCC)28P628-lead, 0.600" Wide, Plastic Dual Inline Package (PDIP)28R 28-lead, 0.330" Wide, Plastic Gull Wing Small Outline (SOIC)28T28-lead, Thin Small Outline Package (TSOP)AT27C256R 20.Packaging Information20.132J – PLCC1120.228P6 – PDIP12AT27C256RAT27C256R 20.328R – SOIC1320.428T – TSOP14AT27C256RHeadquarters InternationalAtmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USATel: 1(408) 441-0311 Fax: 1(408) 487-2600Atmel AsiaRoom 1219Chinachem Golden Plaza77 Mody Road TsimshatsuiEast KowloonHong KongTel: (852) 2721-9778Fax: (852) 2722-1369Atmel EuropeLe Krebs8, Rue Jean-Pierre TimbaudBP 30978054 Saint-Quentin-en-Yvelines CedexFranceTel: (33) 1-30-60-70-00Fax: (33) 1-30-60-71-11Atmel Japan9F, Tonetsu Shinkawa Bldg.1-24-8 ShinkawaChuo-ku, Tokyo 104-0033JapanTel: (81) 3-3523-3551Fax: (81) 3-3523-7581Product ContactWeb SiteTechnical Supporteprom@Sales Contact/contactsLiterature Requests/literatureDisclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI-TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDEN-TAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life.© 2007 Atmel Corporation. All rights reserved. Atmel®, logo and combinations thereof, and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others.。

AT90CAN128中文资料

特点•高性能，低功耗的A VR ® 8位微控制器•先进的RISC结构- 133 - 最强大的单时钟周期指令执行- 32个8位通用工作寄存器+外设控制寄存器- 全静态工作- 高达16 MIPS的吞吐量为16兆赫- 片2周期乘法器•非挥发性程序和数据存储器- 在系统内32K/64K/128K字节可重编程闪存（A T90CAN32/64/128）•耐久性：10,000写入/擦除周期- 可选启动代码段与独立锁定位•可选启动大小：1K字节，2K字节，4K字节或8K 字节•在系统编程的片上引导程序（CAN总线，UART 的，...）•真正的了解，同时，写操作- 1K/2K/4K字节的EEPROM（耐力：100,000写入/擦除周期）（A T90CAN32/64/128）- 2K/4K/4K字节内部SRAM（AT90CAN32/64/128）- 高达64K字节可选外部存储空间- 编程软件安全锁•JTAG接口（IEEE标准。

1149.1兼容）接口- 边界扫描功能根据JTAG标准- 编程闪存（硬件的ISP）的EEPROM，熔丝位和锁定- 广泛的片上调试支持•CAN控制器的电流及2.0B - 的ISO 16845认证（1）- 15个具有独立完整的邮件对象标识标签和面具- 发送，接收，自动回复和帧缓冲区接收模式- 1Mbits / s的8 MHz的最大传输速率- 冲压时，公车及听力模式（间谍或自动波特）•外设特点- 可编程看门狗定时器，带有片上振荡器- 8位同步Timer/Counter-0•10位预分频器•外部事件计数器•输出比较或8位PWM输出- 8位异步Timer/Counter-2•10位预分频器•外部事件计数器•输出比较或8位PWM输出•32kHz振荡器实时时钟运行- 双通道16位同步Timer/Counters-1＆3 •10位预分频器•输入捕获噪声抵消•外部事件计数器•3输出比较或16位PWM输出•输出比较调制- 8通道，10位SAR ADC•8个单端通道•7个差分通道•2个差分通道，再加上1倍，10倍，或200x中可编程增益- 片内模拟比较器- 字节为导向的两线串行接口- 双可编程串行的USART- 主/从SPI串行接口•编程闪存（硬件的ISP）•特殊的处理器特点- 上电复位和可编程欠压检测- 内部RC振荡器校准- 8个外部中断源- 5睡眠模式：空闲，ADC噪声降低，电力保存，掉电和待机- 软件可选的时钟频率- 全球拉禁用•I / O和软件包- 53可编程I / O口线- 64引脚TQFP和64引脚QFN封装•工作电压：2.7 - 5.5V的•工作温度：工业（-40 °C至+85℃）•最大工作频率：在2.7V 8兆赫，16兆赫在4.5V 注：1。

550C中文资料

550C中文资料关键信息项：1、资料名称：550C 中文资料2、资料用途：＿___________________________3、资料提供方：＿___________________________4、资料接收方：＿___________________________5、资料使用期限：＿___________________________6、资料保密要求：＿___________________________7、违约责任：＿___________________________8、争议解决方式：＿___________________________11 协议背景本协议旨在规范550C 中文资料的相关事宜，确保资料的合理使用、保护和传播。

111 资料的定义和范围本协议中所提及的550C 中文资料包括但不限于文字、图表、图像、音频、视频等与 550C 相关的各类中文形式的信息。

112 资料的用途资料接收方应仅将 550C 中文资料用于具体合法且明确的用途，不得用于其他任何未经授权的目的。

12 资料提供方的权利和义务121 提供方应确保所提供的 550C 中文资料的真实性、准确性和完整性。

122 提供方有权对资料接收方的使用情况进行监督和检查。

13 资料接收方的权利和义务131 接收方应按照协议约定的用途使用 550C 中文资料。

132 接收方有义务对资料进行妥善保管，采取合理的安全措施防止资料泄露、丢失或损坏。

133 未经提供方书面同意，接收方不得将资料转让、出售、出租或提供给任何第三方。

14 资料使用期限141 双方约定 550C 中文资料的使用期限为具体时间段。

142 在使用期限届满后，接收方应立即停止使用并按照提供方的要求归还或销毁资料。

15 资料保密要求151 接收方应对 550C 中文资料予以保密，不得向任何无关人员透露资料的内容。

152 接收方应采取必要的保密措施，如限制访问、加密存储等，以确保资料的保密性。

AT90S2313资料

Features•AVR ® - High Performance and Low Power RISC Architecture •118 Powerful Instructions - Most Single Clock Cycle Execution •2K bytes of In-System Reprogrammable Flash –SPI Serial Interface for Program Downloading –Endurance: 1,000 Write/Erase Cycles •128 bytes EEPROM–Endurance: 100,000 Write/Erase Cycles •128 bytes Internal RAM•32 x 8 General Purpose Working Registers •15 Programmable I/O Lines •V CC : 2.7 - 6.0V•Fully Static Operation –0 - 10 MHz, 4.0 - 6.0V –0 - 4 MHz, 2.7 - 6.0V•Up to 10 MIPS Throughput at 10 MHz•One 8-Bit Timer/Counter with Separate Prescaler •One 16-Bit Timer/Counter with Separate Prescaler and Compare and Capture Modes •Full Duplex UART•Selectable 8, 9 or 10 bit PWM•External and Internal Interrupt Sources•Programmable Watchdog Timer with On-Chip Oscillator •On-Chip Analog Comparator•Low Power Idle and Power Down Modes •Programming Lock for Software Security •20-Pin DeviceDescriptionThe AT90S2313 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the AT90S2313 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.The AVR core combines a rich instruction set with 32 general purpose working regis-ters. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU),allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.(continued)Pin Configuration8-BitMicrocontroller with 2K bytesBlock DiagramFigure 1. The A T90S2313 Block DiagramThe AT90S2313 provides the following features: 2K bytes of In-System Programmable Flash, 128 bytes EEPROM, 128 bytes SRAM, 15 general purpose I/O lines, 32 general purpose working registers, flexible timer/counters with compare modes, internal and external interrupts, a pro-grammable serial UART, programmable Watchdog Timer with internal oscillator, an SPI serial port for Flash Memory downloading and two software selectable power saving modes. The Idle Mode stops the CPU while allowing the SRAM, timer/counters, SPI port and interrupt system to continue functioning. The power down mode saves the reg-ister contents but freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset. The device is manufactured using Atmel’s high density non-volatile memory technology. The on-chip In-System Programmable Flash allows the program memory to be reprogrammed in-system through an SPI serial interface or by a conventional nonvolatile memory programmer. By combining an enhanced RISC 8-bit CPU with In-System Programmable Flash on a monolithic chip, the Atmel AT90S2313 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embed-ded control applications.The AT90S2313 AVR is supported with a full suite of pro-gram and system development tools including: C compil-ers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits.AT90S2313Pin DescriptionsVCCSupply voltage pin.GNDGround pin.Port B (PB7..PB0)Port B is an 8-bit bi-directional I/O port. Port pins can pro-vide internal pull-up resistors (selected for each bit). PB0 and PB1 also serve as the positive input (AIN0) and the negative input (AIN1), respectively, of the on-chip analog comparator. The Port B output buffers can sink 20mA and can drive LED displays directly. When pins PB0 to PB7 are used as inputs and are externally pulled low, they will source current if the internal pull-up resistors are activated. Port B also serves the functions of various special features of the AT90S2313 as listed on page38.Port D (PD6..PD0)Port D has seven bi-directional I/O pins with internal pull-up resistors, PD6..PD0. The Port D output buffers can sink 20 mA. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated.Port D also serves the functions of various special features of the AT90S2313 as listed on page43.Reset input. A low on this pin for two machine cycles while the oscillator is running resets the device.XTAL1Input to the inverting oscillator amplifier and input to the internal clock operating circuit.XTAL2Output from the inverting oscillator amplifierCrystal OscillatorXTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 2. Either a quartz crystal or a ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 3.Figure 2. Oscillator ConnectionsFigure 3.External Clock Drive Configuration元器件交易网AT90S2313 Architectural OverviewThe fast-access register file concept contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This means that during one single clock cycle, one ALU (Arithmetic Logic Unit) operation is executed. Two operands are output from the register file, the operation is executed, and the result is stored back in the register file -in one clock cycle.Six of the 32 registers can be used as three 16-bits indirect address register pointers for Data Space addressing -enabling efficient address calculations. One of the three address pointers is also used as the address pointer for the constant table look up function. These added function reg-isters are the 16-bits X-register, Y-register and Z-register. The ALU supports arithmetic and logic functions between registers or between a constant and a register. Single reg-ister operations are also executed in the ALU. Figure 4 shows the AT90S2313 AVR Enhanced RISC microcontrol-ler architecture.In addition to the register operation, the conventional mem-ory addressing modes can be used on the register file as well. This is enabled by the fact that the register file is assigned the 32 lowermost Data Space addresses ($00 -$1F), allowing them to be accessed as though they were ordinary memory locations.The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, Timer/Counters, A/D-converters, and other I/O functions. The I/O memory can be accessed directly, or as the Data Space locations following those of the register file, $20 - $5F.The AVR has Harvard architecture - with separate memo-ries and buses for program and data. The program memory is accessed with a two stage pipeline. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is In-system Programmable Flash memory.With the relative jump and call instructions, the whole 1K address space is directly accessed. Most AVR instructions have a single 16-bit word format. Every program memory address contains a 16- or 32-bit instruction.During interrupts and subroutine calls, the return address program counter (PC) is stored on the stack. The stack is effectively allocated in the general data SRAM, and conse-quently the stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initial-ize the SP in the reset routine (before subroutines or inter-rupts are executed). The 8-bit stack pointer SP is read/write accessible in the I/O space.The 128 bytes data SRAM + register file and I/O registers can be easily accessed through the five different address-ing modes supported in the AVR architecture.The memory spaces in the AVR architecture are all linear and regular memory maps.元器件交易网AT90S2313Figure 4. The AT90S2313 AVR Enhanced RISC ArchitectureFigure 5.Memory Maps元器件交易网元器件交易网Address Name Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0Page$3F ($5F) SREG I T H S V N Z C17 $3E ($5E) Reserved$3D ($5D) SPL SP7SP6SP5SP4SP3SP2SP1SP018 $3C ($5C) Reserved$3B ($5B) GIMSK INT1INT0------23 $3A ($5A) GIFR INTF1INTF023 $39 ($59) TIMSK TOIE1OCIE1A--TICIE1-TOIE0-23 $38 ($58) TIFR TOV1OCF1A--ICF1-TOV0-24 $37 ($57) Reserved$36 ($56) Reserved$35 ($55) MCUCR--SE SM ISC11ISC10ISC01ISC0025 $34 ($54) Reserved$33 ($53) TCCR0-----CS02CS01CS0028 $32 ($52) TCNT0 Timer/Counter0 (8 Bit)29 $31 ($51) Reserved$30 ($50) Reserved$2F ($4F) TCCR1A COM1A1COM1A0----PWM11PWM1030 $2E ($4E) TCCR1B ICNC1ICES1.-CTC1CS12CS11CS1031 $2D ($4D) TCNT1H Timer/Counter1 - Counter Register High Byte32 $2C ($4C) TCNT1L Timer/Counter1 - Counter Register Low Byte32 $2B ($4B) OCR1AH Timer/Counter1 - Compare Register High Byte32 $2A ($4A) OCR1AL Timer/Counter1 - Compare Register Low Byte32 $29 ($49) Reserved$28 ($48) Reserved$27 ($47) Reserved$26 ($46) Reserved$25 ($45) ICR1H Timer/Counter1 - Input Capture Register High Byte33 $24 ($44) ICR1L Timer/Counter1 - Input Capture Register Low Byte33 $23 ($43) Reserved$22 ($42) Reserved$21 ($41) WDTCR---WDTOE WDE WDP2WDP1WDP035 $20 ($40) Reserved$1F ($3F) Reserved$1E ($3E) EEAR- EEPROM Address Register36 $1D ($3D) EEDR EEPROM Data register37 $1C ($3C) EECR-----EEMWE EEWE EERE37 $1B ($3B) Reserved$1A ($3A) Reserved$19 ($39) Reserved$18 ($38) PORTB PORTB7PORTB6PORTB5PORTB4PORTB3PORTB2PORTB1PORTB046 $17 ($37) DDRB DDB7DDB6DDB5DDB4DDB3DDB2DDB1DDB046 $16 ($36) PINB PINB7PINB6PINB5PINB4PINB3PINB2PINB1PINB046 $15 ($35) Reserved$14 ($34) Reserved$13 ($33) Reserved$12 ($32) PORTD-PORTD6PORTD5PORTD4PORTD3PORTD2PORTD1PORTD051 $11 ($31) DDRD-DDD6DDD5DDD4DDD3DDD2DDD1DDD051 $10 ($30) PIND-PIND6PIND5PIND4PIND3PIND2PIND1PIND051 $0F ($2F) Reserved$0E ($2E) Reserved$0D ($2D) Reserved$0C ($2C) UDR UART I/O Data Register40 $0B ($2B) USR RXC TXC UDRE FE OR---40 $0A ($2A) UCR RXCIE TXCIE UDRIE RXEN TXEN CHR9RXB8TXB841 $09 ($29) UBRR UART Baud Rate Register43 $08 ($28) ACSR ACD-ACO ACI ACIE ACIC ACIS1ACIS044…Reserved$00 ($20) Reserved元器件交易网AT90S2313 AT90S2313 Instruction Set SummaryMnemonics Operands Description Operation Flags#Clocks ARITHMETIC AND LOGIC INSTRUCTIONSADD Rd, Rr Add two Registers Rd ← Rd + Rr Z,C,N,V,H1 ADC Rd, Rr Add with Carry two Registers Rd ← Rd + Rr + C Z,C,N,V,H1 ADIW Rdl,K Add Immediate to Word Rdh:Rdl ← Rdh:Rdl + K Z,C,N,V,S2 SUB Rd, Rr Subtract two Registers Rd ← Rd − Rr Z,C,N,V,H1 SUBI Rd, K Subtract Constant from Register Rd ← Rd − K Z,C,N,V,H1 SBIW Rdl,K Subtract Immediate from Word Rdh:Rdl ← Rdh:Rdl − K Z,C,N,V,S2 SBC Rd, Rr Subtract with Carry two Registers Rd ← Rd − Rr − C Z,C,N,V,H1 SBCI Rd, K Subtract with Carry Constant from Reg.Rd ← Rd − K − C Z,C,N,V,H1 AND Rd, Rr Logical AND Registers Rd ← Rd • Rr Z,N,V1 ANDI Rd, K Logical AND Register and Constant Rd ← Rd • K Z,N,V1 OR Rd, Rr Logical OR Registers Rd ← Rd v Rr Z,N,V1 ORI Rd, K Logical OR Register and Constant Rd ← Rd v K Z,N,V1 EOR Rd, Rr Exclusive OR Registers Rd ← Rd ⊕ Rr Z,N,V1 COM Rd One’s Complement Rd ← $FF − Rd Z,C,N,V1 NEG Rd Two’s Complement Rd ← $00 − Rd Z,C,N,V,H1 SBR Rd,K Set Bit(s) in Register Rd ← Rd v K Z,N,V1 CBR Rd,K Clear Bit(s) in Register Rd ← Rd • ($FF − K)Z,N,V1 INC Rd Increment Rd ← Rd + 1Z,N,V1 DEC Rd Decrement Rd ← Rd − 1 Z,N,V1 TST Rd Test for Zero or Minus Rd ← Rd • Rd Z,N,V1 CLR Rd Clear Register Rd ← Rd ⊕ Rd Z,N,V1 SER Rd Set Register Rd ← $FF None1 BRANCH INSTRUCTIONSRJMP k Relative Jump PC ← PC + k + 1 None2 IJMP Indirect Jump to (Z)PC ← Z None2 RCALL k Relative Subroutine Call PC ← PC + k + 1None3 ICALL Indirect Call to (Z)PC ← Z None3 RET Subroutine Return PC ← STACK None4 RETI Interrupt Return PC ← STACK I4 CPSE Rd,Rr Compare, Skip if Equal if (Rd = Rr) PC ← PC + 2 or 3None 1 / 2 CP Rd,Rr Compare Rd − Rr Z, N,V,C,H1 CPC Rd,Rr Compare with Carry Rd − Rr − C Z, N,V,C,H1 CPI Rd,K Compare Register with Immediate Rd − K Z, N,V,C,H1 SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b)=0) PC ← PC + 2 or 3 None 1 / 2 SBRS Rr, b Skip if Bit in Register is Set if (Rr(b)=1) PC ← PC + 2 or 3None 1 / 2 SBIC P, b Skip if Bit in I/O Register Cleared if (P(b)=0) PC ← PC + 2 or 3 None 1 / 2 SBIS P, b Skip if Bit in I/O Register is Set if (R(b)=1) PC ← PC + 2 or 3None 1 / 2 BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PC←PC + k + 1None 1 / 2 BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PC←PC + k + 1None 1 / 2 BREQ k Branch if Equal if (Z = 1) then PC ← PC + k + 1None 1 / 2 BRNE k Branch if Not Equal if (Z = 0) then PC ← PC + k + 1None 1 / 2 BRCS k Branch if Carry Set if (C = 1) then PC ← PC + k + 1None 1 / 2 BRCC k Branch if Carry Cleared if (C = 0) then PC ← PC + k + 1None 1 / 2 BRSH k Branch if Same or Higher if (C = 0) then PC ← PC + k + 1None 1 / 2 BRLO k Branch if Lower if (C = 1) then PC ← PC + k + 1None 1 / 2 BRMI k Branch if Minus if (N = 1) then PC ← PC + k + 1None 1 / 2 BRPL k Branch if Plus if (N = 0) then PC ← PC + k + 1None 1 / 2 BRGE k Branch if Greater or Equal, Signed if (N ⊕ V= 0) then PC ← PC + k + 1None 1 / 2 BRLT k Branch if Less Than Zero, Signed if (N ⊕ V= 1) then PC ← PC + k + 1None 1 / 2 BRHS k Branch if Half Carry Flag Set if (H = 1) then PC ← PC + k + 1None 1 / 2 BRHC k Branch if Half Carry Flag Cleared if (H = 0) then PC ← PC + k + 1None 1 / 2 BRTS k Branch if T Flag Set if (T = 1) then PC ← PC + k + 1None 1 / 2 BRTC k Branch if T Flag Cleared if (T = 0) then PC ← PC + k + 1None 1 / 2 BRVS k Branch if Overflow Flag is Set if (V = 1) then PC ← PC + k + 1None 1 / 2 BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC ← PC + k + 1None 1 / 2 BRIE k Branch if Interrupt Enabled if (I = 1) then PC ← PC + k + 1None 1 / 2 BRID k Branch if Interrupt Disabled if (I = 0) then PC ← PC + k + 1None 1 / 2元器件交易网Mnemonics Operands Description Operation Flags#Clocks DATA TRANSFER INSTRUCTIONSMOV Rd, Rr Move Between Registers Rd ← Rr None1 LDI Rd, K Load Immediate Rd ←K None1 LD Rd, X Load Indirect Rd ← (X)None2 LD Rd, X+Load Indirect and Post-Inc.Rd ← (X), X ← X + 1None2 LD Rd, - X Load Indirect and Pre-Dec.X ← X − 1, Rd ← (X)None2 LD Rd, Y Load Indirect Rd ← (Y)None2 LD Rd, Y+Load Indirect and Post-Inc.Rd ← (Y), Y ← Y + 1None2 LD Rd, - Y Load Indirect and Pre-Dec.Y ← Y − 1, Rd ← (Y)None2 LDD Rd,Y+q Load Indirect with Displacement Rd ← (Y + q)None2 LD Rd, Z Load Indirect Rd ← (Z)None2 LD Rd, Z+Load Indirect and Post-Inc.Rd ← (Z), Z ← Z+1None2 LD Rd, -Z Load Indirect and Pre-Dec.Z ← Z - 1, Rd ← (Z)None2 LDD Rd, Z+q Load Indirect with Displacement Rd ← (Z + q)None2 LDS Rd, k Load Direct from SRAM Rd ← (k)None2 ST X, Rr Store Indirect(X) ← Rr None2 ST X+, Rr Store Indirect and Post-Inc.(X) ← Rr, X ← X + 1None2 ST- X, Rr Store Indirect and Pre-Dec.X ← X - 1, (X) ← Rr None2 ST Y, Rr Store Indirect(Y) ← Rr None2 ST Y+, Rr Store Indirect and Post-Inc.(Y) ← Rr, Y ← Y + 1None2 ST- Y, Rr Store Indirect and Pre-Dec.Y ← Y - 1, (Y) ← Rr None2 STD Y+q,Rr Store Indirect with Displacement(Y + q) ← Rr None2 ST Z, Rr Store Indirect(Z) ← Rr None2 ST Z+, Rr Store Indirect and Post-Inc.(Z) ← Rr, Z ← Z + 1None2 ST-Z, Rr Store Indirect and Pre-Dec.Z ← Z - 1, (Z) ← Rr None2 STD Z+q,Rr Store Indirect with Displacement(Z + q) ← Rr None2 STS k, Rr Store Direct to SRAM(k) ← Rr None2 LPM Load Program Memory R0 ← (Z)None3 IN Rd, P In Port Rd ←P None1 OUT P, Rr Out Port P ← Rr None1 PUSH Rr Push Register on Stack STACK ← Rr None2 POP Rd Pop Register from Stack Rd ← STACK None2 BIT AND BIT-TEST INSTRUCTIONSSBI P,b Set Bit in I/O Register I/O(P,b) ←1None2 CBI P,b Clear Bit in I/O Register I/O(P,b) ←0None2 LSL Rd Logical Shift Left Rd(n+1) ← Rd(n), Rd(0) ← 0Z,C,N,V1 LSR Rd Logical Shift Right Rd(n) ← Rd(n+1), Rd(7) ← 0Z,C,N,V1 ROL Rd Rotate Left Through Carry Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7)Z,C,N,V1 ROR Rd Rotate Right Through Carry Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0)Z,C,N,V1 ASR Rd Arithmetic Shift Right Rd(n) ← Rd(n+1), n=0..6Z,C,N,V1 SWAP Rd Swap Nibbles Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0)None1 BSET s Flag Set SREG(s) ← 1SREG(s)1 BCLR s Flag Clear SREG(s) ← 0 SREG(s)1 BST Rr, b Bit Store from Register to T T ← Rr(b)T1 BLD Rd, b Bit load from T to Register Rd(b) ←T None1 SEC Set Carry C ←1C1 CLC Clear Carry C ← 0 C1 SEN Set Negative Flag N ←1N1 CLN Clear Negative Flag N ← 0 N1 SEZ Set Zero Flag Z ←1Z1 CLZ Clear Zero Flag Z ← 0 Z1 SEI Global Interrupt Enable I ←1I1 CLI Global Interrupt Disable I ← 0 I1 SES Set Signed Test Flag S ←1S1 CLS Clear Signed Test Flag S ← 0 S1 SEV Set Twos Complement Overflow V ←1V1 CLV Clear Twos Complement Overflow V ← 0 V1 SET Set T in SREG T ←1T1 CLT Clear T in SREG T ← 0 T1 SEH Set Half Carry Flag in SREG H ←1H1 CLH Clear Half Carry Flag in SREG H ← 0 H1 NOP No Operation None1 SLEEP Sleep(see specific descr. for Sleep function)None3 WDR Watchdog Reset(see specific descr. for WDR/timer)None1。

at90s1200中文资料

I/O 内存
地址 16 进制 $3F $3B $39 $38 $35 $33 $32 $21 $1E $1D $1C $18 $17 $16 $12 $11 $10 $08
表1 名称 SREG GIMSK TIMSK TIFR MCUCR TCCR0 TCNT0 WDTCR EEAR EEDR EECR PORTB DDRB PINB PORTD DDRD OIND ACSR
在线可编程 FLASH
AT90S1200 具有 1K 字节的 FLASH 因为所有的指令为 16 位宽故尔 FLASH 结构为 512 16 FLASH 的擦除次数至少为 1000 次 AT90S1200 的程序计数器 PC 为 9 位宽可以寻址到 512 个字的 FLASH 程序区
程序和数据寻址模式
AT90S1200 的 I/O 空间
功能状态寄存器通用中断屏蔽寄存器 T/C 屏蔽寄存器 T/C 中断标志寄存器 MCU 控制寄存器 T/C0 控制寄存器 T/C0 8 位看门狗控制寄存器 EEPROM 地址寄存器 EEPROM 数据寄存器 EEPROM 控制寄存器 B 口数据寄存器 B 口数据方向寄存器 B 口输入引脚 D 口数据寄存器 D 口数据方向寄存器 D 口输入引脚模拟比较器控制及状态寄存器
状态寄存器 SREG Status Register
BIT
7
6
5
4
3
2
1
0
$3F
I
T
H
S
V
N
Z
C
读/写 R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
初始值
0
0

LT8920C数据手册1.0

LT8920C2.4G 可变数据率射频芯片芯片特点●包括射频前端和数字基带的单芯片解决方案。

●支持跳频●支持SPI 和I2C 接口●内置auto_ack 功能●数据率1Mbps ，250Kbps ，125Kbps ，62.5Kbps ●1Mbps 时同步位为64bits ，48bits ，32bits ，16bits ；250Kbps ，125Kbps ，62.5Kbps 时同步位为32bits ，16bits 。

推荐使用32bits ，容错1bits 。

●极低功耗●支持信号能量检测●单芯片传输距离200米Page 22017年5月2.极限值.............................................................................................................................................................53.电气特性.........................................................................................................................................................64.典型应用.........................................................................................................................................................95.管脚描述.......................................................................................................................................................106.SPI 接口.......................................................................................................................................................116.1.SPI 默认格式...........................................................................................................................................116.2.SPI Optional Format .. (11)6.3.SPI 时序要求...........................................................................................................................................127.IIC 接口.......................................................................................................................................................137.1.I2C 命令格式...........................................................................................................................................137.2.I2C 特性...................................................................................................................................................137.3.I2C 器件地址...........................................................................................................................................148.状态机框图...................................................................................................................................................159.寄存器信息...................................................................................................................................................169.1.Register 3–Read only .....................................................................................................................169.2.Register 6–Read only .....................................................................................................................169.3.Register 7...............................................................................................................................................169.4.Register 9...............................................................................................................................................179.5.Register 10.............................................................................................................................................179.6.Register 11.............................................................................................................................................179.7.Register 23.............................................................................................................................................179.8.Register 27.............................................................................................................................................189.9.Register 29–Read only ...................................................................................................................189.10.Register 30–Read only ...............................................................................................................189.11.Register 31–Read only ...............................................................................................................189.12.Register 32.........................................................................................................................................199.13.Register 33.........................................................................................................................................219.14.Register 34.........................................................................................................................................219.15.Register 35.........................................................................................................................................219.16.Register 36.........................................................................................................................................229.17.Register 37.........................................................................................................................................229.18.Register 38.........................................................................................................................................239.19.Register 39.........................................................................................................................................239.20.Register 40.........................................................................................................................................239.21.Register 41.........................................................................................................................................Page 32017年5月9.23.Register 43.........................................................................................................................................249.24.Register 48–Read only ...............................................................................................................259.25.Register 50 (25)9.26.Register 52.........................................................................................................................................2610.寄存器推荐值...............................................................................................................................................2711.注意事项.......................................................................................................................................................2811.1.上电和寄存器初始化数据...................................................................................................................2811.2.进入sleep mode 和唤醒.....................................................................................................................2911.3.数据包格式...........................................................................................................................................2911.4.清空FIFO 指针.....................................................................................................................................2911.5.Packet Payload Length (29)11.6.状态机决定包长度...............................................................................................................................3111.6.1.发射时序........................................................................................................................................3111.7.接收时序 (33)11.8.MCU/应用决定包长度...........................................................................................................................3411.8.1.FW_TERM_TX=1..............................................................................................................................3511.8.2.FW_TERM_TX=0(发射状态).......................................................................................................3711.8.3.FW_TERM_TX=0(RX)....................................................................................................................3911.9.晶体振荡器...........................................................................................................................................4111.9.1.Quartz crystal application ...................................................................................................4111.9.2.外部时钟输入................................................................................................................................4111.9.3.减小管脚数....................................................................................................................................4212.封装形式.......................................................................................................................................................43....................................................................................................................................................错误！未定义书签。

AT90SC系列CPU卡

AT90SC系列CPU卡
AT90SC3232C型CPU卡的构成
AVR RISC（精简指令集）增强型结构
高性能的ALU（算术逻辑单元）可在一个时钟周期内完成取指令、运算和输出的工作
ALU的操作:：算术、逻辑和位操作功能
AT90SC系列CPU卡
AT90SC3232C型CPU卡的构成
32个工作寄存器
IC卡技术及其应用
AT90SC系列CPU卡
基本特征
集成了AVR微处理器（内含一个16bit定时器、分两级优先的5个中断源）、Flash程序存储器、EEPROM数据存储器、随机数发生器和符合ISO/IEC7816标准的通信接口电路
触点安排符合ISO7816标准有的型号还自带专门用于加密、解密的协处理器。
护中断，确保数据的完整性。
AT90SC系列CPU卡
安全防范特性
3）防追踪保护，当时钟（SCL）频率低于500kHz时，器件也会自动产生安全防护中断，这一功能可以防范低频或静态追踪分析。因为同步记录并分析传送数据时，如果被记录或分析的数据变化越快对记录分析装置的要求就越高。
AT90SC系列CPU卡
安全防范特性
4）程序代码加密，防范COS的非法复制。 5）具有64bit的传输代码，可保护芯片在运输过程中不被盗
用。
AT90SC系列CPU卡
两种节电工作方式
闲置模式：CPU停止工作，芯片上其他部分继续工作。在闲置状态下，电流大约是芯片处于完全工作状态时电流的 15％。
休眠模式：芯片上一切活动均被挂起，RAM中还保留数据。在休眠状态下，芯片的电流通常低于15，最低可达到0.6。
AT90SC系列CPU卡
主要技术参数
1）工作电压与具体型号有关，分为4种：1.62～5.5 V（宽电压）；2.7～5.5 V（宽电压）；2.7～3.3 V（3V供电）； 4.5～5.5 V（5V供电）。

卡萨帝电烤箱 COR90S295-XX说明书

COR90S295-AC&XX两1180900600160120AE B挡风板高度底脚高度关于烤箱附近过热表面防护的安装条件，必须符合图7.1 或 7.2。

烤箱必须放置在距离任意一侧墙壁不少于200毫米的位置，墙壁应高于炉灶面。

使用的装饰面合成材料和胶必须耐90°C的温度，避免开胶或变形。

不要在烤箱或在两侧500毫米内后部安装窗帘。

如果烤箱位于基座上，需要提供安全措施防止掉落。

烤箱必须放在耐热的区域。

该区域的墙壁必须不能高于操作台，同时能够耐高于室温75 °C 的温度。

不要把烤箱安装在易燃材料附近（如：窗帘）。

■ 1级(图7.1)煤气连接使用橡胶软管，必须可见并易于检查，或者使用硬的或者软的金属管。

在烤箱和任何邻近的家具之间保持2毫米空间，不能高于炉灶面。

■ 2级■ 1子级(图7.2)煤气连接使用硬的或者软的金属管。

按照尺寸炉灶系统半快速灶头半快速灶头双灶头辅助灶头快速灶头控制功能描述备注：1.右前灶头控制旋钮2. 右后灶头控制旋钮3. 中间灶头控制旋钮4. 左后灶头控制旋钮5. 左前灶头控制旋钮6. 多功能烤箱恒温器控制旋钮7. 多功能烤箱功能选择器控制旋钮8. 电子程序器9. 烤箱温度指示灯烤箱安装了冷却扇，使控制器达到最佳效率，确保维持最低表面温度。

当烤箱工作时，冷却扇电机的开与关取决于温度的高低。

甚至在烤箱关闭后，冷却扇可能还会持续工作，这取决于烹饪温度和时间。

该持续时间取决于前一次烹饪的温度和持续时间。

炉盘炉灶1. 辅助灶头 (A) 1,00 kW2. 半快速灶头(SR) 1,75 kW3. 快速灶头(R) 3,00 kW4. 双灶头(D) 4,50 kW备注:电打火和旋钮是一体设计。

烤箱安装了安全阀系统，当火焰意外熄灭时，煤气流会停止供应。

注意：如果灶头意外熄灭，用控制旋钮关闭煤气，至少等待1分钟后再尝试点火。

在其所在安装处，炉盘会对环境产生热量和湿气。

通过打开自然排风口或安装抽油烟机与出口管连接，把烟排出去，确保烹饪区域通风良好。

AT91SC25672RC资料

1FeaturesGeneral•Based on the ARM ® SC100™ SecurCore ™ 32-bit RISC Processor •Two Instruction Sets –ARM High-performance 32-bit Instruction Set –Thumb ® High-code-density 16-bit Instruction Set •4-Gbyte Linear Address Space•Von Neumann Load/Store Architecture–Single 32-bit Data Bus for Instructions and Data •3-stage Pipeline Architecture–Fetch, Decode and Execute Stages •8-bit, 16-bit, and 32-bit Data Types•On-chip Programmable System Clock up to 50 MHz •Very Low Power Consumption: –Industry Leader in MIPS/Watt–Low-power Idle and Power-down Modes •Bond Pad Locations Conforming to ISO 7816-2•ESD Protection to ± 6000V•Operating Ranges: 2.7V to 5.5V, GSM/3G Compliant, PC Industry Compatible, EMVMemory•256K Bytes of ROM Program Memory•72K Bytes of EEPROM User Memory, Including 256 OTP Bytes–Typically More than 500,000 Write/Erase Cycles •10K Bytes of RAMPeripherals•Two I/O Ports –Configurable to Support Communication Protocols, Including ISO 7816-3 and 2-wire Protocols •ISO 7816 Controller–Up to 625 kbps at 5 MHz•Serial Peripheral Interface (SPI) Controller (up to 12 MHz)•Two 16-bit Timers•Random Number Generator (RNG)•2-level, 12-vector Interrupt Controller •Hardware DES and Triple DES •Checksum Accelerator •CRC 16 / 32 Engine•32-bit Cryptographic Accelerator for Public Key Operations Including GF(2N )–RSA, DSA, ECC, Diffie-Hellman •Advanced MPU•High-performance Hardware Java Card AcceleratorSecurity•Dedicated Hardware for Protection Against SPA/DPA Attacks •Advanced Protection Against Physical Attack •Environmental Protection Systems •Voltage and Frequency Monitors•Secure Memory Management/Access ProtectionDevelopment Tools•Hardware Development Support on the ATV3-91SC Voyager Emulation Platform. Seethe ATV3-91SC Emulator Product Preview for Further Details.Note: This is a summary document. A complete document isavailable under NDA. For more information, please contact your local Atmel sales office.2AT91SC25672RC1575CS–SMIC–09/03DescriptionThe AT91SC25672RC is a low-power, high-performance, 32-bit RISC microcontroller with ROM program memory, EEPROM data memory, and cryptographic accelerator,based on the new ARM SC100 advanced secure processor. The SC100 embedded core is the first member of the ARM SecurCore family. This general-purpose 32-bit pro-cessor offers high performance, very low power consumption, and additional features to help combat fraud.The AT91SC25672RC features 72K bytes of high-performance EEPROM (fast erase/write time, high endurance). This allows system developers to offer their custom-ers a true 64K bytes EEPROM, while still being able to use the remaining 8K bytes for their own purposes (e.g. customization and patches).The cryptographic accelerator featured in the AT91SC series is the new AdvX ™. It is based on a 32-bit multiplier-accumulator architecture which is designed to perform fast encryption and authentication functions. This enables fast computation and low-power operation. The AdvX, in conjunction with controlling firmware running within the SC100core, supports standard finite fields arithmetic functions (including RSA, DSA, DH, ECC)and GF(2N ).On top of the SC100´s MPU, a real hardware firewall can be used to increase the overall security level of the application without intense software development.Unique hardware features significantly accelerate the execution of Java Card Byte Code by removing the common software bottlenecks encountered during the implementation of a Java Virtual Machine.Additional security features include power and frequency protection logic, logical scram-bling on program data and addresses, power analysis countermeasures and memory accesses controlled by a supervisor mode.Pin ConfigurationThe AT91SC25672RC pinout conforms to the ISO 7816-2 interface. It also provides a second I/O port.Note:By convention, the RST pin corresponds to the RST signal of the ISO 7816-3 Protocol.Both are active low.GND Ground (reference voltage)V CC Power supply inputI/O0Input or output for serial dataI/O1Second input or output for serial dataAlso used as Slave Select line for the SPI controller MOSI SPI Master output – Slave input MISO SPI Master input – Slave output SCK SPI ClockCLK Clock signal input to internal clock operating circuit RSTReset signal input, a low state stops the ARM core3AT91SC25672RC1575CS–SMIC–09/03Architectural OverviewThe SC100 is a 3-stage pipeline, 32-bit RISC processor. It uses a Von Neumann load/store architecture, which is characterized by a single data and address bus for instructions and data.The SC100 processor employs a unique architectural strategy known as Thumb ®, a super-reduced instruction set that is ideally suited for high-volume applications with memory restrictions, and applications where code density is an important factor. Essen-tially, the SC100 processor has two instruction sets:•The standard ARM instruction set uses 32-bit instructions and offers maximum performance.•The Thumb instruction set uses 16-bit instructions and offers maximum code density.Both instruction sets operate on 8-bit, 16-bit, and 32-bit data types.The Thumb´s 16-bit instruction length allows it to achieve almost twice the density of standard ARM code, while retaining most of the ARM´s performance advantage over a traditional 16-bit processor using 16-bit registers. This is possible because the 16-bit Thumb instructions operate on the same 32-bit register set as the 32-bit ARM instruc-tions. Thumb code can be up to 35% smaller than the equivalent ARM code, while providing 160% of the performance of an equivalent ARM processor connected to a 16-bit memory system.© Atmel Corporation 2003.Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life support devices or systems.Atmel HeadquartersAtmel OperationsCorporate Headquarters2325 Orchard Parkway San Jose, CA 95131TEL 1(408) 441-0311FAX 1(408) 487-2600EuropeAtmel SarlRoute des Arsenaux 41Case Postale 80CH-1705 Fribourg SwitzerlandTEL (41) 26-426-5555FAX (41) 26-426-5500AsiaRoom 1219Chinachem Golden Plaza 77 Mody Road Tsimhatsui East Kowloon Hong KongTEL (852) 2721-9778FAX (852) 2722-1369Japan9F, Tonetsu Shinkawa Bldg.1-24-8 ShinkawaChuo-ku, Tokyo 104-0033JapanTEL (81) 3-3523-3551FAX (81) 3-3523-7581Memory2325 Orchard Parkway San Jose, CA 95131TEL 1(408) 441-0311FAX 1(408) 436-4314Microcontrollers2325 Orchard Parkway San Jose, CA 95131TEL 1(408) 441-0311FAX 1(408) 436-4314La Chantrerie BP 7060244306 Nantes Cedex 3, France TEL (33) 2-40-18-18-18FAX (33) 2-40-18-19-60ASIC/ASSP/Smart CardsZone Industrielle13106 Rousset Cedex, France TEL (33) 4-42-53-60-00FAX (33) 4-42-53-60-011150 East Cheyenne Mtn. Blvd.Colorado Springs, CO 80906TEL 1(719) 576-3300FAX 1(719) 540-1759Scottish Enterprise Technology Park Maxwell BuildingEast Kilbride G75 0QR, Scotland TEL (44) 1355-803-000FAX (44) 1355-242-743RF/AutomotiveTheresienstrasse 2Postfach 353574025 Heilbronn, Germany TEL (49) 71-31-67-0FAX (49) 71-31-67-23401150 East Cheyenne Mtn. Blvd.Colorado Springs, CO 80906TEL 1(719) 576-3300FAX 1(719) 540-1759Biometrics/Imaging/Hi-Rel MPU/High Speed Converters/RF DatacomAvenue de Rochepleine BP 12338521 Saint-Egreve Cedex, France TEL (33) 4-76-58-30-00FAX (33) 4-76-58-34-80e-mailliterature@Web Site1575CS–SMIC–09/03 xMATMEL ® is the registered trademark of Atmel; AdvX ™ is the trademark of Atmel.ARM ®, Thumb ®, and ARM Powered ® are the registered trademarks of ARM Ltd. SC100™ and SecurCore ™ are the trademarks of ARM Ltd. Other terms and product names may be the trademarks of others.。

HT95CXXX资料

HT95CXXXCID Type Phone 8-Bit MCURev.1.501May 26,2005Features·Provide MASK type and OTP type version ·Operating voltage range:-FSK:3.0V~5.5V -Others:2.4V~5.5V ·Program ROM-HT95C400/40P:16K ´16bits -HT95C300/30P:8K ´16bits -HT95C200/20P:8K ´16bits ·Data RAM-HT95C400/40P:2880´8bits -HT95C300/30P:2112´8bits -HT95C200/20P:1152´8bits ·Bidirectional I/O lines-HT95C400/40P:40~28I/O lines -HT95C300/30P:28~16I/O lines -HT95C200/20P:28~20I/O lines ·16-bit table read instructions ·Subroutine nesting-HT95C400/40P:12levels -HT95C300/30P:8levels -HT95C200/20P:8levels·Timer-Two 16-bit programmable Timer/Event Counter -Real time clock (RTC)-Watchdog Timer (WDT)·Programmable frequency divider (PFD)·Dual system clock:32768Hz,3.58MHz·Four operating modes:Idle mode,Sleep mode,Green mode and Normal mode·Up to 1.117m s instruction cycle with 3.58MHz systemclock·All instructions in one or two machine cycles ·Built-in 3.58MHz DTMF Generator ·Built-in FSK decoder:-Supports Bell 202and V.23-Supports ring and line reversal detection ·Built-in dialer I/O·Built-in low battery detector·LCD driver-LCD contrast can be adjusted by software or exter-nal resistor-Support two LCD frame frequency 64Hz,128Hz -Support 16or 8common driver pins-Some segments or commons can option tobidirectional I/O lines-HT95C400/40P:48seg.´16com.-HT95C300/30P:48seg.´16com.-HT95C200/20P:24seg.´16com.·128-pin QFP packageApplications·Deluxe Feature Phone ·Caller ID Phone ·Cordless Phone·Fax and answering machines ·Other communication systemGeneral DescriptionThe HT95CXXX family MCU are 8-bit high performance RISC-like microcontrollers with built-in DTMF generator,FSK decoder and dialer I/O which provide MCU dialer implementation or system control features for telecom product applications.The phone controller has a built-in program ROM,data RAM,LCD driver and I/O lines for high end products design.In addition,for power man-agement purpose,it has a built-in frequency up conver-sion circuit (32768Hz to 3.58MHz)which provides dual system clock and four types of operation modes.For ex-ample,it can operate with low speed system clock rate of 32768Hz in green mode with little power consump-tion.It can also operate with high speed system clock rate of 3.58MHz in normal mode for high performance operation.To ensure smooth dialer function and to avoid MCU shut-down in extreme low voltage situation,the dialer I/O circuit is built-in to generate hardware di-aler signals such as on-hook,hold-line and hand-free.Built-in real time clock and programmable frequency di-vider are provided for additional fancy features in prod-uct developments.The device is best suited for feature phone products that comply with versatile dialer specifi-cation requirements of different areas or countries.Selection TableNote:Part numbers suffixed with²P²are OTP devices,all others are mask version devices.Block Diagram(HT95C400/40P)Rev.1.502May26,2005Pin AssignmentHT95C400/40PRev.1.503May26,2005HT95C300/30PRev.1.504May26,2005HT95C200/20PPin DescriptionPin Name I/O DescriptionCPUVDD¾Positive power supplyVDD2Positive power supply for FSK decoderVSS¾Negative power supply,groundVSS2Negative power supply for FSK decoder,groundX1I A32768Hz crystal(or resonator)should be connected to this pin and X2. X2O A32768Hz crystal(or resonator)should be connected to this pin and X1. XC I External low pass filter used for frequency up conversion circuit.RES I Schmitt trigger reset input,active low.INT/TMR1I Schmitt trigger input for external interrupt or Timer/Event Counter1.No internal pull-high resistor.For INT:Edge trigger activated on a falling edge.For TMR1:Activated on falling or rising transition edge,selected by software.TMR0I Schmitt trigger input for Timer/Event Counter0.No internal pull-high resistor.Activated on falling or rising transition edge,selected by software.Rev.1.505May26,2005Pin Name I/O Description LCD DriverSEG47~SEG0OorI/OLCD panel segment outputs.Some segment outputs can be optioned to Bidirectional input/output ports by software.(See the²LCD Driver²function)COM15~COM0OorI/OLCD panel common outputs.Some common outputs can be optioned to Bidirectional input/output ports by software.(See the²LCD Driver²function)VLCD I LCD driver power source. Normal I/OPA7~PA0I/O Bidirectional input/output ports.Schmitt trigger input and CMOS output.See mask option table for pull-high and wake-up functionPB7~PB0I/O Bidirectional input/output ports.Schmitt trigger input and CMOS output. See mask option table for pull-high functionPD7~PD0I/O Bidirectional input/output ports.Schmitt trigger input and CMOS output.See mask option table for pull-high functionPort D could be optioned to LCD signal output,see the²Input/Output Ports²functionPE3~PE0I/O Bidirectional input/output ports.Schmitt trigger input and CMOS output.See mask option table for pull-high functionPort E could be optioned to LCD signal output,see the²Input/Output Ports²functionPF7~PF0I/O Bidirectional input/output ports.Schmitt trigger input and CMOS output. See mask option table for pull-high functionPG3~PG0I/O Bidirectional input/output ports.Schmitt trigger input and CMOS output. See mask option table for pull-high functionDialer I/O(See the²Dialer I/O function²)HFI I Schmitt trigger input structure.An external RC network is recommended for input debouncing.This pin is pulled low with internal resistance of200k W typ.HFO O CMOS output structure.HDI I Schmitt trigger input structure.An external RC network is recommended for input debouncing.This pin is pulled high with internal resistance of200k W typ.HDO O CMOS output structure.HKS I This pin detects the status of the hook-switch and its combination with HFI/HDI can con-trol the PO pin output to make or break the line.PO O CMOS output structure controlled by HKS and HFI/HDI pins and which determines whether the dialer connects or disconnects the telephone line.DNPO O NMOS output structure.XMUTE O NMOS output ually,XMUTE is used to mute the speech circuit when trans-mitting the dialer signal.Rev.1.506May26,2005Pin Name I/O Description PeripheralsDTMF O This pin outputs dual tone signals to dial out the phone number.The load resistor should not be less than5k W.MUSIC O This pin outputs the single tone that is generated by the PFD generator.TIP I Input pin connected to the tip side of the twisted pair wires.It is internally biased to1/2 VDD when the device is in power-up mode.This pin must be DC isolated from the line.RING I Input pin connected to the ring side of the twisted pair wires.It is internally biased to1/2 VDD when the device is in power-up mode.This pin must be DC isolated from the line.RDET1I This pin detects ring energy on the line through an attenuating network.RTIME I/O Schmitt trigger input and NMOS output pin which functions with RDET1pin to make an RC network that performs ring detection function.LBIN I This pin detects battery low through external R1/R2to determine threshold voltage.Absolute Maximum RatingsSupply Voltage..........................V SS-0.3V to V SS+5.5V Storage Temperature...........................-50°C to125°C Input Voltage..............................V SS-0.3to V DD+0.3V Operating Temperature..........................-20°C to70°CNote:These are stress ratings only.Stresses exceeding the range specified under²Absolute Maximum Ratings²may cause substantial damage to the device.Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil-ity.Electrical Characteristics Ta=25°CSymbol ParameterTest ConditionsMin.Typ.Max.Unit V DD ConditionsCPUI IDL Idle Mode Current5V 32768Hz off,3.58MHz off,CPU off,LCD off,WDT off,no load¾¾2m AI SLP Sleep Mode Current5V 32768Hz on,3.58MHz off,CPU off,LCD off,WDT off,no load¾1730m AI GRN Green Mode Current5V 32768Hz on,3.58MHz off,CPU on,LCD off,WDT off,no load¾2850m AI NOR Normal Mode Current5V 32768Hz on,3.58MHz on,CPU on,LCD on,WDT on,DTMF generator off,FSK decoder off,no load¾ 1.83mAV IL I/O Port Input Low Voltage5V¾0¾1VV IH I/O Port Input High Voltage5V¾4¾5VI OL I/O Port Sink Current5V¾46¾mAI OH I/O Port Source Current5V¾-2-3¾mAR PH Pull-high Resistor5V¾1030¾k WV LBIN Low Battery DetectionReference Voltage5V¾ 1.05 1.15 1.25V Rev.1.507May26,2005Symbol ParameterTest ConditionsMin.Typ.Max.Unit V DD ConditionsLCD DriverV LCD LCD Panel Power Supply¾¾¾35VI LCD LCD Operation Current¾V LCD=5V,32768Hz,no load¾¾100m A Dialer I/OI XMO XMUTE Leakage Current 2.5V XMUTE pin=2.5V¾¾1m A I OLXM XMUTE Sink Current 2.5V XMUTE pin=0.5V1¾¾mA I HKS HKS Input Current 2.5V HKS pin=2.5V¾¾0.1m A R HFI HFI Pull-low Resistance 2.5V V HFI=2.5V¾200¾k W R HDI HDI Pull-high Resistance 2.5V V HDI=0V¾200¾k W I OH2HFO Source Current 2.5V V OH=2V-1¾¾mA I OL2HFO Sink Current 2.5V V OL=0.5V1¾¾mA I OH3HDO Source Current 2.5V V OH=2V-1¾¾mA I OL3HDO Sink Current 2.5V V OL=0.5V1¾¾mA I OH4PO Source Current 2.5V V OH=2V-1¾¾mA I OL4PO Sink Current 2.5V V OL=0.5V1¾¾mA I OL5DNPO Sink Current 2.5V V OL=0.5V1¾¾mA DTMF GeneratorV TDC DTMF Output DC Level¾¾0.45V DD¾0.7V DD VV TOL DTMF Sink Current¾V DTMF=0.5V0.1¾¾mA V TAC DTMF Output AC Level¾Row group,R L=5k W120155180mVrms R L DTMF Output Load¾THD£-23dB5¾¾k W A CR Column Pre-emphasis¾Row group=0dB123dB THD Tone Signal Distortion¾R L=5k W¾-30-23dB FSK DecoderInput Sensitivity:TIP,RING¾¾-40-45¾dBmTransmission Rate5V¾118812001212baud S/N Signal to Noise Ratio¾¾¾20¾dB Band-pass FilterFrequency ResponseRelative to1700Hz at0dBm£60Hz 550Hz 2700Hz ³3300Hz ¾¾¾¾¾¾-64-4-3-34¾¾¾¾dBCarrier Detect Sensitivity¾¾¾-48¾dBmt SUPD Power Up to FSK Signal SetUp Time¾¾15¾¾ms Rev.1.508May26,2005Functional DescriptionExecution FlowThe system clock for the telephone controller is derived from a32768Hz crystal oscillator.A built-in frequency up conversion circuit provides dual system clock,namely; 32768Hz and3.58MHz.The system clock is internally divided into four non-overlapping clocks.One instruc-tion cycle consists of four system clock cycles.Instruc-tion fetching and execution are pipelined in such a way that a fetch takes an instruction cycle while decoding and execution takes the next instruction cycle.The pipelining scheme causes each instruction to be effec-tively executed in a instruction cycle.If an instruction changes the program counter,two instruction cycles are required to complete the instruction.Program Counter-PCThe program counter(PC)controls the sequence in which the instructions stored in the program ROM are executed and its contents specify a full range of pro-gram memory.After accessing a program memory word to fetch an instruction code,the contents of the program counter are incremented by1.The program counter then points to the memory word containing the next in-struction code.When executing a jump instruction,conditional skip ex-ecution,loading PCL register,subroutine call,initial re-set,internal interrupt,external interrupt or return from subroutine,the program counter manipulates the pro-gram transfer by loading the address corresponding to each instruction.The conditional skip is activated by in-structions.Once the condition is met,the next instruc-tion,fetched during the current instruction execution,is discarded and a dummy cycle replaces it to get the proper instruction.Otherwise proceed to the next in-struction.The program counter lower order byte register (PCL:06H)is a readable and write-able register.Moving data into the PCL performs a short jump.The destina-tion will be within256locations.When a control transfer takes place,an additional dummy cycle is required.Execution FlowModeProgram Counter*13*12*11*10*9*8*7*6*5*4*3*2*1*0Initial reset00000000000000 External interrupt00000000000100 Timer/Event Counter0overflow00000000001000 Timer/Event Counter1overflow00000000001100 Peripheral interrupt00000000010000 RTC interrupt00000000010100 Dialer I/O interrupt00000000011000 Skip Program Counter+2(within current bank)Loading PCL*13*12*11*10*9*8@7@6@5@4@3@2@1@0 Jump,call branch BP.5#12#11#10#9#8#7#6#5#4#3#2#1#0 Return from subroutine S13S12S11S10S9S8S7S6S5S4S3S2S1S0Program ROM AddressNote:*13~*0:Program counter bits S13~S0:Stack register bits#12~#0:Instruction code bits@7~@0:PCL bitsAvailable bits of program counter for HT95C400/40P:Bit13~Bit0Available bits of program counter for HT95C300/30P:Bit12~Bit0Available bits of program counter for HT95C200/20P:Bit12~Bit0Rev.1.509May26,2005Program Memory-ROMThe program memory is used to store the program in-structions which are to be executed.It also contains data,table,and interrupt entries,and is organized into 8K´16bits´2banks(HT95C400/40P)or8K´16bits (HT95C300/30P,HT95C200/20P)addressed by the program counter and table pointer.For the HT95C400/40P,the program memory is divided into2banks,each bank having a ROM Size8K´16bits. To move from the present ROM bank to a different ROM bank,the higher1bits of the ROM address are set by the BP(Bank Pointer),while the remaining13bits of the PC are set in the usual way by executing the appropriate jump or call instruction.As the14address bits are latched during the execution of a call or jump instruction, the correct value of the BP must first be setup before a jump or call is executed.When either a software or hard-ware interrupt is received,note that no matter which ROM bank the program is in,the program will always jump to the appropriate interrupt service address in Bank0.The original14bits address will be stored on the stack and restored when the relevant RET/RETI instruc-tion is executed,automatically returning the program to the original ROM bank.This eliminates the need for pro-grammers to manage the BP when interrupts occur. Certain locations in the program memory are reserved for special usage:·Location0000H(Bank0)This area is reserved for the initialization program.Af-ter chip power-on reset or external reset or WDT time-out reset,the program always begins execution at location0000H.·Location0004H(Bank0)This area is reserved for the external interrupt service program.If the INT/TMR1input pin is activated,the external interrupt is enabled and the stack is not full, the program begins execution at location0004H.·Location0008H(Bank0)This area is reserved for the Timer/Event Counter0in-terrupt service program.If a timer interrupt results from a Timer/Event Counter0overflow,the Timer/Event Counter0interrupt is enabled and the stack is not full,the program begins execution at loca-tion0008H.·Location000CH(Bank0)This location is reserved for the Timer/Event Counter 1interrupt service program.If a timer interrupt results from a Timer/Event Counter1overflow,the Timer/Event Counter1interrupt is enabled and the stack is not full,the program begins execution at loca-tion000CH.·Location0010H(Bank0)This location is reserved for the peripherals interrupt service program.When the FSK decoder detects a ringer or line reversal or FSK carrier signal or FSK packet data,the FSK interrupt is generated.If these interrupts occurred,the peripheral interrupt is en-abled and the stack is not full,the program begins ex-ecution at location0010H.The programmer could distinguish from these interrupts from the FSKS regis-ter.·Location0014H(Bank0)This location is reserved for real time clock(RTC)in-terrupt service program.When RTC generator is en-abled and time-out occurs,the RTC interrupt is enabled and the stack is not full,the program begins execution at location0014H.·Location0018H(Bank0)This location is reserved for the HKS pin edge transi-tion or HDI pin falling edge transition or HFI pin rising edge transition.If this condition occurs,the dialer I/O interrupt is enabled and the stack is not full,the pro-gram begins execution at location18H.Program MemoryRev.1.5010May26,2005Table LocationAny location in the ROM space can be used as look-up tables.The instructions²TABRDC[m]²(the current page,one page=256words)and²TABRDL[m]²(the last page)transfer the contents of the lower-order byte to the specified data memory,and the higher-order byte to TBLH(08H).For the HT95C400/40P,the instruction ²TABRDC[m]²is used for any page of any bank.Only the destination of the lower-order byte in the table is well-defined,and the higher-order byte of the table word is transferred to TBLH.The table pointer(TBLP)or (TBHP,TBLP for the HT95C400/40P)is a read/write register(07H)or(1FH,07H for the HT95C400/40P), which indicates the table location.Before accessing the table,the location must be placed in the(TBLP)or (TBHP,TBLP for the HT95C400/40P).The TBLH is read only and cannot be restored.If the main routine and the ISR(Interrupt Service Routine)both employ the table read instruction,the contents of the TBLH in the main routine are likely to be changed by the table read in-struction used in the ISR.Errors will then occur.Hence, simultaneously using the table read instruction in the main routine and the ISR should be avoided.However,if the table read instruction has to be applied in both the main routine and the ISR,the interrupt should be dis-abled prior to the table read instruction.It will not be en-abled until the TBLH has been backed-up.All table related instructions require two cycles to complete the operation.These areas may function as normal pro-gram memory depending on the requirements.Stack RegisterThis is a special part of the memory which is used to save the contents of the program counter only.The stack is organized into12levels(HT95C400/40P)or8 levels(HT95C300/30P,HT95C200/20P)and is neither part of the data nor part of the program space,and is neither readable nor writable.The activated level is in-dexed by the stack pointer(SP)and is neither readable nor writable.At a subroutine call or interrupt acknowl-edge signal,the contents of the program counter are pushed onto the stack.At the end of a subroutine or an interrupt routine,signaled by a return instruction(RET or RETI),the program counter is restored to its previous value from the stack.After a chip reset,the SP will point to the top of the stack.If the stack is full and an interrupt takes place,the interrupt request flag will be recorded but the acknowledge signal will be inhibited even if this interrupt is enabled.When the stack pointer is decremented(by RET or RETI),the interrupt will be ser-viced.This feature prevents stack overflow allowing the programmer to use the structure more easily.If the stack is full and a²CALL²is subsequently executed,stack overflow occurs and the first entry will be lost(only the most recent12or8,depending on various MCU type, returned addresses are stored).Data MemoryThe data memory is divided into four functional groups: special function registers,embedded control register, LCD display memory and general purpose memory. Most are read/write,but some are read only.The special function registers are located from00H to 1FH.The embedded control registers are located in the memory areas from20H to3FH.The remaining spaces which are not specified in the following table before the 40H are reserved for future expanded usage and read-ing these locations will get²00H².The general purpose data memory is divided into15banks(HT95C400/40P), 11banks(HT95C300/30P)or6banks(HT95C200/ 20P).The banks in the RAM are all addressed from40H to0FFH and they are selected by setting the value of the bank pointer(BP).HT95C400/40PInstruction(s)Table Location*13*12*11*10*9*8*7*6*5*4*3*2*1*0TABRDC[m]#5#4#3#2#1#0@7@6@5@4@3@2@1@0 TABRDL[m]111111@7@6@5@4@3@2@1@0HT95C300/30P,HT95C200/20PInstruction(s)Table Location*12*11*10*9*8*7*6*5*4*3*2*1*0TABRDC[m]P12P11P10P9P8@7@6@5@4@3@2@1@0 TABRDL[m]11111@7@6@5@4@3@2@1@0Note:*13~*0:Table location bits#7~#0:TBHP register bit7~bit0@7~@0:TBLP register bit7~bit0P12~P8:Current program counter bitsRev.1.5011May26,2005All of the data memory areas can handle arithmetic, logic,increment,decrement and rotate operations di-rectly.Except for some dedicated bits,each bit in the data memory can be set and reset by²SET[m].i²and ²CLR[m].i².They are also indirectly accessible through memory pointer registers(MP0or MP1).The bank1~bank14and bank27are only indirectly accessi-ble through memory pointer1register(MP1).The LCD display memory is located at bank1BH.They can be read and written to by the indirect addressing mode using memory pointer1(MP1).To turn the display On or Off,a²1²or²0²is written to the corresponding bit of the memory area.Special Register,Embedded Control Register,LCD Display Memory and General Purpose RAMBP (RAM Bank)Address Function DescriptionSupported for HT95CXXX400/P300/P200/PSpecial Function Register00H00H IAR0Indirect addressing register0ÖÖÖ00H01H MP0Memory pointer register0ÖÖÖ00H02H IAR1Indirect addressing register1ÖÖÖ00H03H MP1Memory pointer register1ÖÖÖ00H04H BP Bank Pointer registerÖÖÖ00H05H ACC AccumulatorÖÖÖ00H06H PCL Program counter lower-order byte registerÖÖÖ00H07H TBLP Table pointerÖÖÖ00H08H TBLH Table higher-order byte registerÖÖÖ00H09H WDTS Watchdog Timer option setting registerÖÖÖ00H0AH STATUS Status registerÖÖÖ00H0BH INTC0Interrupt control register0ÖÖÖ00H0CH TMR0H Timer/Event Counter0high-order byteregisterÖÖÖ00H0DH TMR0L Timer/Event Counter0low-order byteregisterÖÖÖ00H0EH TMR0C Timer/Event Counter0control registerÖÖÖ00H0FH TMR1H Timer/Event Counter1high-order byteregisterÖÖÖ00H10H TMR1L Timer/Event Counter1low-order byteregisterÖÖÖ00H11H TMR1C Timer/Event Counter1control registerÖÖÖ00H12H PA Port A data registerÖÖÖ00H13H PAC Port A control registerÖÖÖ00H14H PB Port B data registerÖÖÖ00H15H PBC Port B control registerÖÖÖ00H16H DIALERIO Dialer I/O registerÖÖÖ00H18H PD Port D data registerÖÖÖ00H19H PDC Port D control registerÖÖÖ00H1AH PE Port E data registerÖÖÖ00H1BH PEC Port E control registerÖÖÖ00H1EH INTC1Interrupt control register1ÖÖÖ00H1FH TBHP Table high-order byte pointerÖ¾¾Rev.1.5012May26,2005BP (RAM Bank)Address Function DescriptionSupported for HT95CXXX400/P300/P200/PEmbedded Control Register00H20H DTMFC DTMF generator control registerÖÖÖ00H21H DTMFD DTMF generator data registerÖÖÖ00H22H LINE Line control registerÖÖÖ00H24H RTCC Real time clock control registerÖÖÖ00H26H MODE Operation mode control registerÖÖÖ00H28H LCDIO LCD segment and I/O option registerÖÖ¾00H29H FSKC FSK decoder control registerÖÖÖ00H2AH FSKS FSK decoder status registerÖÖÖ00H2BH FSKD FSK packet data registerÖÖÖ00H2DH LCDC LCD driver control registerÖÖÖ00H2EH PFDC PFD control registerÖÖÖ00H2FH PFDD PFD data registerÖÖÖ00H34H PF Port F data registerÖ¾¾00H35H PFC Port F control registerÖ¾¾00H36H PG Port G data registerÖ¾¾00H37H PGC Port G control registerÖ¾¾General Purpose RAM00H40H~FFH BANK0RAM General purpose RAM spaceÖÖÖ01H40H~FFH BANK1RAM General purpose RAM spaceÖÖÖ02H40H~FFH BANK2RAM General purpose RAM spaceÖÖÖ03H40H~FFH BANK3RAM General purpose RAM spaceÖÖÖ04H40H~FFH BANK4RAM General purpose RAM spaceÖÖÖ05H40H~FFH BANK5RAM General purpose RAM spaceÖÖÖ06H40H~FFH BANK6RAM General purpose RAM spaceÖÖ¾07H40H~FFH BANK7RAM General purpose RAM spaceÖÖ¾08H40H~FFH BANK8RAM General purpose RAM spaceÖÖ¾09H40H~FFH BANK9RAM General purpose RAM spaceÖÖ¾0AH40H~FFH BANK10RAM General purpose RAM spaceÖÖ¾0BH40H~FFH BANK11RAM General purpose RAM spaceÖ¾¾0CH40H~FFH BANK12RAM General purpose RAM spaceÖ¾¾0DH40H~FFH BANK13RAM General purpose RAM spaceÖ¾¾0EH40H~FFH BANK14RAM General purpose RAM spaceÖ¾¾LCD RAM Display Memory1BH40H~9FH LCD RAM LCD RAM mapping space for COM0~COM15(see²LCD Driver²function)Rev.1.5013May26,2005Indirect Addressing RegisterLocation00H and02H are indirect addressing registers that are not physically implemented.Any read/write op-eration of[00H]and[02H]will access the memory pointed to by MP0and MP1,respectively.Reading loca-tion[00H]or[02H]indirectly returns the result00H, while writing it leads to no operation.MP0is indirectly addressable in bank0,but MP1is available for all banks by switch BP[04H].If BP is unequal to00H,the indirect addressing mode to read/write operation from00H~3FH will return the result as same as the value of bank0.The memory pointer registers MP0and MP1are8-bits registers,and the bank pointer register BP is6-bits reg-ister for the HT95C400/40P or5-bits for the other de-vices in the series.AccumulatorThe accumulator is closely related to ALU operations.It is also mapped to location05H of the data memory and can operate with immediate data.All data movement between two data memory locations must pass through the accumulator.Arithmetic and Logic Unit-ALUThis circuit performs8-bit arithmetic and logic opera-tions and provides the following functions:·Arithmetic operations(ADD,ADC,SUB,SBC,DAA)·Logic operations(AND,OR,XOR,CPL)·Rotation(RL,RR,RLC,RRC)·Increment and Decrement(INC,DEC)·Branch decision(SZ,SNZ,SIZ,SDZ,etc.)The ALU not only saves the results of a data operation but also changes the status register.Status Register-STATUSThis status register contains the carry flag(C),auxiliary carry flag(AC),zero flag(Z),overflow flag(OV),power down flag(PDF),and watchdog time-out flag(TO).It also records the status information and controls the op-eration sequence.Except for the TO and PDF flags,bits in the status regis-ter can be altered by instructions,similar to the other registers.Data written into the status register will not change the TO or PDF flag.Operations related to the status register may yield different results from those in-tended.The TO flag can be affected only by system power-up,a WDT time-out or executing the²CLR WDT²or²HALT²instruction.The PDF flag can be affected only by executing the²HALT²or²CLR WDT²instruction or during a system power-up.The Z,OV,AC and C flags generally reflect the status of the latest operations.On entering the interrupt sequence or executing the subroutine call,the status register will not be automati-cally pushed onto the stack.If the contents of the status are important and if the sub-routine can corrupt the status register,precautions must be taken to save it.InterruptThe telephone controller provides an external interrupt, internal timer/event counter interrupt,a peripheral inter-rupt,an internal real time clock interrupt and internal di-aler I/O interrupt.The Interrupt Control Registers0and Interrupt Control Register1both contains the interrupt control bits that set the enable/disable and the interrupt request flags.Once an interrupt subroutine is serviced,all the other in-terrupts will be blocked(by hardware clearing the EMI bit).This scheme may prevent any further interrupt nest-ing.Other interrupt requests may occur during this inter-val but only the interrupt request flag is recorded.If a certain interrupt requires servicing within the service routine,the EMI bit and the corresponding bit of the INTC0(INTC1)may be set to allow interrupt nesting.Bit bel Function0C C is set if the operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation;otherwise C is cleared.Also it is affected by a rotate through carry instruction.1AC AC is set if the operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction;otherwise AC is cleared.2Z Z is set if the result of an arithmetic or logic operation is0;otherwise Z is cleared.3OV OV is set if the operation results in a carry into the highest-order bit but not a carry out of the highest-order bit,or vice versa;otherwise OV is cleared.4PDF PDF is cleared when either a system power-up or executing the²CLR WDT²instruction.PDF is set by executing the²HALT²instruction.5TO TO is cleared by a system power-up or executing the²CLR WDT²or²HALT²instruction.TO is set by a WDT time-out.6,7¾Unused bit,read as²0²STATUS(0AH)RegisterRev.1.5014May26,2005。

ZERO-TURN 系列信息手册说明书

BY CUSTOM EQUIPMENT LLCPARTS MANUALZT-1230ZT-1630SERIAL NO.MOBILE ELEVATING WORKPLATFORMSANSI A92.20CSA B354.6:17ZERO-TURN SERIESOriginal instructions written in English.The serial number is located above the control side caster. An additional reference is on the platform above the manual box.FOREWORDThis manual refers to serial number(s):ZT-1230 ZT12-50001 -ZT-1630 ZT16-50001 -For older Serial Numbers refer to our website: /Manuals.htmGeneral Information2647 Hwy 175Richfield, WI 53076U.S.A.+1-262-644-1300 +1-262-644-1320 Service Information+1-262-297-5195**************************Parts Information+1-262-297-5196************************Register your Hy-Brid Lift at:/RegisterOnline.htm Register your Hy-Brid Lift to:• Recieve product updates and recalls• Recieve service bulletins, product and partrecalls, and other important notifications • Comply with ANSI A92.20 Standards • Provide better records for serviceREGISTERING YOUR MEWP WITH THE MANUFACTURER IS AN ANSI A92.20REQUIREMENT.FIGURE 1: Serial Number LocationTABLE OF CONTENTS TABLE OF CONTENTS FOREWORD (3)TABLE OF CONTENTS (4)SECTION 1 BASE (6)1.1 | POTHOLE GUARD PARTS (6)1.2 | CASTER PARTS (7)1.3 | CASTER SUBPARTS (8)1.4 | REAR WHEEL PARTS (9)1.5 | DRIVE PARTS (10)1.6 | PUMP PARTS (11)1.7 | PUMP SUBPARTS (12)1.8 | MISCELLANEOUS BASE PARTS (13)SECTION 2 CONTROLS (14)2.1 | CONTROL PARTS (14)2.2 | MAIN CABLE PARTS (16)2.3 | UPPER CONTROL PARTS (17)2.4 | LOWER CONTROL PARTS (18)2.5 | MASTER POWER SWITCH (19)SECTION 3 SCISSORS (20)3.1 | SCISSOR PARTS (20)3.2 | CYLINDER SUBPARTS (21)SECTION 4 PLATFORM & RAILS (22)4.1 | PLATFORM & RAILS PARTS (22)SECTION 5 DECALS (26)5.1 | ZT-1230 DECALS (26)5.2 | ZT-1630 DECALS (28)SECTION 6 OPTIONS & MISCELLANEOUS (30)6.1 | OPTIONS (30)NOTES ........................................................................................................................................................................................32FIGURE 1: Serial Number Location .. (3)FIGURE 2: Pothole Guard Parts (6)FIGURE 3: Caster Parts (7)FIGURE 4: Caster Subparts (8)FIGURE 5: Rear Wheel Parts (9)FIGURE 6: Drive Parts (10)FIGURE 7: Pump Parts (11)FIGURE 8: Pump Subparts (12)FIGURE 9: Miscellaneous Base Parts (13)FIGURE 10: Controls/Electrical Parts (14)FIGURE 11: Main Cable Parts (16)FIGURE 12: Upper Control Parts (17)FIGURE 13: Lower Control Parts (18)FIGURE 14: Master Power Switch (19)FIGURE 15: Scissor Parts (20)FIGURE 16: Cylinder Subparts (21)FIGURE 17: Platform & Rail Parts (22)FIGURE 18: ZT-1230 Decals (26)FIGURE 19: ZT-1630 Decals (28)FIGURE 20: Options & Miscellaneous Parts (30)REVISION LOG:REV A.................................................................................................................................................................................September 2020 REV B.............................................................................................................................................................................................June 2021 REV C..................................................................................................................................................................................December 2021 REV D..............................................................................................................................................................................................May 2022 INDEX OF FIGURES1.1 | POTHOLE GUARD PARTSFIGURE 2: Pothole Guard PartsItem #Part Number Part Description Notes Qty Superseded By 1112-01-254-01BASE,PH BAR L (HBMD)12112-01-255-01BASE,PH BAR R (HBMD)13RND-HB-002-P PIN,HINGE,0.50,5.044129-21-263-14-K ASM,BASE PH ARMS15129-21-263-09-K ASM,BASE PH ARMS16HARD-696-10.38X2.25 SPRING17HARD-804SPRING, EXT 3.5500 X .88018ELEC-123-5SWITCH,LIMIT,ROT LVR,NO/NC PO 21.2 | CASTER PARTSFIGURE 3: Caster PartsItem #Part Number Part Description Notes Qty Superseded By 1129-21-215-50-K ASM,CASTER12HARD-725COTTER PIN, 3/16 X 213WHEE-714-100 1.75 HUB,COVER14WHEE-716 1.06X1.75X0.16 WASH15WHEE-717SEAL16WHEE-718 1.06X0.58 TAPER ROLL BEARING27WHEE-7191-14 HEX SLOTTED AXLE NUT18129-01-101-05HITCH PIN,5/8 X 519129-01-102-03COILED SPRING PIN, 5/32,1 L1FIGURE 4: Caster Subparts1.3 | CASTER SUBPARTSItem #Part Number Part Description Notes Qty Superseded By 1129-01-260-01BASE,CASTER WLDMNT12129-06-023-02BASE,CASTER PIN13HARD-001-2 1.00X1.00 SLEEVE BEARING,PTFE4 4HARD-021RET RING 1.02 5WHEE-609-SS WASHER, 1.015ID,2OD,.03 THK SS3 6WHEE-706-KIT WHL,8X2,GREY NM BORE 1.252 7WHEE-708 2.00 WHL, RACEWAY SPLIT 2FIGURE 5: Rear Wheel PartsItem #Part Number Part Description Notes Qty Superseded By 1112-01-572-02HUB,KEYWAY 1.0,2.012WHEE-624WHL,12X4,NM RUBBER13WHEE-735WHL,LUG NUT 7/16-2051.4 | REAR WHEEL PARTS1.5 | DRIVE PARTSFIGURE 6: Drive PartsItem #Part Number Part Description Notes Qty Superseded By 1129-01-408-02BASE,REAR PIVOT12129-01-455-04BASE,DELRIN SLIDER23129-06-606-02PIN,DRIVE MNT,1.2500,14.060014ELEC-790DRIVE MOTOR,24V,HB,AUB25HARD-001DU BEARING, 1.25 ID, 1 LENGTH26HARD-641-25.25X.94U X 1.13L CLEVIS PIN87129-01-415-02BASE,CAM BAR WLDMNT18129-01-416-02BASE,CAM LINK WLDMNT19129-01-445-04BASE,CAM SHAFT GUIDE210129-06-401-02PIN,PIVOT LOCK CONNECTING ARM211HARD-4010.38X0.50 SLEEVE BEARING,PTFE412HARD-157KEY,0.25 X 0.25 X 2213HARD-021RET RING 1.0214WHEE-625-KIT WHL,12X4 NM RUBBER W /HUB 2FIGURE 7: Pump PartsItem #Part Number Part Description Notes Qty Superseded By 1ELEC-634D TERMINAL BOOT BLACK12HYDR-019FITTING,ELB,NPTM 3/8-1/4 PUSH13HYDR-022-3LOW PRESSURE HOSE QTY IN 1324HYDR-032HYDRAULIC OILNot available as areplacement part.Replace with Flomite#150, Dexron II,Mobil-DTE 2 or equivalent.15HYDR-050-16E PUMP,24VDC,0.132,0.7516HYDR-600HOSE ASM,HB-2X17HYDR-677FITNG,ELB,JICM 9/16-SAEORM #611.6 | PUMP PARTS1.7 | PUMP SUBPARTSFIGURE 8: Pump SubpartsItem #Part Number Part Description Notes Qty Superseded By 1HYDR-101MANIFOLD,KTI UNIVERSAL12HYDR-105PUMP MOTOR,24V,0.132 CIR13HYDR-107PRESSURE RELIEF,ADJ,3000 PST14HYDR-108#8 POPPET CHECK VALVE 0.3 BAR15HYDR-119PUMP RESERVOIR,0.75 GAL16HYDR-664COIL, 18V17HYDR-665VALVE,NO,2W/2P,#8,UP18HYDR-670PLUG,SAEOR M #6,HEX SOCKET 1/419HYDR-690FITTING,STR,3/4 NPTM X 3/8 NPTF110HYDR-692SOLENOID,24V,100 AMP111HYDR-698PLUG, SAE#8112HYDR-019FITTING,ELB,NPTM 3/8-1/4 PUSH113HYDR-677FITTING,ELB,JICM 9/16-SAEORM #611.8 | MISCELLANEOUS BASE PARTSFIGURE 9: Miscellaneous Base PartsItem #Part Number Part Description Notes Qty Superseded By 1129-01-433-19BASE,DRIVE COVER12129-01-434-19L BASE,SIDE WIRE COVER13129-01-434-19R BASE,SIDE WIRE COVER14129-05-211-19BASE,COVER WLDMNT L15129-05-219-19BASE,COVER WLDMNT R16129-01-232-02BASE,SCISSORS LOCK27HARD-0670.38SNAP BUTTON,SINGLE END28HARD-651RING, 1.4 ID19HARD-644-04LOW FRICTION CABLE, 43/52110112-01-552-01BASE,STEP FULL PERFORATED111129-01-250-04BEARING RACE1FIGURE 10: Controls/Electrical Parts Item #Part Number Part Description Notes Qty Superseded By 1129-21-404-55ASM,CTL UPR ZT S412129-21-407-51ASM,CTL LWR (HBMD S4)13129-21-419-50CTL,WIRE HARNESS BRAKES24129-21-532-50CTL,WIRE HARNESS MAIN ZT163015HARD-641-27.25X2.81U X 3.00L CLEVIS PIN16129-01-090-50CABLE,6GA,RED,10,R/R,.38 EYES17129-01-090-51CBL,6GA,RED,42&50,R/R,.38 EYES18ELEC-641A CABLE,6GA,BLACK,63,B/B29ELEC-641C CABLE,6GA,RED,50,B/R110ELEC-641E CABLE,6GA,BLACK,22.0000,B/B111ELEC-634C TERMINAL COVER (RED)312HYDR-666SOLENOID,24V,ISOLATED,SPST113129-21-533-50-K BOARD,DRIVE/LIFT CTL ZT S5114ELEC-047-5BATTERY,12V,GR27 AGM215ELEC-634D TERMINAL BOOT (BLACK)216129-01-428-01BASE,CGHR MNT PLATE PRO117ELEC-795CHARGER,24V 12A PRO118ELEC-123-5SWITCH,LIMIT,ROT LVR,NO/NC PO219ELEC-959FUSE, 20A ATC120ELEC-646-5TOOL,PGT PROGRAMMER,EZ-CAL121129-21-535-50CTL,WIRE HARNESS BRAKES1SECTION 2 CONTROLS SECTION 2 CONTROLS 2.1 | CONTROL PARTSItem #Part Number Part Description NotesQty Superseded By1ELEC-749CONN,CPC,PLUG,14 POS 12ELEC-750CABLE CLAMP,CPC,BACK SHELL 13ELEC-752CONTACT PIN,CPC,14-18GA122.2 | MAIN CABLE PARTSFIGURE 11: Main Cable PartsSECTION 2 CONTROLSItem #Part Number Part Description NotesQty Superseded By1129-03-441-01RAIL,CTL UPR PANEL 12129-03-442-01RAIL,CTL BOX LWR 13129-03-443-01RAIL,CTL MNT CHNL14ELEC-609JOYSTICK,MULTI-AXIS W/GUARD 15ELEC-071-KIT SWITCH,PUSH/PULL RED E-STOP 16ELEC-067SWITCH,PUSH BTN,GREEN 17ELEC-068SWITCH, ROTARY MAINT. ,2-POS 18ELEC-892POWER PORT,USB 12/24V 19ELEC-636LED, RED110ELEC-635-4ALARM, CONTINUOUS 111129-21-435-50CTL,WIRE HARNESS,UPR CTL 112ELEC-751CONN,CPC,RECEPT,14 POS12.3 | UPPER CONTROL PARTSFIGURE 12: Upper Control Parts2.4 | LOWER CONTROL PARTSFIGURE 13: Lower Control PartsSECTION 2 CONTROLSSECTION 2 CONTROLSItem #Part Number Part DescriptionNotesQty Superseded By1129-05-405-19BASE,CTL PANEL WLDMNT 12ELEC-633-4SWITCH,MASTER DISCONNECT 13ELEC-610-2METER,HOUR14ELEC-635-4ALARM, CONTINUOUS15ELEC-071BUTTON,PUSH/PULL RED E-STOP 16ELEC-071BASE SWITCH,BASE/COLLAR 27ELEC-072CONTACT BLOCK,NC 18ELEC-603CONTACT BLOCK,NO29ELEC-073D SWITCH,KEY,3-POS MAINTAINED 110ELEC-636LED,RED 111ELEC-610-4METER,VOLT,24V 112ELEC-133B SWITCH,ROCKER DPDT 113ELEC-073EKEY KEY,SPARE114129-21-436-50CTL,WIRES DRIVE MOTORS115129-21-322-50CTL,WIRE HARNESS PRESSURE SENSOR12.5 | MASTER POWER SWITCHFIGURE 14: Master Power SwitchItem #Part Number Part DescriptionNotesQty Superseded By1ELEC-633-5SWITCH KNOB,MASTER DISCONNECT1FIGURE 15: Scissor PartsItem #Part Number Part Description Notes Qty Superseded By 110210001-02 1.25X2.00X0.69 SHAFT COLLAR 62HARD-022 1.25 RETAINING RING,EXT 23129-21-009-50-K ASM,ROLLER,1.25 W/DU 44HARD-001DU BEARING, 1.25 ID, 1 LENGTH 15129-07-001-02ROLLER,1.25,1.75 OD,1.250016HARD-694.28 PUSH-IN BUMPER 127129-02-569-04SCISSOR,ANG MNT SINGLE 18129-21-523-50-K ASM,CYL ZT S519129-02-578-01SCISSOR,UPR CONDUIT 110ELEC-647SENSOR,ANGLE 2SECTION 3 SCISSORSSECTION 3 SCISSORS3.1 | SCISSOR PARTS 3.2 | CYLINDER SUBPARTS FIGURE 16: Cylinder SubpartsItem #Part NumberPart Description Notes Qty Superseded By1HYDR-012-SK-BAI CYL,SEAL KIT 2.5 B, 1.5 R 12HARD-001DU BEARING, 1.25 ID, 1 LENGTH 43HYDR-019FITTING,ELB,NPTM 3/8-1/4 PUSH 14129-21-573-50-K ASM, MANIFOLD CYL S515HYDR-007-2E-4COIL,24V,HC 16HYDR-044-FL2GASKET FOR HIRSCHMANN CONN.17HYDR-044-FL1HIRSCHMANN CONNECTOR 18ELEC-648SENSOR,PRESSURE 19HYDR-007-2E-5VALVE,NC,2W/2P,#8,DWN,PULL,DEL 110HARD-621038X0.63X075 SLEEVE BEARING 111HARD-6500.44X0.88X0.44 SHAFT COLLAR 112HYDR-627-1FLOW CONTROL INLINE 2.0GPM 113HARD-644-11LOW FRICTION CABLE, 120.25/129114HARD-900SLEEVE,CABLE STOP 0.09115129-02-573-03SCISSOR,PATE E-DOWN ACT 1FIGURE 17: Platform & Rail Parts Item #Part Number Part Description Notes Qty Superseded By 1129-04-401-19PF,WLDMNT HBMD 12129-03-417-03PF,DECK 13MISC-026-06ADHESIVE,VHB,0.5X3.0034129-03-420-01RAIL,WC R STANDARD COLOR 14129-03-420-20RAIL,WC R GREEN 15129-03-421-01RAIL,WC L STANDARD COLOR 15129-03-421-20RAIL,WC L GREEN 16HARD-0670.38SNAP BUTTON,SINGLE END 17HARD-757PLUG,0.31 DIA, BLACK 108129-03-450-11PF,TOE BOARD,R STANDARD COLOR 18129-03-450-20R PF,TOE BOARD,R GREEN 19129-03-450-06PF,TOE BOARD,L STANDARD COLOR 19129-03-450-20L PF,TOE BOARD,L GREEN 110129-04-415-01PF,CONDUIT CHNL LWR 111129-04-416-01PF,CONDUIT CHNL UPR 112HARD-6360.25X0.50X0.19 SPACER 313HARD-645PLUG,11/16 DIA, BLACK 2114129-03-422-01RAIL,SO R STANDARD COLOR 114129-03-422-20RAIL,SO R GREEN 115129-03-423-01RAIL,SO L STANDARD COLOR 115129-03-423-20RAIL,SO L GREEN 116129-03-427-01RAIL,SO BRKT STANDARD COLOR 216129-03-427-20RAIL,SO BRKT GREEN 217129-03-430-01RAIL,SO BRKT MID STANDARD COLOR 217129-03-430-20RAIL,SO BRKT MID GREEN 218129-03-436-01RAIL,SO CHNL STANDARD COLOR 218129-03-436-20RAIL,SO CHNL GREEN 219HARD-092PLUG,1 SQR,BLACK 220HARD-837ROLLER,0.386,1.25 OD,1.15421HARD-838ROLLER,0.25,0.50 OD,1.15422129-03-480-01RAIL,SO STOP BAR STANDARD COLOR 222129-03-480-20RAIL,SO STOP BAR GREEN 223129-03-418-01RAIL,SO TOE BOARD,D STANDARD COLOR 123129-03-419-20RAIL,SO TOE BOARD,D GREEN 124129-03-419-20RAIL,SO FLOOR BOLT ON STANDARD COLOR 124129-03-419-20RAIL,SO FLOOR BOLT ON GREEN 125MISC-031-01ANTI-SLIP TAPE,4.00,31.00 LENG 3LIST CONTINUED ON THE NEXT PAGE (38)SECTION 4 PLATFORM & RAILSSECTION 4 PLATFORM & RAILS 4.1 | PLATFORM & RAILS PARTS26112-03-412-01RAIL,TOOL TRAY CAP STANDARD COLOR2 26112-03-412-20RAIL,TOOL TRAY CAP GREEN2 27112-03-413-01RAIL,SO FRONT PANEL/TOOL TRAY STANDARD COLOR1 27112-03-413-20RAIL,SO FRONT PANEL/TOOL TRAY GREEN1 28HARD-603MANUAL BOX1 29129-03-438-01RAIL,SO LATCH STANDARD COLOR1 29129-03-438-20RAIL,SO LATCH GREEN1 30129-03-439-01RAIL,SO LOCK BRKT STANDARD COLOR1 30129-03-439-20RAIL,SO LOCK BRKT GREEN1 31129-03-460-03PF,RAIL SPACER1 32HARD-626-2WASHER,0.3ID,0.7OD,0.06THK,NYL5 33HARD-840SPRING,COMP 2.00 X 0.721 34SPBB-10240.25 X 1.50 BIND BARREL,10-242 35HARD-0660.50 SNAP BUTTON,SINGLE END1 36HARD-634PLUG,1.00X1.50,BLACK1 37HARD-6490.25 X 1.25 BARREL SCRW,10-24138LAS-M089-PC/PCGRAIL,GATE LATCH139SCREW-110010-24 X 0.50 PAN HEAD SCRW140112-04-412-01PF,GATE MNT STANDARD COLOR1 40112-04-412-20PF,GATE MNT GREEN1 41129-03-472-01RAIL,GATE TOEBOARD STANDARD COLOR1 41129-03-472-20RAIL,GATE TOEBOARD GREEN1 42HARD-641-23.25X.44U X .63L CLEVIS PIN2 43HARD-822SPRING,TOR .095 DIA,17 IN-LB1 44129-03-471-01RAIL,GATE WLDMNT STANDARD COLOR1 44129-03-471-20RAIL,GATE WLDMNT GREEN1 45143-04-007-04SPACER,.5ID,1.25OD,0.5 THK2 46HARD-636-20.25X0.50X0.25 SPACER1 47HARD-656-11/2 PUSH NUT CAP,QUICK2THIS PAGE WAS INTENTIONALLY LEFT BLANKSECTION 4 PLATFORM & RAILSFIGURE 18: ZT-1230 Decals1129-21-517-50-K DECALS,ZT-1230 S5 ANSI1 2DE717-61DECAL,SAFETY STRIPE (24.00)4 3DE717-63DECAL,SAFETY STRIPE (22.25)1 4DE1008DECAL,HYDR FLUID1 5DE1022DECAL,BATT/CHR COMPATABILITY1 6DE1024DECAL,CASTERLOCK2 7DE1031DECAL,MADE IN USA MIRROR1 8DE1204DECAL,CAPACITY,TOOL TRAY1 9DE1207DECAL,HY-BRID LIFTS1 10DE1208DECAL,BRAKE RELEASE/NO TOW1 11DE1221DECAL,MADE IN USA1 12DE1230DECAL,PROP 651 13DE1233DECAL,SERIES ZT2 14DE1243DECAL,E-DOWN CABLE1 15DE1246DECAL,MANUAL BOX1 16DE1248DECAL,LANYARD ATTACHMENT2 17DE1249DECAL,ANNUAL INSPECTION1 18DE1250DECAL,SCISSOR CRUSH HAZARD2 19DE1252DECAL,WEBSITE2 20DE1259DECAL,SLIDEOUT1 21DE1278DECAL,TIEDOWN3 22DE1282DECAL,PH CRUSH HAZARD2 23DE1291DECAL,ZT FRONT PANEL1 24DE1301DECAL,WHEEL LOAD ZT-12304 25DE1303DECAL,CHARGER CORD1 26DE1304DECAL,PTP1 27DE1305DECAL,MAINT LOCK2 28DE1307DECAL,CAPACITY,650#,1P,I,WO/SO1 29DE1317DECAL,QR ZT SERIES 52 30DE795.1DECAL,CTL UPR ZTS51 31DE796.1DECAL,CTL UPR ID ZT S41 32DE839DECAL,CHARGER PRO 24V12A1 33DE841DECAL,BATT DISCONNECT1 34DE842DECAL,CTL PANEL1 35DE1215DECAL,MODEL ZT-12302 36DE7036DECAL,SERIAL NO ZT-SERIES1FIGURE 19: ZT-1630 Decals1129-21-517-55-K DECALS,ZT-1630 S5 ANSI1 2DE717-61DECAL,SAFETY STRIPE (24.00)4 3DE717-63DECAL,SAFETY STRIPE (22.25)1 4DE1008DECAL,HYDR FLUID1 5DE1022DECAL,BATT/CHR COMPATABILITY1 6DE1024DECAL,CASTERLOCK2 7DE1031DECAL,MADE IN USA MIRROR1 8DE1204DECAL,CAPACITY,TOOL TRAY1 9DE1207DECAL,HY-BRID LIFTS1 10DE1208DECAL,BRAKE RELEASE/NO TOW1 11DE1221DECAL,MADE IN USA1 12DE1230DECAL,PROP 651 13DE1233DECAL,SERIES ZT2 14DE1243DECAL,E-DOWN CABLE1 15DE1246DECAL,MANUAL BOX1 16DE1248DECAL,LANYARD ATTACHMENT2 17DE1249DECAL,ANNUAL INSPECTION1 18DE1250DECAL,SCISSOR CRUSH HAZARD2 19DE1252DECAL,WEBSITE2 20DE1259DECAL,SLIDEOUT1 21DE1278DECAL,TIEDOWN3 22DE1282DECAL,PH CRUSH HAZARD2 23DE1291DECAL,ZT FRONT PANEL1 24DE1302DECAL,WHEEL LOAD ZT-16304 25DE1303DECAL,CHARGER CORD1 26DE1304DECAL,PTP1 27DE1305DECAL,MAINT LOCK2 28DE1307DECAL,CAPACITY,650#,1P,I,WO/SO1 29DE1317DECAL,QR ZT SERIES 52 30DE795.1DECAL,CTL UPR ZTS51 31DE796.1DECAL,CTL UPR ID ZT S41 32DE839DECAL,CHARGER PRO 24V12A1 33DE841DECAL,BATT DISCONNECT1 34DE842DECAL,CTL PANEL1 35DE1216DECAL,MODEL ZT-16302 36DE7032DECAL,SERIAL NO ZT-SERIES1SECTION 6 OPTIONS & MISCELLANEOUSFIGURE 20: Options & Miscellaneous PartsItem #Part Number Part Description Notes Qty Superseded By 1129-21-238-50ASM,INVERTER OPT12MISC-602MANUAL,RESP,A92.2-2413ZT5.0-S MANUAL OP,ZERO TURN S514ZT5.0-M MANUAL MAINT,ZERO TURN S515ZT5.0-P MANUAL PARTS,ZERO TURN S516129-21-519-50ASM,PTP SUB ZT1630 S517129-21-518-50ASM,PTP SUB ZT163018129-21-519-55ASM,PTP SUB ZT1230 S519129-21-518-55ASM,PTP SUB ZT12301THIS PAGE WAS INTENTIONALLY LEFT BLANK6.1 | OPTIONS。