NCP5181PG中文资料

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CS42L51中文资料

Advance Product InformationThis document contains information for a new product.Cirrus Logic reserves the right to modify this product without notice.Low Power, Stereo CODEC with Headphone AmpDIGITAL to ANALOG FEATURES!98 dB Dynamic Range (A-wtd) !-86 dB THD+N!Headphone Amplifier - GND Centered–On-Chip Charge Pump Provides -VA_HP –No DC-Blocking Capacitor Required –46mW Power Into Stereo 16Ω @ 1.8V –88mW Power Into Stereo 16Ω @ 2.5V –-75 dB THD+N!Digital Signal Processing Engine–Bass & Treble Tone Control, De-Emphasis –PCM + ADC Mix w/Independent Vol Control –Master Digital Volume Control–Soft Ramp & Zero Cross Transitions ! Beep Generator–Tone Selections Across Two Octaves –Separate Volume Control–Programmable On & Off Time Intervals –Continuous, Periodic or One-Shot Beep Selections!Programmable Peak-Detect and Limiter !Pop and Click SuppressionANALOG to DIGITAL FEATURES!98 dB Dynamic Range (A-wtd)! -88 dB THD+N !Analog Gain Controls–+32 dB or +16 dB MIC Pre-Amplifiers –Analog Programmable Gain Amplifier (PGA)!+20 dB Digital Boost!Programmable Automatic Level Control (ALC)–Noise Gate for Noise Suppression –Programmable Threshold and Attack/Release Rates!Independent Channel Control !Digital Volume Control!High-Pass Filter Disable for DC Measurements !Stereo 3:1 Analog Input MUX !Dual MIC Inputs–Programmable, Low Noise MIC Bias Levels –Differential MIC Mix for Common Mode Noise Rejection!Very Low 64 Fs Oversampling Clock ReducesPower ConsumptionCS42L51SYSTEM FEATURES!24-bit Converters! 4 kHz to 96kHz Sample Rate!Multi-bit Delta Sigma Architecture!Low Power Operation–Stereo Playback: 12.93 mW @ 1.8 V–Stereo Record and Playback: 20.18 mW @1.8 V!Variable Power Supplies– 1.8 V to 2.5 V Digital & Analog– 1.8 V to 3.3V Interface Logic!Power Down Management–ADC, DAC, CODEC, MIC Pre-Amplifier, PGA!Software Mode (I²C & SPI™ Control)!Hardware Mode (Stand-Alone Control)!Digital Routing/Mixes:–Analog Out=ADC+Digital In–Digital Out=ADC+Digital In–Internal Digital Loopback–Mono Mixes!Flexible Clocking Options–Master or Slave Operation–High-Impedance Digital Output Option (for easy MUXing between CODEC and OtherData Sources)–Quarter-Speed Mode - (i.e. Allows 8 kHz Fs while maintaining a flat noise floor up to16kHz)APPLICATIONS!HDD & Flash-Based Portable Audio Players !MD Players/Recorders!PDAs!Personal Media Players!Portable Game Consoles!Digital Voice Recorders!Digital Camcorders!Digital Cameras!Smart Phones GENERAL DESCRIPTIONThe CS42L51 is a highly integrated, 24-bit, 96kHz, low power stereo CODEC. Based on multi-bit, delta-sigma modulation, it allows infinite sample rate adjustment be-tween 4 kHz and 96 kHz. Both the ADC and DAC offer many features suitable for low power, portable system applications.The ADC input path allows independent channel control of a number of features. An input multiplexer selects be-tween line-level or microphone level inputs for each channel. The microphone input path includes a select-able programmable-gain pre-amplifier stage and a low noise MIC bias voltage supply. A PGA is available for line or microphone inputs and provides analog gain with soft ramp and zero cross transitions. The ADC also fea-tures a digital volume attenuator with soft ramp transitions. A programmable ALC and Noise Gate mon-itor the input signals and adjust the volume levels appropriately.The DAC output path includes a digital signal process-ing engine. Tone Control provides bass and treble adjustment of four selectable corner frequencies. The Mixer allows independent volume control for both the ADC mix and the PCM mix, as well as a master digital volume control for the analog output. All volume level changes may be configured to occur on soft ramp and zero cross transitions. The DAC also includes de-em-phasis, limiting functions and a beep generator delivering tones selectable across a range of two full octaves.The stereo headphone amplifier is powered from a sep-arate positive supply and the integrated charge pump provides a negative supply. This allows a ground-cen-tered analog output with a wide signal swing and eliminates external DC-blocking capacitors.In addition to its many features, the CS42L51 operates from a low-voltage analog and digital core, making this CODEC ideal for portable systems that require ex-tremely low power consumption in a minimal amount of space.The CS42L51 is available in a 32-pin QFN package in both Commercial (-10 to +70° C) and Automotive grades (-40 to +85° C). The CDB42L51 Customer Dem-onstration board is also available for device evaluation and implementation suggestions. Please see “Ordering Information” on page81 for complete details.TABLE OF CONTENTS1. PIN DESCRIPTIONS - SOFTWARE (HARDWARE) MODE (7)1.1 Digital I/O Pin Characteristics (9)2. TYPICAL CONNECTION DIAGRAMS (10)3. CHARACTERISTIC AND SPECIFICATION TABLES (12)SPECIFIED OPERATING CONDITIONS (12)ABSOLUTE MAXIMUM RATINGS (12)ANALOG INPUT CHARACTERISTICS (COMMERCIAL - CNZ) (13)ANALOG INPUT CHARACTERISTICS (AUTOMOTIVE - DNZ) (14)ADC DIGITAL FILTER CHARACTERISTICS (15)ANALOG OUTPUT CHARACTERISTICS (COMMERCIAL - CNZ) (16)ANALOG OUTPUT CHARACTERISTICS (AUTOMOTIVE - DNZ) (17)LINE OUTPUT VOLTAGE CHARACTERISTICS (18)HEADPHONE OUTPUT POWER CHARACTERISTICS (19)COMBINED DAC INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE (20)SWITCHING SPECIFICATIONS - SERIAL PORT (20)SWITCHING SPECIFICATIONS - I²C CONTROL PORT (22)SWITCHING CHARACTERISTICS - SPI CONTROL PORT (23)DC ELECTRICAL CHARACTERISTICS (24)DIGITAL INTERFACE SPECIFICATIONS & CHARACTERISTICS (24)POWER CONSUMPTION (25)4. APPLICATIONS (26)4.1 Overview (26)4.1.1 Architecture (26)4.1.2 Line & MIC Inputs (26)4.1.3 Line & Headphone Outputs (26)4.1.4 Signal Processing Engine (26)4.1.5 Beep Generator (26)4.1.6 Device Control (Hardware or Software Mode) (26)4.1.7 Power Management (26)4.2 Hardware Mode (27)4.3 Analog Inputs (28)4.3.1 Digital Code, Offset & DC Measurement (28)4.3.2 High-Pass Filter and DC Offset Calibration (29)4.3.3 Digital Routing (29)4.3.4 Differential Inputs (29)4.3.4.1 External Passive Components (29)4.3.5 Analog Input Multiplexer (30)4.3.6 MIC & PGA Gain (31)4.3.7 Automatic Level Control (ALC) (31)4.3.8 Noise Gate (32)4.4 Analog Outputs (33)4.4.1 De-Emphasis Filter (33)4.4.2 Volume Controls (34)4.4.3 Mono Channel Mixer (34)4.4.4 Beep Generator (34)4.4.5 Tone Control (35)4.4.6 Limiter (35)4.4.7 Line-Level Outputs and Filtering (36)4.4.8 On-Chip Charge Pump (36)4.5 Serial Port Clocking (37)4.5.1 Slave (37)4.5.2 Master (38)4.5.3 High-Impedance Digital Output (38)4.5.4 Quarter- and Half-Speed Mode (39)4.6 Digital Interface Formats (39)4.7 Initialization (40)4.8 Recommended Power-Up Sequence (40)4.9 Recommended Power-Down Sequence (41)4.10 Software Mode (42)4.10.1 SPI Control (42)4.10.2 I²C Control (42)4.10.3 Memory Address Pointer (MAP) (44)4.10.3.1 Map Increment (INCR) (44)5. REGISTER QUICK REFERENCE (45)6. REGISTER DESCRIPTION (47)6.1 Chip I.D. and Revision Register (Address 01h) (Read Only) (47)6.2 Power Control 1 (Address 02h) (47)6.3 MIC Power Control & Speed Control (Address 03h) (48)6.4 Interface Control (Address 04h) (49)6.5 MIC Control (Address 05h) (51)6.6 ADC Control (Address 06h) (52)6.7 ADCx Input Select, Invert & Mute (Address 07h) (53)6.8 DAC Output Control (Address 08h) (54)6.9 DAC Control (Address 09h) (55)6.10 ALCX & PGAX Control:ALCA, PGAA (Address 0Ah) & ALCB, PGAB (Address 0Bh) (56)6.11 ADCx Attenuator:ADCA (Address 0Ch) & ADCB (Address 0Dh) (57)6.12 ADCx Mixer Volume Control:ADCA (Address 0Eh) & ADCB (Address 0Fh) (58)6.13 PCMX Mixer Volume Control:PCMA (Address 10h) & PCMB (Address 11h) (59)6.14 Beep Frequency & Timing Configuration (Address 12h) (60)6.15 Beep Off Time & Volume (Address 13h) (61)6.16 Beep Configuration & Tone Configuration (Address 14h) (62)6.17 Tone Control (Address 15h) (63)6.18 AOUTx Volume Control:AOUTA (Address 16h) & AOUTB (Address 17h) (64)6.20 Limiter Threshold SZC Disable (Address 19h) (65)6.21 Limiter Release Rate Register (Address 1Ah) (66)6.22 Limiter Attack Rate Register (Address 1Bh) (67)6.23 ALC Enable & Attack Rate (Address 1Ch) (67)6.24 ALC Release Rate (Address 1Dh) (68)6.25 ALC Threshold (Address 1Eh) (69)6.26 Noise Gate Configuration & Misc. (Address 1Fh) (70)6.27 Status (Address 20h) (Read Only) (71)6.28 Charge Pump Frequency (Address 21h) (71)7. ANALOG PERFORMANCE PLOTS (72)7.1 Headphone THD+N versus Output Power Plots (72)7.2 ADC_FILT+ Capacitor Effects on THD+N (74)8. EXAMPLE SYSTEM CLOCK FREQUENCIES (75)8.1 Auto Detect Enabled (75)8.2 Auto Detect Disabled (76)9. PCB LAYOUT CONSIDERATIONS (77)9.1 Power Supply, Grounding (77)9.2 QFN Thermal Pad (77)10. ADC & DAC DIGITAL FILTERS (78)11. PARAMETER DEFINITIONS (79)12. PACKAGE DIMENSIONS (80)THERMAL CHARACTERISTICS (80)13. ORDERING INFORMATION (81)14. REFERENCES (81)15. REVISION HISTORY (82)LIST OF FIGURESFigure 1. Typical Connection Diagram (Software Mode) (10)Figure 2. Typical Connection Diagram (Hardware Mode) (11)Figure 3. Headphone Output Test Load (19)Figure 4. Serial Audio Interface Slave Mode Timing (21)Figure 5. TDM Serial Audio Interface Timing (21)Figure 6. Serial Audio Interface Master Mode Timing (21)Figure 7. Control Port Timing - I²C (22)Figure 8. Control Port Timing - SPI Format (23)Figure 9. Analog Input Architecture (28)Figure 10. MIC Input Mix w/Common Mode Rejection (30)Figure 11. Differential Input (30)Figure 12. ALC (31)Figure 13. Noise Gate Attenuation (32)Figure 14. Output Architecture (33)Figure 15. De-Emphasis Curve (33)Figure 16. Beep Configuration Options (34)Figure 17. Peak Detect & Limiter (35)Figure 18. Master Mode Timing (38)Figure 19. Tri-State Serial Port (38)Figure 20. I²S Format (39)Figure 21. Left-Justified Format (39)Figure 22. Right-Justified Format (DAC only) (39)Figure 23. Initialization Flow Chart (41)Figure 24. Control Port Timing in SPI Mode (42)Figure 25. Control Port Timing, I²C Write (43)Figure 26. Control Port Timing, I²C Read (43)Figure 27. AIN & PGA Selection (53)Figure 28. THD+N vs. Ouput Power per Channel at 1.8V (16 Ω load) (72)Figure 29. THD+N vs. Ouput Power per Channel at 2.5V (16 Ω load) (72)Figure 30. THD+N vs. Ouput Power per Channel at 1.8V (32 Ω load) (73)Figure 31. THD+N vs. Ouput Power per Channel at 2.5V (32 Ω load) (73)Figure 32. ADC THD+N vs. Frequency w/Capacitor Effects (74)Figure 33. ADC Passband Ripple (78)Figure 34. ADC Stopband Rejection (78)Figure 35. DAC Passband Ripple (78)Figure 36. DAC Stopband (78)Figure 35. DAC Transition Band (78)Figure 36. DAC Transition Band (Detail) (78)Figure 35. ADC Transition Band (78)Figure 36. ADC Transition Band (Detail) (78)1.PIN DESCRIPTIONS - SOFTWARE (HARDWARE) MODEPin Name#Pin DescriptionLRCK 1Left Right Clock (Input/Output ) - Determines which channel, Left or Right, is currently active on the serial audio data line.SDA/CDIN 2Serial Control Data (Input /Output ) - SDA is a data I/O in I²C mode. CDIN is the input data line for the control port interface in SPI mode.(MCLKDIV2)MCLK Divide by 2 (Input ) - Hardware Mode: Divides the MCLK by 2 prior to all internal circuitry.SCL/CCLK 3Serial Control Port Clock (Input ) - Serial clock for the serial control port.(I²S/LJ)Interface Format Selection (Input ) - Hardware Mode: Selects between I²S & Left-Justified interface for-mats for the ADC & DAC.AD0/CS 4Address Bit 0 (I²C) / Control Port Chip Select (SPI) (Input) - AD0 is a chip address pin in I²C mode; CS is the chip select signal for SPI format.(DEM)De-Emphasis (Input) - Hardware Mode: Enables/disables the de-emphasis filter.VA_HP 5Analog Power For Headphone (Input) - Positive power for the internal analog headphone section.FLYP 6Charge Pump Cap Positive Node (Input) - Positive node for the external charge pump capacitor.GNDHP 7Analog Ground (Input ) - Ground reference for the internal headphone/charge pump section.FLYN 8Charge Pump Cap Negative Node (Input) - Negative node for the external charge pump capacitor.VSS_HP 9Negative Voltage From Charge Pump (Output) - Negative voltage rail for the internal analog head-phone section.AOUTB AOUTA 1011Analog Audio Output (Output ) - The full-scale output level is specified in the DAC Analog Characteris-tics specification table.VA 12Analog Power (Input) - Positive power for the internal analog section.AGND13Analog Ground (Input) - Ground reference for the internal analog section.M /S )V S S _H A O U T BA O U T V A G N D A C _F I L T A D C _F I L T VDAC_FILT+ ADC_FILT+1416Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits.VQ15Quiescent Voltage (Output) - Filter connection for internal quiescent voltage.MICIN1/ AIN3A 17Microphone Input 1 (Input) - The full-scale level is specified in the ADC Analog Characteristics specifi-cation table.MICIN2/ BIAS/AIN3B 18Microphone Input 2 (Input/Output) - The full-scale level is specified in the ADC Analog Characteristics specification table. This pin can also be configured as an output to provide a low noise bias supply for an external microphone. Electrical characteristics are specified in the DC Electrical Characteristics table.AIN2A19Analog Input (Input) - The full-scale level is specified in the ADC Analog Characteristics specification table.AIN2B/BIAS20Analog Input (Input/Output) - The full-scale level is specified in the ADC Analog Characteristics specifi-cation table. This pin can also be configured as an output to provide a low noise bias supply for an exter-nal microphone. Electrical characteristics are specified in the DC Electrical Characteristics table.AFILTA AFILTB 2122Filter Connection (Output) - Filter connection for the ADC inputs.AIN1A AIN1B 2324Analog Input (Input) - The full-scale level is specified in the ADC Analog Characteristics specification table.RESET25Reset (Input) - The device enters a low power mode when this pin is driven low.VL26Digital Interface Power (Input) - Determines the required signal level for the serial audio interface and host control port. Refer to the Recommended Operating Conditions for appropriate voltages.VD27Digital Power (Input) - Positive power for the internal digital section.DGND28Digital Ground (Input) - Ground reference for the internal digital section.SDOUT29Serial Audio Data Output (Output) - Output for two’s complement serial audio data.(M/S)Serial Port Master/Slave (Input/Output) - Hardware Mode Startup Option: Selects between master and slave mode for the serial port.MCLK30Master Clock (Input) -Clock source for the delta-sigma modulators.SCLK31Serial Clock (Input/Output) - Serial clock for the serial audio interface.SDIN32Serial Audio Data Input (Input) - Input for two’s complement serial audio data.Thermal Pad-Thermal relief pad for optimized heat dissipation. See “QFN Thermal Pad” on page77.1.1Digital I/O Pin CharacteristicsThe logic level for each input should adhere to the corresponding power rail and should not exceed the maximum ratings.Power Rail Pin NameSW/(HW)I/O Driver ReceiverVL RESET Input- 1.8 V - 3.3 V SCL/CCLK(I²S/LJ)Input- 1.8 V - 3.3 V, with HysteresisSDA/CDIN(MCLKDIV2)Input/Output 1.8 V - 3.3 V, CMOS/Open Drain 1.8 V - 3.3 V, with HysteresisAD0/CS(DEM)Input- 1.8 V - 3.3 V MCLK Input- 1.8 V - 3.3 VLRCK Input/Output 1.8 V - 3.3 V, CMOS 1.8 V - 3.3 VSCLK Input/Output 1.8 V - 3.3 V, CMOS 1.8 V - 3.3 VSDOUT(M/S)Input/Output 1.8 V - 3.3 V, CMOS 1.8 V - 3.3 V SDIN Input- 1.8 V - 3.3 VTable 1. I/O Power Rails2.TYPICAL CONNECTION DIAGRAMSFigure 1. Typical Connection Diagram (Software Mode)Figure 2. Typical Connection Diagram (Hardware Mode)3.CHARACTERISTIC AND SPECIFICATION TABLES(All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are derived from measurements taken at nominal supply voltages and T A = 25° C.)SPECIFIED OPERATING CONDITIONS(AGND=DGND=0 V, all voltages with respect to ground.)ABSOLUTE MAXIMUM RATINGS(AGND = DGND = 0 V; all voltages with respect to ground.)WARNING:Operation at or beyond these limits may result in permanent damage to the device. Normal operationis not guaranteed at these extremes.Notes:1.The device will operate properly over the full range of the analog, headphone amplifier, digital core andserial/control port interface supplies.2.Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not causeSCR latch-up.3.The maximum over/under voltage is limited by the input current.ParametersSymbol Min NomMaxUnitsDC Power Supply (Note 1)Analog Core VA 1.712.37 1.82.5 1.892.63V V Headphone Amplifier VA_HP 1.712.37 1.82.5 1.892.63V V Digital CoreVD 1.712.37 1.82.5 1.892.63V V Serial/Control Port InterfaceVL1.712.373.14 1.82.53.3 1.892.633.47V V V Ambient TemperatureCommercial - CNZ Automotive - DNZT A-10-40--+70+85°C °CParametersSymbol MinMaxUnitsDC Power SupplyAnalog Digital Serial/Control Port Interface VA, VA_HP VDVL-0.3-0.3-0.3 3.03.04.0V V V Input Current(Note 2)I in -±10mAAnalog Input Voltage(Note 3)V INAGND-0.7VA+0.7VDigital Input Voltage (Note 3))V IND-0.3VL+ 0.4V Ambient Operating Temperature Commercial - CNZ(power applied)Automotive - DNZT A -20-50+85+95°C °C Storage TemperatureT stg-65+150°C(Test Conditions (unless otherwise specified): All supplies = VA = 2.5 V and 1.8 V; Input sine wave (relative to dig-ital full-scale): 1kHz through passive input filter; Measurement Bandwidth is 10Hz to 20kHz unless otherwise specified. Sample Frequency = 48kHz)VA = 2.5V VA = 1.8VParameter (Note 4)Min Typ Max Min Typ Max Unit Analog In to ADC (PGA bypassed)Dynamic Range A-weightedunweighted 93909996--90879693--dBdBTotal Harmonic Distortion + Noise -1dBFS-20dBFS-60dBFS ----86-76-36-80------84-73-33-78--dBdBdBAnalog In to PGA to ADC Dynamic RangePGA Setting: 0 dB A-weightedunweighted 92899895--89869592--dBdBPGA Setting: +12 dB A-weightedunweighted 85829188--82798885--dBdBTotal Harmonic Distortion + NoisePGA Setting: 0 dB -1dBFS -60dBFS ---88-35-82----86-32-80-dBdBPGA Setting: +12 dB -1dBFS--85-79--83-77dB Analog In to MIC Pre-Amp(+16 dB) to PGA to ADCDynamic RangePGA Setting: 0 dB A-weightedunweighted --8683----8380--dBdBTotal Harmonic Distortion + NoisePGA Setting: 0 dB -1dBFS--76---74-dB Analog In to MIC Pre-Amp(+32 dB) to PGA to ADCDynamic RangePGA Setting: 0 dB A-weightedunweighted --7874----7571--dBdBTotal Harmonic Distortion + NoisePGA Setting: 0 dB -1dBFS--74---71-dB Other CharacteristicsDC AccuracyInterchannel Gain Mismatch-0.1--0.1-dB Gain Drift-±100--±100-ppm/°C InputInterchannel Isolation-90--90-dB DAC Isolation (Note 5)-70--70-dB Full-scale Input Voltage (x•VA) (Note 7)0.70•VA0.72•VA0.75•VA0.70•VA0.72•VA0.75•VA VppInput Impedance (Note 6)ADCPGAMIC 184050------184050------kΩkΩkΩ(Test Conditions (unless otherwise specified): All supplies = VA = 2.5 V and 1.8 V; Input sine wave (relative to full-scale): 1 kHz through passive input filter; Measurement Bandwidth is 10Hz to 20kHz unless otherwise specified. Sample Frequency = 48kHz)Notes:4.Referred to the typical full-scale voltage.5.Measured with DAC delivering full-scale output power into 16 Ω.VA = 2.5V VA = 1.8V Parameter (Note 4)MinTypMaxMinTypMaxUnitAnalog In to ADCDynamic RangeA-weighted unweighted91789996--88859693--dB dB Total Harmonic Distortion + Noise -1dB -20dB-60dB ----86-76-36-78------84-73-33-76--dB dB dBAnalog In to PGA to ADC Dynamic RangePGA Setting: 0 dB A-weighted unweighted 90879895--87849592--dB dB PGA Setting: +12 dBA-weighted unweighted83809188--80778885--dB dB Total Harmonic Distortion + Noise PGA Setting: 0 dB -1dB -60dB ---88-35-80----86-32-78-dB dB PGA Setting: +12 dB -1dB--85-77--83-75dBAnalog In to MIC Pre-Amp (+16 dB) to PGA to ADC Dynamic RangePGA Setting: 0 dBA-weighted unweighted--8683----8380--dB dB Total Harmonic Distortion + Noise PGA Setting: 0 dB-1dB--76---74-dBAnalog In to MIC Pre-Amp (+32 dB) to PGA to ADC Dynamic RangePGA Setting: 0 dBA-weighted unweighted--7874----7571--dB dB Total Harmonic Distortion + Noise PGA Setting: 0 dB-1dB--74---71-dBOther CharacteristicsDC AccuracyInterchannel Gain Mismatch -0.1--0.1-dB Gain Drift-±100--±100-ppm/°C InputInterchannel Isolation -90--90-dB DAC Isolation (Note 5)-70--70-dB Full-scale Input Voltage (Note 7) 0.70•VA 0.72•VA0.75•VA0.70•VA 0.72•VA0.75•VAVpp Input Impedance (Note 6)ADC PGA MIC 184050------184050------k Ωk Ωk ΩNotes:6.Measured between AINxx and AGND.7.Full-scale input voltage characteristics for the PGA and Microphone inputs are scaled based on the gainsetting for each.ADC DIGITAL FILTER CHARACTERISTICSNotes:8.Response is clock dependent and will scale with Fs. Note that the response plots (Figures 33to 36 onpage 78) have been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs.Parameter (Note 8)MinTypMaxUnitPassband (Frequency Response) to -0.1 dB corner0-0.4948Fs Passband Ripple -0.09-0dB Stopband0.6677--Fs Stopband Attenuation 48.4--dB Total Group Delay-2.7/Fs -s High-Pass Filter CharacteristicsFrequency Response -3.0 dB -0.13 dB -- 3.724.2--Hz Hz Phase Deviation @ 20Hz-10-Deg Passband Ripple --0.17dB Filter Settling Time-105/Fss(Test conditions (unless otherwise specified): Input test signal is a full-scale 997 Hz sine wave; measurement bandwidth is 10 Hz to 20 kHz; Sample Frequency = 48 kHz; test load R L = 10 kΩ, C L = 10 pF for the line output (see Figure3), and test load R L = 16 Ω, C L = 10 pF (see Figure3) for the headphone output. HP_GAIN[2:0] = 011.)Parameter(Note 9)VA = 2.5VMin Typ MaxVA = 1.8VMin Typ Max UnitR L = 10 kΩDynamic Range18 to 24-Bit A-weighted unweighted 16-Bit A-weightedunweighted 9289--98959693----8986--95929390----dBdBdBdBTotal Harmonic Distortion + Noise18 to 24-Bit0 dB-20 dB-60 dB 16-Bit0 dB-20 dB-60 dB -------86-75-35-86-73-33-80------------88-72-32-88-70-30-82-----dBdBdBdBdBdBR L = 16 ΩDynamic Range18 to 24-Bit A-weightedunweighted 16-Bit A-weightedunweighted 9289--98959693----8986--95929390----dBdBdBdBTotal Harmonic Distortion + Noise18 to 24-Bit0 dB-20 dB-60 dB 16-Bit0 dB-20 dB-60 dB -------75-75-35-75-73-33-69------------75-72-32-75-70-30-69-----dBdBdBdBdBdBOther Characteristics for R L = 16 Ω or 10 kΩOutput Parameters Modulation Index (MI) (Note 10)Analog Gain Multiplier (G)-0.67870.6047--0.67870.6047-Full-scale Output Voltage (2•G•MI•VA) (Note 10)Refer to Table“Line Output Voltage Characteristics” onpage18VppFull-scale Output Power (Note 10)Refer to Table“Headphone Output Power Characteristics” onpage19Interchannel Isolation (1 kHz)16 Ω10 kΩ--8095----8093--dBdBInterchannel Gain Mismatch-0.10.25-0.10.25dB Gain Drift-±100--±100-ppm/°C AC-Load Resistance (R L)(Note 11)16--16--ΩLoad Capacitance (C L)(Note 11)--150--150pF(Test conditions (unless otherwise specified): Input test signal is a full-scale 997 Hz sine wave; measurement bandwidth is 10 Hz to 20 kHz; Sample Frequency = 48 kHz and 96 kHz; test load R L = 10 kΩ, C L = 10 pF for the line output (see Figure3), and test load R L = 16 Ω, C L = 10 pF (see Figure3) for the headphone output.HP_GAIN[2:0] = 011.)Parameter(Note 9)VA = 2.5VMin Typ MaxVA = 1.8VMin Typ Max UnitR L = 10 kΩDynamic Range18 to 24-Bit A-weighted unweighted 16-Bit A-weightedunweighted 9087--98959693----8784--95929390----dBdBdBdBTotal Harmonic Distortion + Noise18 to 24-Bit0 dB-20 dB-60 dB 16-Bit0 dB-20 dB-60 dB -------86-75-35-86-73-33-78------------88-72-32-88-70-30-80-----dBdBdBdBdBdBR L = 16 ΩDynamic Range18 to 24-Bit A-weightedunweighted 16-Bit A-weightedunweighted 9087--98959693----8784--95929390----dBdBdBdBTotal Harmonic Distortion + Noise18 to 24-Bit0 dB-20 dB-60 dB 16-Bit0 dB-20 dB-60 dB -------75-75-35-75-73-33-67------------75-72-32-75-70-30-67-----dBdBdBdBdBdBOther Characteristics for R L = 16 Ω or 10 kΩOutput Parameters Modulation Index (MI) (Note 10)Analog Gain Multiplier (G)-0.67870.6047--0.67870.6047-Full-scale Output Voltage (2•G•MI•VA) (Note 10)Refer to Table “Line Output Voltage Characteristics” onpage18VppFull-scale Output Power (Note 10)Refer to Table “Headphone Output Power Characteristics” onpage19Interchannel Isolation (1 kHz)16 Ω10 kΩ--8095----8093--dBdBInterchannel Gain Mismatch-0.10.25-0.10.25dB Gain Drift-±100--±100-ppm/°C AC-Load Resistance (R L)(Note 11)16--16--ΩLoad Capacitance (C L)(Note 11)--150--150pF。

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目录版权声明 (1)安全须知 (2)目录 (3)第一章.注册引导 (4)第二章.产品概述 (5)2.1产品介绍 (5)2.2软硬件优势 (5)2.3产品参数 (6)2.4整机介绍 (6)2.5产品清单 (6)2.5整机介绍 (7)2.5.1K518PRO主机 (7)2.5.2OBDII转接头+转接线 (8)2.5.3采集模拟天线+采集L-JCD线 (10)2.5.4KPROG适配器 (11)2.6功能展示 (12)2.6.1主界面功能 (12)2.6.2特殊功能界面 (13)2.6.3系统设置界面 (14)2.6.4功能操作界面 (15)第三章.售后服务 (16)保修服务卡 (18)第一章：注册引导注：开机后，请连接好WIFI，进入注册流程。

NCP5181中文资料

NCP5181High Voltage High and Low Side DriverThe NCP5181 is a High V oltage Power MOSFET Driver providing two outputs for direct drive of 2 N−channel power MOSFETs arranged in a half−bridge (or any other high−side + low−side) configuration. It uses the bootstrap technique to insure a proper drive of the High−side power switch. The driver works with 2 independent inputs to accommodate any topology (including half−bridge, asymmetrical half−bridge, active clamp and full−bridge…).Features•High V oltage Range: up to 600 V•dV/dt Immunity ±50 V/nsec•Gate Drive Supply Range from 10 V to 20 V•High and Low DRV Outputs•Output Source / Sink Current Capability 1.1 A / 2.4 A•3.3 V and 5 V Input Logic Compatible•Up to V CC Swing on Input Pins•Matched Propagation Delays between Both Channels •Outputs in Phase with the Inputs•Independent Logic Inputs to Accommodate All Topologies •Under V CC LockOut (UVLO) for Both Channels•Pin to Pin Compatible with IR2181(S)•These are Pb−Free DevicesApplications•High Power Energy Management•Half−bridge Power Converters•Any Complementary Drive Converters (asymmetrical half−bridge, active clamp)•Full−bridge Converters•Bridge Inverters for UPS SystemsPIN ASSIGNMENTPINFUNCTIONIN_HI Logic Input for High Side Driver Output In Phase IN_LO Logic Input for Low Side Driver Output In Phase GND GroundDRV_LO Low Side Gate Drive OutputV CC Low Side and Main Power SupplyVBOOT Bootstrap Power SupplyDRV_HI High Side Gate Drive OutputBRIDGE Bootstrap Return or High Side Floating Supply ReturnMARKING DIAGRAMSPDIP−8P SUFFIXCASE 626Device Package Shipping†ORDERING INFORMATIONNCP5181P,5181= Specific Device CodeA= Assembly LocationL= Wafer LotY, YY= YearW, WW= Work WeekG, G= Pb−Free PackageNCP5181PAWLYYWWGSOIC−8D SUFFIXCASE 751NCP5181PG PDIP−8(Pb−Free)50 Units/TubeNCP5181DR2G SOIC−8(Pb−Free)2.500/Tape & Reel†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.IN_HIIN_LOGNDDRV_LOV BOOTDRV_HIBRIDGEV CCFigure 1. Typical ApplicationFigure 2. Detailed Block DiagramMAXIMUM RATINGSRating Symbol Value Unit Main power supply voltage V CC−0.3 to 20V VHV: High Voltage BRIDGE pin V BRIDGE−1 to 600V VHV: Floating supply voltage V BOOT − V BRIDGE0 to 20V VHV: High side output voltage V DRV_HI V BRIDGE−0.3 to V BOOT+0.3V Low side output voltage V DRV_LO−0.3 to V CC+0.3V Allowable output slew rate dV BRIDGE/d t50V/ns Inputs IN_HI, IN_LO V IN_XX−1.0 to V CC+0.3V ESD Capability:HBM model (all pins except pins 6−7−8) Machine model (all pins except pins 6−7−8)2.0200kVVLatch up capability per Jedec JESD78 Power dissipation and thermal characteristicsPDIP8: Thermal resistance, Junction−to−Air SO−8: Thermal resistance, Junction−to−Air R q JAR q JA100178°C/WOperating junction temperature T J_minT J_max−55+150°CMaximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected.ELECTRICAL CHARACTERISTICS (V CC = V boot = 15 V, V gnd = V bridge, −40°C < T A< 125°C, Outputs loaded with 1 nF)Rating Symbol T A −40°C to 125°C Units OUTPUT SECTIONMin Typ MaxI DRVhigh− 1.4−A Output high short circuit pulsed currentV DRV= 0 V, PW ≤ 10 m s, (Note 1)I DRVlow− 2.2−A Output low short circuit pulsed currentV DRV= V CC, PW ≤ 10 m s, (Note 1)R OH−512W Output resistor (Typical value @ 25°C only)SourceOutput resistor (Typical value @ 25°C only)R OL−28W SinkDYNAMIC OUTPUT SECTIONRating Symbol Min Typ Max Units Turn−on propagation delay (V bridge = 0 V)t ON−100170ns Turn−off propagation delay (V bridge = 0 V or 50 V) (Note 2)t OFF−100170nst r−4060ns Output voltage rise time(from 10% to 90% @ V CC = 15 V) with 1 nF loadt f−2040ns Output voltage falling edge(from 90% to 10% @ V CC = 15 V) with 1 nF loadD t−2035ns Propagation delay matching between the High side and the Low side@ 25°C (Note 3)Minimum input pulse width that changes the output t PW−−100ns INPUT SECTIONLow level input voltage threshold V IN−−0.8V Input pull−down resistor (V IN < 0.5 V)R IN−200−k W High level input voltage threshold V IN 2.3−−V SUPPLY SECTIONV CC UV Start−up voltage threshold V CC_stup7.98.99.8V V CC UV Shut−down voltage threshold V CC_shtdwn7.38.29.0V Hysteresis on V CC V CC_hyst0.30.7−V V boot Start−up voltage threshold reference to bridge pinV boot_stup7.98.99.8V (V boot_stup = V boot − V bridge)V boot UV Shut−down voltage threshold V boot_shtdwn7.38.29.0V Hysteresis on V boot V boot_shtdwn0.30.7−VI HV_LEAK−0.540m A Leakage current on high voltage pins to GND(V BOOT= V BRIDGE= DRV_HI = 600 V)I CC1− 4.5 6.5mA Consumption in active mode(V CC= V boot, f sw= 100 kHz and 1 nF load on both driver outputs)Consumption in inhibition mode (V CC= V boot)I CC2−250400m A V CC current consumption in inhibition mode I CC3−215−m A V boot current consumption in inhibition mode I CC4−35−m A *Note: see also characterization curves1.Guaranteed by design.2.Turn−off propagation delay @ V bridge = 600 V is guaranteed by design3.See characterization curve for D t parameters variation on the full range temperature.4.Timing diagram definition see Figures 4, 5 and 6.IN_HI IN_LODRV_HI DRV_LOIN_HI 50%90%90%10%10%IN_LODRV_HI DRV_LO50%Figure 3. Input/Output Timing DiagramFigure 4. Switching Time Waveform Definitions50%90%10%50%90%10%DRV_HIDRV_LOIN_LO IN_HIDelta_t Delta_tFigure 5. Delay Matching Waveforms Definition50%90%10%50%90%10%DRV_HIDRV_LOIN_LO IN_HIDelta_tDelta_t&Figure 6. Other Delay Matching Waveforms Definitiont ont rt offt ft ont off t ont off t on_HIt on_LOt on_LOt off_HITYPICAL CHARACTERISTICS020406080100120160020406080100160180Figure 11. High Side Turn−on PropagationDelay vs. V BRIDGE Voltage Figure 12. High Side Turn−off PropagationDelay vs. V BRIDGE VoltageBRIDGE PIN VOLTAGE (V)BRIDGE PIN VOLTAGE (V)507090*********T o n P R O P A G A T I O N D E L A Y (n s )120140T o f f P R O P A G A T I O N D E L A Y (n s )T o n P R O P A G A T I O N D E L A Y (n s )TYPICAL CHARACTERISTICS05.0101520253040Figure 15. Turn−off Fall Time vs. TemperatureFigure 16. Turn−off Fall Time vs. V CC Voltage(V CC = V boot )TEMPERATURE (°C)SUPPLY VOLTAGE; V CC = V boot (V)05.010********Figure 17. Propagation Delay Matching Between High Side and Low Side Driver35T U R N −O N R I S E T I M E (n s )T U R N −O F F F A L L T I M E (n s )TEMPERATURE (°C)10080604020−20−400510152025304012035P R O P A G A T I O N D E L A Y M A T C H I N G (n s )TYPICAL CHARACTERISTICSFigure 18. Low Level Input Voltage Thresholdvs. TemperatureFigure 19. Low Level Input Voltage Thresholdvs. V CC VoltageTEMPERATURE (°C)SUPPLY VOLTAGE; V CC = V boot (V)00.20.61.01.420181614121000.20.41.01.4L O W L E V E L I N P U T V O L T A G E T H R E S H O L D (V )L O W L E V E L I N P U T V O L T A G E T H R E S H O L D (V )10080604020−20−401200.40.81.20.60.81.2Figure 20. High Level Input Voltage Thresholdvs. TemperatureFigure 21. High Level Input Voltage Thresholdvs. V CC VoltageTEMPERATURE (°C)SUPPLY VOLTAGE; V CC = V boot (V)100806040200−20−4000.51.01.52.520181********0.51.01.52.02.5Figure 22. Leakage Current on High Voltage Pins (600 V) to Ground vs. TemperatureFigure 23. Leakage Current on High VoltagePins to Ground vs. V bridge Voltage(V bridge = V boot = V DRV_HI )TEMPERATURE (°C)BRIDGE PIN VOLTAGE (V)100806040200−20−4000.51.01.52.53.04.060040030020010000.050.100.150.200.250.401202.0120L E A K A G E C U R R E N T T O G N D (m A )H I G H S I D E L E A K A G E C U R R E N T T O G N D (m A )0.300.35H I G H L E V E L I N P U T V O L T A G E T H R E S H O L D (V )H I G H L E V E L I N P U T V O L T A G E T H R E S H O L D (V )2.03.5500TYPICAL CHARACTERISTICSFigure 24. High Side Supply Current vs.TemperatureFigure 25. High Side Supply Current vs.Bootstrap Supply VoltageTEMPERATURE (°C)BOOTSTRAP SUPPLY VOLTAGE (V)040100201816141210020100B O O T S T R A P S U P P L YC U R R E N T (m A )B O O T S T R A P S U P P L YC U R R E N T (m A )100806040200−20−40120206080406080Figure 26. V CC Supply Current vs.TemperatureFigure 27. V CC Supply Current vs. V CC SupplyVoltageTEMPERATURE (°C)V CC , SUPPLY VOLTAGE (V)100806040200−20−401002003004005002018161412100100200300400500Figure 28. UVLO Start Up Voltage vs.Temperature Figure 29. UVLO Shut Down Voltage vs.Bootstrap Supply VoltageTEMPERATURE (°C)TEMPERATURE (°C)10120V C C S U P P L Y C U R R E N T (m A )V C C S U P P L Y C U R R E N T (m A )U V L O S T A R T U P V O L T A G E t h (V )U V L O S H U T D O W N V O L T A G E t h (V )TYPICAL CHARACTERISTICSFigure 30. ICC1 Consumption vs. Switching Frequency with 15 nC Load on Each DriverFigure 31. ICC1 Consumption vs. Switching Frequency with 33 nC Load on Each DriverSWITCHING FREQUENCY (kHz)SWITCHING FREQUENCY (kHz)05.0152535010204060I C C + I b o o t C U R R E N T S U P P L Y (m A )I C C + I b o o t C U R R E N T S U P P L Y (m A )1020303050Figure 32. ICC1 Consumption vs. Switching Frequency with 50 nC Load on Each Driver Figure 33. ICC1 Consumption vs. Switching Frequency with 100 nC Load on Each DriverSWITCHING FREQUENCY (kHz)SWITCHING FREQUENCY (kHz)01020304050608070I C C + I b o o t C U R R E N T S U P P L Y (m A )11PACKAGE DIMENSIONSSOIC−8 NB CASE 751−07NOTES:1.DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.2.CONTROLLING DIMENSION: MILLIMETER.3.DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION.4.MAXIMUM MOLD PROTRUSION 0.15 (0.006)PER SIDE.5.DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBARPROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.6.751−01 THRU 751−06 ARE OBSOLETE. NEWSTANDARD IS 751−07.DIM A MIN MAX MIN MAX INCHES4.805.000.1890.197MILLIMETERS B 3.80 4.000.1500.157C 1.35 1.750.0530.069D 0.330.510.0130.020G 1.27 BSC 0.050 BSC H 0.100.250.0040.010J 0.190.250.0070.010K 0.40 1.270.0160.050M 0 8 0 8 N 0.250.500.0100.020S5.806.200.2280.244YM0.25 (0.010)Z SXS____ǒmm inchesǓSCALE 6:1*For additional information on our Pb−Free strategy and solderingdetails, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.SOLDERING FOOTPRINT*PACKAGE DIMENSIONS8 LEAD PDIP CASE 626−05NOTES:1.DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL.2.PACKAGE CONTOUR OPTIONAL (ROUND OR SQUARE CORNERS).3.DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.DIM MIN MAX MIN MAX INCHESMILLIMETERS A 9.4010.160.3700.400B 6.10 6.600.2400.260C 3.94 4.450.1550.175D 0.380.510.0150.020F 1.02 1.780.0400.070G 2.54 BSC 0.100 BSC H 0.76 1.270.0300.050J 0.200.300.0080.012K 2.92 3.430.1150.135L 7.62 BSC 0.300 BSC M −−−10 −−−10 N0.76 1.010.0300.040__ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.PUBLICATION ORDERING INFORMATIONThe product described herein (NCP5181), is covered by U.S. patent: 6,362, 067. There may be some other patent pending.。

MAX5181BEEG+中文资料

Ordering Information
PART
TEMP RANGE
MAX5181BEEG
-40°C to +85°C
MAX5184BEEG
-40°C to +85°C
MAX5184ETG
-40°C to +85°C
*EP = Exposed paddle.
PIN-PACKAGE 24 QSOP 24 QSOP 24 Thin QFN-EP*
Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

NCP5181 36 W镇流器评估板用户手册说明书

NCP5181BAL36WEVB NCP5181 36 W Ballast Evaluation Board User's ManualDescriptionThis document describes how the NCP5181 driver can be implemented in a ballast application. The scope of this evaluation board user’s manual is to highlight the NCP5181driver and not to explain or detail how to build an electronic ballast.The NCP5181 is a high voltage power MOSFET driver providing two outputs for direct drive of two N-channel power MOSFETs arranged in a half-bridge (or any other high-side + low-side topology) configuration.It uses the bootstrap technique to ensure a proper drive of the high-side power switch. The driver works with two independent inputs to accommodate with any topology (including half-bridge, asymmetrical half-bridge, active clamp and full-bridge).Evaluation Board Specification•Input Range: 85−145Vac OR 184−265Vac •Ballast Output Power: 36W (type PL −L 36W)•Pre-heating Current: 295mA •Pre-heating Time: 1second •Nominal Current: 414mADetailed OperationThe lamp ballast is powered via a half bridge configuration. The two power MOSFETs are driven with the NCP5181 driver. The driver is supplied by the V CC rail, and the high side driver is supplied by the bootstrap diode: when the low side power MOSFET (Q2) is switched ON, the BRIDGE pin is pulled down to the ground, thus the capacitor connected between the BRIDGE pin and VBOOT pin is refuelled via the diode D3 and the resistor R5 connected to V CC . When Q2 is switched OFF, the bootstrap capacitor C6supplies the high side driver with a voltage equal to V CC level minus D3 forward voltage diode. Given the NCP5181architecture, it is up to the designer to generate the right input signal polarity. This includes a dead time to avoid a short circuit between the high and low side power MOSFET.The 555 timer generates only one signal for the driver, the second one, in opposite phase is built by inserting an NPN transistor (Q4) for inverting the signal. Afterwards, the dead time is built with R2, D2 and C13 (typically 260ns, see Figure 2).Figure 1. NCP5181 Evaluation BoardWARNING:BEFORE PLUGGING IN THE EVALUATION BOARD, MAKE SURE THE JUMPER IS IN THE CORRECT POSITION: IF J2IS USED, THEN Vin MUST BE LOWER THAN 145Vac.EVAL BOARD USER’S MANUALNCP5181BAL36WEVBDRV_HI (5 V/div)DRV_LO (5 V/div)Time(400 ns/div)Dead time260nsFigure 2. Dead Time Between the High and Low Side DriverIN_HI (10 V/div)DRV_HI (10 V/div)IN_LO(10 V/div)DRV_LO (10 V/div)Time (4 μs/div)Figure 3. Input Output Timing DiagramTube V oltage (100 V /div)Tube current (0.5 V /div)Tube Power (50W/div)TubeAverage power = 32WFigure 4. Tube SignalsNCP5181BAL36WEVBFigure 5. Evaluation Board Schematic720n F 00V820n F 00VFigure 6. PCB Printout: Top and Bottom ViewTEST PROCEDUREFigure 7. Test Setup ConnectionR Load 200 WTable 1. REQUIRED EQUIPMENTAC Power Source can be able to deliver 230V rms or 110V rmsTwo Volt-metersTwo Ampere-meters1 Resistive Load: 200W /50WOne NCP5181 Evaluation Board−Test Procedure1.First of all check if you need jumper #2 (J2 on the board close the diode bridge). This jumper must be removed for use with European mains (230Vac input voltage), and must be in place when using US mains (110Vac). This jumper is used to build a voltage doubler just after the bridge diode in case one is using US mains input voltage range.2.Connect the test setup as shown in Figure 7:•AC Source•V oltmeter and Ampmeter on the Load •Load on the Output3.Apply 230Vac for European mains or 110Vac for US mains on the input connector.4.Check I Load and V Load with the appropriate value in the table below.5.If you get the correct output and input voltage, you can then connect a 36W fluorescent tube on the output (see Figure 8).Table 2. TEST RESULTSInput Mains J2V in (V rms )I in (A rms)V Load (V rms )ILoad (A rms )European Removed230V 278mA 303V 370mA US Yes → Max Input Voltage: 132 V rms110V514mA263V340mAFigure 8. Ballast ConnectionInput ConnectionOutput Connection36W TubeTable 3. BILL OF MATERIAL FOR THE NCP5181 EVALUATION BOARDDesignator Qty.Description Value Tolerance Footprint Manufacturer ManufacturerPart NumberSubstitutionAllowedLeadFreeU21NCP5181NA NA DIP8ON Semiconductor NCP5181PG No Yes U11CMOS IC Analog/Timer NA DIP8Texas Instruments TLC555CP Yes No C1, C22Electrolytic Capacitor47m F, 400V20%Radial Panasonic ECA2GM470Yes No C31Electrolytic Capacitor220m F, 16V20%Radial Panasonic ECA1CM221Yes No C41Electrolytic Capacitor 4.7m F, 63V20%Radial Panasonic EEUEB1J4R7Yes No C5, C62Capacitor100nF, 50V10%Radial Murata RPER71H104K2M1A05U Yes No C7, C82Capacitor220nF, 400V10%Radial Vishay MKT1822422405Yes No C9, C102Capacitor220nF, 100V5%Radial Murata RPE5C2A221J2M1Z05A Yes No C111Capacitor10nF, 100V10%Radial Murata RPER72A103K2M1B05A Yes No C12, C132Capacitor18pF, 100V2%Radial Vishay2252 586 20154Yes Yes C141Capacitor220pF, 400V10%Radial Panasonic ECKATS221KB Yes No C151Capacitor 6.8nF, 1600V5%Radial Vishay2222 375 30682Yes No C161Capacitor NC−Radial−−−−C171Electrolytic Capacitor100m F, 16V20%Radial Panasonic ECA1CM101Yes No D11Zener Diode15V, 1.3W5%Axial Vishay BZX85C15Yes No D21High-speed Diode0.2A, 75V NA Axial PhilipsSemiconductor1N4148Yes No D3, D5, D63Rectifier Diode1A, 400V NA Axial ON Semiconductor1N4936G Yes Yes D41Zener Diode 5.1V, 1.3W5%Axial Vishay BZX85C5V1Yes No F11Fuse500mA, 250V NA Radial Schurter0034.6612Yes No L11Inductor 1.4mH NA NA Vogt53−044No No PT11Diode Bridge600V, 1A NA DFM Vishay DF06M Yes No R11Resistor12k W, 0.33W5%Axial Vishay CFA020712K Yes No R21Resistor82k W, 0.33W5%Axial Vishay CFA020782K Yes No R3, R42Resistor82k W, 3W5%Axial Vishay CPF382K000JN Yes No R5, R6, R73Resistor10W, 0.33W5%Axial Vishay CFA020710R Yes No R8, R92Resistor10k W, 0.33W5%Axial Yageo CFA020710K Yes No R101Resistor33k W, 0.33W5%Axial Vishay CFA020733K Yes No R111Resistor47k W, 0.33W5%Axial Vishay CFA020747K Yes No R121Resistor27k W, 0.33W5%Axial Vishay CFA020727K Yes No R131Resistor15k W, 0.33W5%Axial Vishay CFA020715K Yes No R141Resistor390k W, 0.33W5%Axial Vishay CFA0207390K Yes No R151Resistor22k W, 0.33W5%Axial Vishay CFA020722K Yes No R161Resistor68 k W, 0.33 W5%Axial Vishay CFA020768K Yes NoQ1, Q22Power MOSFETN-channel 8A, 500V NA TO220InternationalRectifierIRF840LC Yes NoQ3, Q42NPN Transistor100mA, 45V NA TO−92ON Semiconductor BC547BG Yes Yes B1, J12Connector2/″NA 5.08mm Weidmuller PM5.08/2/90(1760510000)Yes No J21Jumper Resistor0W, 0.25W NA Axial Yageo ZOR−25−B−52Yes NoADDITIONAL INFORMATIONTECHNICAL PUBLICATIONS :Technical Library: /design/resources/technical−documentation onsemi Website: ONLINE SUPPORT : /supportFor additional information, please contact your local Sales Representative at /support/sales。

TEA1753TN1,518;中文规格书,Datasheet资料

2.4 Flyback green features
Valley switching for minimum switching losses (NXP patented) Frequency reduction with adjustable minimum peak current at low-power operation to maintain high efficiency at low output power levels
3 ofductors
TEA1753T
HV start-up flyback controller with integrated PFC controller
5. Block diagram
3)&'5,9(5 3)& GULYHU
TEA1753T
HV start-up DCM/QR flyback controller with integrated DCM/QR PFC controller
Rev. 3 — 24 August 2012 Product data sheet
1. General description
The TEA1753T is the third generation of green Switched Mode Power Supply (SMPS) controller ICs. The TEA1753T combines a controller for Power Factor Correction (PFC) and a flyback controller. Its high level of integration allows the design of a cost-effective power supply with a very low number of external components. The special built-in green functions provide high efficiency at all power levels. This efficiency applies to quasi-resonant operation at high-power levels, quasi-resonant operation with valley skipping, as well as reduced frequency operation at lower power levels. At low-power levels, the PFC switches off to maintain high efficiency. During low-power conditions, the flyback controller switches to frequency reduction mode and limits the peak current to an adjustable minimum value. This mode ensures high efficiency at low-power and good standby power performance while minimizing audible noise from the transformer. The controller is switched to the power-down mode for no-load operation. In this mode, the controller is shut down for very low standby power applications. The TEA1753T is a Multi-Chip Module, (MCM), containing two chips. The proprietary high-voltage BCD800 process which makes direct start-up possible from the rectified universal mains voltage in an effective and green way. The second low voltage Silicon On Insulator (SOI) is used for accurate, high-speed protection functions and control. The TEA1753T enables the design of highly efficient and reliable supplies with power requirements of up to 250 W using the minimum number of external components. Remark: All values provided throughout this data sheet are typical values unless otherwise stated.

ControlLogix 類比 I O 模組 1756-IF16、1756-IF6CIS、1756-

熱電中插拔 (RIUP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 模組故障報告 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 可設定的軟體 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 電子鍵控 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 更多資訊 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 存取系統時脈的時間戳記功能 . . . . . . . . . . . . . . . . . . . . . . . . . 33 連續的時間戳記 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 生產者 / 消費者模型 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 狀態指示燈資訊 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

AI-518 518P 型人工智能温度控制器说明书 v7.1

二、技术规格...........................................................................................................10 三、仪表接线...........................................................................................................12 四、面板说明及操作说明 .........................................................................................16
（一）显示状态....................................................................................................................17 （二）基本使用操作.............................................................................................................19 （三）AI 人工智能调节及自整定(AT)操作 ............................................................................20 （四）程序操作（仅适用 AI-518P 型）................................................................................22

NCP1582资料

NCP1582, NCP1582A,NCP1583Low Voltage Synchronous Buck ControllersThe NCP158x is a low cost PWM controller designed to operate from a 5 V or 12 V supply. This device is capable of producing an output voltage as low as 0.8 V. This 8−pin device provides an optimal level of integration to reduce size and cost of the power supply. Features include a0.7 A gate driver and an internally set 350 kHz (NCP1582, NCP1582A) and a 300 kHz (NCP1583) oscillator. The NCP158x also incorporates an externally compensated transconductance error amplifier and a programmable soft−start function. Protection features include short circuit protection (SCP) and under voltage lockout (UVLO). The NCP158x comes in an 8−pin SOIC package.Features•Input V oltage Range from 4.5 V to 13.2 V•350 kHz (NCP1582, NCP1582A), 300 kHz (NCP1583) Internal Oscillator•Boost Pin Operates to 30 V•V oltage Mode PWM Control•0.8 V $1.5% Internal Reference V oltage•Adjustable Output V oltage•Programmable Soft−Start•Internal 0.7 A Gate Drivers•80% Max Duty Cycle•Input UVLO•R DS(on) Current Sensing for Short Circuit Protection •These are Pb−Free DevicesApplications•Graphics Cards•Desktop Computers•Servers/Networking•DSP and FPGA Power Supply•DC−DC Regulator ModulesFigure 1. Typical Application DiagramSOIC−8D SUFFIXCASE 7511MARKING DIAGRAMPIN CONNECTIONSx= 2, 2A or 3A= Assembly LocationL= Wafer LotY= YearW= Work WeekG= Pb−Free DeviceBST PHASETGGNDBGCOMP/DISFBV CC(Top View)Device Package Shipping†ORDERING INFORMATIONNCP1582DR2G SOIC−8(Pb−Free)2500/Tape & Reel†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our T ape and Reel Packaging Specifications Brochure, BRD8011/D.NCP1582ADR2G SOIC−8(Pb−Free)2500/Tape & ReelNCP1583DR2G SOIC−8(Pb−Free)2500/Tape & Reel NCP158xSeriesOscillatorFrequencySCP Trip Voltage NCP1582350 kHz−350 mV NCP1582A350 kHz−450 mV NCP1583300 kHz−350 mVFigure 2. Typical VGA Card Application DiagramFigure 3. Detailed Block DiagramV CCTG BST PHASEBG GNDPIN FUNCTION DESCRIPTIONPin No.Symbol Description1BST Supply rail for the floating top gate driver. To form a boost circuit, use an external diode to bring thedesired input voltage to this pin (cathode connected to BST pin). Connect a capacitor (C BST) between this pinand the PHASE pin. Typical values for C BST range from 0.1 m F to 1 m F. Ensure that C BST is placed near the IC.2TG Top gate MOSFET driver pin. Connect this pin to the gate of the top N−Channel MOSFET.3GND IC ground reference. All control circuits are referenced to this pin.4BG Bottom gate MOSFET driver pin. Connect this pin to the gate of the bottom N−Channel MOSFET.5V CC Supply rail for the internal circuitry. Operating supply range is 4.5 V to 15 V. Decouple with a 1 m Fcapacitor to GND. Ensure that this decoupling capacitor is placed near the IC.6FB This pin is the inverting input to the error amplifier. Use this pin in conjunction with the COMP pin tocompensate the voltage−control feedback loop. Connect this pin to the output resistor divider (if used) ordirectly to Vout.7COMP/DIS Compensation Pin. This is the output of the error amplifier (EA) and the non−inverting input of the PWM comparator. Use this pin in conjunction with the FB pin to compensate the voltage−control feedback loop. Thecompensation capacitor also acts as a soft−start capacitor. Pull this pin low with an open drain transistor fordisable.8PHASE Switch node pin. This is the reference for the floating top gate driver. Connect this pin to the source of the top MOSFET.ABSOLUTE MAXIMUM RATINGSPin Name Symbol V MAX V MINMain Supply Voltage Input V CC15 V−0.3 VBootstrap Supply Voltage Input BST30 V wrt/GND15 V wrt/PHASE−0.3 VSwitching Node (Bootstrap Supply Return)PHASE24 V−0.7 V−5 V for < 50 nsHigh−Side Driver Output (Top Gate)TG30 V wrt/GND15 V wrt/PHASE−0.3 V wrt/PHASELow−Side Driver Output (Bottom Gate)BG15 V−0.3 V−2 V for < 200 ns Feedback FB 5.5 V−0.3 V COMP/DISABLE COMP/DIS 5.5 V−0.3 VMAXIMUM RATINGSRating Symbol Value Unit Thermal Resistance, Junction−to−Ambient R q JA165°C/W Thermal Resistance, Junction−to−Case R q JC45°C/W Operating Junction Temperature Range T J−40 to 150°C Operating Ambient Temperature Range T A−40 to 85°C Storage Temperature Range T stg−55 to +150°CLead Temperature Soldering (10 sec): Reflow (SMD styles only) Pb−Free(Note 1)260 peak°C Moisture Sensitivity Level MSL1−Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.1.60−180 seconds minimum above 237°C.ELECTRICAL CHARACTERISTICS (0_C < T A < 70_C, −40_C < T J < 125_C (Note 2), 4.5 V < V CC < 13.2 V, 4.5 V < BST < 26.5 V, C TG= C BG= 1.0 nF(REF:NTD30N02), for min/max values unless otherwise noted.)Characteristic Conditions Min Typ Max Unit Input Voltage Range⎯ 4.513.2V Boost Voltage Range⎯ 4.526.5V Supply CurrentQuiescent Supply Current V FB = 1.0 V, No SwitchingV CC= 13.2 V− 1.0 1.75mA Boost Quiescent Current V FB = 1.0 V, No Switching−140−m A Under Voltage LockoutUVLO Threshold V CC Rising Edge 3.85 4.2V UVLO Hysteresis⎯−0.5V Switching RegulatorVFB Feedback Voltage, Control Loop in Regulation T A = 0 to 70°C−40 to 125°C0.7880.80.80.812VOscillator Frequency (NCP1582, NCP1582A)T A = 0 to 70°C−40 to 125°C300350350400kHzOscillator Frequency (NCP1583)T A = 0 to 70°C−40 to 125°C 275300300325kHzRamp−Amplitude Voltage− 1.1−V Minimum Duty Cycle−0−% Maximum Duty Cycle707580% Minimum Pulse Width Static Operating100150ns Blanking Time50ns BG Minimum On Time~500ns Error Amplifier (GM)Transconductance 5.0mmho Open Loop DC Gain5570−DBOutput Source Current Output Sink Current V FB = 0.8 VV FB > 0.8 V8080120120m Am AInput Offset Voltage−2.00 2.0mV Input Bias Current0.1 1.0m A Unity Gain Bandwidth 4.0Mhz Soft−StartSS Source Current V FB < 0.8 V 5.01015m A Switch Over Threshold100% of Vref Current LimitTrip Voltage (NCP1582, NCP1583)Vphase to ground−350mV Trip Voltage (NCP1582A)Vphase to ground−450mV Gate DriversUpper Gate Source Vgs = 6.0 V−0.7A Upper Gate Sink Vugate wrt Phase = 1.0 V 2.4W Lower Gate Source Vgs = 6.0 V−0.7A Lower Gate Sink Vlgate wrt GND = 1.0 V 2.2W PHASE Falling to BG Rising Delay V CC = 12 V, PHASE < 2.0 V, BG > 2.0 V−3090ns BG Falling to TG Rising Delay V CC = 12 V, BG < 2.0 V, TG > 2.0 V−3060ns Enable Threshold0.4V 2.Specifications to −40°C are guaranteed via correlation using standard quality control (SQC), not tested in production.TYPICAL OPERATING CHARACTERISTICSF S W , F R E Q U E N C Y (k H z )V r e f , R E F E R E N C E V O L T A G E (m V )−50−250255075100125T J , JUNCTION TEMPERATURE (°C)S O F T S T A R T S O U R C I N G C U R R E N T (m A )Figure 8. Soft Start Sourcing Current vs.TemperatureFigure 9. I−Limit vs. TemperatureT J , JUNCTION TEMPERATURE (°C)−50−250255075100125DETAILED OPERATING DESCRIPTION GeneralThe NCP158x is an 8−pin PWM controller intended forDC−DC conversion from 5.0 V & 12 V buses. The NCP158xhas a 0.7 A internal gate driver circuit designed to driveN−channel MOSFETs in a synchronous−rectifier bucktopology. The output voltage of the converter can beprecisely regulated down to 800 mV 1.5% when the V FB pinis tied to V OUT. The switching frequency is internally set. Ahigh gain operational transconductance error amplifier(OTA) is used.Duty Cycle and Maximum Pulse Width LimitsIn steady state DC operation, the duty cycle will stabilizeat an operating point defined by the ratio of the input to theoutput voltage. The NCP158x can achieve an 80% dutycycle. There is a built in off−time which ensures that thebootstrap supply is charged every cycle. The NCP158x,which is capable of a 100 nsec pulse width (min.), can allow a 12 V to 0.8 V conversion at 350 kHz.Input Voltage Range (V CC and BST)The input voltage range for both V CC and BST is 4.5 V to 13.2 V with respect to GND and PHASE, respectively. Although BST is rated at 13.2 V with respect to PHASE, it can also tolerate 26.5 V with respect to GND.External Enable/DisableWhen the Comp pin voltage falls or is pulled externally below the 400 mv threshold, it disables the PWM Logic and the gate drive outputs. In this disabled mode, the operational transconductance error amplifier’s (EOTA) output source current is reduced and limited to the Soft Start current of 10m A. Normal Shutdown BehaviorNormal shutdown occurs when the IC stops switching because the input supply reaches UVLO threshold. In this case, switching stops, the internal SS is discharged, and all GATE pins go low. The switch node enters a high impedance state and the output capacitors discharge through the load with no ringing on the output voltage.External Soft StartThe NCP158x features an external soft start function, which reduces inrush current and overshoot of the output voltage. Soft start is achieved by using the internal current source of 10 m A. (typ), which charges the external integrator capacitor of the transconductance amplifier. Figure 10 is a typical soft start sequence. This sequence begins once V CC surpasses its UVLO threshold. During Soft Start, as the Comp Pin rises through 400 mV, the PWM Logic and gate drives are enabled. When the feedback voltage crosses 800mV, the EOTA will be given control to switch to its higher regulation mode output current of 120m A. In the event of an overcurrent during soft start, the overcurrent logic will override the soft start sequence and will shut down the PWM logic and both the high side and low side gates.Figure 10. Soft Start ImplementationVEnableVIsource/SinkTiming Diagram NCP1582: Enable SequenceUVLOUnder V oltage Lockout (UVLO) is provided to ensure that unexpected behavior does not occur when V CC is too low to support the internal rails and power the converter. For the NCP158x, the UVLO is set to ensure that the IC will start up when V CC reaches 4.2 V and shutdown when V CC drops below 3.7 V. This permits operation when converting from a 5.0 input voltage.Current Limit ProtectionIn case of a short circuit or overload, the low−side (LS) FET will conduct large currents. The controller will shut down the regulator in this situation for protection against overcurrent. The low−side R DSon sense is implemented by comparing the voltage at the Phase node when BG starts going low to an internally generated fixed voltage. If the phase voltage is lower than SCP trip voltage, an overcurrent condition occurs and a counter is initiated. When the counter completes, the PWM logic and both HS−FET and LS−FET are turned off. The controller will retry to see if the short circuit or overload condition is removed through the soft start cycle. The minimum turn−on time of the LS−FET is set to be 500 ns. The trip thresholds have a −95 mV, +45 mV process and temperature variation.DriversThe NCP158x includes 0.7 A gate drivers to switch external N−channel MOSFETs. This allows the NCP158x to address high−power as well as low−power conversion requirements. The gate drivers also include adaptive non−overlap circuitry. The non−overlap circuitry increase efficiency, which minimizes power dissipation, by minimizing the body diode conduction time.A detailed block diagram of the non−overlap and gate drive circuitry used in the chip is shown in Figure 11.Figure 11. Block Diagram of Gate Driverand Non−Overlap CircuitryPHASETG BSTV CC BGGNDCareful selection and layout of external components is required, to realize the full benefit of the onboard drivers.The capacitors between V CC and GND and between BST and SWN must be placed as close as possible to the IC. The current paths for the TG and BG connections must be optimized. A ground plane should be placed on the closest layer for return currents to GND in order to reduce loop area and inductance in the gate drive circuit.APPLICATION SECTIONInput Capacitor SelectionThe input capacitor has to sustain the ripple current produced during the on time of the upper MOSFET, so it must have a low ESR to minimize the losses. The RMS value of this ripple is:Iin RMS +I OUT D (1*D)Ǹ,where D is the duty cycle, Iin RMS is the input RMS current,& I OUT is the load current. The equation reaches its maximum value with D = 0.5. Losses in the input capacitors can be calculated with the following equation:P CIN +ESR CIN Iin RMS 2,where P CIN is the power loose in the input capacitors &ESR CIN is the effective series resistance of the input capacitance. Due to large d I /d t through the input capacitors,electrolytic or ceramics should be used. If a tantalum must be used, it must be surge protected. Otherwise, capacitor failure could occur.Calculating Input Start−up CurrentTo calculate the input start up current, the following equation can be used.I inrush +C OUT V OUTt SS,where I inrush is the input current during start−up, C OUT is the total output capacitance, V OUT is the desired output voltage,and t SS is the soft start interval.If the inrush current is higher than the steady state input current during max load, then the input fuse should be rated accordingly, if one is used.Calculating Soft Start TimeTo calculate the soft start time, the following equation can be used.t SS +(C P )C C)*D VI SSWhere C C is the compensation as well as the soft start capacitor,C P is the additional capacitor that forms the second pole.I SS is the soft start currentD V is the comp voltage from zero to until it reachesregulation.V compV outThe above calculation includes the delay from comp rising to when output voltage becomes valid.To calculate the time of output voltage rising to when it reaches regulation; D V is the difference between the comp voltage reaching regulation and 1.1 V .Output Capacitor SelectionThe output capacitor is a basic component for the fast response of the power supply. In fact, during load transient,for the first few microseconds it supplies the current to the load. The controller immediately recognizes the load transient and sets the duty cycle to maximum, but the current slope is limited by the inductor value.During a load step transient the output voltage initial drops due to the current variation inside the capacitor and the ESR. (neglecting the effect of the effective series inductance (ESL)):D V OUT−ESR +D I OUT ESR COUT ,where V OUT−ESR is the voltage deviation of V OUT due to the effects of ESR and the ESR COUT is the total effective series resistance of the output capacitors.A minimum capacitor value is required to sustain the current during the load transient without discharging it. The voltage drop due to output capacitor discharge is given by the following equation:D V OUT−DISCHARGE +D I OUT 2 L OUT2 C OUT (V IN D *V OUT ),where V OUT−DISCHARGE is the voltage deviation of V OUT due to the effects of discharge, L OUT is the output inductor value & V IN is the input voltage.It should be noted that ΔV OUT−DISCHARGE and V OUT−ESR are out of phase with each other, and the larger of these two voltages will determine the maximum deviation of the output voltage (neglecting the effect of the ESL).Inductor SelectionBoth mechanical and electrical considerations influence the selection of an output inductor. From a mechanical perspective, smaller inductor values generally correspond to smaller physical size. Since the inductor is often one of the largest components in the regulation system, a minimum inductor value is particularly important in space−constrained applications. From an electrical perspective, the maximum current slew rate through the output inductor for a buck regulator is given by:SlewRate LOUT +V IN *VOUT L OUT.This equation implies that larger inductor values limit the regulator’s ability to slew current through the output inductor in response to output load transients. Consequently,output capacitors must supply the load current until the inductor current reaches the output load current level. Thisresults in larger values of output capacitance to maintain tight output voltage regulation. In contrast, smaller values of inductance increase the regulator’s maximum achievable slew rate and decrease the necessary capacitance, at the expense of higher ripple current. The peak−to−peak ripple current is given by the following equation:Ipk *pk LOUT +V OUT (1*D)L OUT 350kHz,where Ipk−pk LOUT is the peak to peak current of the output.From this equation it is clear that the ripple current increases as L OUT decreases, emphasizing the trade−off between dynamic response and ripple current.Feedback and CompensationThe NCP158x allows the output of the DC−DC converter to be adjusted from 0.8 V to 5.0 V via an external resistor divider network. The controller will try to maintain 0.8 V at the feedback pin. Thus, if a resistor divider circuit was placed across the feedback pin to V OUT , the controller will regulate the output voltage proportional to the resistordivider network in order to maintain 0.8 V at the FB pin.FBThe relationship between the resistor divider network above and the output voltage is shown in the following equation:R 2+R 1 ǒV REFV OUT *V REFǓ.Resistor R1 is selected based on a design tradeoff between efficiency and output voltage accuracy. For high values of R1 there is less current consumption in the feedback network, However the trade off is output voltage accuracy due to the bias current in the error amplifier. The output voltage error of this bias current can be estimated using the following equation (neglecting resistor tolerance):Error%+0.1m A R 1V REF100%.Once R1 has been determined, R2 can be calculated.Figure 12. Type II Transconductance ErrorAmplifierR C Figure 12 shows a typical Type II transconductance error amplifier (EOTA). The compensation network consists of the internal error amplifier and the impedance networks ZIN (R 1, R 2) and external Z FB (R c , C c and C p ). The compensation network has to provide a closed loop transfer function with the highest 0 dB crossing frequency to have fast response (but always lower than F SW /8) and the highest gain in DC conditions to minimize the load regulation. A stable control loop has a gain crossing with −20dB/decade slope and a phase margin greater than 45°. Include worst−case component variations when determining phase margin. Loop stability is defined by the compensation network around the EOTA, the output capacitor, output inductor and the output divider. Figure 13. shows the open loop and closed loop gain plots.Compensation Network Frequency:The inductor and capacitor form a double pole at the frequencyF LC +12p @L O @C OǸThe ESR of the output capacitor creates a “zero” at the frequency,F ESR +12p @ESR @C O The zero of the compensation network is formed as,F Z +12p @R C C CThe pole of the compensation network is calculated as,F P +12p @R C @C PFigure 13. Gain Plot of the Error AmplifierG A I N (d B )FREQUENCY (Hz)100100010 k100 k1000 kThermal ConsiderationsThe power dissipation of the NCP158x varies with the MOSFETs used, V CC , and the boost voltage (V BST ). The average MOSFET gate current typically dominates the control IC power dissipation. The IC power dissipation is determined by the formula:P IC +(I CC @V CC ))P TG )P BG .Where:P IC = control IC power dissipation,I CC = IC measured supply current,V CC = IC supply voltage,P TG = top gate driver losses,P BG = bottom gate driver losses.The upper (switching) MOSFET gate driver losses are:P TG +Q TG @f SW @V BST .Where:Q TG = total upper MOSFET gate charge at V BST ,f SW = the switching frequency,V BST = the BST pin voltage.The lower (synchronous) MOSFET gate driver losses are:P BG.Where:Q BG = total lower MOSFET gate charge at V CC .The junction temperature of the control IC can then be calculated as:T J +T A )P IC @q JA .Where:T J = the junction temperature of the IC,T A = the ambient temperature,θJA = the junction−to−ambient thermal resistance of the IC package.The package thermal resistance can be obtained from the specifications section of this data sheet and a calculation can be made to determine the IC junction temperature. However,it should be noted that the physical layout of the board, the proximity of other heat sources such as MOSFETs and inductors, and the amount of metal connected to the IC,impact the temperature of the device. Use these calculations as a guide, but measurements should be taken in the actual application.Layout ConsiderationsAs in any high frequency switching converter, layout is very important. Switching current from one power device to another can generate voltage transients across the impedances of the interconnecting bond wires and circuit traces. These interconnecting impedances should be minimized by using wide, short printed circuit traces. The critical components should be located as close together as possible using ground plane construction or single point grounding. The figure below shows the critical power components of the converter. To minimize the voltage overshoot the interconnecting wires indicated by heavy lines should be part of ground or power plane in a printed circuit board. The components shown in the figure below should be located as close together as possible. Please note that the capacitors C IN and C OUT each represent numerous physical capacitors. It is desirable to locate the NCP158x within 1inch of the MOSFETs, Q1 and Q2. The circuit traces for the MOSFETs’ gate and source connections from the NCP158x must be sized to handle up to 2 A peak current.Figure 14. Components to be Considered forLayout SpecificationsRETURNNCP1582, NCP1582A, NCP1583 Design ExampleSwitching Frequency F SW = 350 KHZOutput Capacitance C ESR = 45 m W/EachOutput Capacitance C out = 6630 m FOutput Inductance L out = 0.75 m HInput V oltage V in = 12 VOutput V oltage V out = 3.3 VChoose the loop gain crossover frequency;F CO+110*F SW+35kHzThe corner frequency of the output filter is calculatedbelow;F LC+12*p*0.75m H*6630m FǸ+2.3kHzLet R C = 1500Check that the ESR zero frequency is not too high;F ESR+12*p@CESR@C O t F SW5This condition is mandatory for loop stability.Zero of the compensation network is calculated as follows;F Z+F LCC C+1Z C+12*p*2.3kHz*1500+46nFThe compensation capacitor also acts as the soft start capacitor. By adjusting the value of this compensation capacitor, the soft start time can be adjusted.Pole of the compensation network is calculated as follows;F P+5*F CO+175kHzC P+12*p*F P*R C+12*p*175kHz*1500+700pFThe recommended compensation values are;R C = 1500, C C = 46 nF, C P = 700 pFThe NCP158x bode plot as measured from the network analyzer is shown below.Figure 15. Typical Bode plot of the Open−loop Frequency Response of the NCP158x Top plot: Phase−Frequency (Phase Margin = 62.519°) Bottom plot: Gain−Frequency (UGBW= 5 MHz)NCP1582, NCP1582A, NCP1583 Demo Board PCB LayoutBill of MaterialsItem Number Part Reference Value Quantity MFG 1C1 C2 C3 C41500 m F4PANASONIC 2C5 C6 C722 m F3TDK3C8 1.0 m F1TAIYO YUDEN 4C9100 pF1AVX5C100.022 m F1KEMET6C110.1 m F1AVX7C12 C13 C14 C151800 m F4PANASONIC 8C16 C17 C18 C1910 m F4KEMET9C20OPEN1−10C21OPEN1−11CR1BAS116LT11ON SEMICONDUCTOR 12L10.75 m H1TOKO13Q1 Q240N032ON SEMICONDUCTOR 14R14021DALE15R2OPEN1−16R3 1.02 K1DALE17R4OPEN1−18R6 R702DALE19R8OPEN1−20U1NCP158x1ON SEMICONDUCTORTYPICAL PERFORMANCE CHARACTERISTICSFigure 16. Start UpFigure 17. Gate Waveforms15 A Load SustainingFigure 18. Transient Response (0−10 A Step Load)8083868992123456789101112131415LOAD CURRENT (A)E F F I C I E N C Y (%)Figure 19. Transient ResponseFigure 20. Over Current Protection (22 A DC Trip)Figure 21. Efficiency vs. Load CurrentPACKAGE DIMENSIONSSOIC−8D SUFFIXCASE 751−07ISSUE AHNOTES:1.DIMENSIONING AND TOLERANCING PERANSI Y14.5M, 1982.2.CONTROLLING DIMENSION: MILLIMETER.3.DIMENSION A AND B DO NOT INCLUDEMOLD PROTRUSION.4.MAXIMUM MOLD PROTRUSION 0.15 (0.006)PER SIDE.5.DIMENSION D DOES NOT INCLUDE DAMBARPROTRUSION. ALLOWABLE DAMBARPROTRUSION SHALL BE 0.127 (0.005) TOTALIN EXCESS OF THE D DIMENSION ATMAXIMUM MATERIAL CONDITION.6.751−01 THRU 751−06 ARE OBSOLETE. NEWSTANDARD IS 751−07.DIMAMIN MAX MIN MAXINCHES4.805.000.1890.197MILLIMETERSB 3.80 4.000.1500.157C 1.35 1.750.0530.069D0.330.510.0130.020G 1.27 BSC0.050 BSCH0.100.250.0040.010J0.190.250.0070.010K0.40 1.270.0160.050M0 8 0 8N0.250.500.0100.020S 5.80 6.200.2280.244 YM0.25 (0.010)Z S X S____ǒmminchesǓSCALE 6:1*For additional information on our Pb−Free strategy and solderingdetails, please download the ON Semiconductor Soldering andMounting Techniques Reference Manual, SOLDERRM/D.SOLDERING FOOTPRINT*ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. 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CS5181资料

Copyright © Cirrus Logic, Inc. 1999Cirrus Logic, Inc.P.O. Box 17847, Austin, Texas 78760CS5181∆Σ Modulator & 400 kHz to 625 kHz 16-Bit ADCFeaturesl 16-Bit Delta-Sigma A/D Converter l Fully Differential Input with 4.0 V pp Rangel Dynamic Range: 93dBl Spurious Free Dynamic Range: 90 dBc l Harmonic Distortion: 89 dBl Up to 625kHz Output Word Rate l No Missing Codesl Non-Aliasing Low-Pass Digital Filter l High Speed 3-Wire Serial Interface l Supply Requirements:-VA+ = 5 V, VD+ = 3.3 V: 570 mWl Modulator Output Mode l Power-Down ModeDescriptionCS5181 is a fully calibrated high-speed ∆Σ analog-to-digital converter, capable of 625kSamples/second out-put word rate (OWR). The OWR scales with the master clock. It consists of a 5th order ∆Σ modulator, decimation filter, and serial interface. The chip can use the 2.375V on-chip voltage reference, or an external 2.5V refer-ence. The input voltage range is 1.6× VREFIN V pp fully differential. Multiple CS5181s can be fully synchronized in multi-channel applications with a sync signal. The part has a power-down mode to minimize power consump-tion at times of system inactivity. The high speed digital I/O lines have complementary signals to help reduce ra-diated noise from traces on the PC board layout. The CS5181 can also be operated in modulator-only mode which provides the delta-sigma modulator bitstream as the output.ORDERING INFORMATIONCS5181-BL -40 °C to +85 °C28-pin PLCCAPR ‘99TABLE OF CONTENTSCHARACTERISTICS/SPECIFICATIONS (4)ANALOG CHARACTERISTICS (4)DYNAMIC CHARACTERISTICS (5)DIGITAL CHARACTERISTICS (5)SWITCHING CHARACTERISTICS (6)RECOMMENDED OPERATING CONDITIONS (7)ABSOLUTE MAXIMUM RATINGS (7)GENERAL DESCRIPTION (8)THEORY OF OPERATION (8)Converter Initialization: Calibration and Synchronization (8)Clock Generator (9)Voltage Reference (9)Analog Input (10)Output Coding (10)Modulator-Only mode (10)Instability Indicator (12)Digital Filter Characteristics (12)Serial Interface (12)Power Supplies / Board Layout (12)Power-down Mode (14)PIN DESCRIPTIONS (15)PARAMETER DEFINITIONS (18)APPENDIX A: CIRCUIT APPLICATIONS (20)PACKAGE OUTLINE DIMENSIONS (23)Contacting Cirrus Logic SupportFor a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at: /corporate/contacts/Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product infor-mation describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provid ed “AS IS” without warranty of any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trade-marks and service marks can be found at .TABLE OF FIGURES1.Serial Port Timing (not to scale) (6)2.RESET and SYNC logic and timing. (8)3.CS5181 connection diagram for using the internal voltage reference. (9)4.CS5181 connection diagram for using an external voltage reference. (10)5.Modulator Only Mode Data RTZ Format. (11)6.Circuit to ReconstructReturn-to-Zero (RTZ) Data from SDO/SDO into Original Modulator Bitstream (11)7.Magnitude versus frequency spectrum of modulator bitstream(MCLK = 40.0 MHz). (11)8.Expanded view of the magnitude versus frequency spectrum of modulatorbitstream (MCLK = 40 MHz). (11)9.CS5181 Digital Filter Magnitude Response (MCLK = 40 MHz) (12)10.CS5181 Digital Filter Phase Response (MCLK = 40 MHz) (12)11.CS5181 System Connection Diagram (13)12.Single amplifier driving only AIN+, with AIN- held at a steady dc value (20)13.Performance of amplifier of Figure 11 overdriving AIN+ input to theCS5181 at 3.8 VPP (20)14.Performance of amplifier of Figure 11 with AIN+ driven at 2.0 VPP (20)15.Four amplifier balanced driver. (21)16.Performance of amplifier in Figure 14 (21)17.Performance of amplifier in Figure 14 (22)18.CS5181 Differential Non-linearity plot. (Data taken with repeating ramp) (22)19.Histogram of DNL from Figure 17 (22)20.CS5181 Noise Histogram, 32768 samples. (22)CHARACTERISTICS/SPECIFICATIONSANALOG CHARACTERISTICS (T A = -40 to 85 °C; VA+ = 5 V ±5%, VD+ = 3.3 V ±0.3V; AGND =DGND = 0 V; MCLK = 40.0 MHz; VREFIN = VREFOUT; MODE = VD+; Analog Source Impedance = 301 Ohms with 2200 pF to AGND; Full-Scale input Sinewave at 22 kHz; Unless otherwise noted.)Notes: 1.Dynamic range is tested with a 22 kHz input signal 60 dB below full scale.2.Specification guaranteed by design, characterization, and/or test.3.Full scale fully-differential input span is nominally 1.6 X the VREFIN voltage. The peak negativeexcursion of the signals at AIN+ or AIN- should not go below AGND for proper operation.4.VREFIN current is less than 1 µA under normal operation, but can be as high as ±320 µA during calibration.5.Drift of the on-chip reference alone is typically about ±30 ppm/°C. If using an external reference, totalfull scale drift will be that of the external reference plus an additional ±20 ppm/°C, which is the typical drift of the X1.6 buffer.6.Applies after self-calibration at final operating ambient temperature.ParameterSymbolMin Typ Max Unit Dynamic Performance Dynamic Range(Note 1)DR 8993-dB Total Harmonic Distortion @ 22 kHz (Note 1)THD 8489-dB Signal to (Noise + Distortion)SINAD 8287-dB Spurious Free Dynamic Range SFDR8490-dBc Static Performance Integral Nonlinearity(Note 2)INL -±2-LSB Differential Non-Linearity (Note 2)DNL--±0.5LSB Full Scale Error(Note 6)-±8-LSB Full Scale Drift with Internal Reference (Notes 2 and 5)-±50-ppm/°C Offset Error (Note 6)-±8-LSB Offset Drift (Note 2)-±6.0-µV/°C Analog InputDifferential Input Voltage Range(Note 3)- 1.6 X VREFIN-V pp Common Mode Range CMR 1-VREFIN + 0.25V Input Capacitance- 4.0-pF Differential Input Impedance (capacitive)-300-k ΩCommon Mode Rejection Ratio (Note 2)CMRR50--dB Common Mode Input Current-±160±320µA Reference Input VREFIN2.252.375 2.6V VREFIN Current (Note 4)-1±320µA Reference Output VREFOUT Voltage2.25 2.375 2.5V VREFOUT Output Current --±500µA VREFOUT Impedance-0.1-ΩANALOG CHARACTERISTICS (Continued)Notes:7.All outputs unloaded. All inputs except MCLK held static at VD+ or DGND.8.Power consumption when PWDN = 0 applies only for no master clock applied (MCLK held high or low).9.Measured with a 100 mV pp sine wave on the VA+ supplies at a frequency of 100 Hz.DYNAMIC CHARACTERISTICSDIGITAL CHARACTERISTICS (T A = -40 to 85 °C; VD = 3.3V ±0.3V; AGND = DGND = 0 V)Specifications are subject to change without notice.ParameterSymbolMin TypMaxUnitPower SuppliesPower Supply Current (MODE = 1, PWDN = 1)(Note 7)VA1+, VA2+ = 5 V VD1+, VD2+ = 3.3 V--5392.465100mA mA Power Supply Current (MODE = 1, PWDN = 0)(Notes 7, 8)VA1+, VA2+ = 5 V VD1+, VD2+ = 3.3 V -- 3.70.06260.2mA mA Power Supply Current (MODE = 0, PWDN = 1)(Note 7)VA1+, VA2+ = 5 V VD1+, VD2+ = 3.3 V--5318.96522mA mA Power Supply Current (MODE = 0, PWDN = 0)(Notes 7, 8)VA1+, VA2+ = 5 V VD1+, VD2+ = 3.3 V -- 3.70.06260.2mA mA Power Supply Rejection(Note 9)PSRR-55-dBParameterSymbolMin Typ Max Unit Modulator Sampling Frequency -MCLK -Hz Output Word Rate-MCLK/64-Hz Filter Characteristics (Note 2)-3 dB Corner -MCLK/142.3804-Hz Passband Ripple --±0.05dB Stopband Frequency -MCLK/128-Hz Stopband Rejection 90--dB Group Delay-2370/MCLK-sParameterSymbol Min Typ Max Unit High-Level Input Voltage V IH 2.0--V Low-Level Input VoltageV IL --0.8V High-Level Output Voltage (I O = -100 µA)V OH 2.7--V Low-Level Output Voltage (I O = 100 µA)V OL --0.3V Input Leakage Current I in -±1±10µA Input CapacitanceCin-6-pFSWITCHING CHARACTERISTICS (T A = -40 to 85 °C; VA+ = 5 V ±5%, VD+ = 3.3 V ±0.3 V;AGND = DGND = 0 V; MODE = VD+)Notes:10.Rise and Fall times are specified at 10% to 90% points on waveform.11.RESET, SYNC, and PWDN have Schmitt-trigger inputs.12.Specifications applicable to complementary signals SCLK and SDO.ParameterSymbol Min Typ Max Unit Master Clock Frequency (Note 2)MCLK0.51225 to 4041MHz Master Clock Duty Cycle 45-55%Rise Times(Notes 2, 10, and 11)Any Digital Input, Except MCLKMCLKAny Digital Output t rise-----20100.2/MCLK-ns s ns Fall Times(Notes 2, 10, and 11)Any Digital Input, Except MCLKMCLKAny Digital Outputt fall-----20100.2/MCLK-ns s nsCalibration/SyncRESET rising to MCLK rising-3-ns RESET rising recognized, to FSO falling -988205/MCLK-s SYNC rising to MCLK rising-3-ns SYNC rising recognized to FSO falling -5161/MCLK -s PWDN rising recognized to FSO falling -5168/MCLK-s SYNC high time 1/MCLK --s RESET low time1/MCLK--s Serial Port Timing (Note 12)SCLK frequency -MCLK/3-Hz SCLK high time t 1-1/MCLK -s SCLK low timet 2-2/MCLK -s FSO falling to SCLK rising t 3-2/MCLK +2E-9-s SCLK falling to new data bit t 4- 1.5-ns SCLK rising to FSO risingt 5-1/MCLK -2E-9-sFigure 1. Serial Port Timing (not to scale)RECOMMENDED OPERATING CONDITIONS (AGND = DGND = 0 V)ABSOLUTE MAXIMUM RATINGSWARNING:Operation beyond these limits may result in permanent damage to the device. Normal operation is notguaranteed at these extremes.Specifications are subject to change without notice.ParameterSymbol Min Typ Max Unit DC Power Supplies Digital AnalogVD+VA+ 3.04.75 3.35 3.65.25V V Analog Reference Voltage VREFIN2.25 2.5 2.6V AGND to DGND differential -1000100mV Operating Junction TemperatureT j--120°CParameterSymbolMin Max Unit DC Power SuppliesGround Digital Analog AGND/DGND VD+VA+-0.3-0.3-0.3(VD+) + 0.36.06.0V V V Input Current, Any pin except Supplies I in -±10mA Output CurrentI out -±25mA Power Dissipation (Total)-1000mW Analog Input Voltage V INA -0.3(VA+) + 0.3V Digital Input VoltageV IND -0.3(VD+) + 0.3V Ambient Operating Temperature T A -4085°C Storage TemperatureT stg-65150°CGENERAL DESCRIPTIONThe CS5181 is a monolithic CMOS 16-bit A/D converter designed to operate in continuous mode after being reset.The CS5181 can operate in modulator-only mode in which the bit stream from the modulator is the data output from the device.THEORY OF OPERATIONThe front page of this data sheet illustrates the block diagram of the CS5181.Converter Initialization: Calibration and SynchronizationThe CS5181 does not have an internal power-on re-set circuit. Therefore when power is first applied to the device the RESET pin should be held low until power is established. This resets the converter’s log-ic to a known state. When power is fully established the converter will perform a self-calibration, starting with the first MCLK rising edge after RESET goes high. The converter will use 988,205 MCLK cycles to complete the calibration and to allow the digital filter to fully settle, after which, it will output fully-settled conversion words. The converter will then continue to output conversion words at an output word rate equal to MCLK/64. Figure 2 illustrates the RESET and SYNC logic and timing for the con-verter.The CS5181 is designed to perform conversions continuously with an output rate that is equivalent to MCLK/64. The conversions are performed and the serial port is updated independent of external controls. The converter is designed to measure dif-ferential bipolar input signals, and unipolar signals, with a common mode voltage of between 1.0 V and VREF + 0.25 V. Calibration is performed when the RESET signal to the device is released. If RESET is properly framed to MCLK, the converter can be synchronized to a specific MCLK cycle at the sys-tem level.The SYNC signal can also be used to synchronize multiple converters in a system. When SYNC is used, the converter does not perform calibration. The SYNC signal is recognized on the first rising edge of MCLK after SYNC goes high. SYNC aligns the output conversion to occur every 64 MCLK clock cycles after the SYNC signal is rec-ognized and the filter is settled. After the SYNC is initiated by going high, the converter will wait 5,161 MCLK cycles for the digital filter to settle before putting out a fully-settled conversion word. To synchronize multiple converters in a system, the SYNC pulse should rise on a falling edge of the MCLK signal. This ensures that the SYNC input to all CS5181s in the system will be recognized on the next rising edge of MCLK. Use of the SYNC inputFigure 2. RESET and SYNC logic and timing.is not necessary to make the converter operate properly. If it is unused it should be tied to DGND. Conversion data is output from the SDO and SDO pins of the device. The data is output from the SDO pin MSB first, in two’s complement format. The converter furnishes a serial clock SCLK and its complement SCLK to latch the data bits; and a data frame signal, Frame Signal Output (FSO), which frames the output conversion word. The SCLK output frequency is MCLK/3.Clock GeneratorThe CS5181 must be driven from a CMOS-com-patible clock at its MCLK pin. The MCLK input is powered from the VD+ supply and its signal input should not exceed this supply. The required MCLK is 64 × OWR (Output Word Rate). To achieve an Output Word Rate of 625 kHz, the MCLK frequency must be 64 × 625 kHz, or 40MHz. A second clock input pin, MCLK, is not actually used inside the device but allows the user to run a fully differential clock to the converter to minimize radiated noise from the PC board layout. The CS5181 can be operated with MCLK frequen-cies from 512 kHz up to 40 MHz. The output word rate scales with the MCLK rate with OWR=MCLK/64. Voltage ReferenceThe CS5181 can be configured to operate from ei-ther its internal voltage reference, or from an exter-nal voltage reference.The on-chip voltage reference is nominally 2.375V and is referenced to the AGND pins. This 2.375V reference is output from the VREFOUT pin. It is then filtered and returned to the VREFIN pin. The VREFIN pin is connected to a buffer which has a typical gain of 1.6. This scales the on-chip reference of 2.375V to 3.8V. This value sets the peak-to-peak input voltage into the AIN pins of the converter. Fig-ure 3 illustrates the CS5181 connected to use the in-ternal voltage reference. Note that a 1.0 µF and 0.1µF capacitor are shown connected to the VREFCAP pin to filter out noise. A larger capacitor can be used, but may require a longer reset period when first pow-ering up the part to allow for the reference to stabilize before the part self-calibrates.Alternatively, the CS5181 can be configured to use an external voltage reference. Figure 4 illustrates the CS5181 connected to use a 2.5V external ref-erence. In this case, the maximum peak-to-peak signal input at the AIN pins is 4.0V.Figure 3. CS5181 connection diagram for using the internal voltage reference.Analog InputThe analog signal to the converter is input into the AIN+ and AIN- pins. The input signal is fully dif-ferential with the maximum peak-to-peak ampli-tude of VREFIN X 1.6 V. The signal needs to have a common mode voltage in a range from 1.0V to VREF + 0.25 V for minimum distortion. A resis-tor-capacitor filter should be included on the AIN+ and AIN- inputs of the converter. This should con-sist of a 20Ω resistor and a 2200pF capacitor on each input to ground as illustrated in the systemconnection diagram (Figure 11).Output CodingTable 1 illustrates the output coding for the con-verter when operating with the digital filter (MODE = 1). The converter outputs its data from the serial port in twos complement format, MSB first.The chip offers an MFLAG signal to indicate when the modulator has gone unstable. MFLAG is set when an overrange signal forces the modulator into an unstable condition. Under this condition, output codes from the converter will be locked to either plus or minus full scale as is appropriate for the overrange condition.Modulator-Only modeThe CS5181 can be operated in modulator-only mode by connecting the MODE pin to a logic 0 (DGND).In modulator-only mode the noise-shaped bit-stream from the fifth-order delta-sigma modulator is output from the SDO and SDO (inverse bit-stream) pins.Figure 4. CS5181 connection diagram for using an external voltage reference.Fully Differential BipolarInput Voltage1Twos Complement>(V FS - 1.5 LSB)7FFFV FS - 1.5 LSB7FFF7FFE-0.5 LSB 0000 FFFF-V FS + 0.5 LSB80018000 <(-V FS + 0.5 LSB)8000 Notes: 1.V FS = VREFIN x 1.6Table 1. Output Coding.The data from the modulator is output from SDO/SDO in RTZ (Return to Zero) format. The circuit in Figure 6 can be used to reconstruct the data so it can be captured with the rising or falling edge of MCLK.Table 2 illustrates the magnitude of the input signal into the chip versus the ones density out of the modulator. The table does not take into account the potential offset and gain errors of the modulator and their effect on the ones density.Figure 7 and Figure 8 illustrate magnitude versus frequency plots of the modulator bitstream when running at 40.0 MHz.Fully Differential BipolarInput Voltage 2Modulator OnesDensity 3V FS 75%050%-V FS25%Notes: 2.V FS = VREFIN x 1.63.Ones density is approximate; it does nottake offset and gain errors into consideration.Table 2. Modulator-Only Mode Ones Density.Figure 5. Modulator Only Mode Data RTZ Format.Figure 6. Circuit to Reconstruct Return-to-Zero (RTZ) Data fromSDO/SDO into Original Modulator Bitstream.Figure 7. Magnitude versus frequency spectrum ofmodulator bitstream (MCLK = 40.0 MHz).Figure 8. Expanded view of the magnitude versus fre-quency spectrum of modulator bitstream(MCLK = 40 MHz).Instability IndicatorThe MFLAG signal is functional in both modes of operation of the part and indicates when the modu-lator has been overdriven into an unstable condi-tion. In the modulator only mode (MODE = 0), the MFLAG signal will remain set for 3 MCLK cycles when the modulator goes unstable, before being re-turned to the reset state. While the input condition causing modulator instability persists, the MFLAG signal will continually get set for 3 MCLK cycles and then get reset.When the decimation filter on the part is operation-al (MODE = 1), the MFLAG signal is set when the modulator goes unstable. In this mode, however, the MFLAG signal stays set until 5,120 MCLK cy-cles after the input condition causing modulator in-stablility is removed. This delay is provided to allow the digital filter time to settle, and the part will output fully settled conversion words after the MFLAG signal goes low.Digital Filter CharacteristicsFigure 9 illustrates the magnitude versus frequency plot of the converter when operating at a 625 kHz output word rate. The filter is a non-aliasing 4265 tap filter with a -3 dB corner at 0.4495 of the output word rate and an out-of-band attenuation of at least 90 dB at frequencies above one half the output word rate. The passband ripple is less than ±0.05dB up to the -3 dB corner frequency.Figure10 illustrates the phase response of the dig-ital filter with the converter operating at 625 kHz output word rate. The filter characteristics change proportional to changes in the MCLK rate.The group delay of the digital filter is 2370MCLK cycles (59.3µs with MCLK=40MHz), and the settling time is 4740MCLK cycles (118.5 µs). Serial InterfaceThe CS5181 has a serial interface through which conversion words are output in a synchronous self-clocking format. The serial port consists of the Se-rial Data Output pin (SDO), and its complement (SDO); Serial Clock (SCLK), and its complement (SCLK); and the Frame Sync Output (FSO). FSO falls at the beginning of an output word. Data is output in twos complement format, MSB first. FSO stays low for 16 SCLK cycles. SCLK is out-put at a rate equal to MCLK/3.Power Supplies / Board LayoutThe CS5181 requires an analog supply voltage of 5.0 Volts and a digital supply voltage of 3.3 Volts(nominal) for proper operation.Figure 9. CS5181 Digital Filter Magnitude Response(MCLK = 40 MHz)Figure 10. CS5181 Digital Filter Phase Response(MCLK = 40 MHz)Figure 11 illustrates the system connection diagram for the chip. For best performance, each of the supply pins should be bypassed to the nearest ground pin on the chip. The bypass capacitors should be located as close to the chip as possible. If the chip is surface mounted the bypass capacitors should be on the same side of the circuit card as the chip.The CS5181 is a high speed component that re-quires adherence to standard high-frequency print-ed circuit board layout techniques to maintain optimum performance. These include the use of ground and power planes, using low noise power supplies in conjunction with proper supply decou-pling, minimizing circuit trace lengths, and physi-cal separation of digital and analog components and circuit traces.It is preferred that any clock oscillator circuitry be located on a ground plane separate from the digital plane in order to ensure that digital noise does not induce clock jitter.For additional insight, see the CDB5181 evaluation board for more details. Also refer to Application Note AN18 which covers layout and design rules for high resolution data converters.Figure 11. CS5181 System Connection DiagramPower-down ModeThe CS5181 has a PWDN (power-down) function. When active low, power to most of the converter’s circuitry will be reduced. If MCLK is to be stopped to save power, it should not be stopped until at least ten clock cycles after PWDN is taken low. The ten clock cycles are required to allow the part to turn off it’s internal circuitry. If the part does not get the full ten clock cycles, it will still go into a power down state, but the power dissipation could be more than is listed in the specifications for the full power down condition. When PWDN is active, the calibration information inside of the converter is maintained. When coming out of the power-down state, the converter is not recalibrated and willstart-up similar to when SYNC is initiated.PIN DESCRIPTIONSAnalog Ground AGND Pos. Reference VREF+VA1+Positive Analog Supply Neg. Reference VREF-AIN-Negative Analog Input Reference Output VREFOUT AIN+Positive Analog Input Pos. Reference InputVREFINPWDNPower Down Mode Reference Bypass VREFCAPMODE Modulator Only Mode Analog Ground AGND RESET Reset and CalibrationAnalog Supply VA2+DGND Digital Ground Invalid ConversionMFLAG VD1+Positive Digital Supply Sync. Filter SYNC MCLK Master Clock Digital Ground DGND MCLK Inverse Master Clock Pos. Digital Supply VD2+AGND Analog Ground Inverse Serial ClockSCLK FSO Frame Sync Output Serial ClockSCLKSDO Serial Data Out SDO Inverse Serial Data Out\CS518112342827265678910111213141516171920212223242518AGNDAnalog Ground Analog Ground AGND VA1+Positive Analog Supply Pos. Reference VREF+AGND Analog Ground Neg. Reference VREF-AIN-Negative Analog Input Reference Output VREFOUTAIN+Positive Analog Input Analog Ground AGND AGND Analog Ground Analog Ground AGND PWDN Power Down Mode Reference Input VREFINMODE Modulator Only Mode Reference Bypass VREFCAPRESET Reset and CalibrationAnalog Ground AGND DGND Digital Ground Analog Ground AGND DGND Digital Ground Analog Supply VA2+VD1+Positive Digital Supply Analog Supply VA2+VD1+Positive Digital Supply Invalid ConversionMFLAG DGND Digital Ground Sync. Filter SYNC MCLK Master Clock Digital Ground DGND MCLK Inverse Master Clock Digital Ground DGND DGND Digital Ground Pos. Digital Supply VD2+NC Pos. Digital SupplyVD2+AGND Analog Ground Digital Ground DGND NC Inverse Serial ClockSCLK FSO Frame Sync Output Serial ClockSCLKSDO Serial Data Out SDOInverse Serial Data Out\1234567891011121314151617181920212233323130292827262524234443424140393837363534CS5181Supply InputsV A1+, V A2+ — Positive Analog SupplyInput for the positive analog supply is +5.0 V typical when AGND is 0 V.AGND — Analog GroundAnalog ground for circuits supplied by V A+.VD1+, VD2+ — Positive Digital SupplyInput for positive digital supply is +3.3 V typical when DGND is 0 V.DGND — Digital GroundDigital ground for circuits supplied by VD+.Signal and Reference Related InputsAIN+, AIN- — Differential Analog InputsFully differential signal inputs.VREFIN — Voltage Reference InputVREFOUT or an external reference is connected to VREFIN. Analog input voltage (full scale fully differential peak-to-peak) into the converter is 1.6 times this value.VREF+ — Positive Voltage ReferenceFilter capacitor connection for the reference input buffer. The voltage on this pin equals VREFIN X 1.6.VREF- — Negative Voltage ReferenceVREF- is connected to AGND.VREFOUT — Voltage Reference OutputOutput pin for the 2.375 volt on-chip reference relative to AGND.VREFCAP — Reference BypassFilter capacitor connection for internal reference.Serial Interface I/O SignalsSCLK, SCLK — Serial Interface ClockSerial Clock Output. A gated serial clock output from the converter at a rate equal to 1/3 the MCLK clock rate. The SCLK output is a complement of SCLK and helps reduce radiated noise if the two lines are run adjacent on the PC board layout and drive a balanced load.SDO, SDO — Serial Data OutSerial Data Output. Output pin for 16-bit serial data word. The SDO output is the complement of SDO and helps to reduce radiated noise if the two lines are run adjacent on the PC board layout. Output data is output in twos complement format MSB first.FSO — Frame Sync OutputFrame Sync Output. The Frame Sync Output turns low to indicate the beginning of an output word from the SDO pin. It returns high after the 16 data bits have been clocked out.Control PinsRESET — Reset and CalibrationWhen the RESET pin is pulled to a logic low the converter will perform a reset of its digital logic. When the level on this pin is brought back to a logic high the chip starts normal operation, following a two clock cycle delay period. When MODE = 1, the chip goes through an internal gain and offset calibration routine following this reset sequence.PWDN — Power Down ModeA logic 0 on the PWDN pin will put the device into a power-down mode.MODE — Modulator Only ModeMODE is held at a logic high for normal operation. In normal operation the device utilizes the digital decimation filter and calibration ciruitry. MODE = 0 puts the part in modulator only mode whereby most of the digital circuitry is powered-down and the modulator bit-stream isSYNC — Synchronization of FilterThe SYNC input can be used to restart the digital filter of the converter at the beginning of its convolution cycle. The SYNC input is used to synchronize the filters of multiple converters ina system. When the SYNC signal goes high, the filter will be initialized and will begin itsconvolution cycle on the next rising edge of MCLK. If not used, tie SYNC to DGND.MFLAG — Invalid Conversion FlagMFLAG goes high if the modulator portion of the converter goes unstable. If MFLAG is high, the output data from the converter may be invalid.MCLK, MCLK — Master Clock SignalMaster clock input accepts a CMOS level clock input to the converter with worst case duty cycle of 45-55% (typically 40 MHz). MCLK is not actually used inside the device, but can be PC board.。

NCP5010FCT1G;中文规格书,Datasheet资料

NCP5010500 mW Boost Converter for White LEDsThe NCP5010 is a fixed frequency PWM boost converter with integrated rectification optimized for constant current applications such as driving white LEDs. This device features small size, minimal external components and high−efficiency for use in portable applications and is capable of providing up to 500 mW output power to 2−5 series connected white LEDs. A single resistor sets the LED current and the CTRL pin can be pulse width modulated (PWM) to reduce the LED Current.The device includes True−Cutoff circuitry to disconnect the load from the battery when the device is put into standby mode. To protect the device, an output overvoltage protection, and short circuit protection have been incorporated. The NCP5010 is housed in a low profile, space efficient 1.7 x 1.7 mm Flip−Chip package. The device has been optimized for use with small inductors and ceramic capacitors.Features•2.7 to 5.5 V Input V oltage Range•Efficiency: 84% for 5 LED (V F = 3.5 V by LED) at 30 mA and 4.2 V V IN•Low Noise 1 MHz PWM DC−DC Converter•Open LED Protection and Short Circuit Protection•Serial LEDs Architecture for Uniform Current Matching •1 m A Shutdown Current Facility with True−Cutoff •V ery Small 8−Pin Flip−Chip 1.7 x 1.7 mm Package •This is a Pb−Free DeviceTypical Applications•White LED Backlighting for Small Color LCD Displays •Cellular Phones •Digital Cameras •MP3 Players•High Efficiency Step−up ConverterSee detailed ordering and shipping information in the package dimensions section on page 16 of this data sheet.ORDERING INFORMATIONFigure 1. Efficiency vs. Output Current110100E F F I C I E N C Y (%)I OUT (mA)ENABLEFigure 2. Typical Application CircuitPIN FUNCTION DESCRIPTIONPIN PIN NAME TYPE DESCRIPTIONA1AGND POWER System ground for the analog circuitry. A high quality ground must be provided to avoid spikes and/or uncontrolled operations. This pin is to be connected to the PGND pin.B1V IN POWER Power Supply Input. A ceramic capacitor with a minimum value of 1 m F/6.3 V (X5R or X7R) must beconnected to this pin. This capacitor should be placed as close as possible to this pin. In addition,one end of the external inductor is to be connected at this point.C1V OUT POWER DC−DC converter output. This pin should be directly connected to the load and a low ESR(<30 m W) 1 m F (min) 25 V bypass capacitor. This capacitor is required to smooth the current flowinginto the load, thus limiting the noise created by the fast transients present in this circuit. Since this isa current regulated output, this pin has over voltage protection to protect from open load conditions.Care must be taken to avoid EMI through the PCB copper tracks connected to this pin.A2CTRL INPUT An Active High logic level on this pin enables the device. A built−in pulldown resistor disables thedevice if the pin is left open. This pin can also be used to control the average current into the loadby applying a low frequency PWM signal. If a PWM signal is applied, the frequency should be highenough to avoid optical flicker but be no greater than 1 kHz.C2SW POWER Power switch connection for inductor. Typical application will use a coil from 10 m H to 22 m H andmust be able to handle at least 350 mA. If the desired output power is above 300 mW, the inductorshould have a DCR < 1.4 W.A3NC N/A Not ConnectedB3FB INPUT Feedback voltage input used to close the loop by means of a sense resistor connected between theprimary LED branch and the ground. The output current tolerance is depends upon the accuracy ofthis resistor and a ±5% or better accuracy metal film resistor is recommended. An analog dimmingsignal can be applied to this point to reduce the output current. Please refer to the applicationsection for additional details.C3PGND POWER Power ground. A high quality ground must be used to avoid spikes and/or uncontrolled operation.Care must be taken to avoid high−density current flow in a limited PCB copper track. This pin is tobe connected to the AGND pin.MAXIMUM RATINGSRating Symbol Value Unit Power Supply Voltage (Note 2)V IN7.0V Over Voltage Protection V OUT24V Human Body Model (HBM) ESD Rating (Note 3)ESD HBM2000V Machine Model (MM) ESD Rating (Note 3)ESD MM200VDigital Input Voltage Digital Input Current CTRL−0.3 < V IN < V bat+0.31.0VmAPower Dissipation @ T A = +85 °C P D150mWThermal Resistance Junction−to−Air 8−Pin Flip−Chip Package R q JA(Note 6)°C/WOperating Ambient T emperature Range T A−40 to +85°C Operating Junction T emperature Range T J−40 to +125°C Storage T emperature Range T stg−65 to +150°C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.1.Maximum electrical ratings are defined as those values beyond which damage to the device may occur at T A = 25°C.2.According to JEDEC standard JESD22−A108B.3.This device series contains ESD protection and passes the following tests:Human Body Model (HBM) ±2.0 kV per JEDEC standard: JESD22−A114 for all pins.Machine Model (MM) ±200 V per JEDEC standard: JESD22−A115 for all pins.tchup Current Maximum Rating: ±100 mA per JEDEC standard: JESD78.5.Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J−STD−020A.6.For the 8−Pin Flip−Chip CSP Package, the R q JA is highly dependent on the PCB Heatsink area. For example R q JA can be to 195°C/W with50 mm total area and also 135°C/W with 500 mm. All the bumps have the same thermal resistance and need to be connected thereby optimizingthe power dissipation.ELECTRICAL CHARACTERISTICS (Limits apply for T A between −40°C to +85°C and V IN = 3.6 V, unless otherwise noted)Pin Symbol Rating Min Typ Max Unit B1V IN Supply Voltage 2.7 5.5V C2I PEAK_MAX Switch Current Limit280420560mA NMOS R DS(on)Internal Switch On Resistor0.6 1.0WF OSC PWM Oscillator Frequency0.8 1.0 1.2MHzM DUTY Maximum Duty Cycle9195%E FF Efficiency (Note 7)84%C1OVP ON Overvoltage Clamp Voltage2022V C1OVP H Overvoltage Clamp Hysteresis 1.0V C1P OUT Output power (Note 8)V IN = 3.1 V V IN < 3.1 V 500300mWC1I OUT Minimum Output Current Controlled No Skip Mode(Note 9)1.0mA B3F BV Feedback Voltage Threshold in Steady StateOvertemperature range At 25°C 475490500500525510mVC1F BVLR Feedback Voltage Line Regulation (Notes 9 and 10)From DC to 100 Hz0.20.5%/V B1U VLO V IN Undervoltage Lockout measured at 25°CThreshold to Enable the Converter Threshold to Disable the Converter 2.22.02.42.22.62.4VB1U VLOH Undervoltage Lockout Hysteresis200mV C1I OUTSC Short Circuit Output Current20mA B1S CPT Short Circuit Protection ThresholdDetected Released 354750676587% of V INB1 C2ISTDB Stand by Current, I OUT = 0 mA, CTRL = LowV bat = 4.2 V2.0m AI Q Quiescent CurrentDevice Not Switching (BF = VIN)Device Switching (R FB disconnected)0.41.0mAA2V IL Voltage Input Logic Low0.3V A2V IH Voltage Input Logic High 1.2V A2R CTRL CTRL Pin Pulldown Resistance175370k W 7.Efficiency is defined by 100 * (P out / P in) at 25°CV IN = 4.2 V with L= Coilcraft DT1608C−223I OUT = 30 mA, Load = 5 LEDs (V F = 3.5 V per LED) bypassed by 1 m F X5R8.Guaranteed by design and characterized with L = 22 m H, DCR = 0.7 W max.9.Load = 4 LEDs (V F = 3.5 V by LED), C OUT = 1 m F X5R, L= Coilcraft DT1608C−223.10.V IN = 3.6 V, Ripple = 0.2 V P−P, I OUT= 15 mA.Figure 7. Efficiency vs. Current @ 5 LEDS (17.5 V)L = Coilcraft DT1608C−223Figure 8. Efficiency vs. Current @ 5 LEDS (17.5 V)L = TDK VLF4012AT−2205060708090E F F I C I E N C Y (%)5060708090E F F I C I E N C Y (%)506070809010203040506070E F F I C I E N C Y (%)I OUT (mA)010203040506070I OUT (mA)E F F I C I E N C Y (%)Figure 13. Oscillator Frequency vs. TemperatureFigure 14. NMOS R DS(on) vs. TemperatureE F F I C I E N C Y (%)TEMPERA TURE (°C)F R E Q U E N C Y (M H z )TEMPERA TURE (°C)Figure 15. Typical Skip Mode Threshold vs. V IN(C OUT = 1 m F X5R 25 V )Figure 16. Typical V OUT Ripple in OVP Conditions1 V OUT , 500 mV/div, AC 3 V OUT , 5 V/div, DCFigure 17. Continuous Current Mode (CCM)1 SW, 5 V/div DC, 4 I SW , 50 mA/div, DC, I OUT = 15 mA Figure 18. Discontinuous Current Mode (DCM)1 SW, 5 V/div DC, 4 I SW , 50 mA/div, DC, I OUT = 1 mAFigure 19. Startup for LED Operating, 4 LEDS R BF = 22 W , 1 CTRL, 2 V/div DC, 2 FB, 500 mV/div DC,4 I L 100 mA/div, T = 100 m s/divFigure 20. Duty Cycle Control Waveforms 1 CTRL, 2 V/div DC, 2 FB, 500 mV/div DC,4 I L 100 mA/div, T = 1 ms/div01232.53.0 3.54.0 4.55.0 5.5I O U T (m A )V IN (V)Figure 21. Typical Ripple for Voltage Operation 1 SW, 10 V/div DC, 2 FB, 500 mV/div DC, 3 V OUT20 mV/div AC, T = 500 ns/divDETAIL OPERATING DESCRIPTIONFigure 22. Functional Block DiagramOperationThe NCP5010 DC−DC converter is based on a Current Mode PWM architecture which regulates the feedback voltage at 500 mV under normal operating conditions. The boost converter operates in two separate phases (See Figure 23). The first one is T ON when the inductor is charged by current from the battery to store up energy,followed by T OFF step where the power is transmitted through the internal rectifier to the load. The capacitor C OUT is used to store energy during the T OFF time and to supply current to the load during the T ON stage thus constantly powering the load.Figure 23. Basic DC−DC OperationStart CycleT offT onI valleyI peak 1 MHzSWILI SWI outThe internal oscillator provides a 1 MHz clock signal to trigger the PWM controller on each rising edge (SET signal)which starts a cycle. During this phase the low side NMOS switch is turned on thus increasing the current through the inductor. The switch current is measured by the SENSE CURRENT and added to the RAMP COMP signal. Then PWM COMP compares the output of the adder and the signal from ERROR AMP . When the comparator threshold is exceeded, the NMOS switch is turned off until the rising edge of the next clock cycle. In addition, there are six functions which can reset the flip−flop logic to switch off the NMOS.The MAX DUTY CYCLE COMP monitors the pulse width and if it exceeds 95% (nom) of the cycle time the switch will be turned off. This limits the switch from being on for more than one cycle. Due to IPEAK COMP , the current through the inductor is monitored and compared with the I PEAK_MAX threshold set at 440 mA (nom). If the current exceeds this value, the controller is will turn off the NMOS switch for the remainder of the cycle. This is a safety function to prevent any excessive current that could overload the inductor and the power stage. The four other safety circuits are SHORT CIRCUIT PROTECTION, OVP , UVLO, and THERMAL PROTECTION. Please refer to the detail in following sections.The loop stability is compensated by the ERROR AMP built in integrator. The gain and the loop bandwidth are fixed internally and provides a phase margin greater than 45° whatever the current supplied.LED Current SelectionThe feedback resistor (R FB) determines the average maximum current through the LED string. The control loop regulated the current such that the average voltage at the FB input is 500 mV (nom). For example, should one need a 20 mA output current in the primary branch, R FB should be selected according to the following equation:R FB+F BVI OUT +500mV20mA+25WIn white LED applications it is desirable to operate the LEDs at a specific operating current as the color will shift as the bias current is changed. As a result of this effect, it is recommended to dim the LED string by a pulse width modulation techniques. A low frequency PWM signal can be applied to the CTRL input and by varying the duty cycle the brightness of the LED can be changed. To avoid any optical flicker, the frequency must be higher than 100 Hz and preferably less than 1 kHz. Due to the soft−start function set at 600 m s (nom) with higher frequency the device remains active but the brightness can decrease. Nevertheless in this case, a dimming control using a filtered PWM signal (See Figure 33) can be used. Also for DC voltage control the same technique is suitable and the filter is takes away.Inductor SelectionTo choose the inductor there are three different electrical parameters that need to be considered, the absolute value of the inductor, the saturation current and the DCR. In normal operation, this device is intended to operate in Continuous Conduction Mode (CCM) so the following equation below can be used to calculate the peak current:I PEAK+I OUTh(1*D))V IN D2LFIn the equation above, V IN is the battery voltage, I OUT is the load current, L the inductor value, F the switching frequency, and the duty cycle D is given by:D+ǒ1*V INV OUTǓh is the global converter efficiency which can vary with load current (see Figure 3 thru Figure 8). A good approximation is to use h = 0.8. Figure 24 − Figure 26 are a graphical representation of the above equations, as a function of the desired I OUT, V IN, and number of LEDs in series (V F = 3.5 V nominal). The curves are limited to an I PEAK_MAX of 300 mA. It is important to analyze this at worst case Vf conditions to ensure that the inductor current rated is high enough such that it not saturate.The recommended inductor value should range between 10 m H and 22 m H. As can be seen from the curves, as the inductor size is reduced, the peak current for a given set of conditions increases along with higher current ripple so it is not possible to deliver maximum output power at lower inductor values.IPEAK(mA)IPEAK(mA)Figure 26. Peak Inductor Currents vs. I OUT (mA)@ 5 LEDs, 17.5 VI OUT (mA)IPEAK(mA)分销商库存信息: ONSEMINCP5010FCT1G。

W5181读卡器用户手册

W5181 读写器
用户手册
(V1.0)பைடு நூலகம்
北京握奇数据系统有限公司
二○○九年九月
W5181 读写器用户手册
目录
一、读写器功能和性能介绍............................................................................................................................................ 3 1. W5181 读写器主要功能....................................................................................................................................... 4 2. W5181 读写器主要技术指标..............................................................................................................................5 3. 配套软件............................................................................................................................................................... 6 4. 符合标准.......................................................................................

罗克韦尔 Compact 5000 I O 数字量模块说明书

模块类型 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 模块概述 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 本地 I/O 模块或远程 I/O 模块 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
基于 EtherNet/IP 的连接 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 使用 External Means 时连接的其他注意事项 . . . . . . . . . . . . . . . . 57 受限操作 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 安全模块特定注意事项 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 整体系统安全功能 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 单通道或双通道模式 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 与安全控制器结合使用 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 确定符合性 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

UC5181CQ中文资料

Octal Line ReceiverFEATURES•Meets EIA232E/423A/422A and CCITT V.10, V.11, V.28, X.26, X.27•Single +5V Supply—TTL Compatible Outputs•Differential Inputs withstand ±25V •Low Open Circuit Voltage for Improved Failsafe Characteristic•Reduced Supply Current—35mA Max •Internal Hysteresis DESCRIPTIONThe UC5181C is an octal line receiver designed to meet a wide range of digital communications requirements as outlined in EIA standards EIA232E, EIA422A, EIA423A and CCITT V.10, V.11, V.28, X.26, and X.27. The UC5181C is similar to the UC5180C, but without the input filtering. Thus, it covers the entire range of data rates up to 10MBPS. A failsafe function allows these devices to “fail” to a known state under a wide variety of fault conditions at the inputs.ABSOLUTE MAXIMUM RATINGS(Note 1)Supply Voltage, V CC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V Output Sink Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA Output Short Circuit Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Sec Common Mode Input Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15V Differential Input Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25V Failsafe Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to V CC PLCC Power Dissipation, T A=25° C (Note 2). . . . . . . . . . . . . . . . . . . 1000 mW DIP Power Dissipation, T A=25° C (Note 2). . . . . . . . . . . . . . . . . . . . . 1200 mW Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . -65° C to +150° C Lead Temperature (Soldering, 10 seconds). . . . . . . . . . . . . . . . . . . . . . -300° C Note 1:All voltages are with respect to ground, pin 14. Currents are positive in, negative out of the specified terminal.Note 2:Consult packaging section of Databook for thermal limitations and considerations of package.CONNECTION DIAGRAMSDC ELECTRICAL CHARACTERISTICS:Note 3:R S is a resistor in series with each input.Note 4:Measure after 100 ms warm up (at 0°C).Note 5:Only 1 output may be shorted at a time and then only for amaximum of 1 sec.Note 6:The delays, either t PLH or t PHL , shall not vary from receiver to receiver by more than 35ns.V TL , V TH ,V H DefinitionUnless otherwise stated, these specifications apply for T A = 0°C to +70°C; V CC= 5V ±5%, Input Common Mode Range ±7V, T A =T J.V CC =5V ±5%. T A =0°C to +70°C, Figure 2 T A =T J.APPLICATIONS INFORMATIONFailsafe OperationThese devices provide a failsafe operating mode to guard against input fault conditions as defined in EIA422A and EIA423A standards. These fault conditions are (1) driver in power-off condition, (2) receiver not interconnected with driver, (3) open-circuited interconnecting cable, and (4) short-circuited interconnecting cable. If one of these four fault conditions occurs at the inputs of a receiver,then the output of that receiver is driven to a known logic level. The receiver is programmed by connecting the fail-safe input to V CC or ground. A connection to V CC provides a logic “1" output under fault conditions, while a connec-tion to ground provides a logic ”0". There are two failsafe pins (F S1 and F S2) on the UC5181C where each provides common failsafe control for four receivers.UNITRODE INTEGRA TED CIRCUITS7 CONTINENTAL BLVD. • MERRIMACK, NH 03054TEL. (603) 424-2410 • FAX (603) 424-3460GENERAL LAYOUT NOTESThe drivers and receivers should be mounted close to the system common ground point, with the ground reference tied to the common point to reduce RFI/EMI.Filter connectors or transzorbs should be used to reduce the RFI/EMI, and protecting the system from static (ESD),and electrical overstress (EOS). A filter connector or ca-pacitor will reduce the ESD pulse by 90% typically. A ca-ble dragged across a carpet and connected to a system can easily be charged to over 25,000 volts. This is a met-al to metal contact when the cable is connected to thesystem (no resistance), currents exceed 80 amps with less than a nanosecond rise time. A transzorb provides two functions, the device capacitance inherently acts as a filter capacitor, and the device clamps the ESD and EOS pulses which would pass through the capacitor and de-stroy the devices. The recommended transzorb for the UC5180C and the UC5181C is P6KE22CA.* Transzorb is a trademark of General Semiconductor Industries.PACKAGING INFORMATIONOrderable DeviceStatus (1)Package Type Package Drawing Pins Package Qty Eco Plan (2)Lead/Ball Finish MSL Peak Temp (3)UC5181CQ ACTIVE PLCC FN 2837TBD Cu NiPdAu Level-2-220C-1YEAR UC5181CQTRACTIVEPLCCFN28750TBDCu NiPdAuLevel-2-220C-1YEAR(1)The marketing status values are defined as follows:ACTIVE:Product device recommended for new designs.LIFEBUY:TI has announced that the device will be discontinued,and a lifetime-buy period is in effect.NRND:Not recommended for new designs.Device is in production to support existing customers,but TI does not recommend using this part in a new design.PREVIEW:Device has been announced but is not in production.Samples may or may not be available.OBSOLETE:TI has discontinued the production of the device.(2)Eco Plan -The planned eco-friendly classification:Pb-Free (RoHS),Pb-Free (RoHS Exempt),or Green (RoHS &no Sb/Br)-please check /productcontent for the latest availability information and additional product content details.TBD:The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS):TI's terms "Lead-Free"or "Pb-Free"mean semiconductor products that are compatible with the current RoHS requirements for all 6substances,including the requirement that lead not exceed 0.1%by weight in homogeneous materials.Where designed to be soldered at high temperatures,TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1)lead-based flip-chip solder bumps used between the die and package,or 2)lead-based die adhesive used between the die and leadframe.The component is otherwise considered Pb-Free (RoHS compatible)as defined above.Green (RoHS &no Sb/Br):TI defines "Green"to mean Pb-Free (RoHS compatible),and free of Bromine (Br)and Antimony (Sb)based flame retardants (Br or Sb do not exceed 0.1%by weight in homogeneous material)(3)MSL,Peak Temp.--The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications,and peak solder temperature.Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.TI bases its knowledge and belief on information provided by third parties,and makes no representation or warranty as to the accuracy of such information.Efforts are underway to better integrate information from third parties.TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing orchemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary,and thus CAS numbers and other limited information may not be available for release.In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s)at issue in this document sold by TI to Customer on an annual basis.PACKAGE OPTION ADDENDUM30-Jul-2008TAPE AND REEL INFORMATION*All dimensions are nominalDevicePackage Type Package Drawing Pins SPQReel Diameter (mm)Reel Width W1(mm)A0(mm)B0(mm)K0(mm)P1(mm)W (mm)Pin1Quadrant UC5181CQTR PLCCFN28750330.024.412.9512.95 5.016.024.0Q1*All dimensions are nominalDevice Package Type Package Drawing Pins SPQ Length(mm)Width(mm)Height(mm) UC5181CQTR PLCC FN28750346.0346.041.0IMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries(TI)reserve the right to make corrections,modifications,enhancements,improvements, and other changes to its products and services at any time and to discontinue any product or service without notice.Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty.Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty.Except where mandated by government requirements,testing of all parameters of each product is not necessarily performed.TI assumes no liability for applications assistance or customer product design.Customers are responsible for their products and applications using TI components.To minimize the risks associated with customer products and applications,customers should provide adequate design and operating safeguards.TI does not warrant or represent that any license,either express or implied,is granted under any TI patent right,copyright,mask work right, or other TI intellectual property right relating to any combination,machine,or process in which TI products or services are rmation published by TI regarding third-party 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NCP1014中文数据手册

NCP1010, NCP1011, NCP1012, NCP1013, NCP1014低待机功耗离线SMPS的自给式单片转换器NCP101X 系列集成了一个固定频率的电流模式控制器和一个700V 的MOSFET 。

NCP101X 采用PDIP-7,PDIP-7 鸥翼或SOT-223封装，可提供构造可靠，低成本电源所需的一切，包括软启动，频率抖动，短路保护，跳周期模式（skip cycle ），最大峰值电流调整和动态自供电（无需辅助线圈）。

不像其他的单片解决方案，NCP101X 本来就是没有噪声的：在额定负载工作期间，器件的转换频率为65-100-130kHz 中的一种。

当电流调整值降到给定值以下，例如，输出功率的需求减小，IC 会自动进入通常所说的skip-cycle 模式，从而在较轻负载下提供出色的效率。

因为此时典型的电流值为最大峰值的1/4，所以没有音频噪声。

因此，在待机功耗降到最小的同时，不会产生噪声。

当反馈信号减弱，例如，发生短路或光耦合器损坏时，会进行短路检测。

通过下拉反馈脚的电压或使它经过一个SCR 接地以进行完全锁存，可实现外部禁用。

最后，软启动和频率抖动进一步简化了设计者的工作，可以快速开发出低成本，可靠的离线电源。

为了提高待机性能，连接辅助线圈可停止DSS 工作，在高压下消耗少于100mW 的功率。

在这种模式下，内置的锁存过压保护可以避免在光耦合器损坏时出现致命的电压失控。

这些器件采用经济的8引脚双列直插式和4引脚SOT-223封装。

订购信息参见该数据手册21页封装尺寸部分详细的订购和发货信息。

特点• 内置700V MOSFET ，典型的R Dson 为11Ω和22Ω• 高电压引脚之间有较大的爬电距离• 电流模式固定频率工作：65kHz-100kHz-130kHz • 仅在低峰值电流下的Skip-cycle 工作：无音频噪声！• 动态自供电，无需辅助线圈• 内部1.0ms 的软启动• 带有辅助线圈工作的锁存过压保护• 频率抖动从而有更好的EMI 特征• 自动恢复的内部输出短路保护• 使用辅助线圈时有低于100mW 的待机功耗• 内部热关闭• 直接光耦合器连接• 提供用于瞬态分析的SPICE 模型• 可提供无铅封装典型应用• 用于充电器的低功率AC/DC 适配器• 辅助电源（USB ，办公设备，TV 等）引脚连接NCP1014的最大输出功率特征值-Ip230Vac100-250Vac RDson11Ω-450 mA 动态自供电14W 6.0W11Ω-450 mA 辅助线圈19W8.0W1. 仅为特征值：Tamb=50℃, Fswitching=65kHz, 电路安装在推荐的最小敷铜区域内。

NCV5171中文资料

Characteristic
Test Conditions
Min
Typ
Max Unit
Positive and Negative Error Amplifiers FB Reference Voltage FB Input Current FB Reference Voltage Line Regulation
and Control Changes
• This is a Pb−Free Device

SOIC−8 D SUFFIX CASE 751
MARKING DIAGRAM AND PIN CONNECTIONS
1 VC FB
Test SS
5171E ALYW
G
8 VSW PGND
PGND AGND VSW
VMAX 35 V 30 V 6.0 V 10 V 6.0 V 0.3 V 0V 40 V
VMIN −0.3 V −0.3 V −0.3 V −0.3 V −0.3 V −0.3 V
0V −0.3 V
ISOURCE N/A
1.0 mA 10 mA 1.0 mA 1.0 mA
VC tied to FB; measure at FB FB = VREF VC = FB
1.246 1.276 1.300 V
−1.0
0.1
1.0
mA
−
0.01 0.03 %/V
Positive Error Amp Transconductance Positive Error Amp Gain
FB = 1.0 V, VC = 1.25 V FB = 1.5 V, VC = 1.25 V FB = 1.0 V; VC sources 25 mA FB = 1.5 V; VC sinks 25 mA Reduce VC from 1.5 V until switching stops

NCP1654

400ma?lowoperatingconsumption?15atotempolegatedrive?accuratefullyintegrated65khzoscillator?latchingpwmforcycle?by?cycleduty?cyclecontrol?internallytrimmedinternalreference?2versionsofundervoltagelockoutwithhysteresis?soft?startforsmoothlystartupoperationbversiononly?shutdownfunctionsafetyfeatures?inrushcurrentsdetection?overvoltageprotection?undervoltagedetectionforopenloopdetectionshutdown?brown?outdetection?soft?start?accurateovercurrentlimitation?trueoverpowerlimitationtypicalapplications?tvmonitorspcdesktopsmps?acadapterssmps?whitegoodsotheroff?linesmpsthisdocumentcontainsinformationonaproductunderdevelopment
0−97
%
OSCILLATOR / RAMP GENERATOR BLOCK
Fsw
Switching Frequency
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet.

ICT518FR手册（1）

ICT518FR⼿册（1）第⼀章系統安裝1. 配備表2. 使⽤環境2.1. 使⽤電源2.2. 氣壓2.3. 最⼩⼯作空間2.4. 操作溫度2.5. ⼯作照明2.6. 不斷電系統或穩壓器2.7. ⼀般性注意事項3. 設備安裝3.1. 機械部分組裝3.2. 細部連接3.3. 壓床安裝3.4. 治具安裝3.5. 軟體安裝3.6. 軟體移除3.7. 開機3.8. 關機3.9. 軟體安裝問題排除4. 注意事項4.1. 印表機操作注意事項4.2. 待測電路板注意事項4.3. ⾃動放電功能使⽤環境4.4. ⽇常保養事項5. 系統規格5.1. 測試點數5.2. 測試步驟5.3. 測試時間5.4. 量測範圍5.5. 隔離點電路5.6. IC 開路測試5.7. 可測電路板尺⼨5.8. 主控制電腦5.9. 監視器5.10. 週邊配備5.11. 印表機5.12. 治具型式5.13. 氣壓零件5.14. ⼯作氣壓5.15. 供應電壓5.16. 尺⼨重量5.17. 溫度及溼度5.18. 其他選購配備1. 配備表TR-518FR的標準配備包括下列各項，如因貴客⼾在採購時另有需求，則以送貨單為準。

項⽬品名數量1.使⽤⼿冊 12.TR-518FR Windows95 版軟體 113.電腦主機附 TR-518FR DIGITAL I/O Card(for Windows95)4.14" 彩⾊監視器 15.TR-518FR 測試主機附測試桌 16.壓床 17.40-COLUMN 印表機 18.旋轉臂 19.64-Pin 排線 410.34-Pin 排線 111.D-Type 15-Pin 信號線 112.探棒 113壓棒 6014.內六⾓板⼿ 115. 5 × 20 mm 螺絲 616.印表機⾊帶 117.印表機紙捲 218.PVC 桌墊 119.防塵套 120.壓縮空氣管 12. 使⽤環境適宜的⼯作環境可確保 TR-518FR 之使⽤壽命及⼯作效率。

NCP3101BMNTXG,系列,NCP3101BUCK1GEVB,NCP3101BUCK2GEVB, 规格书,Datasheet 资料

NCP3101CWide Input VoltageSynchronous Buck ConverterThe NCP3101C is a high efficiency, 6 A DC −DC buck converter designed to operate from a 5 V to 12 V supply. The device is capable of producing an output voltage as low as 0.8 V . The NCP3101C can continuously output 6 A through MOSFET switches driven by an internally set 275 kHz oscillator. The 40−pin device provides an optimal level of integration to reduce size and cost of the power supply. The NCP3101C also incorporates an externally compensated transconductance error amplifier and a capacitor programmable soft −start function. Protection features include programmable short circuit protection and input under voltage lockout (UVLO). The NCP3101C is available in a 40−pin QFN package.Features•Split Power Rail 2.7 V to 18 V on PWRVCC •275 kHz Internal Oscillator•Greater Than 90% Max Efficiency •Boost Pin Operates to 35 V •V oltage Mode PWM Control•0.8 V $1% Internal Reference V oltage •Adjustable Output V oltage•Capacitor Programmable Soft −Start •85% Max Duty Cycle•Input Undervoltage Lockout•Resistor Programmable Current Limit •These are Pb −Free DevicesApplications•Servers / Networking•DSP and FPGA Power Supply •DC −DC Regulator ModulesFigure 1. Typical Application Diagram Figure 2. EfficiencyE F F I C I E N C Y (%)I OUT (A)MARKING DIAGRAMSee detailed ordering and shipping information in the package dimensions section on page 24 of this data sheet.ORDERING INFORMATIONQFN40, 6x6CASE 485AKA = Assembly Location WL = Wafer Lot YY = YearWW = Work WeekG= Pb −Free PackageNCP3101C AWLYYWWGFigure 3. Detailed Block DiagramFigure 4. Pin ConnectionsPWRPHS 1PWRPHS 2PWRPHS 3PWRPHS 4PWRGND 5PWRGND 6PWRGND 7PWRGND 8PWRGND 9PWRGND 10P W R G N D 11P W R G N D 1V C C 1A G N D 1A G N D 1F B 16C O M P 1N C 1A G N D 1A G N D 230 PWRVCC 29 PWRVCC 28 PWRVCC 27 PWRVCC 26 PWRVCC 25 TGIN 24 BST 23 AGND 22 CPHS 21 TGOUT0 P W R P H S 9 P W R P H S 8 P W R P H S 7 P W R P H S 6 P W R P H S 5 B G 4 P W R V C C 3 P W R V C C 2 P W R V C C 1 P W R V C CTable 1. PIN FUNCTION DESCRIPTIONPin No Symbol Description1−4, 36−40PWRPHS Power phase node (PWRPHS). Drain of the low side power MOSFET.5−12PWRGNDPower ground. High current return for the low −side power MOSFET. Connect PWRGND with large copper areas to the input and output supply returns, and negative terminals of the input and output capacitors.13VCCSupply rail for the internal circuitry. Operating supply range is 4.5 V to 13.2 V.Decouple with a 1 m F capacitor to GND. Ensure that this decoupling capacitor is placed near the IC.14,15,19,20,23AGND IC ground reference. All control circuits are referenced to these pins.16FBThe inverting input pin to the error amplifier. Use this pin in conjunction with theCOMP pin to compensate the voltage −control feedback loop. Connect this pin to the output resistor divider (if used) or directly to output voltage.17COMP/DISCompensation or disable pin. The output of the error amplifier (EA) and thenon −inverting input of the PWM comparator. Use this pin in conjunction with the FB pin to compensate the voltage −control feedback loop. The compensation capacitor also acts as a soft start capacitor. Pull the pin below 400 mV to disable controller.18NC Not Connected. The pin can be connected to AGND or not connected.21TGOUT High side MOSFET driver output.22CPHS The controller phase sensing for short circuit protection.24BSTSupply rail for the floating top gate driver. To form a boost circuit, use an external diode to bring the desired input voltage to this pin (cathode connected to BST pin).Connect a capacitor (C BST ) between this pin and the CPHS pin.25TGIN High side MOSFET gate.26−34PWRVCC Input supply pin for the high side MOSFET. Connect VCCPWR to the VCC pin or power separately for split rail application..35BGThe current limit set pin.Table 2. ABSOLUTE MAXIMUM RATINGSPin NameSymbol Min Max Unit Main Supply Voltage Control Input V CC −0.315V Main Supply Voltage Power Input PWRVCC −0.330V Bootstrap Supply Voltage vs GroundV BST −0.335V Bootstrap Supply Voltage vs Ground (spikes < =50 ns)V BST_spike−5.040VTable 2. ABSOLUTE MAXIMUM RATINGSSymbolMinPin Name UnitMaxBootstrap Pin Voltage vs V PWRPHS V BST−V PWRPHS−0.315V High Side Switch Max DC Current I PHS07.5AV PWRPHS Pin Voltage V PWRPHS−0.730VV PWRPHS Pin Voltage (spikes < 50 ns)V PWRPHSSP−540V CPHASE Pin Voltage V CPHS−0.730V CPHASE Pin Voltage (spikes < 50 ns)V CPHSTR−540V Current Limit Set and Bottom Gate V BG−0.3V CC < V BG < 15V Current Limit Set and Bottom Gate (spikes < 200 ns)V BGSP−2.0V CC < V BGSP < 15V Top Gate vs Ground V TG−0.330V Top Gate vs Phase V TG−0.3V CC < V TG < 15V Top Gate vs Phase (spikes < 200 ns)V TGSP−2.0V CC < V TGSP < 15VFB Pin Voltage V FB−0.3V CC < V FB < 6.0V COMP/DISABLE VCOMP/DIS−0.3V CC < V COMP/DIS < 6.0V Rating Symbol Symbol Unit Thermal Resistance, Junction−to−Ambient (Note 2)R q JA35°C/W Thermal Resistance, Junction−to−Case (Note 2) atR q JC5°C/W 85°CContinuous Power Distribution (T A = +85°C)P D 1.8W Storage Temperature Range T stg−55 to 150°C Junction Operating Temperature T J−40 to 150°CRF260 peak°C Lead Temperature Soldering (10 sec):Reflow (SMD styles only) Pb−Free (Note 1)Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.NOTE:These devices have limited built−in ESD protection. The devices should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the device.1.60−180 seconds minimum above 237°C2.Based on 110 * 100 mm double layer PCB with 35 m m thick copper plating.Table 3. ELECTRICAL CHARACTERISTICS (−40°C < T J < 125°C; VCC =12 V, BST − PHS = 12 V, BST = 12 V, PHS = 24 V, for min/max values unless otherwise noted).Characteristic Conditions Min Typ Max Unit Power Power Channel PWRV CC− GND 2.718V Input Voltage Range V CC− GND 4.513.2V Boost Voltage Range V BST− GND 4.526.5V SUPPLY CURRENTQuiescent Supply Current V FB = 0.85 V V COMP = 0.4 V,No Switching, V CC = 13.2 V4.1mAQuiescent Supply Current V FB = 0.85 V V COMP = 0.4 VNo Switching, V CC = 5.0 V3.2mA V CC Supply Current V FB = V COMP = 1 V, Switching, V CC = 13.2 V9.115mA V CC Supply Current V FB = V COMP = 1 V, Switching, V CC = 5 V4.88.0mA Boost Quiescent Current V FB = 0.85 V, No Switching, V CC = 13.2 V63m A Shutdown Supply Current V FB = 1 V, VCOMP= 0 V, No Switching, V CC = 13.2 V− 4.1−mA UNDER VOLTAGE LOCKOUTV CC UVLO Threshold V CC Rising Edge 3.8− 4.3V V CC UVLO Hysteresis−−364−mV BST UVLO Threshold Rising BST Rising− 3.82−V BST UVLO Threshold Falling− 3.71−V SWITCHING REGULATORVFB Feedback Voltage, Control Loop in Regulation0°C < T J < 70°C, 4.5 V < V CC < 13.2 V−40°C < T J < 125°C, 4.5 < V CC < 13.2 V0.7920.7880.8000.8000.8080.812VOscillator Frequency0°C < T J < 70°C, 4.5 V < V CC < 13.2 V−40°C < T J < 125°C, 4.5 < V CC < 13.2 V 250233275275300317kHzRamp−Amplitude Voltage0.8 1.1 1.4V Minimum Duty Cycle−7.0−% Maximum Duty Cycle88.5% TG Falling to BG Rising Delay V CC = 12 V, T G < 2.0 V, B G > 2.0 V46ns BG Falling to TG Rising Delay V CC = 12 V, B G < 2.0 V, T G > 2.0 V41ns PWM COMPENSATIONTransconductance 3.1− 3.5mS Open Loop DC Gain Guaranteed by design5570−DBOutput Source Current Output Sink Current V FB < 0.8 VV FB > 0.8 V8080140131200200m AInput Bias Current−0.160 1.0m A ENABLEEnable Threshold (Falling)0.370.4.43V SOFT−STARTDelay to Soft−Start1−5ms SS Source Current V FB < 0.8 V−10.6−m A Switch Over Threshold V FB = 0.8 V−100−% ofVref OVER−CURRENT PROTECTIONOCSET Current Source Sourced from BG Pin before Soft−Start−10−m A OC Threshold R BG = 5 k W−50−mV OC Switch−Over Threshold−700−mV Fixed OC Threshold−99−mV PWM OUTPUT STAGEHigh−Side Switch On−Resistance V CC = 12 V I D = 1 A−18−m W Low−Side Switch On−Resistance V CC = 12 V I D = 1 A−18−m WT J , JUNCTION TEMPERATURE (°C)F S W , F R E Q U E N C Y (k H z )Figure 5. Frequency (F SW ) vs.TemperatureT J , JUNCTION TEMPERATURE (°C)I C C , S U P P L Y C U R R E N T S W I T C H I N G (m A )Figure 6. Switching Current vs. TemperatureT J , JUNCTION TEMPERATURE (°C)V r e f , R E F E R E N C E V OL T A G E (m V )Figure 7. Reference Voltage (V ref ) vs.TemperatureT J , JUNCTION TEMPERATURE (°C)U V L O R I S I N G /F A L L I N G (V )Figure 8. UVLO Threshold vs. Temperature−40−20020406080100120−40−20020406080100120S O F T −S T A R T C U R R E N T (m A )T J, JUNCTION TEMPERATURE (°C)Figure 9. Soft −Start Sourcing vs. TemperatureT J , JUNCTION TEMPERATURE (°C)Figure 10. R DS(on) vs. TemperatureR D S (o n ) (m W )05101520253035−40−2020406080100120T J , JUNCTION TEMPERATURE (°C)I C C , S U P P L Y C U R R E N T S W I T C H I N G (m A )Figure 11. I CC vs. TemperatureL O W −S I D E R D S (o n ) (m W )T J , JUNCTION TEMPERATURE (°C)Figure 12. Low −Side R DS(on)vs. Temperature−40−2020406080100120T J , JUNCTION TEMPERATURE (°C)Figure 13. Transconductance vs. TemperatureT R A N S C O N D U C T A N C E (m S )3.203.253.303.353.403.453.503.553.60−40−2020406080100120I C C , C O N T R O L C I R C U I T R Y CU R -R E N T D R A W (m A )V IN , INPUT VOLTAGE (V)Figure 14. Maximum Duty Cycle vs. InputVoltage838485868788−D U T Y C Y C L E (%)JUNCTION TEMPERATURE (°C)Figure 15. Controller Current vs. Input Voltage 798.0798.2798.4798.6798.8799.045678910111213V O L T A G E R E F E R E N C E (m V )V IN , INPUT VOLTAGE (V)Figure 16. Reference Voltage vs. Input Voltage123456−40−20020406080100120D U T Y C Y C LE (%)JUNCTION TEMPERATURE (°C)Figure 17. Minimum Duty Cycle vs.TemperatureDETAILED OPERATING DESCRIPTIONGeneralNCP3101C is a high efficiency integrated wide input voltage 6 A synchronous PWM buck converter designed to operate from a 4.5 V to 13.2 V supply. The output voltage of the converter can be precisely regulated down to 800 mV +1.0% when the VFB pin is tied to the output voltage. The switching frequency is internally set to 275 kHz. A high gain Operational Transconductance Error Amplifier (OTEA) is used for feedback and stabilizing the loop.Input VoltageThe NCP3101C can be used in many applications by using the V CC and PWRVCC pins together or separately.The PWRVCC pin provides voltage to the switching MOSFETS. The V CC pin provides voltage to the control circuitry and driver stage.If the V CC and the PWRVCC pin are not tied together, the input voltage of the PWRVCC pin can accept 2.7 V to 18 V .If the V CC and PWRVCC pins are tied together the input voltage range is 4.5 V to 13.2 V .Duty Cycle and Maximum Pulse Width LimitsIn steady state DC operation, the duty cycle will stabilize at an operating point defined by the ratio of the input to the output voltage. The NCP3101C can achieve an 82% duty ratio. The part has a built in off −time which ensures that the bootstrap supply is charged every cycle. The NCP3101C is capable of a 100 ns pulse width (minimum) and allows a 12 V to 0.8 V conversion at 275 kHz. The duty cycle limit and the corresponding output voltage are shown below in graphical format in Figure 18. The green area represents the safe operating area for the lowest maximum operational duty cycle for 4.5 V and 13.2 V .Figure 18. Maximum Input to Output Voltage4.5.6.7.8.9.3.54.55.56.57.58.59.510.511.5I N P U T V O L T A G E (V )OUTPUT VOLTAGE (V)Input voltage range (VCC and BST)The input voltage range for both VCC and BST is 4.5 V to 13.2 V with reference to GND and PHS, respectively.Although BST is rated at 13.2 V with reference to PHS, it can also tolerate 26.5 V with respect to GND.External Enable/DisableOnce the input voltage has exceeded the boost and UVLO threshold at 3.82 V and V CC threshold at 4 V , the COMP pin starts to rise. The PWRPHS node is tri −stated until the COMP voltage exceeds 830 mV . Once the 830 mV threshold is exceeded, the part starts to switch and is considered enabled. When the COMP pin voltage is pulled below the 400 mV threshold, it disables the PWM logic, the top MOSFET is driven off, and the bottom MOSFET is driven on as shown in Figure 19. In the disabled mode, the OTA output source current is reduced to 10 m A.When disabling the NCP3101C using the COMP / Disable pin, an open collector or open drain drive should be used asshown in Figure 20.COMP0.83 VBG TGFigure 19. Enable/Disable Driver State DiagramCOMPCOMPFigure 20. Recommended Disable Circuits Power SequencingPower sequencing can be achieved with NCP3101C using two general purpose bipolar junction transistors or MOSFETs. An example of the power sequencing circuit using the external components is shown in Figure 21.Figure 21. Power SequencingNormal Shutdown BehaviorNormal shutdown occurs when the IC stops switching because the input supply reaches UVLO threshold. In this case, switching stops, the internal soft start, SS, is discharged, and all gate pins go low. The switch node enters a high impedance state and the output capacitors discharge through the load with no ringing on the output voltage. External Soft−StartThe NCP3101C features an external soft start function, which reduces inrush current and overshoot of the output voltage. Soft start is achieved by using the internal current source of 10 m A (typ), which charges the external integrator capacitor of the transconductance amplifier. Figures 22 and 23 are typical soft start sequences. The sequence begins once V CC surpasses its UVLO threshold. During Soft Start as the Comp Pin rises through 400 mV, the PWM logic and gate drives are enabled. When the feedback voltage crosses 800 mV, the EOTA will be given control to switch to its higher regulation mode with the ability to source and sink 130 m A. In the event of an over current during the soft start, the overcurrent logic will override the soft start sequence and will shut down the PWM logic and both the high side and low side gates of the switching MOSFETS.VfbsinkNormalStart upFigure 22. Soft−Start ImplementationDelay DelayFigure 23. Soft−Start SequenceUVLOUnder V oltage Lockout (UVLO) is provided to ensure that unexpected behavior does not occur when V CC is too low to support the internal rails and power the converter. For the NCP3101C, the UVLO is set to ensure that the IC will start up when VCC reaches 4.0 V and shutdown when V CC drops below 3.6 V. The UVLO feature permits smooth operation from a varying 5.0 V input source.Current Limit ProtectionIn case of a short circuit or overload, the low−side (LS) FET will conduct large currents. The low−side R DS(on) sense is implemented to protect from over current by comparing the voltage at the phase node to AGND just prior to the low side MOSFET turnoff to an internally generated fixed voltage. If the differential phase node voltage is lower than OC trip voltage, an overcurrent condition occurs and a counter is initiated. If seven consecutive over current trips are counted, the PWM logic and both HS−FET and LS−FET are turned off. The converter will be latched off until input power drops below the UVLO threshold. The operation of key nodes are displayed in Figure 24 for both normal operation and during over current conditions.Switch Node 2V2VHS Gate DriveSwitch Node ComparatorBG Comparator2V LS Gate DriveSCP Trip VoltageC PhaseSCP Comparator/Latch OutputFigure 24. Switching and Current Limit Timing Overcurrent Threshold SettingThe NCP3101C overcurrent threshold can be set from 50 mV to 450 mV by adding a resistor (RSET) between BG and GND. During a short period of time following V CC rising above the UVLO threshold, an internal 10 m A current (IOCSET) is sourced from the BG pin, creating a voltage drop across RSET. The voltage drop is compared against a stepped internal voltage ramp. Once the internal stepped voltage reaches the RSET voltage, the value is stored internally until power is cycled. The overall time length for the OC setting procedure is approximately 3 ms. When connecting an RSET resistor between BG and GND, the programmed threshold will be:I OCth +I OCSET *R SETR DS(on)³7.2A +10m A *13k W18m W(eq. 1)I OCSET = Sourced current I OCTH = Current trip threshold R DS(on) = On resistance of the low side MOSFET R SET = Current set resistorThe RSET values range from 5 k W to 45 k W . If RSET is not connected or the RSET value is too high, the device switches the OCP threshold to a fixed 96 mV value (5.3 A)typical at 12 V . The internal safety clamp on BG is triggeredas soon as BG voltage reaches 700 mV , enabling the 96 mV fixed threshold and ending the OC setting period. The current trip threshold tolerance is $25 mV . The accuracy is best at the highest set point (550 mV). The accuracy will decrease as the set point decreases.DriversThe NCP3101C drives the internal high and low side switching MOSFETS with 1 A gate drivers. The gate drivers also include adaptive non −overlap circuitry. The non −overlap circuitry increases efficiency which minimizes power dissipation by minimizing the low −side MOSFET body diode conduction time.A block diagram of the non −overlap and gate drive circuitry used is shown in Figure 24.Figure 25. Block DiagramTGBSTV CC BGGNDCareful selection and layout of external components is required to realize the full benefit of the onboard drivers.The capacitors between V CC and GND and between BST and CPHS must be placed as close as possible to the IC. A ground plane should be placed on the closest layer for return currents to GND in order to reduce loop area and inductance in the gate drive circuit.APPLICATION SECTION Design ProcedureWhen starting the design of a buck regulator, it isimportant to collect as much information as possible aboutthe behavior of the input and output before starting thedesign.ON Semiconductor has a Microsoft Excel® based designtool available online under the design tools section of theNCP3101C product page. The tool allows you to captureyour design point and optimize the performance of yourregulator based on your design criteria.Table 4. DESIGN PARAMETERSDesign Parameter Example ValueInput voltage (VCC)10.8 V to 13.2 VOutput voltage (V OUT) 3.3 VInput ripple voltage (VCC RIPPLE)300 mVOutput ripple voltage (V OUTRIPPLE)40 mVOutput current rating (I OUT) 6 AOperating frequency (F SW)275 kHzThe buck converter produces input voltage V CC pulsesthat are LC filtered to produce a lower DC output voltageV OUT. The output voltage can be changed by modifying theon time relative to the switching period T or switching frequency. The ratio of high side switch on time to theswitching period is called duty ratio D. Duty ratio can alsobe calculated using V OUT, V CC, Low Side Switch V oltageDrop V LSD, and High Side Switch V oltage Drop V HSD.F SW+1T(eq. 2)D+T ONT(1*D)+T OFFT(eq. 3)D+V OUT)V LSDV CC*V HSD)V LSD[D+V OUTV CC³(eq. 4)27.5%+3.3V 12VD= Duty cycleF SW= Switching frequencyT= Switching periodT OFF= High side switch off timeT ON= High side switch on timeV HSD= High side switch voltage dropVCC= Input voltageV LSD= Low side switch voltage dropV OUT= Output voltageInductor SelectionWhen selecting an inductor, the designer may employ a rule of thumb for the design where the percentage of ripple current in the inductor should be between 10% and 40%. When using ceramic output capacitors, the ripple current can be greater because the ESR of the output capacitor is small, thus a user might select a higher ripple current. However, when using electrolytic capacitors, a lower ripple current will result in lower output ripple due to the higher ESR of electrolytic capacitors. The ratio of ripple current to maximum output current is given in Equation 5.ra+D II OUT(eq. 5) D I = Ripple currentI OUT= Output currentra = Ripple current ratioUsing the ripple current rule of thumb, the user can establish acceptable values of inductance for a design using Equation 6.L OUT+V OUTI OUT*ra*F SW*(1*D)³(eq. 6) 5.6m H+12V6.0A*26%*275kHz*(1*27.5%)D = Duty ratioF SW= Switching frequencyI OUT= Output currentL OUT= Output inductancera = Ripple current ratioFigure 26. Inductance vs. Current Ripple Ratio INDUCTANCE(mH)RIPPLE CURRENT RATIO (%)When selecting an inductor, the designer must not exceed the current rating of the part. To keep within the bounds of the part’s maximum rating, a calculation of the RMS current and peak current are required.I RMS+I OUT*1)ra2 12Ǹ³(eq. 7)6.02A+6A*1)26%2 12ǸI OUT= Output currentI RMS= Inductor RMS current ra = Ripple current ratioI PK+I OUT*ǒ1)ra2Ǔ³6.78A+6.0A*ǒ1)26%2Ǔ(eq. 8)I OUT= Output currentI PK= Inductor peak currentra = Ripple current ratioA standard inductor should be found so the inductor will be rounded to 5.6 m H. The inductor should support an RMS current of 6.02 A and a peak current of 6.78 A.The final selection of an output inductor has both mechanical and electrical considerations. From a mechanical perspective, smaller inductor values generally correspond to smaller physical size. Since the inductor is often one of the largest components in the regulation system, a minimum inductor value is particularly important in space constrained applications. From an electrical perspective, the maximum current slew rate through the output inductor for a buck regulator is given by Equation 9.SlewRate LOUT+V CC*V OUTL OUT³1.56A+12V*3.3V5.6m H(eq. 9)L OUT= Output inductanceV CC= Input voltageV OUT= Output voltageEquation 9 implies that larger inductor values limit the regulator’s ability to slew current through the output inductor in response to output load transients. Consequently, output capacitors must supply the load current until the inductor current reaches the output load current level. Reduced inductance to increase slew rates results in larger values of output capacitance to maintain tight output voltage regulation. In contrast, smaller values of inductance increase the regulator’s maximum achievable slew rate and decrease the necessary capacitance at the expense of higher ripple current. The peak−to−peak ripple current is given by the following equation:I PP+V OUTǒ1*DǓL OUT*F SW³(eq. 10)1.56A+3.3Vǒ1*27.5%Ǔ5.6m H*275kHzD= Duty ratioF SW= Switching frequency I PP=Peak−to−peak current of the inductorL OUT= Output inductanceV OUT= Output voltageFrom Equation 10 it is clear that the ripple current increases as L OUT decreases, emphasizing the trade−off between dynamic response and ripple current.The power dissipation of an inductor falls into two categories: copper and core losses. Copper losses can be further categorized into DC losses and AC losses. A good first order approximation of the inductor losses can be made using the DC resistance as shown below:LP CU_DC+I RMS2*DCR³199mW+6.022*5.5m W(eq. 11)I RMS= Inductor RMS currentDCR= Inductor DC resistanceLP CU_DC= Inductor DC power dissipationThe core losses and AC copper losses will depend on the geometry of the selected core, core material, and wire used. Most vendors will provide the appropriate information to make accurate calculations of the power dissipation, at which point the total inductor losses can be captured by the equation below:LP tot+LP CU_DC)LP CU_AC)LP Core³(eq. 12) 204mW+199mW)2mW)3mWLP CU_DC= Inductor DC power dissipationLP CU_AC= Inductor AC power dissipationLP Core= Inductor core power dissipationOutput Capacitor SelectionThe important factors to consider when selecting an output capacitor are DC voltage rating, ripple current rating, output ripple voltage requirements, and transient response requirements.The output capacitor must be rated to handle the ripple current at full load with proper derating. The RMS ratings given in datasheets are generally for lower switching frequency than used in switch mode power supplies, but a multiplier is usually given for higher frequency operation. The RMS current for the output capacitor can be calculated below:CO RMS+I OUTraǸ³0.45A+6.0A26%Ǹ(eq. 13) Co RMS= Output capacitor RMS currentI OUT= Output currentra = Ripple current ratioThe maximum allowable output voltage ripple is a combination of the ripple current selected, the output capacitance selected, the Equivalent Series Inductance (ESL), and Equivalent Series Resistance (ESR).The main component of the ripple voltage is usually due to the ESR of the output capacitor and the capacitance selected, which can be calculated as shown in Equation 14:V ESR_C+I OUT*raǒCO ESR)18*F SW*C OUTǓ(eq. 14)19.6mV+6*26%ǒ12m W)18*275kHz*820m FǓCo ESR= Output capacitor ESRC OUT= Output capacitanceF SW= Switching frequencyI OUT= Output currentra = Ripple current ratioThe ESL of capacitors depends on the technology chosen, but tends to range from 1 nH to 20 nH, where ceramic capacitors have the lowest inductance and electrolytic capacitors have the highest. The calculated contributing voltage ripple from ESL is shown for the switch on and switch off below:V ESLON+ESL*I PP*F SWD³(eq. 15)15.6mV+10nH*1.56A*275kHz27.5%V ESLOFF+ESL*I PP*F SWǒ1*DǓ³(eq. 16)5.92mV+10nH*1.56A*275kHzǒ1*27.5%ǓD= Duty ratioESL = Capacitor inductanceF SW= Switching frequencyIpp= Peak−to−peak currentThe output capacitor is a basic component for fast response of the power supply. For the first few microseconds of a load transient, the output capacitor supplies current to the load. Once the regulator recognizes a load transient, it adjusts the duty ratio, but the current slope is limited by the inductor value.During a load step transient, the output voltage initially drops due to the current variation inside the capacitor and the ESR (neglecting the effect of the ESL). The user must also consider the resistance added due to PCB traces and any connections to the load. The additional resistance must be added to the ESR of the output capacitor.D V OUT−ESR+I TRANǒCO ESR)RCONǓ³(eq. 17) 111mV+3Aǒ12m W)25m WǓCo ESR= Output capacitor Equivalent SeriesResistanceI TRAN= Output transient current D V OUT_ESR= V oltage deviation of V OUT due to theeffects of ESRA minimum capacitor value is required to sustain the current during the load transient without discharging it. The voltage drop due to output capacitor discharge is given by the following equation:D V OUT−DIS+ǒITRANǓ2LOUT2*D MAX*C OUTǒV CC*V OUTǓ³(eq. 18) 4.16mV+ǒ3AǓ2 5.6m H2*82%*820m Fǒ12V*3.3VǓC OUT = Output capacitanceD MAX = Maximum duty ratioI TRAN = Output transient currentL OUT = Output inductor valueVCC = Input voltageV OUT = Output voltageD V OUT_DIS= V oltage deviation of V OUT due to theeffects of capacitor dischargeIn a typical converter design, the ESR of the output capacitor bank dominates the transient response. Please note that D V OUT_DIS and D V OUT_ESR are out of phase with each other, and the larger of these two voltages will determine the maximum deviation of the output voltage (neglecting the effect of the ESL).Table 5 shows values of voltage drop and recovery time of the NCP3101C demo board with the configuration shown in Figure 27. The transient response was measured for the load current step from 3 A to 6 A (50% to 100% load). Input capacitors are 2 x 47 m F ceramic and 1 x 270 m F OS−CON, output capacitors are 2 x 100 m F ceramic and OS−CON as mentioned in Table 5. Typical transient response waveforms are shown in Figure 27.More information about OS−CON capacitors is available at .。

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