IS24C01-PA中文资料

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CAT24C0A1GWA-1.8TE13资料

© 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 1Doc. No. 1081, Rev. EVDis co n ti n ue dPa rt CAT24C01B2Doc. No. 1081, Rev. E© 2005 by Catalyst Semiconductor, Inc.Characteristics subject to change without noticeABSOLUTE MAXIMUM RATINGS*Temperature Under Bias .................–55°C to +125°C Storage Temperature.......................–65°C to +150°C Voltage on Any Pin withRespect to Ground (1)...........–2.0V to +V CC + 2.0V V CC with Respect to Ground ...............–2.0V to +7.0V Package Power DissipationCapability (Ta = 25°C)..................................1.0W Lead Soldering Temperature (10 secs)............300°C Output Short Circuit Current (2)........................100mA *COMMENTStresses above those listed under “Absolute Maximum Ratings ” may cause permanent damage to the device.These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.RELIABILITY CHARACTERISTICS Symbol Parameter Min MaxUnits Reference Test MethodN END (3)Endurance 1,000,000Cycles/Byte MIL-STD-883, Test Method 1033T DR (3)Data Retention 100Years MIL-STD-883, Test Method 1008V ZAP (3)ESD Susceptibility 2000Volts MIL-STD-883, Test Method 3015I LTH (3)(4)Latch-up100mAJEDEC Standard 17D.C. OPERATING CHARACTERISTICSV CC = +1.8V to +6.0V, unless otherwise specified.Limits Symbol ParameterMin TypMax Units Test Conditions I CC Power Supply Current 3mA f SCL = 100 KHz I SB (5)Standby Current (V CC = 5.0V)1µA V IN = GND or V CC I LI Input Leakage Current 10µA V IN = GND to V CC I LO Output Leakage Current 10µA V OUT = GND to V CCV IL Input Low Voltage –1V CC x 0.3V V IH Input High VoltageV CC x 0.7V CC + 0.5V V OL1Output Low Voltage (V CC = 3.0V)0.4V I OL = 3 mA V OL2Output Low Voltage (V CC = 1.8V)0.5VI OL = 1.5 mANote:(1)The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DCvoltage on output pins is V CC +0.5V, which may overshoot to V CC + 2.0V for periods of less than 20ns.(2)Output shorted for no more than one second. No more than one output shorted at a time.(3)These parameter are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100and JEDEC test methods.(4)Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V CC +1V.(5)Maximum standby current (I SB ) = 10µA for the Automotive and Extended Automotive temperature range.CAPACITANCE T A = 25°C, f = 1.0 MHz, V CC = 5V Symbol TestMax Units Conditions C I/O (3)Input/Output Capacitance (SDA)8pF V I/O = 0V C IN (3)Input Capacitance (A0, A1, A2, SCL, WP)6pFV IN = 0VCAT24C01B3Doc. No. 1081, Rev. E© 2005 by Catalyst Semiconductor, Inc.Characteristics subject to change without noticeA.C. CHARACTERISTICSV CC = +1.8V to +6.0V, C L =1TTL Gate and 100pF (unless otherwise specified).Read & Write Cycle Limits Note:(1)This parameter is tested initially and after a design or process change that affects the parameter.(2)t PUR and t PUW are the delays required from the time V CC is stable until the specified operation can be initiated.The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write cycle, the businterface circuits are disabled, SDA is allowed to remainhigh, and the device does not respond to its input.dPa rt CAT24C01B4Doc. No. 1081, Rev. E© 2005 by Catalyst Semiconductor, Inc.Characteristics subject to change without noticeFUNCTIONAL DESCRIPTIONThe CAT24C01B uses a 2-wire data transmission pro-tocol. The protocol defines any device that sends data to the bus to be a transmitter and any device receiving data to be a receiver. Data transfer is controlled by the Master device which generates the serial clock and all START and STOP conditions for bus access. The CAT24C01B operates as a Slave device. Both the Master and Slave devices can operate as either transmitter or receiver, but the Master device controls which mode is activated.PIN DESCRIPTIONSSCL: Serial ClockThe CAT24C01B serial clock input pin is used to clock all data transfers into or out of the device. This is an input pin.SDA: Serial Data/AddressThe CAT24C01B bidirectional serial data/address pin is used to transfer data into and out of the device. The SDA pin is an open drain output and can be wired with other open drain or open collector outputs.2-WIRE BUS PROTOCOLThe following defines the features of the 2-wire bus protocol:(1)Data transfer may be initiated only when the bus isnot busy.(2)During a data transfer, the data line must remainstable whenever the clock line is high. Any changes in the data line while the clock line is high will be interpreted as a START or STOP condition.Figure 3. Start/Stop Timing5020 FHD F055020 FHD F03SCLSDA INSDA OUTSTART BITSDA STOP BITSCLDis co n ti n ue dPa rt CAT24C01B5Doc. No. 1081, Rev. E© 2005 by Catalyst Semiconductor, Inc.Characteristics subject to change without noticeSTART ConditionThe START Condition precedes all commands to the device, and is defined as a HIGH to LOW transition of SDA when SCL is HIGH. The CAT24C01B monitors the SDA and SCL lines and will not respond until this condition is met.STOP ConditionA LOW to HIGH transition of SDA when SCL is HIGH determines the STOP condition. All operations must end with a STOP condition.AcknowledgeAfter a successful data transfer, each receiving device is required to generate an acknowledge. The Acknowledg-ing device pulls down the SDA line during the ninth clock cycle, signaling that it received the 8 bits of data.The CAT24C01B responds with an acknowledge after receiving a START condition and its slave address. If the device has been selected along with a write operation,it responds with an acknowledge after receiving each 8-bit byte.When the CAT24C01B is in a READ mode it transmits 8 bits of data, releases the SDA line, and monitors the line for an acknowledge. Once it receives this acknowl-edge, the CAT24C01B will continue to transmit data. If no acknowledge is sent by the Master, the device terminates data transmission and waits for a STOP condition.WRITE OPERATIONSByte WriteIn the Byte Write mode, the Master device sends the START condition and the slave address information (with the R/W bit set to zero) to the Slave device. After the Slave generates an acknowledge, the Master sends the byte address that is to be written into the address pointer of the CAT24C01B. After receiving another acknowl-edge from the Slave, the Master device transmits the data byte to be written into the addressed memory location. The CAT24C01B acknowledge once more and the Master generates the STOP condition, at which time the device begins its internal programming cycle to nonvolatile memory. While this internal cycle is in progress, the device will not respond to any request from the Master device.Page WriteThe CAT24C01B writes up to 4 bytes of data in a single write cycle, using the Page Write operation. The Page Write operation is initiated in the same manner as the Byte Write operation, however instead of terminating after the initial word is transmitted, the Master is allowed to send up to 3 additional bytes. After each byte has been transmitted the CAT24C01B will respond with an ac-knowledge, and internally increment the low order ad-dress bits by one. The high order bits remain un-changed.If the Master transmits more than 4 bytes prior to sending the STOP condition, the address counter ‘wraps around,’and previously transmitted data will be overwritten.Once all 4 bytes are received and the STOP condition has been sent by the Master, the internal programming cycle begins. At this point all received data is written to the CAT24C01B in a single write cycle.Note: Catalyst Semiconductor does program all "1" datainto the entire memory array prior to shipping our EEPROM products.Figure 4. Acknowledge Timing5020 FHD F06ACKNOWLEDGESTARTSCL FROM MASTERDATA OUTPUTFROM TRANSMITTERDATA OUTPUT FROM RECEIVERDis co n ti n ue dPa rt CAT24C01B6Doc. No. 1081, Rev. E© 2005 by Catalyst Semiconductor, Inc.Characteristics subject to change without noticeFigure 6. Page Write TimingFigure5. Byte Write Timinging with an acknowledge and by issuing a stop condition.Refer to Figure 7 for the start word address, read bit,acknowledge and data transfer sequence.Sequential ReadThe Sequential READ operation can be initiated after the 24C01B sends the initial 8-bit byte requested, the Master will respond with an acknowledge which tells the device it requires more data. The CAT24C01B will continue to output an 8-bit byte for each acknowledge sent by the Master. The operation is terminated when the Master fails to respond with an acknowledge, thus sending the STOP condition.The data being transmitted from the CAT24C01B is output sequentially with data from address N followed by data from address N+1. The READ operation address counter increments all of the CAT24C01B address bits so that the entire memory array can be read during one operation. If more than bytes are read out, the counter will “wrap around ” and continue to clock out data bytes.Acknowledge PollingThe disabling of the inputs can be used to take advan-tage of the typical write cycle time. Once the stop condition is issued to indicate the end of the host ’s write operation, the CAT24C01B initiates the internal write cycle. ACK polling can be initiated immediately. This involves issuing the start condition followed by the byte address for a write operation. If the CAT24C01B is still busy with the write operation, no ACK will be returned.If the CAT24C01B has completed the write operation, an ACK will be returned and the host can then proceed with the next read or write operation.READ OPERATIONSThe READ operation for the CAT24C01B is initiated in the same manner as the write operation with the one exception that the R/W bit is set to a one. Two different READ operations are possible: Byte READ and Se-quential READ.It should be noted that the ninth clock cycle of the read operation is not a "don't care." To terminate a read operation, the master must either issure a stop condition during the ninth cycle or hold SDA HIGH during the ninth clock cycle and then issue a stop condition.Byte ReadTo initiate a read operation, the master sends a start condition followed by a seven bit word address and a read bit. The CAT24C01B responds with an acknowl-edge and then transmits the eight bits of data. The read operation is terminated by the master; by not respond-BUS ACTIVITY:SDA LINEC KC KDATA n S T O C K C KS T A R WORD S BS B /W BUS ACTIVITY:BUS ACTIVITY:SDA LINEA C KA C KDATA nST O P SST A R TPWORD ADDRESS(n)MS BL S B R /W BUS ACTIVITY:ue drt CAT24C01B7Doc. No. 1081, Rev. E© 2005 by Catalyst Semiconductor, Inc.Characteristics subject to change without noticeFigure 7. Byte Read TimingBUS ACTIVITYMASTER SDA LINE KA C ST O AC A C /W BUS ACTIVITY CAT24C01BFigure 8. Sequential Read TimingORDERING INFORMATIONNotes:(1)The device used in the above example is a 24C01BJI-1.8TE13 (SOIC, Industrial Temperature, 1.8 Volt to 6 Volt OperatingVoltage, Tape & Reel)(2)Product die revision letter is marked on top of the package as a suffix to the production date code (e.g. AYWWA). For additionalinformation, please contact your Catalyst sales office.BUS ACTIVITYMASTERSDA LINE A C KA C KDATA nS T O P S S T A R T PWORD ADDRESS(n)M S BL S B R /W BUS ACTIVITY CAT24C01B(2)Dis co n ti n ue dPa rt Catalyst Semiconductor, Inc.Corporate Headquarters 1250 Borregas Avenue Sunnyvale, CA 94089Phone: 408.542.1000Fax: 408.542.1200Copyrights, Trademarks and PatentsTrademarks and registered trademarks of Catalyst Semiconductor include each of the following:DPP ™AE 2 ™MiniPot™Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000.CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a situation where personal injury or death may occur.Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications and may not be complete.Publication #:1081Revison:EIssue date:08/03/05REVISION HISTORYe t a D n o i s i v e R st n e m m o C 4002/71/40Bn o i t a m r o f n I g n i r e d r O e t a d p U re b m u N .v e R e t a d p U 4002/7/7C n o i t a m r of n Ig n i r e d r O o t n o i s i v e r e i d d e d d A 50/30/80Eno i t a m r o f n I g n i r e d r O e t a d p U。

24C01中文资料

©1996 Microchip Technology Inc.DS11183D-page 124C01A/02A/04AFEATURES•Low power CMOS technology •Hardware write protect•Two wire serial interface bus, I 2 C ™ compatible • 5.0V only operation•Self-timed write cycle (including auto-erase)•Page-write buffer•1ms write cycle time for single byte•1,000,000 Erase/Write cycles guaranteed •Data retention >200 years •8-pin DIP/SOIC packages•Available for extended temperature ranges DESCRIPTIONThe Microchip Technology Inc. 24C01A/02A/04A is a 1K/2K/4K bit Electrically Erasable PROM. The device is organized as shown, with a standard two wire serial interface. Advanced CMOS technology allows a signif-icant reduction in power over NMOS serial devices. A special feature in the 24C02A and 24C04A provides hardware write protection for the upper half of the block.The 24C01A and 24C02A have a page write capability of two bytes and the 24C04A has a page length of eight bytes. Up to eight 24C01A or 24C02A devices and up to four 24C04A devices may be connected to the same two wire bus.This device offers fast (1ms) byte write and extended (-40 ° C to 125 ° C) temperature operation. It is recommended that all other applications use Microchip’s 24LCXXB.-Commercial (C):0˚C to +70˚C -Industrial (I):-40˚C to +85˚C -Automotive (E):-40˚C to +125˚C24C01A24C02A 24C04A Organization 128 x 8258 x 8 2 x 256 x 8Write Protect None 080-0FF 100-1FF Page Write Buffer2 Bytes2 Bytes8 BytesPACKAGE TYPESBLOCK DIAGRAMNC SS CC A0A1NC A2NCV 1234567141312NC SCL SDA NC981110WP V NC * “TEST” pin in 24C01A24C01A 24C02A 24C04A24C01A 24C02A 24C04A24C01A 24C02A 24C04AA0A1A2V SS12348765V CC WP*SCL SDAA0A1A2V SS12348765V CC WP*SCL SDADIP8-leadSOIC14-lead SOICVcc VssSDASCLData Buffer (FIFO)Data Reg.VppR/W AmpMemory ArrayA d d r e s s P o in te rA0 to A7IncrementA8Slave Addr.Control LogicA0A1A2WP1K/2K/4K 5.0V I 2 C ™Serial EEPROMsI 2 C is a trademark of Philips Corporation.This document was created with FrameMaker 404元器件交易网24C01A/02A/04ADS11183D-page 2 © 1996 Microchip Technology Inc.1.0ELECTRICAL CHARACTERISTICS1.1Maximum Ratings*V CC ...................................................................................7.0V All inputs and outputs w.r.t. V SS ...............-0.6V to V CC +1.0V Storage temperature.....................................-65˚C to +150˚C Ambient temp. with power applied................-65˚C to +125˚C Soldering temperature of leads (10 seconds).............+300˚C ESD protection on all pins................................................4 kV*Notice: Stresses above those listed under “Maximum ratings”may cause permanent damage to the device. This is a stress rat-ing only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this speciﬁcation is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.TABLE 1-1:PIN FUNCTION TABLEName FunctionA0No Function for 24C04A only, Must be connected to V CC or V SS A0, A1, A2Chip Address Inputs V SS GroundSDA Serial Address/Data I/O SCL Serial ClockTEST (24C01A only) V CC or V SS WP Write Protect Input VCC+5V Power SupplyTABLE 1-2:DC CHARACTERISTICSFIGURE 1-1:BUS TIMING START/STOPVCC = +5V ( ± 10%)Commercial (C):Tamb =0 ° C to +70 ° C Industrial (I):Tamb =-40 ° C to +85 ° C Automotive (E):Tamb =-40 ° C to +125 ° CParameterSymbolMin.Max.Units ConditionsV CC detector threshold V TH 2.8 4.5V SCL and SDA pins:High level input voltage Low level input voltage Low level output voltage V IH V IL V OL V CC x 0.7-0.3V CC + 1V CC x 0.30.4V V V I OL = 3.2 mA (SDA only)A1 & A2 pins:High level input voltage Low level input voltage V IH V IL V CC - 0.5-0.3V CC + 0.50.5V V Input leakage current ILI—10 µ A V IN = 0V to V CC Output leakage current ILO —10 µ A V OUT = 0V to V CCPin capacitance (all inputs/outputs)C IN , C OUT —7.0pF V IN /V OUT = 0V (Note) Tamb = +25˚C, f = 1 MHzOperating current I CC Write — 3.5mA F CLK = 100 kHz, program cycle time = 1 ms, Vcc = 5V, Tamb = 0˚C to +70˚CI CC Write—4.25mAF CLK = 100 kHz, program cycle time = 1 ms, Vcc = 5V, Tamb = (I) and (E)ICC Read—750 µ AV CC = 5V, Tamb= (C), (I) and (E)Standby current ICCS—100 µ A SDA=SCL=VCC=5V (no PROGRAM active)Note:This parameter is periodically sampled and not 100% testedT SU :STAT HD :STAV HYST SU :STOSTART STOPSCLSDA元器件交易网©1996 Microchip Technology Inc.DS11183D-page 324C01A/02A/04ATABLE 1-3:AC CHARACTERISTICSFIGURE 1-2:BUS TIMING DATAParameterSymbol Min.Typ Max.Units RemarksClock frequency F CLK ——100kHz Clock high time T HIGH 4000——ns Clock low timeT LOW 4700——ns SDA and SCL rise time T R ——1000ns SDA and SCL fall time T F ——300ns START condition hold time T HD :S TA 4000——ns After this period the ﬁrst clock pulse is generated START condition setup time T SU :S TA 4700——ns Only relevant for repeated START conditionData input hold time T HD :D AT 0——ns Data input setup time T SU :D AT 250——nsData output delay time T AA 300—3500(Note 1)STOP condition setup time T SU :S TO 4700——ns Bus free timeT BUF4700——nsTime the bus must be free before a new transmission can startInput ﬁlter time constant (SDA and SCL pins)T I ——100ns Program cycle timeTWC—.41ms Byte mode.4N N ms Page mode, N=# of bytesEndurance —1M ——cycles25 °C, Vcc = 5.0V, BlockMode (Note 2)Note 1:As transmitter the device must provide this internal minimum delay time to bridge the undeﬁned region (min-imum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.2:This parameter is not tested but guaranteed by characterization. For endurance estimates in a speciﬁc appli-cation, please consult the Total Endurance Model which can be obtained on our BBS or website.T SU :STAT FT LOWT HIGHT RT HD :DATT SU :DAT T SU :STOT HD :STAT BUFT AAT AAT SPT HD :STASCLSDA INSDA OUT元器件交易网24C01A/02A/04ADS11183D-page 4© 1996 Microchip Technology Inc.2.0FUNCTIONAL DESCRIPTIONThe 24C01A/02A/04A supports a bidirectional two wire bus and data transmission protocol. A device that sends data onto the bus is deﬁned as transmitter, and a device receiving data as receiver. The bus has to be controlled by a master device which generates the serial clock (SCL), controls the bus access, and gener-ates the START and STOP conditions, while the 24C01A/02A/04A works as slave. Both master and slave can operate as transmitter or receiver but the master device determines which mode is activated.Up to eight 24C01/24c02s can be connected to the bus,selected by the A0, A1 and A2 chip address inputs. Up to four 24C04As can be connected to the bus, selected by A1 and A2 chip address inputs. A0 must be tied to V CC or V SS for the 24C04A. Other devices can be con-nected to the bus but require different device codes than the 24C01A/02A/04A (refer to section Slave Address).3.0BUS CHARACTERISTICSThe following bus protocol has been deﬁned:•Data transfer may be initiated only when the bus is not busy.•During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH will be interpreted as a START or STOP condition.Accordingly, the following bus conditions have been deﬁned (Figure 3-1).3.1Bus not Busy (A)Both data and clock lines remain HIGH.3.2Start Data Transfer (B)A HIGH to LOW transition of the SDA line while the clock (SCL) is HIGH determines a START condition. All commands must be preceded by a START condition.3.3Stop Data Transfer (C)A LOW to HIGH transition of the SDA line while the clock (SCL) is HIGH determines a STOP condition. All operations must be ended with a STOP condition.3.4Data Valid (D)The state of the data line represents valid data when,after a START condition, the data line is stable for the duration of the HIGH period of the clock signal.The data on the line must be changed during the LOW period of the clock signal. There is one clock pulse per bit of data.Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of the data bytes transferred between the START and STOP conditions is determined by the master device and is theoretically unlimited.3.5AcknowledgeEach receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse which is associated with this acknowledge bit.The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line HIGH to enable the master to generate the STOP condition.Note:The 24C01A/02A/04A does not generate any acknowledge bits if an internal pro-gramming cycle is in progress.FIGURE 3-1:DATA TRANSFER SEQUENCE ON THE SERIAL BUS(A)(B)(D)(D)(A)(C)START CONDITIONADDRESS OR ACKNOWLEDGEVALID DATA ALLOWED TO CHANGESTOP CONDITIONSCLSDA元器件交易网© 1996 Microchip Technology Inc.DS11183D-page 524C01A/02A/04A4.0SLAVE ADDRESSThe chip address inputs A0, A1 and A2 of each 24C01A/02A/04A must be externally connected to either V CC or ground (V SS ), assigning to each 24C01A/02A/04A a unique address. A0 is not used on the 24C04A and must be connected to either V CC or V SS . Up to eight 24C01A or 24C02A devices and up to four 24C04A devices may be connected to the bus. Chip selection is then accomplished through software by setting the bits A0, A1 and A2 of the slave address to the corresponding hard-wired logic levels of the selected 24C01A/02A/04A.After generating a START condition, the bus master transmits the slave address consisting of a 4-bit device code (1010) for the 24C01A/02A/04A, followed by the chip address bits A0, A1 and A2. In the 24C04A, the seventh bit of that byte (A0) is used to select the upper block (addresses 100—1FF) or the lower block (addresses 000—0FF) of the array.The eighth bit of slave address determines if the master device wants to read or write to the 24C01A/02A/04A (Figure 4-1).The 24C01A/02A/04A monitors the bus for its corre-sponding slave address all the time. It generates an acknowledge bit if the slave address was true and it is not in a programming mode.FIGURE 4-1:SLAVE ADDRESS ALLOCATION5.0BYTE PROGRAM MODEIn this mode, the master sends addresses and one data byte to the 24C01A/02A/04A.Following the START signal from the master, the device code (4-bits), the slave address (3-bits), and the R/W bit, which is logic LOW, are placed onto the bus by the master. This indicates to the addressed 24C01A/02A/04A that a byte with a word address will follow after it has generated an acknowledge bit. Therefore the next byte transmitted by the master is the word address and will be written into the address pointer of the 24C01A/02A/04A. After receiving the acknowledge of the 24C01A/02A/04A, the master device transmits the data word to be written into the addressed memory location.The 24C01A/02A/04A acknowledges again and the master generates a STOP condition. This initiates the internal programming cycle of the 24C01A/02A/04A (Figure 6-1).SLAVE ADDRESS1010A2A1A0R/W ASTARTREAD/WRITE6.0PAGE PROGRAM MODETo program the 24C01A/02A/04A, the master sends addresses and data to the 24C01A/02A/04A which is the slave (Figure 6-1 and Figure 6-2). This is done by supplying a START condition followed by the 4-bit device code, the 3-bit slave address, and the R/W bit which is deﬁned as a logic LOW for a write. This indi-cates to the addressed slave that a word address will follow so the slave outputs the acknowledge pulse to the master during the ninth clock pulse. When the word address is received by the 24C01A/02A/04A, it places it in the lower 8 bits of the address pointer deﬁning which memory location is to be written. (The A0 bit transmitted with the slave address is the ninth bit of the address pointer for the 24C04A). The 24C01A/02A/04A will generate an acknowledge after every 8-bits received and store them consecutively in a RAM buffer until a STOP condition is detected. This STOP condi-tion initiates the internal programming cycle. The RAM buffer is 2 bytes for the 24C01A/02A and 8 bytes for the 24C04A. If more than 2 bytes are transmitted by the master to the 24C01A/02A, the device will not acknowl-edge the data transfer and the sequence will be aborted. If more than 8 bytes are transmitted by the master to the 24C04A, it will roll over and overwrite the data beginning with the ﬁrst received byte. This does not affect erase/write cycles of the EEPROM array and is accomplished as a result of only allowing the address registers bottom 3 bits to increment while the upper 5bits remain unchanged.If the master generates a STOP condition after trans-mitting the ﬁrst data word (Point ‘P’ on Figure 6-1), byte programming mode is entered.The internal, completely self-timed PROGRAM cycle starts after the STOP condition has been generated by the master and all received data bytes in the page buffer will be written in a serial manner.The PROGRAM cycle takes N milliseconds, whereby N is the number of received data bytes (N max = 8 for 24C04A, 2 for 24C01A/02A).元器件交易网24C01A/02A/04ADS11183D-page 6© 1996 Microchip Technology Inc.FIGURE 6-1:BYTE WRITEFIGURE 6-2:PAGE WRITESPBUS ACTIVITY MASTER SDA LINE BUS ACTIVITYS T A R TS T O PCONTROL BYTE WORD ADDRESSDATAA C KA C KA C KSPBUS ACTIVITY MASTERSDA LINE BUS ACTIVITYS T A R TCONTROL BYTE WORD ADDRESS (n)DATA n DATA n + 7S T O PA C KA C KA C KA C KA C KDATA n + 17.0ACKNOWLEDGE POLLINGSince the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). Once the stop condition for a write com-mand has been issued from the master, the device ini-tiates the internally timed write cycle. ACK polling can be initiated immediately. This involves the master send-ing a start condition followed by the control byte for a write command (R/W = 0). If the device is still busy with the write cycle, then no ACK will be returned. If the cycle is complete, then the device will return the ACK and the master can then proceed with the next read or write command. See Figure 7-1 for ﬂow diagram.FIGURE 7-1:ACKNOWLEDGE POLLING FLOWSendWrite CommandSend Stop Condition to Initiate Write CycleSend StartSend Control Byte with R/W = 0Did Device Acknowledge (ACK = 0)?Next OperationNOYES元器件交易网© 1996 Microchip Technology Inc.DS11183D-page 724C01A/02A/04A8.0WRITE PROTECTIONProgramming of the upper half of the memory will not take place if the WP pin of the 24C02A or 24C04A is connected to V CC (+5.0V). The device will accept slave and word addresses but if the memory accessed is write protected by the WP pin, the 24C02A/04A will not generate an acknowledge after the ﬁrst byte of data has been received, and thus the program cycle will not be started when the STOP condition is asserted. Polarity of the WP pin has no effect on the 24C01A.9.0READ MODEThis mode illustrates master device reading data from the 24C01A/02A/04A.As can be seen from Figure 9-2 and Figure 9-3, the master ﬁrst sets up the slave and word addresses by doing a write. (Note: Although this is a read mode, the address pointer must be written to). During this period the 24C01A/02A/04A generates the necessary acknowledge bits as deﬁned in the appropriate section.The master now generates another START condition and transmits the slave address again, except this time the read/write bit is set into the read mode. After the slave generates the acknowledge bit, it then outputs the data from the addressed location on to the SDA pin,increments the address pointer and, if it receives an acknowledge from the master, will transmit the next consecutive byte. This auto-increment sequence is only aborted when the master sends a STOP condition instead of an acknowledge.Note 1:If the master knows where the addresspointer is, it can begin the read sequence at the current address (Figure 9-1) and save time transmitting the slave and word addresses.Note 2:In all modes, the address pointer will notincrement through a block (256 byte)boundary, but will rotate back to the ﬁrst location in that block.FIGURE 9-1:CURRENT ADDRESS READFIGURE 9-2:RANDOM READSPBUS ACTIVITY MASTERSDA LINE BUS ACTIVITYS T A R TS T O PCONTROL BYTEDATA nA C KN O A C KSPSBUS ACTIVITY MASTERSDA LINEBUS ACTIVITYS T A R TS T O PCONTROL BYTE A C KWORD ADDRESS (n)CONTROL BYTES T A R TDATA (n)A C KA C KN O A C K元器件交易网24C01A/02A/04ADS11183D-page 8© 1996 Microchip Technology Inc.FIGURE 9-3:SEQUENTIAL READPBUS ACTIVITY MASTER SDA LINE BUS ACTIVITYS T O PCONTROL BYTEA C KN O A C KDATA n DATA n + 1DATA n + 2DATA n + XA C KA C KA C K10.0PIN DESCRIPTION10.1A0, A1, A2 Chip Address InputsThe levels on these inputs are compared with the cor-responding bits in the slave address. The chip is selected if the compare is true. For 24C04 A0 is no function.Up to eight 24C01A/02A's or up to four 24C04A's can be connected to the bus.These inputs must be connected to either V SS or V CC .10.2SDA Serial Address/Data Input/OutputThis is a bidirectional pin used to transfer addresses and data into and data out of the device. It is an open drain terminal, therefore the SDA bus requires a pull-up resistor to V CC (typical 10K Ω).For normal data transfer, SDA is allowed to change only during SCL LOW. Changes during SCL HIGH are reserved for indicating the START and STOP condi-tions.10.3SCL Serial ClockThis input is used to synchronize the data transfer from and to the device.10.4WP Write ProtectionThis pin must be connected to either V CC or V SS for 24C02A or 24C04A. It has no effect on 24C01A.If tied to V CC , PROGRAM operations onto the upper memory block will not be executed. Read operations are possible.If tied to V SS , normal memory operation is enabled (read/write the entire memory).This feature allows the user to assign the upper half of the memory as ROM which can be protected against accidental programming. When write is disabled, slave address and word address will be acknowledged but data will not be acknowledged.Note 1: A “page” is deﬁned as the maximum num-ber of bytes that can be programmed in a single write cycle. The 24C04A page is 8bytes long; the 24C01A/02A page is 2bytes long.Note 2: A “block” is deﬁned as a continuous areaof memory with distinct boundaries. The address pointer can not cross the bound-ary from one block to another. It will how-ever, wrap around from the end of a block to the ﬁrst location in the same block. The 24C04A has two blocks, 256 bytes each.The 24C01A and 24C02A each have only one block.元器件交易网元器件交易网24C01A/02A/04A NOTES:© 1996 Microchip Technology Inc.DS11183D-page 924C01A/02A/04ADS11183D-page 10© 1996 Microchip Technology Inc.NOTES:元器件交易网24C01A/02A/04A© 1996 Microchip Technology Inc.DS11183D-page 1124C01A/02A/04A Product Identiﬁcation SystemTo order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed sales ofﬁces.Package:P =Plastic DIPSN =Plastic SOIC (150 mil Body), 8-lead SM =Plastic SOIC (207 mil Body), 8-leadSL =Plastic SOIC (150 mil Body), 14-lead, 24C04A onlyTemperature Blank =0°C to +70°CRange:I =-40°C to +85°C E =-40°C to +125°C Device:24C01A 1K I 2C Serial EEPROM24C01AT 1K I 2C Serial EEPROM (Tape and Reel)24C02A 2K I 2C Serial EEPROM24C02AT 2K I 2C Serial EEPROM (Tape and Reel)24C04A 4K I 2C Serial EEPROM24C04AT4K I 2C Serial EEPROM (Tape and Reel)24C01A/02A/04A-/P元器件交易网DS11183D-page 12© 1996 Microchip Technology Inc.Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. No repre-sentation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not autho-rized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.W ORLDWIDE S ALES & S ERVICEASIA/PACIFICChinaMicrochip TechnologyUnit 406 of Shanghai Golden Bridge Bldg.2077 Yan’an Road West, Hongiao District Shanghai, Peoples Republic of China Tel: 86 21 6275 5700Fax: 011 86 21 6275 5060 Hong KongMicrochip Technology RM 3801B, Tower Two Metroplaza223 Hing Fong RoadKwai Fong, N.T. Hong KongTel: 852 2 401 1200 Fax: 852 2 401 3431IndiaMicrochip TechnologyNo. 6, Legacy, Convent Road Bangalore 560 025 IndiaTel: 91 80 526 3148 Fax: 91 80 559 9840KoreaMicrochip Technology168-1, Youngbo Bldg. 3 Floor Samsung-Dong, Kangnam-Ku,Seoul, KoreaTel: 82 2 554 7200 Fax: 82 2 558 5934SingaporeMicrochip Technology 200 Middle Road #10-03 Prime Centre Singapore 188980Tel: 65 334 8870 Fax: 65 334 8850Taiwan, R.O.CMicrochip Technology 10F-1C 207Tung Hua North Road Taipei, Taiwan, ROCTel: 886 2 717 7175 Fax: 886 2 545 0139EUROPEUnited KingdomArizona Microchip Technology Ltd.Unit 6, The CourtyardMeadow Bank, Furlong RoadBourne End, Buckinghamshire SL8 5AJ Tel: 44 1628 850303 Fax: 44 1628 850178FranceArizona Microchip Technology SARL Zone Industrielle de la Bonde 2 Rue du Buisson aux Fraises 91300 Massy - FranceTel: 33 1 69 53 63 20 Fax: 33 1 69 30 90 79GermanyArizona Microchip Technology GmbH Gustav-Heinemann-Ring 125D-81739 Muenchen, GermanyTel: 49 89 627 144 0 Fax: 49 89 627 144 44ItalyArizona Microchip Technology SRLCentro Direzionale Colleone Pas Taurus 1Viale Colleoni 120041 Agrate Brianza Milan ItalyTel: 39 39 6899939 Fax: 39 39 689 9883JAPANMicrochip Technology Intl. Inc.Benex S-1 6F3-18-20, Shin Yokohama Kohoku-Ku, Yokohama Kanagawa 222 JapanTel: 81 45 471 6166 Fax: 81 45 471 61229/3/96AMERICASCorporate OfﬁceMicrochip Technology Inc.2355 West Chandler Blvd.Chandler, AZ 85224-6199Tel: 602 786-7200 Fax: 602 786-7277Technical Support: 602 786-7627Web: AtlantaMicrochip Technology Inc.500 Sugar Mill Road, Suite 200B Atlanta, GA 30350Tel: 770 640-0034 Fax: 770 640-0307BostonMicrochip Technology Inc.5 Mount Royal Avenue Marlborough, MA 01752Tel: 508 480-9990 Fax: 508 480-8575ChicagoMicrochip Technology Inc.333 Pierce Road, Suite 180Itasca, IL 60143Tel: 708 285-0071 Fax: 708 285-0075DallasMicrochip Technology Inc.14651 Dallas Parkway, Suite 816Dallas, TX 75240-8809Tel: 972 991-7177 Fax: 972 991-8588DaytonMicrochip Technology Inc.Suite 150Two Prestige Place Miamisburg, OH 45342Tel: 513 291-1654 Fax: 513 291-9175Los AngelesMicrochip Technology Inc.18201 Von Karman, Suite 1090Irvine, CA 92612Tel: 714 263-1888 Fax: 714 263-1338New YorkMicrochip Technmgy Inc.150 Motor Parkway, Suite 416Hauppauge, NY 11788Tel: 516 273-5305 Fax: 516 273-5335San JoseMicrochip Technology Inc.2107 North First Street, Suite 590San Jose, CA 95131Tel: 408 436-7950 Fax: 408 436-7955TorontoMicrochip Technology Inc.5925 Airport Road, Suite 200Mississauga, Ontario L4V 1W1, Canada Tel: 905 405-6279Fax: 905 405-6253All rights reserved. © 1996, Microchip Technology Incorporated, USA. 9/96Printed on recycled paper.元器件交易网。

IS24C08中文资料

IS24C08中⽂资料IS24C01IS24C02IS24C04IS24C08IS24C16ISSICopyright ? 2002 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.1K-bit/2K-bit/4K-bit/8K-bit/16K-bit 2-WIRE SERIAL CMOS EEPROMAPRIL 2002DESCRIPTIONThe IS24CXX (refers to IS24C01, IS24C02, IS24C04,IS24C08, IS24C16) family is a low-cost and low voltage 2-wire Serial EEPROM. It is fabricated using ISSI’s advanced CMOS EEPROM technology and provides a low power and low voltage operation. The IS24CXX family features a write protection feature, and is available in 8-pin DIP and 8-pin SOIC packages.The IS24C01 is a 1K-bit EEPROM; IS24C02 is a 2K-bit EEPROM; IS24C04 is a 4K-bit EEPROM; IS24C08 is a 8K-bit EEPROM; IS24C16 is a 16K-bit EEPROM.The IS24C01 and IS24C02 are available in 8-pin MSOP package. The IS24C01, IS24C02, IS24C04, and IS24C08are available in 8-Pin TSSOP package.Automotive data is preliminary.FEATURESLow Power CMOS Technology–Standby Current less than 8 µA (5.5V)–Read Current (typical) less than 1 mA (5.5V)–Write Current (typical) less than 3 mA (5.5V)?Flexible Voltage Operation–Vcc = 1.8V to 5.5V for –2 version –Vcc = 2.5V to 5.5V for –3 version ?400 KHz (I 2C Protocol) Compatibility ?Hardware Data Protection–Write Protect Pin ?Sequential Read FeatureFiltered Inputs for Noise Suppression 8-pin PDIP and 8-pin SOIC packages 8-pin TSSOP (1K,2K, 4K & 8K only)8-pin MSOP (1K,2K only)Self time write cycle with auto clear 5 ms @ 2.5V Organization:–IS24C01128x8(one block of 128 bytes)–IS24C02256x8(one block of 256 bytes)–IS24C04512x8(two blocks of 256 bytes)–IS24C081024x8(four blocks of 256 bytes)–IS24C162048x8(eight blocks of 256 bytes)?Page Write BufferTwo-Wire Serial Interface–Bi-directional data transfer protocol ?High Reliability–Endurance: 1,000,000 Cycles –Data Retention: 100 YearsCommercial, Industrial and Automotive tempera-ture ranges元器件交易⽹/doc/af5937a6dd3383c4bb4cd241.html元器件交易⽹/doc/af5937a6dd3383c4bb4cd241.htmlIS24C01IS24C02IS24C04IS24C08 IS24C16ISSI?FUNCTIONAL BLOCK DIAGRAM2Integrated Silicon Solution, Inc. — /doc/af5937a6dd3383c4bb4cd241.html — 1-800-379-4774 Rev.DIS24C01IS24C02IS24C04IS24C08 IS24C16ISSIPIN DESCRIPTIONSA0-A2Address InputsSDA Serial Address/Data I/O SCL Serial Clock Input WP Write Protect Input Vcc Power Supply GNDGroundSCLThis input clock pin is used to synchronize the data transfer to and from the device.SDAThe SDA is a Bi-directional pin used to transfer addresses and data into and out of the device. The SDA pin is an open drain output and can be wire-Ored with other open drain or open collector outputs.The SDA bus requires a pullup resistor to Vcc. A0, A1, A2The A0, A1 and A2 are the device address inputs. The IS24C01 and IS24C02 use the A0, A1, and A2 for hardware addressing and a total of 8 devices may be used on a single bus system.PIN CONFIGURATION8-Pin DIP and SOIC8 Pin TSSOP (1K, 2K, 4K and 8K)8-Pin MSOP (1K, 2K)12348765A0A1A2GNDVCC WP SCL SDAThe IS24C04 uses A1 and A2 pins for hardwire addressing and a total of four devices may be addressed on a single bus system.The A0 pin is not used by IS24C04. This pin can be left floating or tied to GND or Vcc.The IS24C08 only use A2 input for hardwire addressing and a total of two devices may be addressed on a single bus system.The A0 and A1 pins are not used by IS24C08. They may be left floating or tied to either GND or Vcc.These pins are not used by IS24C16. A0 and A1 may be left floating or tied to either GND or Vcc. A2 should be tied to either GND or Vcc.WPWP is the Write Protect pin. On the 24C01, 24C02, IS24C04and 24C08, if the WP pin is tied to V CC the entire array becomes Write Protected (Read only). On the 24C16, if the WP pin is tied to Vcc the upper half array becomes Write Protected (Read only). When WP is tied to GND or left floating normal read/write operations are allowed to the device.元器件交易⽹/doc/af5937a6dd3383c4bb4cd241.htmlIS24C01IS24C02IS24C04IS24C08 IS24C16ISSI?DEVICE OPERATIONThe IS24CXX family features a serial communication and supports a bi-directional 2-wire bus transmission protocol. 2-WIRE BUSThe two-wire bus is defined as a Serial Data line(SDA), and a Serial Clock Line (SCL). The protocol defines any device that sends data onto the SDA bus as a transmitter, and the receiving devices as a receiver. The bus is controlled by MASTER device which generates the SCL, controls the bus access and generates the STOP and START conditions. The IS24CXX is the SLAVE device on the bus.THE BUS PROTOCOL:--Data transfer may be initiated only when the bus is not busy--During a data transfer, the data line must remain stable whenever the clock line is high. Any changes in the data line while the clock line is high will be interpreted as a START or STOP condition.The state of the data line represents valid data when after a START condition, the data line is stable for the duration of the HIGH period of the clock signal. The data on the line must be changed during the LOW period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a START condition and terminated with a STOP condition.START CONDITIONThe START condition precedes all commands to the devices and is defined as a HIGH to LOW transition of SDA when SCL is HIGH. The IS24CXX monitors the SDA and SCL lines and will not respond until the START condition is met.STOP CONDITIONThe STOP condition is defined as a LOW to HIGH transition of SDA when SCL is HIGH. All operations must end with a STOP condition.ACKNOWLEDGEAfter a successful data transfer, each receiving device is required to generate an acknowledge. The Acknowledging device pulls down the SDA line.DEVICE ADDRESSINGThe MASTER begins a transmission by sending a START condition. The MASTER then sends the address of the particular slave devices it is requesting. The SLAVE address is 8 bytes.The four most significant bytes of the address are fixed as 1010 for the IS24CXX.For the IS24C16, the bytes(B2, B1 and B0) are used for memory page addressing (the IS24C16 is organized as eight blocks of 256 bytes).For the IS24C04 out of the next three bytes, B0 is for Memory Page Addressing (the IS24C04 is organized as two blocks of 256 bytes) and A2 and A1 bytes are used as device address bytes and must compare to its hard-wire inputs pins (A2 and A1). Up to four IS24C04's may be individually addressed by the system. The page addressing bytes forIS24Cxx should be considered the most significant bytes of the data word address which follows.For the IS24C08 out of the next three bytes, B1 and B0 are for memory page addressing (the IS24C08 is organized as four blocks of 256 bytes) and the A2 bit is used as device address bit and must compare to its hard-wired input pin (A2). Up to two IS24C08 may be individually addressed by the system. The page addressing bytes for IS24CXX should be considered the most significant bytes of the data word address which follows.For the IS24C01 and IS24C02, the A0, A1, and A2 are used as device address bytes and must compare to its hard-wired input pins (A0, A1, and A2) Up to Eight IS24C01 and/ or IS24C02's may be individually addressed by the system. The last bit of the slave address specifies whether a Read or Write operation is to be performed. When this bit is set to 1, a Read operation is selected, and when set to 0, a Write operation is selected.After the MASTER sends a START condition and the SLAVE address byte, the IS24CXX monitors the bus and responds with an Acknowledge (on the SDA line) when its address matches the transmitted slave address. The IS24CXX pulls down the SDA line during the ninth clock cycle, signaling that it received the eight bytes of data. The IS24CXX then performs a Read or Write operation depending on the state of the R/W bit.WRITE OPERATIONBYTE WRITEIn the Byte Write mode, the Master device sends the START condition and the slave address information(with the R/W set to Zero) to the Slave device. After the Slave generates an acknowledge, the Master sends the byte address that is to be written into the address pointer of the IS24CXX. After receiving another acknowledge from the Slave, the Master device transmits the data byte to be written into the address memory location. The IS24CXX acknowledges once more and the Master generatesthe STOP condition, at which time the device begins its internal programming cycle. While this internal cycle is in progress, the device will not respond to any request from the Master device.元器件交易⽹/doc/af5937a6dd3383c4bb4cd241.html4Integrated Silicon Solution, Inc. — /doc/af5937a6dd3383c4bb4cd241.html — 1-800-379-4774Rev.DIS24C01IS24C02IS24C04IS24C08 IS24C16ISSIcondition and the IS24CXX discontinues transmission. If 'n' is the last byte of the memory, then the data from location '0' will be transmitted. (Refer to Current Address Read Diagram.)RANDOM ADDRESS READSelective READ operations allow the Master device to select at random any memory location for a READ operation.The Master device first performs a 'dummy' write operation by sending the START condition, slave address and word address of the location it wishes to read. After the IS24CXX acknowledge the word address, the Master device resends the START condition and the slave address, this time with the R/W bit set to one. The IS24CXX then responds with its acknowledge and sends the data requested. The master device does not send an acknowledge but will generate a STOP condition. (Refer to Random Address Read Diagram.)SEQUENTIAL READSequential Reads can be initiated as either a Current Address Read or Random Address Read. After the IS24CXX sends initial byte sequence, the master device now responds with an ACKnowledge indicating it requires additional data from the IS24CXX. The IS24CXX continues to output data for each ACKnowledge received. The master device terminates the sequential READ operation by pulling SDA HIGH (no ACKnowledge) indicating the last data word to be read, followed by a STOP condition.The data output is sequential, with the data from address n followed by the data from address n+1, ... etc.The address counter increments by one automatically,allowing the entire memory contents to be serially read during sequential read operation. When the memory address boundary (127 for IS24C01; 255 for IS24C02; 511 for IS24C04; 1023 for IS24C08; 2047 forIS24C16) is reached,the address counter “rolls over” to address 0, and the IS24CXX continues to output data for each ACKnowledge received. (Refer to Sequential Read Operation Starting with a Random Address READ Diagram.)PAGE WRITEThe IS24CXX is capable of page-WRITE (8-byte for 24C01/02 and 16-byte for 24C04/08/16) operation. A page-WRITE is initiated in the same manner as a byte write, but instead of terminating the internal write cycle after the first data word is transferred, the master device can transmit up to N more bytes (N=7 for 24C01/02 and N=15 for 24C04/08/16). After the receipt of each data word, the IS24CXX responds immediately with an ACKnowledge on SDA line, and the three lower (24C01/24C02) or four lower (24C04/24C08/24C16) order data word address bits are internally incremented by one, while the higher order bits of the data word address remain constant. If the master device should transmit more than N+1 (N=7 for 24C01/02 and N=15 for 24C04/08/16) words, prior to issuing the STOP condition,the address counter will “roll over,” and the previously written data will be overwritten. Once all N+1 (N=7 for 24C01/02 and N=15 for 24C04/08/16) bytes are received and the STOP condition has been sent by the Master, the internal programming cycle begins. At this point, all received data is written to the IS24CXX in a single write cycle. All inputs are disabled until completion of the internal WRITE cycle. ACKNOWLEDGE POLLINGThe disabling of the inputs can be used to take advantage of the typical write cycle time. Once the stop condition is issued to indicate the end of the host's write operation, the IS24CXX initiates the internal write cycle. ACK polling can be initiated immediately. This involves issuing the start condition followed by the slave address for a write operation.If the IS24CXX is still busy with the write operation, no ACK will be returned. If the IS24CXX has completed the write operation, an ACK will be returned and the host can then proceed with the next read or write operation.READ OPERATIONREAD operations are initiated in the same manner as WRITE operations, except that the read/write bit of the slave address is set to “1”. There are three READ operation options: current address read, random address read and sequential read. CURRENT ADDRESS READThe IS24CXX contains an internal address counter which maintains the address of the last byte accessed, incremented by one. For example, if the previous operation is either a read or write operation addressed to the address location n,the internal address counter would increment to address location n+1. When the IS24CXX receives the Device Addressing Byte with a READ operation (read/write bit set to “1”), it will respond an ACKnowledge and transmit the 8-bit data word stored at address location n+1. The master will not acknowledge the transfer but does generate a STOP元器件交易⽹/doc/af5937a6dd3383c4bb4cd241.html元器件交易⽹/doc/af5937a6dd3383c4bb4cd241.htmlIS24C01IS24C02IS24C04IS24C08 IS24C16ISSI?TYPICAL SYSTEM BUS CONFIGURATIONSTART AND STOP CONDITIONS6Integrated Silicon Solution, Inc. — /doc/af5937a6dd3383c4bb4cd241.html — 1-800-379-4774 Rev.D元器件交易⽹/doc/af5937a6dd3383c4bb4cd241.htmlIS24C01IS24C02IS24C04IS24C08 IS24C16ISSI?DATA VALIDITY PROTOCOL元器件交易⽹/doc/af5937a6dd3383c4bb4cd241.htmlIS24C01IS24C02IS24C04IS24C08 IS24C16ISSI?PAGE WRITE8Integrated Silicon Solution, Inc. — /doc/af5937a6dd3383c4bb4cd241.html — 1-800-379-4774 Rev.D元器件交易⽹/doc/af5937a6dd3383c4bb4cd241.htmlIS24C01IS24C02IS24C04IS24C08 IS24C16ISSI?SEQUENTIAL READ元器件交易⽹/doc/af5937a6dd3383c4bb4cd241.htmlIS24C01IS24C02IS24C04IS24C08 IS24C16ISSI?ABSOLUTE MAXIMUM RATINGS(1)Symbol Parameter Value UnitV S Supply Voltage0.5 to +6.25VV P Voltage on Any Pin–0.5 to Vcc + 0.5VT BIAS Temperature Under Bias–40 to +85°CT STG Storage Temperature–65 to +150°CI OUT Output Current5mANotes:1.Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may causepermanent damage to the device. This is a stress rating only and functional operation of thedevice at these or any other conditions above those indicated in the operational sections ofthis specification is not implied. Exposure to absolute maximum rating conditions forextended periods may affect reliability.OPERATING RANGE(IS24C01-2, IS24C02-2, IS24C04-2 IS24C08-2, & IS24C16-2)Range Ambient Temperature V CCCommercial0°C to +70°C 1.8V to 5.5VIndustrial–40°C to +85°C 1.8V to 5.5VOPERATING RANGE(IS24C01-3, IS24C02-3, IS24C04-3, IS24C08-3, & IS24C16-3)Range Ambient Temperature V CCCommercial0°C to +70°C 2.5V to 5.5VIndustrial–40°C to +85°C 2.5V to 5.5VAutomotive–40°C to +125°C 2.7V to 5.5VNote: Automotive data is preliminary.OPERATING RANGE(IS24C01-5, IS24C02-5, IS24C04-5 IS24C08-5, & IS24C16-5)Range Ambient Temperature V CCAuromotive–40°C to +125°C 4.5V to 5.5VNote: Automotive data is preliminary.10Integrated Silicon Solution, Inc. — /doc/af5937a6dd3383c4bb4cd241.html — 1-800-379-4774 Rev.D元器件交易⽹/doc/af5937a6dd3383c4bb4cd241.htmlIS24C01IS24C02IS24C04IS24C08 IS24C16ISSI?DC ELECTRICAL CHARACTERISTICSSymbol Parameter Test Conditions Min.Max.UnitV OL1Output LOW Voltage V CC = 1.8V, I OL = 0.15 mA—0.2VV OL2Output LOW Voltage V CC = 2.5V, I OL = 1.0 mA—0.4VV IH Input HIGH Voltage V CC X 0.7V CC + 0.5VV IL Input LOW Voltage–1.0V CC X 0.3VI LI Input Leakage Current V IN = V CC max.—3µAI LO Output Leakage Current—3µANotes: V IL min and V IH max are reference only and are not tested.POWER SUPPLY CHARACTERISTICSSymbol Parameter Test Conditions Min.Max.UnitI CC1Vcc Operating Current READ at 100 KHz (Vcc = 5V)— 1.0mAI CC2Vcc Operating Current WRITE at 100 KHz (Vcc = 5V)— 3.0mAI SB1Standby Current Vcc = 1.8V— 4.0µAI SB2Standby Current Vcc = 5.5V—8.0µACAPACITANCE(1,2)Symbol Parameter Conditions Max.UnitC IN Input Capacitance V IN = 0V6pFC OUT Output Capacitance V OUT = 0V8pFNotes:1.Tested initially and after any design or process changes that may affect these parameters.2.Test conditions: T A = 25°C, f = 1 MHz, Vcc = 5.0V.12Integrated Silicon Solution, Inc. — /doc/af5937a6dd3383c4bb4cd241.html — 1-800-379-4774 Rev.D IS24C01IS24C02IS24C04IS24C08 IS24C16ISSIAC ELECTRICAL CHARACTERISTICS (Over Operating Range)Automotive (T A = –40°C to +125°C) 2.7V-5.5V 4.5V-5.5V Symbol Parameter Test ConditionsMin.Max.Min.Max.Unit f SCL SCL Clock Frequency 01000400KHz T Noise Suppression Time (1)—100—50ns t LOW Clock LOW Period 4.7— 1.2—µs t HIGH Clock HIGH Period4—0.6—µs t BUF Bus Free Time Before New Transmission 4.7— 1.2—µs t SU:STA Start Condition Setup Time 4.7—0.6—µs t SU:STO Stop Condition Setup Time 4.7—0.6—µs t HD:STA Start Condition Hold Time 4—0.6—µs t HD:STO Stop Condition Hold Time 4—0.6—µs t SU:DAT Data In Setup Time 200—100—ns t HD:DAT Data In Hold Time 0—0—ns t DH Data Out Hold Time SCL LOW to SDA Data Out Change 100—50—ns t AA Clock to Output SCL LOW to SDA Data Out Valid0.1 4.50.10.9µs t R SCL and SDA Rise Time(1)—1000—300ns t F SCL and SDA Fall Time (1)—300—300ns t WRWrite Cycle Time—10—10msNote:1. This parameter is characterized but not 100% tested.2. Automotive data is preliminary.AC ELECTRICAL CHARACTERISTICS (Over Operating Rnage)Commercial (T A = 0°C to +70°C) Industrial (T A = –40°C to +85°C) 1.8V-5.5V 2.5V-5.5V Symbol Parameter Test ConditionsMin.Max.Min.Max.Unit f SCL SCL Clock Frequency 01000400KHz T Noise Suppression Time (1)—100—50ns t LOW Clock LOW Period 4.7— 1.2—µs t HIGH Clock HIGH Period4—0.6—µs t BUF Bus Free Time Before New Transmission (1) 4.7— 1.2—µs t SU:STA Start Condition Setup Time 4.7—0.6—µs t SU:STO Stop Condition Setup Time 4.7—0.6—µs t HD:STA Start Condition Hold Time 4—0.6—µs t HD:STO StopCondition Hold Time 4—0.6—µs t SU:DAT Data In Setup Time 200—100—ns t HD:DAT Data In Hold Time 0—0—ns t DH Data Out Hold Time SCL LOW to SDA Data Out Change 100—50—ns t AA Clock to Output SCL LOW to SDA Data Out Valid 0.1 4.50.10.9µs t R SCL and SDA Rise Time (1)—1000—300ns t F SCL and SDA Fall Time (1)—300—300ns t WRWrite Cycle Time—10—5msNote:1. This parameter is characterized but not 100% tested.元器件交易⽹/doc/af5937a6dd3383c4bb4cd241.html元器件交易⽹/doc/af5937a6dd3383c4bb4cd241.htmlIS24C01IS24C02IS24C04IS24C08 IS24C16ISSI?AC WAVEFORMSBUS TIMINGWRITE CYCLE TIMING元器件交易⽹/doc/af5937a6dd3383c4bb4cd241.htmlIS24C01IS24C02IS24C04IS24C08 IS24C16ISSI?ORDERING INFORMATIONCommercial Range: 0°C to +70°CVol tageFrequency Range Part Number Package100 KHz 1.8V IS24C01-2P300-mil Plastic DIPto 5.5V IS24C01-2G Small Outline (JEDEC STD)IS24C01-2S MSOPIS24C01-2Z TSSOP100 KHz 1.8V IS24C02-2P300-mil Plastic DIPto 5.5V IS24C02-2G Small Outline (JEDEC STD)IS24C02-2S MSOPIS24C02-2Z TSSOP100 KHz 1.8V IS24C04-2P300-mil Plastic DIPto 5.5V IS24C04-2G Small Outline (JEDEC STD)IS24C04-2Z TSSOP100 KHz 1.8V IS24C08-2P300-mil Plastic DIPto 5.5V IS24C08-2G Small Outline (JEDEC STD)IS24C08-2Z TSSOP100 KHz 1.8V IS24C16-2P300-mil Plastic DIPto 5.5V IS24C16-2G Small Outline (JEDEC STD)400 KHz 2.5V IS24C01-3P300-mil Plastic DIPto 5.5V IS24C01-3G Small Outline (JEDEC STD)IS24C01-3S MSOPIS24C01-3Z TSSOP400 KHz 2.5V IS24C02-3P300-mil Plastic DIPto 5.5V IS24C02-3G Small Outline (JEDEC STD)IS24C02-3S MSOPIS24C02-3Z TSSOP400 KHz 2.5V IS24C04-3P300-mil Plastic DIPto 5.5V IS24C04-3G Small Outline (JEDEC STD)IS24C04-3Z TSSOP400 KHz 2.5V IS24C08-3P300-mil Plastic DIPto 5.5V IS24C08-3G Small Outline (JEDEC STD)IS24C08-3Z TSSOP400 KHz 2.5V IS24C16-3P300-mil Plastic DIPto 5.5V IS24C16-3G Small Outline (JEDEC STD)14Integrated Silicon Solution, Inc. — /doc/af5937a6dd3383c4bb4cd241.html — 1-800-379-4774 Rev.D元器件交易⽹/doc/af5937a6dd3383c4bb4cd241.htmlIS24C01IS24C02IS24C04IS24C08 IS24C16ISSI?ORDERING INFORMATIONIndustrial Range: –40°C to +85°CVoltageFrequency Range Part Number Package100 KHz 1.8V IS24C01-2PI300-mil Plastic DIPto 5.5V IS24C01-2GI Small Outline (JEDEC STD)IS24C01-2SI MSOPIS24C01-2ZI TSSOP100 KHz 1.8V IS24C02-2PI300-mil Plastic DIPto 5.5V IS24C02-2GI Small Outline (JEDEC STD)IS24C02-2SI MSOPIS24C02-2ZI TSSOP100 KHz 1.8V IS24C04-2PI300-mil Plastic DIPto 5.5V IS24C04-2GI Small Outline (JEDEC STD)IS24C04-2ZI TSSOP100 KHz 1.8V IS24C08-2PI300-mil Plastic DIPto 5.5V IS24C08-2GI Small Outline (JEDEC STD)IS24C08-2ZI TSSOP100 KHz 1.8V IS24C16-2PI300-mil Plastic DIPto 5.5V IS24C16-2GI Small Outline (JEDEC STD)400 KHz 2.5V IS24C01-3PI300-mil Plastic DIPto 5.5V IS24C01-3GI Small Outline (JEDEC STD)IS24C01-3SI MSOPIS24C01-3ZI TSSOP400 KHz 2.5V IS24C02-3PI300-mil Plastic DIPto 5.5V IS24C02-3GI Small Outline (JEDEC STD)IS24C02-3SI MSOPIS24C02-3ZI TSSOP400 KHz 2.5V IS24C04-3PI300-mil Plastic DIPto 5.5V IS24C04-3GI Small Outline (JEDEC STD)IS24C04-3ZI TSSOP400 KHz 2.5V IS24C08-3PI300-mil Plastic DIPto 5.5V IS24C08-3GI Small Outline (JEDEC STD)IS24C08-3ZI TSSOP400 KHz 2.5V IS24C16-3PI300-mil Plastic DIPto 5.5V IS24C16-3GI Small Outline (JEDEC STD)元器件交易⽹/doc/af5937a6dd3383c4bb4cd241.html IS24C01IS24C02IS24C04IS24C08 IS24C16ISSI?ORDERING INFORMATIONAutomotive Range: –40°C to +125°CVoltageFrequency Range Part Number Package100 KHz 2.7V IS24C01-3PA300-mil Plastic DIPto 5.5V IS24C01-3GA Small Outline (JEDEC STD)IS24C01-3SA MSOPIS24C01-3ZA TSSOP100 KHz 2.7V IS24C02-3PA300-mil Plastic DIPto 5.5V IS24C02-3GA Small Outline (JEDEC STD)IS24C02-3SA MSOPIS24C02-3ZA TSSOP100 KHz 2.7V IS24C04-3PA300-mil Plastic DIPto 5.5V IS24C04-3GA Small Outline (JEDEC STD)IS24C04-3ZA TSSOP100 KHz 2.7V IS24C08-3PA300-mil Plastic DIPto 5.5V IS24C08-3GA Small Outline (JEDEC STD)IS24C08-3ZA TSSOP100 KHz 2.7V IS24C16-3PA300-mil Plastic DIPto 5.5V IS24C16-3GA Small Outline (JEDEC STD)400 KHz 4.5V IS24C01-5PA300-mil Plastic DIPto 5.5V IS24C01-5GA Small Outline (JEDEC STD)IS24C01-5SA MSOPIS24C01-5ZA TSSOP400 KHz 4.5V IS24C02-5PA300-mil Plastic DIPto 5.5V IS24C02-5GA Small Outline (JEDEC STD)IS24C02-5SA MSOPIS24C02-5ZA TSSOP400 KHz 4.5V IS24C04-5PA300-mil Plastic DIPto 5.5V IS24C04-5GA Small Outline (JEDEC STD)IS24C04-5ZA TSSOP400 KHz 4.5V IS24C08-5PA300-mil Plastic DIPto 5.5V IS24C08-5GA Small Outline (JEDEC STD)IS24C08-5ZA TSSOP400 KHz 4.5V IS24C16-5PA300-mil Plastic DIPto 5.5V IS24C16-5GA Small Outline (JEDEC STD)Note: Automotive data is preliminary.16Integrated Silicon Solution, Inc. — /doc/af5937a6dd3383c4bb4cd241.html — 1-800-379-4774 Rev.D。

AT24C01资料的中文翻译

ATMEL®AT24C01——两线式串行总线电可擦只读存储器1K（128*8）产品特性：•标准电压或低电压操作—5.0（Vcc=4.5V至5.5V ）—2.7（Vcc=2.7V至5.5V ）—2.5（Vcc=2.5V至5.5V ）—1.8（Vcc=1.8V至5.5V ）•内部结构128*8•两线式串行接口•双向数据传送协议•兼容100kHz（2.7V 2.5 V 1.8V）和400kHz（5V）•每页4Byte写模式•自我定时写周期（最大10ms）•可靠性高—100万次擦写—数据保存100年—静电保护大于3000V•自动等级分划、可扩张温度元件•8引脚双列直插，8引脚超小型外形封装，8引脚超薄紧缩小型封装和8引脚JEDEC小外型集成电路封装性能描述：AT24C01提供128*8的1024bit可擦出编程只读存储器。

被广泛应用于低电压、低耗能要求的工业和商业。

可在8引脚PDIP, 8引脚MSOP, 8引脚TSSOP, and 8引脚JEDEC SOIC封装下进行存储，通过两线式串行总线进行读取。

这个芯片系列均支持2.7V（2.7V to 5.5V）、2.5 V(2.5V to 5.5V) 、1.8 (1.8V to 5.5V)和5V(4.5V to 5.5V)。

引脚名称功能NC 无连接SDA 串行数据SCL 串行时钟输入Test 测试输入(接地或接电压)绝对最大功率：运行温度…………-55°至+125°存储温度…………-65°至+150°引脚承受最高电压…………-1V至+7V运行最大电压…………6.25V直流最大电流…………5.0mA*注意：超过上述参数工作会损坏本元件，这是唯一的功能操作参数，超过此功率将不被支持。

按照额定功率工作将使元件更加可靠。

模块图引脚描述：SERIAL CLOCK (SCL):SCL引脚在电压上升沿时输入数据，下降沿时输出数据SERIAL DATA (SDA):SDA引脚用作双向传送数据，高电平驱动可能与其它任何引脚或元件进行线或运算。

芯片24C01C的说明文档

•Single supply with operation from 4.5 to 5.5V •Low power CMOS technology - 1 mA active current typical-10 µ A standby current typical at 5.5V•Organized as a single block of 128 bytes (128 x 8)•2-wire serial interface bus, I 2 C compatible •100kHz and 400 kHz compatibility •Page-write buffer for up to 16 bytes•Self-timed write cycle (including auto-erase)•Fast 1 mS write cycle time for byte or page mode •Address lines allow up to eight devices on bus •1,000,000 erase/write cycles guaranteed •ESD protection > 4,000V •Data retention > 200 years•8-pin PDIP , SOIC or TSSOP packages •Available for extended temperature ranges DESCRIPTIONThe Microchip T echnology Inc. 24C01C is a 1K bit Serial Electrically Erasable PROM with a voltage range of 4.5V to 5.5V . The device is organized as a single block of 128 x 8-bit memory with a 2-wire serial inter-face. Low current design permits operation with typical standby and active currents of only 10 µ A and 1 mA respectively. The device has a page-write capability for up to 16 bytes of data and has fast write cycle times of only 1 mS for both byte and page writes. Functional address lines allow the connection of up to eight 24C01C devices on the same bus for up to 8K bits of contiguous EEPROM memory. The device is available in the standard 8-pin PDIP , 8-pin SOIC (150 mil), and TSSOP packages.-Commercial (C):0 ° C to +70 ° C -Industrial (I): -40 ° C to +85 ° C -Automotive (E) -40 ° C to +125 °C224C01C1.0ELECTRICALCHARACTERISTICS1.1Maximum Ratings*V CC ........................................................................7.0V All inputs and outputs w.r.t. V SS ......-0.6V to V CC +1.0V Storage temperature...........................-65˚C to +150˚C Ambient temp. with power applied.......-65˚C to +125˚C Soldering temperature of leads (10 seconds)...+300˚C ESD protection on all pins ......................................≥ 4 kV*Notice:Stresses above those listed under “Maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this speciﬁcation is not implied. Exposure to maximum rating conditions for extended peri-ods may affect device reliability.TABLE 1-1:PIN FUNCTION TABLEName Function V SS SDA SCL VCC A0, A1, A2T estGround Serial Data Serial Clock+4.5V to 5.5V Power Supply Chip SelectsT est Pin: may be tied high, low or left ﬂoatingTABLE 1-2:DC CHARACTERISTICSAll parameters apply across the speci-ﬁed operating ranges unless otherwise noted.VCC = +4.5V to +5.5V Commercial (C):T amb = 0 ° C to +70 ° C Industrial (I):Tamb = -40 ° C to +85 ° C Automotive (E):T amb = -40 ° C to +125 ° C ParameterSymbol Min.Max.Units ConditionsSCL and SDA pins:High level input voltageV IH 0.7 V CCV Low level input voltageV IL .3 V CC V Hysteresis of Schmitt trigger inputs V HYS 0.05 V CC —V (Note)Low level output voltage V OL .40V I OL = 3.0 mA, V CC = 4.5V Input leakage current ILI -1010 µ A V IN = 0.1V to 5.5V , WP = Vss Output leakage currentILO -1010 µ A V OUT = 0.1V to 5.5V Pin capacitance (all inputs/outputs)C IN , C OUT —10pF VCC = 5.0V (Note)T amb = 25 ° C, f = 1 MHz Operating current I CC Read —1mA V CC = 5.5V , SCL = 400 kHz I CC Write —3mA V CC = 5.5VStandby currentICCS—50µ AV CC = 5.5V , SDA = SCL = VCCNote: This parameter is periodically sampled and not 100% tested.24C01CTABLE 1-3:AC CHARACTERISTICSAll parameters apply across the speciﬁed oper-ating ranges unless otherwise noted.Vcc = 4.5V to 5.5V Commercial (C):T amb = 0 ° C to +70 ° C Industrial (I):T amb = -40 ° C to +85 ° C Automotive (E):Tamb = -40 ° C to +125 ° C ParameterSymbol Tamb > +85 ° C -40 ° C ≤ Tamb ≤+85 ° CUnits RemarksMin.Max.Min.Max. Clock frequency F CLK —100—400kHz Clock high time T HIGH 4000—600—ns Clock low timeT LOW 4700—1300—ns SDA and SCL rise time T R —1000—300ns (Note 1)SDA and SCL fall time T F —300—300ns (Note 1)ST ART condition hold time T HD : STA 4000—600—ns After this period the ﬁrst clock pulse is generated START condition setup time T SU : STA 4700—600—ns Only relevant for repeated ST ART condition Data input hold time T HD : DAT 0—0—ns (Note 2)Data input setup timeT SU : DAT 250—100—ns STOP condition setup time T SU : STO 4000—600—ns Output valid from clock T AA —3500—900ns (Note 2)Bus free timeT BUF4700—1300—nsTime the bus must be free before a new transmission can startOutput fall time from V IH minimum to V IL maximum T OF —25020 +0.1 C B250ns (Note 1), C B ≤ 100 pF Input ﬁlter spike suppression (SDA and SCL pins)T SP —50—50ns(Note 3)Write cycle time TWR— 1.5—1ms Byte or Page modeEndurance1M—1M—cycles 25 ° C, V CC = 5.0V , BlockMode (Note 4)Note 1: Not 100% tested. CB = total capacitance of one bus line in pF .2:As a transmitter, the device must provide an internal minimum delay time to bridge the undeﬁned region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of ST ART or STOP conditions.3:The combined T SP and V HYS speciﬁcations are due to Schmitt trigger inputs which provide improved noise spike suppression. This eliminates the need for a TI speciﬁcation for standard operation.4:This parameter is not tested but guaranteed by characterization. For endurance estimates in a speciﬁc appli-cation, please consult the T otal Endurance Model which can be obtained on our BBS or website.24C01C2.0PIN DESCRIPTIONS2.1SDA Serial DataThis is a bi-directional pin used to transfer addresses and data into and data out of the device. It is an open drain terminal, therefore the SDA bus requires a pull-up resistor to V CC (typical 10 k Ω for 100 kHz, 2 k Ω for 400 kHz).For normal data transfer SDA is allowed to change only during SCL low. Changes during SCL high are reserved for indicating the ST ART and STOP conditions.2.2SCL Serial ClockThis input is used to synchronize the data transfer from and to the device.2.3A0, A1, A2The levels on these inputs are compared with the cor-responding bits in the slave address. The chip is selected if the compare is true.Up to eight 24C01C devices may be connected to the same bus by using different chip select bit combina-tions. These inputs must be connected to either V CC or V SS .2.4TestThis pin is utilized for testing purposes only. It may be tied high, tied low or left ﬂoating.2.5Noise ProtectionThe 24C01C employs a V CC threshold detector circuit which disables the internal erase/write logic if the V CC is below 3.8 volts at nominal conditions.The SCL and SDA inputs have Schmitt trigger and ﬁlter circuits which suppress noise spikes to assure proper device operation even on a noisy bus.3.0FUNCTIONAL DESCRIPTIONThe 24C01C supports a bi-directional 2-wire bus and data transmission protocol. A device that sends data onto the bus is deﬁned as transmitter, and a device receiving data as receiver. The bus has to be controlled by a master device which generates the serial clock (SCL), controls the bus access, and generates the ST ART and STOP conditions, while the 24C01C works as slave. Both master and slave can operate as trans-mitter or receiver but the master device determines which mode is activated.24C01C4.0BUS CHARACTERISTICSThe following bus protocol has been deﬁned:•Data transfer may be initiated only when the bus is not busy.•During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH will be interpreted as a ST ART or STOP condition.Accordingly, the following bus conditions have been deﬁned (Figure 4-1).4.1Bus not Busy (A)Both data and clock lines remain HIGH.4.2Start Data Transfer (B)A HIGH to LOW transition of the SDA line while the clock (SCL) is HIGH determines a START condition. All commands must be preceded by a ST ART condition.4.3Stop Data Transfer (C)A LOW to HIGH transition of the SDA line while the clock (SCL) is HIGH determines a STOP condition. All operations must be ended with a STOP condition.4.4Data Valid (D)The state of the data line represents valid data when,after a ST ART condition, the data line is stable for the duration of the HIGH period of the clock signal.The data on the line must be changed during the LOW period of the clock signal. There is one bit of data per clock pulse.Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of the data bytes transferred between the ST ART and STOP conditions is determined by the master device and is theoretically unlimited, although only the last six-teen will be stored when doing a write operation. When an overwrite does occur it will replace data in a ﬁrst in ﬁrst out fashion.4.5AcknowledgeEach receiving device, when addressed, is required to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse which is associated with this acknowledge bit.The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case,the slave must leave the data line HIGH to enable the master to generate the STOP condition (Figure 4-2).24C01C5.0DEVICE ADDRESSINGA control byte is the ﬁrst byte received following the start condition from the master device (Figure 5-1). The control byte consists of a four bit control code; for the 24C01C this is set as 1010 binary for read and write operations. The next three bits of the control byte are the chip select bits (A2, A1, A0). The chip select bits allow the use of up to eight 24C01C devices on the same bus and are used to select which device is accessed. The chip select bits in the control byte must correspond to the logic levels on the corresponding A2,A1, and A0 pins for the device to respond. These bits are in effect the three most signiﬁcant bits of the word address.The last bit of the control byte deﬁnes the operation to be performed. When set to a one a read operation is selected, and when set to a zero a write operation is selected. Following the start condition, the 24C01C monitors the SDA bus checking the control byte being transmitted. Upon receiving a 1010 code and appropri-ate chip select bits, the slave device outputs an acknowledge signal on the SDA line. Depending on the state of the R/W bit, the 24C01C will select a read or write operation.5.1Contiguous Addressing Across Multiple DevicesThe chip select bits A2, A1, A0 can be used to expand the contiguous address space for up to 8K bits by add-ing up to eight 24C01C devices on the same bus. In this case, software can use A0 of the control byte as address bit A8, A1 as address bit A9, and A2 as address bit A10. It is not possible to write or read across device boundaries.24C01C6.0WRITE OPERATIONS6.1Byte WriteFollowing the start signal from the master, the device code(4 bits), the chip select bits (3 bits), and the R/W bit which is a logic low is placed onto the bus by the master transmitter. The device will acknowledge this control byte during the ninth clock pulse. The next byte transmitted by the master is the word address and will be written into the address pointer of the 24C01C. After receiving another acknowledge signal from the 24C01C the master device will transmit the data word to be written into the addressed memory location. The 24C01C acknowledges again and the master gener-ates a stop condition. This initiates the internal write cycle, and during this time the 24C01C will not generate acknowledge signals (Figure 6-1).6.2Page WriteThe write control byte, word address and the ﬁrst data byte are transmitted to the 24C01C in the same way as in a byte write. But instead of generating a stop condi-tion, the master transmits up to 15 additional data bytes to the 24C01C which are temporarily stored in the on-chip page buffer and will be written into the memory after the master has transmitted a stop condition. After the receipt of each word, the four lower order address pointer bits are internally incremented by one. The higher order four bits of the word address remains con-stant. If the master should transmit more than 16 bytes prior to generating the stop condition, the address counter will roll over and the previously received data will be overwritten. As with the byte write operation,once the stop condition is received an internal write cycle will begin (Figure 6-2).24C01C7.0ACKNOWLEDGE POLLINGSince the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). Once the stop condition for a write com-mand has been issued from the master, the device ini-tiates the internally timed write cycle. ACK polling can be initiated immediately. This involves the master send-ing a start condition followed by the control byte for a write command (R/W = 0). If the device is still busy with the write cycle, then no ACK will be returned. If no ACK is returned, then the start bit and control byte must be re-sent. If the cycle is complete, then the device will return the ACK and the master can then proceed with the next read or write command. See Figure 7-1 for ﬂow diagram.FIGURE 7-1:ACKNOWLEDGE POLLING24C01C8.0READ OPERATIONSRead operations are initiated in the same way as write operations with the exception that the R/W bit of the slave address is set to one. There are three basic types of read operations: current address read, random read,and sequential read.8.1Current Address ReadThe 24C01C contains an address counter that main-tains the address of the last word accessed, internally incremented by one. Therefore, if the previous read access was to address n, the next current address read operation would access data from address n + 1. Upon receipt of the slave address with the R/W bit set to one,the 24C01C issues an acknowledge and transmits the eight bit data word. The master will not acknowledge the transfer but does generate a stop condition and the 24C01C discontinues transmission (Figure 8-1).8.2Random ReadRandom read operations allow the master to access any memory location in a random manner. To perform this type of read operation, ﬁrst the word address must be set. This is done by sending the word address to the 24C01C as part of a write operation. After the wordaddress is sent, the master generates a start condition following the acknowledge. This terminates the write operation, but not before the internal address pointer is set. Then the master issues the control byte again but with the R/W bit set to a one. The 24C01C will then issue an acknowledge and transmits the eight bit data word. The master will not acknowledge the transfer but does generate a stop condition and the 24C01C dis-continues transmission (Figure 8-2). After this com-mand, the internal address counter will point to the address location following the one that was just read.8.3Sequential ReadSequential reads are initiated in the same way as a ran-dom read except that after the 24C01C transmits the ﬁrst data byte, the master issues an acknowledge as opposed to a stop condition in a random read. This directs the 24C01C to transmit the next sequentially addressed 8-bit word (Figure 8-3).To provide sequential reads the 24C01C contains an internal address pointer which is incremented by one at the completion of each operation. This address pointer allows the entire memory contents to be serially read during one operation. The internal address pointer will automatically roll over from address 7F to address 00.24C01CNOTES:24C01C24C01C PRODUCT IDENTIFICATION SYSTEMT o order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales ofﬁce.Sales and SupportData SheetsProducts supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:1.Y our local Microchip sales ofﬁce.2.The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277.3.The Microchip’s Bulletin Board, via your local CompuServe number (CompuServe membership NOT required).。

24C02B中文资料

FEATURES•Single supply with 5.0V operation •Low power CMOS technology - 1 mA active current typical-10 µ A standby current typical at 5.0V - 5 µ A standby current typical at 5.0V•Organized as a single block of 128 bytes (128 x 8) or 256 bytes (256 x 8)•2-wire serial interface bus, I 2 C compatible •100 kHz compatibility•Self-timed write cycle (including auto-erase)•Page-write buffer for up to 8 bytes• 2 ms typical write cycle time for page-write •Hardware write protect for entire memory •Can be operated as a serial ROM •ESD protection > 3,000V•1,000,000 ERASE/WRITE cycles guaranteed Data retention > 200 years •8 pin DIP or SOIC package•Available for extended temperature ranges DESCRIPTIONThe Microchip T echnology Inc. 24C01B and 24C02B are 1K bit and 2K bit Electrically Erasable PROMs. The devices are organized as a single block of 128 x 8 bit or 256 x 8 bit memory with a 2-wire serial interface. The 24C01B and 24C02B also have page-write capability for up to 8 bytes of data. The 24C01B and 24C02B are available in the standard 8-pin DIP and an 8-pin surface mount SOIC package.These devices are for extended temperature applications only. It is recommended that all other applications use Microchip’s 24LC01B/02B.-Automotive (E):-40˚C to +125˚C2元器件交易网24C01B/02B1.0ELECTRICAL CHARACTERISTICS1.1Maximum Ratings*V CC ...................................................................................7.0V All inputs and outputs w.r.t. V SS ................-0.6V to V CC +1.0V Storage temperature.....................................-65˚C to +150˚C Ambient temp. with power applied.................-65˚C to +125˚C Soldering temperature of leads (10 seconds).............+300˚C ESD protection on all pins............................................. ≥ 4 kV*Notice: Stresses above those listed under “Maximum ratings”may cause permanent damage to the device. This is a stress rat-ing only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this speciﬁcation is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.TABLE 1-1:PIN FUNCTION TABLEName FunctionV SS SDA SCL WP V CC NCGroundSerial Address/Data I/O Serial ClockWrite Protect Input +5.0V Power Supply No Internal ConnectionTABLE 1-1:DC CHARACTERISTICSAll parameters apply across the speci-ﬁed operating ranges unless otherwise noted.VCC = +4.5V to 5.5VAutomotive (E):Tamb = -40 ° C to 125 ° C ParameterSymbol Min.Max.Units ConditionsWP , SCL and SDA pins:High level input voltageV IH .7 V CCV Low level input voltageV IL .3 V CC V Hysteresis of Schmidt trigger inputs V HYS .05 V CC —V (Note)Low level output voltage V OL .40V I OL = 3.0 mA, V CC = 2.5V Input leakage current ILI -1010 µ A V IN = .1V to 5.5V Output leakage currentILO -1010 µ mA V OUT = .1V to 5.5VPin capacitance (all inputs/outputs)C IN , C OUT —10pF V CC = 5.0V (Note 1)Tamb = 25˚C, F CLK = 1 MHz Operating current I CC Write —3mA V CC = 5.5V , SCL = 100 kHzI CC Read —1mA Standby current ICCS—30 µ A V CC = 3.0V , SDA = SCL = VCC 100 µ AV CC = 5.5V , SDA = SCL = VCC Note:This parameter is periodically sampled and not 100% tested.元器件交易网24C01B/02BTABLE 1-2:AC CHARACTERISTICSAll Parameters apply across thespeciﬁed operating ranges unless otherwise notedVcc = 4.5V to 5.5V Automotive (E):Tamb = -40˚C to +125˚C,ParameterSymbol Min.Max.Units RemarksClock frequency F CLK —100kHz Clock high time T HIGH 4000—ns Clock low time T LOW 4700—ns SDA and SCL rise time T R —1000ns (Note 1)SDA and SCL fall time T F —300ns (Note 1)ST ART condition hold time T HD : STA 4000—ns After this period the ﬁrst clock pulse is generatedST ART condition setup time T SU : STA 4700—ns Only relevant for repeated ST ART condition Data input hold time T HD : DAT 0—ns (Note 2)Data input setup time T SU : DAT 250—ns STOP condition setup time T SU : STO 4000—ns Output valid from clock T AA —3500ns (Note 2)Bus free timeT BUF 4700—ns Time the bus must be free before a new transmission can start Output fall time from V IH minimum to V IL maximum T OF —250ns (Note 1), CB ≤ 100 pF Input ﬁlter spike suppression (SDA and SCL pins)T SP —50ns (Note 3)Write cycle time T WR —10ms Byte or Page modeEndurance—1M—cycles25 ° C, Vcc = 5.0V , Block Mode (Note 4)Note 1:Not 100% tested. CB = total capacitance of one bus line in pF .2:As a transmitter, the device must provide an internal minimum delay time to bridge the undeﬁned region(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.3:The combined T SP and VHYSspeciﬁcations are due to Schmitt trigger inputs which provide improved noisespike suppression. This eliminates the need for a TI speciﬁcation for standard operation.4:This parameter is not tested but guaranteed by characterization. For endurance estimates in a speciﬁcapplication, please consult the T otal Endurance Model which can be obtained on our BBS or website.元器件交易网24C01B/02B2.0FUNCTIONAL DESCRIPTION The 24C01B/02B supports a bi-directional two wire bus and data transmission protocol. A device that sends data onto the bus is deﬁned as transmitter, and a device receiving data as receiver. The bus has to be controlled by a master device which generates the serial clock (SCL), controls the bus access, and gener-ates the ST ART and STOP conditions, while the 24C01B/02B works as slave. Both master and slave can operate as transmitter or receiver but the master device determines which mode is activated.3.0BUS CHARACTERISTICSThe following bus protocol has been deﬁned:•Data transfer may be initiated only when the busis not busy.•During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH will be interpreted as a ST ART or STOP condition. Accordingly, the following bus conditions have been deﬁned (Figure 3-1).3.1Bus Not Busy (A)Both data and clock lines remain HIGH.3.2Start Data Transfer (B)A HIGH to LOW transition of the SDA line while the clock (SCL) is HIGH determines a ST ART condition. All commands must be preceded by a ST ART condi-tion.3.3Stop Data Transfer (C)A LOW to HIGH transition of the SDA line while the clock (SCL) is HIGH determines a STOP condition. All operations must be ended with a STOP condition.3.4Data Valid (D)The state of the data line represents valid data when, after a ST ART condition, the data line is stable for the duration of the HIGH period of the clock signal.The data on the line must be changed during the LOW period of the clock signal. There is one clock pulse per bit of data.Each data transfer is initiated with a ST ART condition and terminated with a STOP condition. The number of the data bytes transferred between the ST ART and STOP conditions is determined by the master device and is theoretically unlimited, although only the last six-teen will be stored when doing a write operation. When an overwrite does occur it will replace data in a ﬁrst in ﬁrst out fashion.3.5AcknowledgeEach receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse which is associated with this acknowledge bit. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line HIGH to enable the master to generate the STOP condition.元器件交易网24C01B/02B3.6Device AddressAfter generating a ST ART condition, the bus master transmits the slave address consisting of a 4-bit device code (1010) for the 24C01B/02B, followed by three don't care bits.The eighth bit of slave address determines if the master device wants to read or write to the 24C01B/02B (Figure 3-2).The 24C01B/02B monitors the bus for its correspond-ing slave address all the time. It generates an acknowl-edge bit if the slave address was true and it is not in a programming mode.4.0WRITE OPERATION4.1Byte WriteFollowing the start signal from the master, the device code (4 bits), the don't care bits (3 bits), and the R/W bit which is a logic low is placed onto the bus by the master transmitter. This indicates to the addressed slave receiver that a byte with a word address will follow after it has generated an acknowledge bit during the ninth clock cycle. Therefore the next byte transmitted by the master is the word address and will be written into the address pointer of the 24C01B/02B. After receiving another acknowledge signal from the 24C01B/02B the master device will transmit the data word to be written into the addressed memory location.The 24C01B/02B acknowledges again and the master generates a stop condition. This initiates the internal write cycle, and during this time the 24C01B/02B will not generate acknowledge signals (Figure 4-1).4.2Page WriteThe write control byte, word address and the ﬁrst data byte are transmitted to the 24C01B/02B in the same way as in a byte write. But instead of generating a stop condition the master transmits up to eight data bytes to the 24C01B/02B which are temporarily stored in the on-chip page buffer and will be written into the memoryafter the master has transmitted a stop condition. After the receipt of each word, the three lower order address pointer bits are internally incremented by one. The higher order ﬁve bits of the word address remains con-stant. If the master should transmit more than eight words prior to generating the stop condition, the address counter will roll over and the previously received data will be overwritten. As with the byte write operation, once the stop condition is received an inter-nal write cycle will begin (Figure 4-2).元器件交易网24C01B/02B5.0ACKNOWLEDGE POLLINGSince the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). Once the stop condition for a write com-mand has been issued from the master, the device ini-tiates the internally timed write cycle. ACK polling can be initiated immediately. This involves the master send-ing a start condition followed by the control byte for a write command (R/W = 0). If the device is still busy with the write cycle, then no ACK will be returned. If the cycle is complete, then the device will return the ACK and the master can then proceed with the next read or write command. See Figure 5-1 for ﬂow diagram. FIGURE 5-1:ACKNOWLEDGE POLLING6.0WRITE PROTECTIONThe 24C01B/02B can be used as a serial ROM when the WP pin is connected to V CC. Programming will be inhibited and the entire memory will be write-protected.7.0READ OPERATIONRead operations are initiated in the same way as write operations with the exception that the R/W bit of the slave address is set to one. There are three basic types of read operations: current address read, random read, and sequential read.7.1Current Address ReadThe 24C01B/02B contains an address counter that maintains the address of the last word accessed, inter-nally incremented by one. Therefore, if the previous access (either a read or write operation) was to address n, the next current address read operation would access data from address n + 1. Upon receipt of the slave address with R/W bit set to one, the 24C01B/ 02B issues an acknowledge and transmits the eight bit data word. The master will not acknowledge the trans-fer but does generate a stop condition and the 24C01B/ 02B discontinues transmission (Figure 7-1).7.2Random ReadRandom read operations allow the master to access any memory location in a random manner. T o perform this type of read operation, ﬁrst the word address must be set. This is done by sending the word address to the 24C01B/02B as part of a write operation. After the word address is sent, the master generates a start condition following the acknowledge. This terminates the write operation, but not before the internal address pointer is set. Then the master issues the control byte again but with the R/W bit set to a one. The 24C01B/02B will then issue an acknowledge and transmits the eight bit data word. The master will not acknowledge the transfer but does generate a stop condition and the 24C01B/02B discontinues transmission (Figure 7-2).7.3Sequential ReadSequential reads are initiated in the same way as a ran-dom read except that after the 24C01B/02B transmits the ﬁrst data byte, the master issues an acknowledge as opposed to a stop condition in a random read. This directs the 24C01B/02B to transmit the next sequen-tially addressed 8-bit word (Figure 7-3).To provide sequential reads the 24C01B/02B contains an internal address pointer which is incremented by one at the completion of each operation. This address pointer allows the entire memory contents to be serially read during one operation.7.4Noise ProtectionThe 24C01B/02B employs a V CC threshold detector cir-cuit which disables the internal erase/write logic if the V CC is below 1.5 volts at nominal conditions.The SCL and SDA inputs have Schmitt trigger and ﬁlter circuits which suppress noise spikes to assure proper device operation even on a noisy bus.元器件交易网24C01B/02B8.0PIN DESCRIPTIONS8.1Serial DataThis is a bi-directional pin used to transfer addresses and data into and data out of the device. It is an open drain terminal, therefore the SDA bus requires a pull-up resistor to V CC (typically 10 KΩ for 100 kHz).For normal data transfer SDA is allowed to change only during SCL low. Changes during SCL high are reserved for indicating the ST ART and STOP condi-tions.8.2SCL Serial ClockThis input is used to synchronize the data transfer from and to the device.8.3WPThis pin must be connected to either V SS or V CC.If tied to V SS, normal memory operation is enabled (read/write the entire memory).If tied to V CC, WRITE operations are inhibited. The entire memory will be write-protected. Read operations are not affected.This feature allows the user to use the 24C01B/02B as a serial ROM when WP is enabled (tied to V CC).元器件交易网元器件交易网24C01B/02B Array NOTES:元器件交易网24C01B/02B Array NOTES:元器件交易网24C01B/02B Array NOTES:24C01B/02BT o order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales ofﬁce.Data SheetsProducts supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:1.Y our local Microchip sales ofﬁce.2.The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277.3.The Microchip’s Bulletin Board, via your local CompuServe number (CompuServe membership NOT required).Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.元器件交易网元器件交易网MAll rights reserved. © 1997, Microchip T echnology Incorporated, USA. 12/97 Printed on recycled paper.。

常见IC卡型号

常见IC卡型号来源：迈德金卡作者：青青禾更新时间：2010-04-12IC卡（INTEGRATED CIRCUITCARD）又称集成电路卡，它是一个塑料卡片，其大小与磁卡一样，但比磁卡要厚且硬。

在卡片的正面可以看到一块小金属片，在金属片的下面是一块半导体芯片。

这种芯片可以是存储器或是一微处理器（CPU）。

带着存储器的IC卡又称存储卡，带着CPU的IC卡又称智能卡或CPU。

1、ATMEL 24CO1A存储容量：1Kbit,无密码，只有读写两种操作制作标准：ISO 7816应用范围：数据存储2、ATMEL 24C16存储容量：16Kbit，无密码，只有读写两种操作制作标准：ISO 7816应用范围：数据存储3、ATMEL 24C64存储容量：64Kbit，无密码，只有读写两种操作制作标准：ISO 7816应用范围：数据存储4、AT88SC102存储容量：加密存储卡，1Kbit特点：2个应用区，容量均为512Kbit，密码计数器值为4，卡片总密码2字节，一区擦除密码6字节，二区擦除密码4字节制作标准：ISO 7816应用范围：医疗保险、数据存储、网吧收费、身份认证、电子钱包5、AT88SC1604A存储容量：加密存储卡，16Kbit特点：1个公用区和4个应用区，四个应用区中，各个分区都有各自的密码和擦除密码，且各个分区中均有各自的密码计数器，密码均为2字节，密码计数器值为8制作标准：ISO 7816应用范围：医疗保险、数据存储、网吧收费、身份认证、电子钱包6、SLE 4428存储容量：加密存储卡，1K字节特点：卡始终可读，写卡必须通过密码校验，2字节可编程密码，密码错误计数值为8，可对整张卡片写保护制作标准：ISO 7816应用范围：医疗保险、数据存储、网吧收费、高速公路收费、电子钱包7、SLE 5542（SLE4442升级）存储容量：加密存储卡，256字节特点：卡始终可读，写卡必须通过密码校验，3字节可编程密码，密码错误计数值为3，可对卡片前32字节写保护制作标准：ISO 7816应用范围：医疗保险、数据存储、网吧收费、高速公路收费、电子钱包8、Philips Mifare 1 S50存储容量：8Kbit,16个扇区，每区4块，每块16字节，以块为存取单位，每个扇区有独立的一组密码及访问控制，有32位全球唯一序列号工作频率：13.56MHZ通讯速度：106kbps读写距离：2.5-10CM制作标准：ISO 14443应用范围：企业/校园一卡通、公交一卡通、高速公路收费、停车场、小区管理、电子钱包9、Philips Mifare S70存储容量：32Kbit,40个扇区，其中32个扇区每扇区64个字节容量，分为4块，每块16字节；8个扇每扇区256个字节，分为16块，每块16个字节，以块为存取单位，每个扇区有独立的一组密码及访问控制，有32位全球唯一序列号码工作频率：13.56MHZ通讯速度：106Kbps读写距离：2.5-10CM制作标准：ISO 14443应用范围：高容量要求的校园一卡通、城市一卡通、电子钱包10、Mifare Ultra Light存储容量：512bit,16块，每块4字节，唯一的7字节序列号，32位用户可定义的一次性编程区域，384位用户读、写区域工作频率：13.56MHZ通讯速度：106Kbps读写距离：在100MM以内（与天线有关）制作标准：ISO 14443应用范围：一次性票卡，如地铁、城际高铁11、Ti 2048存储容量：2Kbit,分为64×32个区段，唯一64位序列号工作频率：13.56MHZ通讯速度：106Kbps制作标准：ISO 15693应用范围：公交，泊车，身份认证，考勤管理，门票，一卡通付费，产品标识12、ATMEL T5567（原T5557升级版）存储容量：330bit, 10分区,每个分区33bit,8位密码工作频率:125KHZ读写距离:3-10CM制作标准：应用范围:感应式智能门锁、企业一卡通系统、门禁、通道系统13、EM4001 ID卡工作频率：125KHZ读写距离：2—15CM应用范围：身份识别、考勤系统、门禁系统、财物标识14、SLE 4442存储容量：加密存储卡，256bit,特点：卡始终可读，写卡必须通过密码校验，3字节可编程密码，密码错误计数值为3，可对卡片前32字节写保护制作标准：ISO 7816应用范围：医疗保险、数据存储、网吧收费、高速公路收费、电子钱包15、CPU卡存储容量：8K、16K、32K等特点：自带芯片操作系统（COS），安全性能高，可自定义卡片文件结构、容量大、速度快、支持一卡多用。

IC卡24C01资料

I2C总线器件应用单片机应用系统正向小型化、高可靠性、低功耗等方向发展。

在一些设计功能较多的系统中，常需扩展多个外围接口器件。

若采用传统的并行扩展方式，将占用较多的系统资源，且硬件电路复杂，成本高、功耗大、可靠性差。

为此，Philips公司推出了一种高效、可靠、方便的串行扩展总线—I2C总线。

单片机系统采用I2C总线后将大大简化电路结构，增加硬件的灵活性，缩短产品开发周期，降低成本，提高系统可靠性。

I2C总线（Inter IC BUS）是Philips推出的芯片间串行传输总线。

它以两根连线实现了完善的全双工同步数据传送，可以极方便地构成多机系统和外围器件扩展系统。

I2C总线采用了器件地址的硬件设置方法，通过软件寻址完全避免了器件的片选线寻址方法，从而使硬件系统具有最简单而灵活的扩展方法。

第一节I2C总线器件应用概述一、I2C总线器件目前许多单片机厂商引进了Philips公司的I2C总线技术，推出了许多带有I2C总线接口的单片机。

Philips公司除了生产具有I2C总线接口的单片机外，还推出了许多具备I2C总线的外部接口芯片，如24XX系列的E2PROM 、128字节的静态RAM芯片PCF8571、日历时钟芯片PCF8563、4位LED驱动芯片SAA1064、160段LCD驱动芯片PCF8576等多种类多系列接口芯片。

二、I2C总线工作原理采用I2C总线系统结构如图7-1所示。

图7-1 I2C总线系统结构图其中，SCL是时钟线，SDA是数据线。

总线上的各器件都采用漏极开路结构与总线相连，因此，SCL、SDA均需接上拉电阻，总线在空闭状态下均保持高电平。

I2C总线支持多主和主从两种工作方式，通常为主从工作方式。

在主从工作方式中，系统中只有一个主器件（单片机），总线上其它器件都是具有I2C总线的外围从器件。

在主从工作方式中，主器件启动数据的发送（发出启动信号），产生时钟信号，发出停止信号。

为了实现通信，每个从器件均有唯一一个器件地址，具体地址由I2C总线委员会分配。

IS24C08中文资料

IS24C01IS24C02IS24C04IS24C08IS24C16ISSI®Copyright © 2002 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.1K-bit/2K-bit/4K-bit/8K-bit/16K-bit 2-WIRE SERIAL CMOS EEPROMAPRIL 2002DESCRIPTIONThe IS24CXX (refers to IS24C01, IS24C02, IS24C04,IS24C08, IS24C16) family is a low-cost and low voltage 2-wire Serial EEPROM. It is fabricated using ISSI’s advanced CMOS EEPROM technology and provides a low power and low voltage operation. The IS24CXX family features a write protection feature, and is available in 8-pin DIP and 8-pin SOIC packages.The IS24C01 is a 1K-bit EEPROM; IS24C02 is a 2K-bit EEPROM; IS24C04 is a 4K-bit EEPROM; IS24C08 is a 8K-bit EEPROM; IS24C16 is a 16K-bit EEPROM.The IS24C01 and IS24C02 are available in 8-pin MSOP package. The IS24C01, IS24C02, IS24C04, and IS24C08are available in 8-Pin TSSOP package.Automotive data is preliminary.FEATURES•Low Power CMOS Technology–Standby Current less than 8 µA (5.5V)–Read Current (typical) less than 1 mA (5.5V)–Write Current (typical) less than 3 mA (5.5V)•Flexible Voltage Operation–Vcc = 1.8V to 5.5V for –2 version –Vcc = 2.5V to 5.5V for –3 version •400 KHz (I 2C Protocol) Compatibility •Hardware Data Protection–Write Protect Pin •Sequential Read Feature•Filtered Inputs for Noise Suppression •8-pin PDIP and 8-pin SOIC packages •8-pin TSSOP (1K,2K, 4K & 8K only)•8-pin MSOP (1K,2K only)•Self time write cycle with auto clear 5 ms @ 2.5V •Organization:–IS24C01128x8(one block of 128 bytes)–IS24C02256x8(one block of 256 bytes)–IS24C04512x8(two blocks of 256 bytes)–IS24C081024x8(four blocks of 256 bytes)–IS24C162048x8(eight blocks of 256 bytes)•Page Write Buffer•Two-Wire Serial Interface–Bi-directional data transfer protocol •High Reliability–Endurance: 1,000,000 Cycles –Data Retention: 100 Years•Commercial, Industrial and Automotive tempera-ture ranges元器件交易网元器件交易网IS24C01IS24C02IS24C04IS24C08 IS24C16ISSI®FUNCTIONAL BLOCK DIAGRAM2Integrated Silicon Solution, Inc. — — 1-800-379-4774Rev.DIS24C01IS24C02IS24C04IS24C08 IS24C16ISSI®PIN DESCRIPTIONSA0-A2Address InputsSDA Serial Address/Data I/O SCL Serial Clock Input WP Write Protect Input Vcc Power Supply GNDGroundSCLThis input clock pin is used to synchronize the data transfer to and from the device.SDAThe SDA is a Bi-directional pin used to transfer addresses and data into and out of the device. The SDA pin is an open drain output and can be wire-Ored with other open drain or open collector outputs.The SDA bus requires a pullup resistor to Vcc.A0, A1, A2The A0, A1 and A2 are the device address inputs. The IS24C01 and IS24C02 use the A0, A1, and A2 for hardware addressing and a total of 8 devices may be used on a single bus system.PIN CONFIGURATION8-Pin DIP and SOIC8 Pin TSSOP (1K, 2K, 4K and 8K)8-Pin MSOP (1K, 2K)12348765A0A1A2GNDVCC WP SCL SDAThe IS24C04 uses A1 and A2 pins for hardwire addressing and a total of four devices may be addressed on a single bus system.The A0 pin is not used by IS24C04. This pin can be left floating or tied to GND or Vcc.The IS24C08 only use A2 input for hardwire addressing and a total of two devices may be addressed on a single bus system.The A0 and A1 pins are not used by IS24C08. They may be left floating or tied to either GND or Vcc.These pins are not used by IS24C16. A0 and A1 may be left floating or tied to either GND or Vcc. A2 should be tied to either GND or Vcc.WPWP is the Write Protect pin. On the 24C01, 24C02, IS24C04and 24C08, if the WP pin is tied to V CC the entire array becomes Write Protected (Read only). On the 24C16, if the WP pin is tied to Vcc the upper half array becomes Write Protected (Read only). When WP is tied to GND or left floating normal read/write operations are allowed to the device.元器件交易网IS24C01IS24C02IS24C04IS24C08 IS24C16ISSI®DEVICE OPERATIONThe IS24CXX family features a serial communication and supports a bi-directional 2-wire bus transmission protocol. 2-WIRE BUSThe two-wire bus is defined as a Serial Data line(SDA), and a Serial Clock Line (SCL). The protocol defines any device that sends data onto the SDA bus as a transmitter, and the receiving devices as a receiver. The bus is controlled by MASTER device which generates the SCL, controls the bus access and generates the STOP and START conditions. The IS24CXX is the SLAVE device on the bus.THE BUS PROTOCOL:--Data transfer may be initiated only when the bus is not busy--During a data transfer, the data line must remain stable whenever the clock line is high. Any changes in the data line while the clock line is high will be interpreted as a START or STOP condition.The state of the data line represents valid data when after a START condition, the data line is stable for the duration of the HIGH period of the clock signal. The data on the line must be changed during the LOW period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a START condition and terminated with a STOP condition.START CONDITIONThe START condition precedes all commands to the devices and is defined as a HIGH to LOW transition of SDA when SCL is HIGH. The IS24CXX monitors the SDA and SCL lines and will not respond until the START condition is met.STOP CONDITIONThe STOP condition is defined as a LOW to HIGH transition of SDA when SCL is HIGH. All operations must end with a STOP condition.ACKNOWLEDGEAfter a successful data transfer, each receiving device is required to generate an acknowledge. The Acknowledging device pulls down the SDA line.DEVICE ADDRESSINGThe MASTER begins a transmission by sending a START condition. The MASTER then sends the address of the particular slave devices it is requesting. The SLAVE address is 8 bytes.The four most significant bytes of the address are fixed as 1010 for the IS24CXX.For the IS24C16, the bytes(B2, B1 and B0) are used for memory page addressing (the IS24C16 is organized as eight blocks of 256 bytes).For the IS24C04 out of the next three bytes, B0 is for Memory Page Addressing (the IS24C04 is organized as two blocks of 256 bytes) and A2 and A1 bytes are used as device address bytes and must compare to its hard-wire inputs pins (A2 and A1). Up to four IS24C04's may be individually addressed by the system. The page addressing bytes for IS24Cxx should be considered the most significant bytes of the data word address which follows.For the IS24C08 out of the next three bytes, B1 and B0 are for memory page addressing (the IS24C08 is organized as four blocks of 256 bytes) and the A2 bit is used as device address bit and must compare to its hard-wired input pin (A2). Up to two IS24C08 may be individually addressed by the system. The page addressing bytes for IS24CXX should be considered the most significant bytes of the data word address which follows.For the IS24C01 and IS24C02, the A0, A1, and A2 are used as device address bytes and must compare to its hard-wired input pins (A0, A1, and A2) Up to Eight IS24C01 and/ or IS24C02's may be individually addressed by the system. The last bit of the slave address specifies whether a Read or Write operation is to be performed. When this bit is set to 1, a Read operation is selected, and when set to 0, a Write operation is selected.After the MASTER sends a START condition and the SLAVE address byte, the IS24CXX monitors the bus and responds with an Acknowledge (on the SDA line) when its address matches the transmitted slave address. The IS24CXX pulls down the SDA line during the ninth clock cycle, signaling that it received the eight bytes of data. The IS24CXX then performs a Read or Write operation depending on the state of the R/W bit.WRITE OPERATIONBYTE WRITEIn the Byte Write mode, the Master device sends the START condition and the slave address information(with the R/W set to Zero) to the Slave device. After the Slave generates an acknowledge, the Master sends the byte address that is to be written into the address pointer of the IS24CXX. After receiving another acknowledge from the Slave, the Master device transmits the data byte to be written into the address memory location. The IS24CXX acknowledges once more and the Master generates the STOP condition, at which time the device begins its internal programming cycle. While this internal cycle is in progress, the device will not respond to any request from the Master device.元器件交易网4Integrated Silicon Solution, Inc. — — 1-800-379-4774Rev.DIS24C01IS24C02IS24C04IS24C08 IS24C16ISSI®condition and the IS24CXX discontinues transmission. If 'n' is the last byte of the memory, then the data from location '0' will be transmitted. (Refer to Current Address Read Diagram.)RANDOM ADDRESS READSelective READ operations allow the Master device to select at random any memory location for a READ operation.The Master device first performs a 'dummy' write operation by sending the START condition, slave address and word address of the location it wishes to read. After the IS24CXX acknowledge the word address, the Master device resends the START condition and the slave address, this time with the R/W bit set to one. The IS24CXX then responds with its acknowledge and sends the data requested. The master device does not send an acknowledge but will generate a STOP condition. (Refer to Random Address Read Diagram.)SEQUENTIAL READSequential Reads can be initiated as either a Current Address Read or Random Address Read. After the IS24CXX sends initial byte sequence, the master device now responds with an ACKnowledge indicating it requires additional data from the IS24CXX. The IS24CXX continues to output data for each ACKnowledge received. The master device terminates the sequential READ operation by pulling SDA HIGH (no ACKnowledge) indicating the last data word to be read, followed by a STOP condition.The data output is sequential, with the data from address n followed by the data from address n+1, ... etc.The address counter increments by one automatically,allowing the entire memory contents to be serially read during sequential read operation. When the memory address boundary (127 for IS24C01; 255 for IS24C02; 511 for IS24C04; 1023 for IS24C08; 2047 for IS24C16) is reached,the address counter “rolls over” to address 0, and the IS24CXX continues to output data for each ACKnowledge received. (Refer to Sequential Read Operation Starting with a Random Address READ Diagram.)PAGE WRITEThe IS24CXX is capable of page-WRITE (8-byte for 24C01/02 and 16-byte for 24C04/08/16) operation. A page-WRITE is initiated in the same manner as a byte write, but instead of terminating the internal write cycle after the first data word is transferred, the master device can transmit up to N more bytes (N=7 for 24C01/02 and N=15 for 24C04/08/16). After the receipt of each data word, the IS24CXX responds immediately with an ACKnowledge on SDA line, and the three lower (24C01/24C02) or four lower (24C04/24C08/24C16) order data word address bits are internally incremented by one, while the higher order bits of the data word address remain constant. If the master device should transmit more than N+1 (N=7 for 24C01/02 and N=15 for 24C04/08/16) words, prior to issuing the STOP condition,the address counter will “roll over,” and the previously written data will be overwritten. Once all N+1 (N=7 for 24C01/02 and N=15 for 24C04/08/16) bytes are received and the STOP condition has been sent by the Master, the internal programming cycle begins. At this point, all received data is written to the IS24CXX in a single write cycle. All inputs are disabled until completion of the internal WRITE cycle.ACKNOWLEDGE POLLINGThe disabling of the inputs can be used to take advantage of the typical write cycle time. Once the stop condition is issued to indicate the end of the host's write operation, the IS24CXX initiates the internal write cycle. ACK polling can be initiated immediately. This involves issuing the start condition followed by the slave address for a write operation.If the IS24CXX is still busy with the write operation, no ACK will be returned. If the IS24CXX has completed the write operation, an ACK will be returned and the host can then proceed with the next read or write operation.READ OPERATIONREAD operations are initiated in the same manner as WRITE operations, except that the read/write bit of the slave address is set to “1”. There are three READ operation options: current address read, random address read and sequential read.CURRENT ADDRESS READThe IS24CXX contains an internal address counter which maintains the address of the last byte accessed, incremented by one. For example, if the previous operation is either a read or write operation addressed to the address location n,the internal address counter would increment to address location n+1. When the IS24CXX receives the Device Addressing Byte with a READ operation (read/write bit set to “1”), it will respond an ACKnowledge and transmit the 8-bit data word stored at address location n+1. The master will not acknowledge the transfer but does generate a STOP元器件交易网元器件交易网IS24C01IS24C02IS24C04IS24C08 IS24C16ISSI®TYPICAL SYSTEM BUS CONFIGURATIONSTART AND STOP CONDITIONS6Integrated Silicon Solution, Inc. — — 1-800-379-4774Rev.D元器件交易网IS24C01IS24C02IS24C04IS24C08 IS24C16ISSI®DATA VALIDITY PROTOCOL元器件交易网IS24C01IS24C02IS24C04IS24C08 IS24C16ISSI®PAGE WRITE8Integrated Silicon Solution, Inc. — — 1-800-379-4774Rev.D元器件交易网IS24C01IS24C02IS24C04IS24C08 IS24C16ISSI®SEQUENTIAL READ元器件交易网IS24C01IS24C02IS24C04IS24C08 IS24C16ISSI®ABSOLUTE MAXIMUM RATINGS(1)Symbol Parameter Value UnitV S Supply Voltage0.5 to +6.25VV P Voltage on Any Pin–0.5 to Vcc + 0.5VT BIAS Temperature Under Bias–40 to +85°CT STG Storage Temperature–65 to +150°CI OUT Output Current5mANotes:1.Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may causepermanent damage to the device. This is a stress rating only and functional operation of thedevice at these or any other conditions above those indicated in the operational sections ofthis specification is not implied. Exposure to absolute maximum rating conditions forextended periods may affect reliability.OPERATING RANGE(IS24C01-2, IS24C02-2, IS24C04-2 IS24C08-2, & IS24C16-2)Range Ambient Temperature V CCCommercial0°C to +70°C 1.8V to 5.5VIndustrial–40°C to +85°C 1.8V to 5.5VOPERATING RANGE(IS24C01-3, IS24C02-3, IS24C04-3, IS24C08-3, & IS24C16-3)Range Ambient Temperature V CCCommercial0°C to +70°C 2.5V to 5.5VIndustrial–40°C to +85°C 2.5V to 5.5VAutomotive–40°C to +125°C 2.7V to 5.5VNote: Automotive data is preliminary.OPERATING RANGE(IS24C01-5, IS24C02-5, IS24C04-5 IS24C08-5, & IS24C16-5)Range Ambient Temperature V CCAuromotive–40°C to +125°C 4.5V to 5.5VNote: Automotive data is preliminary.10Integrated Silicon Solution, Inc. — — 1-800-379-4774Rev.DDC ELECTRICAL CHARACTERISTICSSymbol Parameter Test Conditions Min.Max.Unit V OL1Output LOW Voltage V CC = 1.8V, I OL = 0.15 mA—0.2V V OL2Output LOW Voltage V CC = 2.5V, I OL = 1.0 mA—0.4V V IH Input HIGH Voltage V CC X 0.7V CC + 0.5V V IL Input LOW Voltage–1.0V CC X 0.3VI LI Input Leakage Current V IN = V CC max.—3µAI LO Output Leakage Current—3µA Notes: V IL min and V IH max are reference only and are not tested.POWER SUPPLY CHARACTERISTICSSymbol Parameter Test Conditions Min.Max.UnitI CC1Vcc Operating Current READ at 100 KHz (Vcc = 5V)— 1.0mAI CC2Vcc Operating Current WRITE at 100 KHz (Vcc = 5V)— 3.0mAI SB1Standby Current Vcc = 1.8V— 4.0µAI SB2Standby Current Vcc = 5.5V—8.0µACAPACITANCE(1,2)Symbol Parameter Conditions Max.UnitC IN Input Capacitance V IN = 0V6pFC OUT Output Capacitance V OUT = 0V8pFNotes:1.Tested initially and after any design or process changes that may affect these parameters.2.Test conditions: T A = 25°C, f = 1 MHz, Vcc = 5.0V.12Integrated Silicon Solution, Inc. — — 1-800-379-4774Rev.D AC ELECTRICAL CHARACTERISTICS (Over Operating Range)Automotive (T A = –40°C to +125°C) 2.7V-5.5V 4.5V-5.5V Symbol Parameter Test ConditionsMin.Max.Min.Max.Unit f SCL SCL Clock Frequency 01000400KHz T Noise Suppression Time (1)—100—50ns t LOW Clock LOW Period 4.7— 1.2—µs t HIGH Clock HIGH Period4—0.6—µs t BUF Bus Free Time Before New Transmission 4.7— 1.2—µs t SU:STA Start Condition Setup Time 4.7—0.6—µs t SU:STO Stop Condition Setup Time 4.7—0.6—µs t HD:STA Start Condition Hold Time 4—0.6—µs t HD:STO Stop Condition Hold Time 4—0.6—µs t SU:DAT Data In Setup Time 200—100—ns t HD:DAT Data In Hold Time 0—0—ns t DH Data Out Hold Time SCL LOW to SDA Data Out Change 100—50—ns t AA Clock to Output SCL LOW to SDA Data Out Valid0.1 4.50.10.9µs t R SCL and SDA Rise Time(1)—1000—300ns t F SCL and SDA Fall Time (1)—300—300ns t WRWrite Cycle Time—10—10msNote:1. This parameter is characterized but not 100% tested.2. Automotive data is preliminary.AC ELECTRICAL CHARACTERISTICS (Over Operating Rnage)Commercial (T A = 0°C to +70°C) Industrial (T A = –40°C to +85°C) 1.8V-5.5V 2.5V-5.5V Symbol Parameter Test ConditionsMin.Max.Min.Max.Unit f SCL SCL Clock Frequency 01000400KHz T Noise Suppression Time (1)—100—50ns t LOW Clock LOW Period 4.7— 1.2—µs t HIGH Clock HIGH Period4—0.6—µs t BUF Bus Free Time Before New Transmission (1) 4.7— 1.2—µs t SU:STA Start Condition Setup Time 4.7—0.6—µs t SU:STO Stop Condition Setup Time 4.7—0.6—µs t HD:STA Start Condition Hold Time 4—0.6—µs t HD:STO Stop Condition Hold Time 4—0.6—µs t SU:DAT Data In Setup Time 200—100—ns t HD:DAT Data In Hold Time 0—0—ns t DH Data Out Hold Time SCL LOW to SDA Data Out Change 100—50—ns t AA Clock to Output SCL LOW to SDA Data Out Valid 0.1 4.50.10.9µs t R SCL and SDA Rise Time (1)—1000—300ns t F SCL and SDA Fall Time (1)—300—300ns t WRWrite Cycle Time—10—5msNote:1. This parameter is characterized but not 100% tested.AC WAVEFORMS BUS TIMINGWRITE CYCLE TIMINGORDERING INFORMATIONCommercial Range: 0°C to +70°CVol tageFrequency Range Part Number Package100 KHz 1.8V IS24C01-2P300-mil Plastic DIPto 5.5V IS24C01-2G Small Outline (JEDEC STD)IS24C01-2S MSOPIS24C01-2Z TSSOP100 KHz 1.8V IS24C02-2P300-mil Plastic DIPto 5.5V IS24C02-2G Small Outline (JEDEC STD)IS24C02-2S MSOPIS24C02-2Z TSSOP100 KHz 1.8V IS24C04-2P300-mil Plastic DIPto 5.5V IS24C04-2G Small Outline (JEDEC STD)IS24C04-2Z TSSOP100 KHz 1.8V IS24C08-2P300-mil Plastic DIPto 5.5V IS24C08-2G Small Outline (JEDEC STD)IS24C08-2Z TSSOP100 KHz 1.8V IS24C16-2P300-mil Plastic DIPto 5.5V IS24C16-2G Small Outline (JEDEC STD)400 KHz 2.5V IS24C01-3P300-mil Plastic DIPto 5.5V IS24C01-3G Small Outline (JEDEC STD)IS24C01-3S MSOPIS24C01-3Z TSSOP400 KHz 2.5V IS24C02-3P300-mil Plastic DIPto 5.5V IS24C02-3G Small Outline (JEDEC STD)IS24C02-3S MSOPIS24C02-3Z TSSOP400 KHz 2.5V IS24C04-3P300-mil Plastic DIPto 5.5V IS24C04-3G Small Outline (JEDEC STD)IS24C04-3Z TSSOP400 KHz 2.5V IS24C08-3P300-mil Plastic DIPto 5.5V IS24C08-3G Small Outline (JEDEC STD)IS24C08-3Z TSSOP400 KHz 2.5V IS24C16-3P300-mil Plastic DIPto 5.5V IS24C16-3G Small Outline (JEDEC STD)14Integrated Silicon Solution, Inc. — — 1-800-379-4774Rev.DORDERING INFORMATIONIndustrial Range: –40°C to +85°CVoltageFrequency Range Part Number Package100 KHz 1.8V IS24C01-2PI300-mil Plastic DIPto 5.5V IS24C01-2GI Small Outline (JEDEC STD)IS24C01-2SI MSOPIS24C01-2ZI TSSOP100 KHz 1.8V IS24C02-2PI300-mil Plastic DIPto 5.5V IS24C02-2GI Small Outline (JEDEC STD)IS24C02-2SI MSOPIS24C02-2ZI TSSOP100 KHz 1.8V IS24C04-2PI300-mil Plastic DIPto 5.5V IS24C04-2GI Small Outline (JEDEC STD)IS24C04-2ZI TSSOP100 KHz 1.8V IS24C08-2PI300-mil Plastic DIPto 5.5V IS24C08-2GI Small Outline (JEDEC STD)IS24C08-2ZI TSSOP100 KHz 1.8V IS24C16-2PI300-mil Plastic DIPto 5.5V IS24C16-2GI Small Outline (JEDEC STD) 400 KHz 2.5V IS24C01-3PI300-mil Plastic DIPto 5.5V IS24C01-3GI Small Outline (JEDEC STD)IS24C01-3SI MSOPIS24C01-3ZI TSSOP400 KHz 2.5V IS24C02-3PI300-mil Plastic DIPto 5.5V IS24C02-3GI Small Outline (JEDEC STD)IS24C02-3SI MSOPIS24C02-3ZI TSSOP400 KHz 2.5V IS24C04-3PI300-mil Plastic DIPto 5.5V IS24C04-3GI Small Outline (JEDEC STD)IS24C04-3ZI TSSOP400 KHz 2.5V IS24C08-3PI300-mil Plastic DIPto 5.5V IS24C08-3GI Small Outline (JEDEC STD)IS24C08-3ZI TSSOP400 KHz 2.5V IS24C16-3PI300-mil Plastic DIPto 5.5V IS24C16-3GI Small Outline (JEDEC STD)ORDERING INFORMATIONAutomotive Range: –40°C to +125°CVoltageFrequency Range Part Number Package100 KHz 2.7V IS24C01-3PA300-mil Plastic DIPto 5.5V IS24C01-3GA Small Outline (JEDEC STD)IS24C01-3SA MSOPIS24C01-3ZA TSSOP100 KHz 2.7V IS24C02-3PA300-mil Plastic DIPto 5.5V IS24C02-3GA Small Outline (JEDEC STD)IS24C02-3SA MSOPIS24C02-3ZA TSSOP100 KHz 2.7V IS24C04-3PA300-mil Plastic DIPto 5.5V IS24C04-3GA Small Outline (JEDEC STD)IS24C04-3ZA TSSOP100 KHz 2.7V IS24C08-3PA300-mil Plastic DIPto 5.5V IS24C08-3GA Small Outline (JEDEC STD)IS24C08-3ZA TSSOP100 KHz 2.7V IS24C16-3PA300-mil Plastic DIPto 5.5V IS24C16-3GA Small Outline (JEDEC STD)400 KHz 4.5V IS24C01-5PA300-mil Plastic DIPto 5.5V IS24C01-5GA Small Outline (JEDEC STD)IS24C01-5SA MSOPIS24C01-5ZA TSSOP400 KHz 4.5V IS24C02-5PA300-mil Plastic DIPto 5.5V IS24C02-5GA Small Outline (JEDEC STD)IS24C02-5SA MSOPIS24C02-5ZA TSSOP400 KHz 4.5V IS24C04-5PA300-mil Plastic DIPto 5.5V IS24C04-5GA Small Outline (JEDEC STD)IS24C04-5ZA TSSOP400 KHz 4.5V IS24C08-5PA300-mil Plastic DIPto 5.5V IS24C08-5GA Small Outline (JEDEC STD)IS24C08-5ZA TSSOP400 KHz 4.5V IS24C16-5PA300-mil Plastic DIPto 5.5V IS24C16-5GA Small Outline (JEDEC STD)Note: Automotive data is preliminary.16Integrated Silicon Solution, Inc. — — 1-800-379-4774Rev.D。

24C0224C04中文资料

ቤተ መጻሕፍቲ ባይዱ
概述
CAT24WC01/02/04/08/16 是一个 1K/2K/4K/8K/16K 位串行 CMOS E2PROM
128/256/512/1024/2048 个 8 位字节 CATALYST 公司的先进 CMOS 技术实质上减少了器件的功耗 CAT24WC01 有一个 8 字节页写缓冲器 CAT24WC02/04/08/16 有一个 16 字节页写缓冲器该器件通过 I2C 总线接口进行操作有一个专门的写保护功能
目录
1 CSI24WC0 1/02/04/08/16 ……………………………….2-10 2 CSI24WC32/64…………………………………………...11-18 3 CSI24WC128. ……………………………..…………….19-26 4 CSI24WC256. ………………………….….…………….27-34
6
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1 个 CAT24WC16 可单独被系统寻址从器件 8 位地址的最低位作为读写控制位进行读操作 0 表示对从器件进行写操作
1 表示对从器件
图2
写周期时序
w
图3 起始/停止时序
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s u mc
n c . y
器件寻址
主器件通过发送一个起始信号启动发送过程然后发送它所要寻址的从器件的地址 8 位从器件地址的高 4 位固定为 1010 见图 5 接下来的 3 位 A2 A1 A0 为器件的地址位用来定义哪个器件以及器件的哪个部分被主器件访问上述 8 个 CAT24WC01/02 4 个 CAT24WC04 2 个 CAT24WC08

24C01en 芯片说明

Features•Low Voltage and Standard Voltage Operation–5.0 (V CC = 4.5V to 5.5V)–2.7 (V CC = 2.7V to 5.5V)–2.5 (V CC = 2.5V to 5.5V)–1.8 (V CC = 1.8V to 5.5V)•Internally Organized 128 x 8•2-Wire Serial Interface•Bidirectional Data Transfer Protocol•100 kHz (1.8V , 2.5V , 2.7V) and 400 kHz (5V) Compatibility •4-Byte Page Write Mode•Self-Timed Write Cycle (10 ms max)•High Reliability–Endurance: 1 Million Write Cycles –Data Retention: 100 Years –ESD Protection: >3000V•Automotive Grade and Extended Temperature Devices Available•8-Pin PDIP , 8-Pin MSOP , 8-Pin TSSOP and 8-Pin JEDEC SOIC PackagesDescriptionThe AT24C01 provides 1024 bits of serial electrically erasable and programmable read only memory (EEPROM) organized as 128 words of 8 bits each. The device is optimized for use in many industrial and commercial applications where low power and low voltage operation are essential. The AT24C01 is available in space saving 8-pin PDIP, 8-pin MSOP, 8-pin TSSOP, and 8-pin JEDEC SOIC packages and is accessed via a 2-wire serial interface. In addition, the entire family is available in 5.0V (4.5V to 5.5V), 2.7V (2.7V to 5.5V), 2.5V (2.5V to 5.5V) and 1.8V (1.8V to 5.5V) ver-sions.Pin ConfigurationsPin Name Function NC No Connect SDA Serial Data SCL Serial Clock Input T estT est Input (GND or V CC )8-Pin PDIP8-Pin SOIC 8-Pin MSOP 8-Pin TSSOPBlock DiagramPin DescriptionSERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device.SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and may be wire-ORed with any number of other open-drain or open collector devices.Memory OrganizationAT24C01, 1K SERIAL EEPROM: Internally organized with 128 pages of 1 byte each. The 1K requires a 7-bit data word address for random word addressing.Absolute Maximum Ratings*Operating T emperature..................................-55°C to +125°C *NOTICE:Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent dam-age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.Storage T emperature.....................................-65°C to +150°C Voltage on Any Pinwith Respect to Ground.....................................-1.0V to +7.0V Maximum Operating Voltage...........................................6.25V DC Output Current........................................................5.0 mAAT24C01Note:1.V IL min and V IH max are reference only and are not tested.Pin CapacitanceApplicable over recommended operating range from T A = 25°C, f = 1.0 MHz, V CC = +1.8V.Symbol Test ConditionMax Units Condition C I/O Input/Output Capacitance (SDA)8pF V I/O = 0V C INInput Capacitance (A0, A1, A2, SCL)6pFV IN = 0VDC CharacteristicsApplicable over recommended operating range from: T AI = -40°C to +85°C, V CC = +1.8V to +5.5V, T AC = 0°C to +70°C,V CC =+1.8V to +5.5V (unless otherwise noted).Symbol Parameter Test ConditionMin TypMax Units V CC1Supply Voltage 1.8 5.5V V CC2Supply Voltage 2.5 5.5V V CC3Supply Voltage 2.7 5.5V V CC4Supply Voltage4.55.5V I CC Supply Current V CC = 5.0V READ at 100 KHz 0.4 1.0mA I CC Supply Current V CC = 5.0V WRITE at 100 KHz 2.0 3.0mA I SB1Standby Current V CC = 1.8V V IN = V CC or V SS 0.6 3.0µA I SB2Standby Current V CC = 2.5V V IN = V CC or V SS 1.4 4.0µA I SB3Standby Current V CC = 2.7V V IN = V CC or V SS 1.6 4.0µA I SB4Standby Current V CC = 5.0V V IN = V CC or V SS 8.018.0µA I LI Input Leakage Current V IN = V CC or V SS 0.10 3.0µA I LO Output Leakage Current V OUT = V CC or V SS0.05 3.0µA V IL Input Low Level (1)-0.6V CC × 0.3V V IH Input High Level (1)V CC × 0.7V CC + 0.5V V OL2Output Low Level V CC = 3.0V I OL = 2.1 mA 0.4V V OL1Output Low Level V CC = 1.8VI OL = 0.15 mA 0.2V 电子发烧友电子技术论坛Note: 1.This parameter is characterized and is not 100% tested. Device OperationCLOCK and DATA TRANSITIONS: The SDA pin is nor-mally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods (refer to Data Validity timing diagram). Data changes during SCL high periods will indicate a start or stop condition as defined below.START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (refer to Start and Stop Definition timing dia-gram).STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition which terminates all communi-cations. After a read sequence, the stop command will place the EEPROM in a standby power mode (refer to Start and Stop Definition timing diagram). ACKNOWLEDGE: All addresses and data words are seri-ally transmitted to and from the EEPROM in 8-bit words. Any device on the system bus receiving data (when com-municating with the EEPROM) must pull the SDA bus low to acknowledge that it has successfully received each word. This must happen during the ninth clock cycle after each word received and after all other system devices have freed the SDA bus. The EEPROM will likewise acknowl-edge by pulling SDA low after receiving each address or data word (refer to Acknowledge Response from Receiver timing diagram).STANDBY MODE: The AT24C01 features a low power standby mode which is enabled: (a) upon power-up and (b) after the receipt of the STOP bit and the completion of any internal operations.MEMORY RESET: After an interruption in protocol, power loss or system reset, any 2-wire part can be reset by follow-ing these steps:(a) Clock up to 9 cycles, (b) look for SDA high in each cycle while SCL is high and then (c) create a start condition as SDA is high.AC CharacteristicsApplicable over recommended operating range from T A = -40°C to +85°C, V CC = +1.8V to +5.5V, CL = 1 TTL Gate and 100pF (unless otherwise noted).Symbol Parameter 2.7-, 2.5-, 1.8-volt 5.0-voltUnits Min Max Min Maxf SCL Clock Frequency, SCL100400KHz t LOW Clock Pulse Width Low 4.7 1.2µs t HIGH Clock Pulse Width High 4.00.6µs t I Noise Suppression Time(1)10050ns t AA Clock Low to Data Out Valid0.1 4.50.10.9µs t BUF Time the bus must be free before a newtransmission can start(1)4.7 1.2µs t HD.ST A Start Hold Time 4.00.6µs t SU.ST A Start Set-up Time 4.70.6µs t HD.DA T Data In Hold Time00µs t SU.DA T Data In Set-up Time200100ns t R Inputs Rise Time(1) 1.00.3µs t F Inputs Fall Time(1)300300ns t SU.STO Stop Set-up Time 4.70.6µs t DH Data Out Hold Time10050ns t WR Write Cycle Time1010msEndurance(1) 5.0V, 25°C, Page Mode1M1MWrite Cycles 电子发烧友电子技术论坛AT24C01Bus TimingSCL: Serial Clock, SDA: Serial Data I/OWrite Cycle TimingSCL: Serial Clock, SDA: Serial Data I/ONote: 1.The write cycle time t WR is the time from a valid stop condition of a write sequence to the end of the internal clear/writecycle. 电子发烧友电子技术论坛Data ValidityStart and Stop DefinitionOutput Acknowledge 电子发烧友电子技术论坛AT24C01Write OperationsBYTE WRITE: Following a start condition, a write operation requires a 7-bit data word address and a low write bit. Upon receipt of this address, the EEPROM will again respond with a zero and then clock in the first 8-bit data word. Fol-lowing receipt of the 8-bit data word, the EEPROM will out-put a zero and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condition. At this time the EEPROM enters an inter-nally-timed write cycle to the nonvolatile memory. All inputs are disabled during this write cycle , t WR , and the EEPROM will not respond until the write is complete (refer to Figure 1).PAGE WRITE: The AT24C01 is capable of a 4-byte page write.A page write is initiated the same as a byte write but the microcontroller does not send a stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcon-troller can transmit up to three more data words. The EEPROM will respond with a zero after each data word received. The microcontroller must terminate the page write sequence with a stop condition (refer to Figure 2).The data word address lower 2 bits are internally incre-mented following the receipt of each data word. The higher five data word address bits are not incremented, retaining the memory page row location. When the word address,internally generated, reaches the page boundary, the fol-lowing byte is placed at the beginning of the same page. If more than four data words are transmitted to the EEPROM,the data word address will “roll over” and previous data will be overwritten.ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and the EEPROM inputs are dis-abled, acknowledge polling can be initiated. This involves sending a start condition followed by the device address word. The read/write bit is representative of the operation desired. Only if the internal write cycle has completed will the EEPROM respond with a zero allowing the read or write sequence to continue.Read OperationsRead operations are initiated the same way as write opera-tions with the exception that the read/write select bit in the device address word is set to one. There are two read operations: byte read and sequential read.BYTE READ: A byte read is initiated with a start condition followed by a 7-bit data word address and a high read bit.The AT24C01 will respond with an acknowledge and then serially output 8 data bits. The microcontroller does not respond with a zero but does generate a following stop condition (refer to Figure 3).SEQUENTIAL READ: Sequential reads are initiated the same as a byte read. After the microcontroller receives an 8-bit data word, it responds with an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. When the memory address limit is reached, the data word address will “roll over” and the sequential read will continue. The sequential read opera-tion is terminated when the microcontroller does not respond with an input zero but does generate a following stop condition (refer to Figure 4).Figure 1.Byte Write 电子发烧友电子技术论坛Figure 2. Page WriteFigure 3. Byte ReadFigure 4.Sequential Read 电子发烧友电子技术论坛AT24C01 Ordering Informationt WR (max)(ms)I CC (max)(µA)I SB (max)(µA)f MAX(kHz)Ordering Code Package Operation Range10300018400A T24C01-10PCA T24C01-10SCA T24C01-10MCA T24C01-10TC 8P38S18M8TCommercial(0°C to 70°C)300018400A T24C01-10PIA T24C01-10SIA T24C01-10MIA T24C01-10TI 8P38S18M8TIndustrial(-40°C to 85°C)1015004100A T24C01-10PC-2.7A T24C01-10SC-2.7A T24C01-10MC-2.7A T24C01-10TC-2.78P38S18M8TCommercial(0°C to 70°C)15004100A T24C01-10PI-2.7A T24C01-10SI-2.7A T24C01-10MI-2.7A T24C01-10TI-2.78P38S18M8TIndustrial(-40°C to 85°C)1010004100A T24C01-10PC-2.5A T24C01-10SC-2.5A T24C01-10MC-2.5A T24C01-10TC-2.58P38S18M8TCommercial(0°C to 70°C)10004100A T24C01-10PI-2.5A T24C01-10SI-2.5A T24C01-10MI-2.5A T24C01-10TI-2.58P38S18M8TIndustrial(-40°C to 85°C)108003100A T24C01-10PC-1.8A T24C01-10SC-1.8A T24C01-10MC-1.8A T24C01-10TC-1.88P38S18M8TCommercial(0°C to 70°C)8003100A T24C01-10PI-1.8A T24C01-10SI-1.8A T24C01-10MI-1.8A T24C01-10TI-1.88P38S18M8TIndustrial(-40°C to 85°C)Package Type8M8-Lead, 0.118” Wide, Miniature Small Outline Package (MSOP)8P38-Lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)8S18-Lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)8T8-Lead, 0.170” Wide, Thin Shrink Small Outline Package (TSSOP)OptionsBlank Standard Operation (4.5V to 5.5V)-2.7Low-Voltage (2.7V to 5.5V)-2.5Low-Voltage (2.5V to 5.5V)-1.8Low-Voltage (1.8V to 5.5V) 电子发烧友电子技术论坛电子发烧友电子技术论坛Packaging Information 电子发烧友电子技术论坛This datasheet has been downloaded from:Datasheets for electronic components.。

S24CS01A_02A_04A_08A_C

1 2 3 4
8 7 6 5
VCC WP SCL SDA
1 2 3 4 5 6 7 8 *1.
备注
图4 S-24CS01APH-TF-G S-24CS02APH-TF-G S-24CS04APH-TF-G
有关形状请参阅「外形尺寸图」。
精工电子有限公司
3
CMOS 2线串行E2PROM
S-24CS01A/02A/04A/08A ■ 框图
地址输入 (但是S-24CS04A/08A为无连接*1) 地址输入 2 A1 (但是S-24CS08A为无连接*1) 地址输入 3 A2 接地 4 GND 串行数据输入输出 5 SDA 串行时钟输入 6 SCL 写入保护输入 VCC连接 : 保护有效 7 WP GND连接 : 保护无效电源 8 VCC *1. 在使用的时候，请与GND或VCC相连接。 1 备注有关形状请参阅「外形尺寸图」。
*1. 在S-24CS08A产品中没有。 *2. 在S-24CS04A/08A产品中没有。图5
4
精工电子有限公司
CMOS 2线串行E2PROM
Rev.4.4_00 ■ 绝对最大额定值
表5
S-24CS01A/02A/04A/08A
额定值单位 V −0.3 ~ +7.0 电源电压 VCC V −0.3 ~ VCC+0.3 输入电压 VIN V −0.3 ~ VCC 输出电压 VOUT °C −40 ~ +105 工作环境温度 Topr °C −65 ~ +150 保存温度 Tstg 注意绝对最大额定值是指无论在任何条件下都不能超过的额定值。万一超过此额定值，有可能造成产品劣化等物理性损伤。
2
精工电子有限公司
CMOS 2线串行E2PROM

M24C04-W1BN6T中文资料

1/25October 2005M24C16, M24C08M24C04, M24C02, M24C0116Kbit, 8Kbit, 4Kbit, 2Kbit and 1Kbit Serial I²C Bus EEPROMFEATURES SUMMARY■Two-Wire I²C Serial Interface Supports 400kHz Protocol ■Single Supply Voltage:– 2.5 to 5.5V for M24Cxx-W – 1.8 to 5.5V for M24Cxx-R ■Write Control Input■BYTE and PAGE WRITE (up to 16 Bytes)■RANDOM and SEQUENTIAL READ Modes ■Self-Timed Programming Cycle ■Automatic Address Incrementing ■Enhanced ESD/Latch-Up Protection ■More than 1 Million Erase/Write Cycles ■More than 40-Year Data Retention ■Packages–ECOPACK® (RoHS compliant)Table 1. Product ListReference Part NumberM24C16M24C16-W M24C16-R M24C08M24C08-W M24C08-R M24C04M24C04-W M24C04-R M24C02M24C02-W M24C02-R M24C01M24C01-W M24C01-RM24C16, M24C08, M24C04, M24C02, M24C01TABLE OF CONTENTSFEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Device internal reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Serial Clock (SCL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Chip Enable (E0, E1, E2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Write Control (WC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4DEVICE OPERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6Start Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Stop Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Acknowledge Bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Data Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Memory Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Byte Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Minimizing System Delays by Polling On ACK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Random Address Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Sequential Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Acknowledge in Read Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11INITIAL DELIVERY STATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .242/253/25M24C16, M24C08, M24C04, M24C02, M24C01SUMMARY DESCRIPTIONThese I²C-compatible electrically erasable pro-grammable memory (EEPROM) devices are orga-nized as 2048/1024/512/256/128x 8 (M24C16,M24C08, M24C04, M24C02 and M24C01).In order to meet environmental requirements, ST offers these devices in ECOPACK® packages.ECOPACK® packages are Lead-free and RoHS compliant.ECOPACK is an ST trademark. ECOPACK speci-fications are available at: .I²C uses a two-wire serial interface, comprising a bi-directional data line and a clock line. The devic-es carry a built-in 4-bit Device Type Identifier code (1010) in accordance with the I²C bus definition.The device behaves as a slave in the I²C protocol,with all memory operations synchronized by the serial clock. Read and Write operations are initiat-ed by a Start condition, generated by the bus mas-ter. The Start condition is followed by a Device scribed in Table 3.), terminated by an acknowl-edge bit.When writing data to the memory, the device in-serts an acknowledge bit during the 9th bit time,following the bus master’s 8-bit transmission.When data is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. Data transfers are terminated by a Stop condition after an Ack for Write, and after a NoAck for Read.Table 2. Signal NamesDevice internal resetIn order to prevent inadvertent Write operations during Power-up, a Power On Reset (POR) circuit is included. At Power-up (continuous rise of V CC ),the device will not respond to any instructions until the V CC has reached the Power On Reset threshold voltage (this threshold is lower than the V CC min. operating voltage defined in DC and AC PARAMETERS ). When V CC has passed over the POR threshold, the device is reset and is in Standby Power mode. At Power-down (continuous decay of V CC ), as soon as V CC drops from the normal operating voltage to below the Power On Reset threshold voltage, the device stops responding to any instruction sent to it.Prior to selecting and issuing instructions to the memory, a valid and stable V CC voltage must be applied. This voltage must remain stable and valid until the end of the transmission of the instruction and, for a Write instruction, until the completion of the internal write cycle (t W ).Note: 1.NC = Not Connected2.See PACKAGE MECHANICAL section for package dimensions, and how to identify pin-1.E0, E1, E2Chip Enable SDA Serial Data SCL Serial Clock WCWrite Control V CC Supply Voltage V SSGroundM24C16, M24C08, M24C04, M24C02, M24C014/25SIGNAL DESCRIPTIONSerial Clock (SCL).This input signal is used to strobe all data in and out of the device. In applica-tions where this signal is used by slave devices to synchronize the bus to a slower clock, the bus master must have an open drain output, and a pull-up resistor can be connected from Serial Clock (SCL) to V CC . (Figure 5. indicates how the value of the pull-up resistor can be calculated). In most applications, though, this method of synchro-nization is not employed, and so the pull-up resis-tor is not necessary, provided that the bus master has a push-pull (rather than open drain) output.Serial Data (SDA).This bi-directional signal is used to transfer data in or out of the device. It is an open drain output that may be wire-OR’ed with other open drain or open collector signals on the bus. A pull up resistor must be connected from Se-rial Data (SDA) to V CC . (Figure 5. indicates how the value of the pull-up resistor can be calculated).Chip Enable (E0, E1, E2).These input signals are used to set the value that is to be looked for on the three least significant bits (b3, b2, b1) of the 7-bit Device Select Code. These inputs must be tied to V CC or V SS , to establish the Device Select Code as shown in Figure 4.for protecting the entire contents of the memory from inadvertent write operations. Write opera-tions are disabled to the entire memory array when nected, the signal is internally read as V IL , and Write operations are allowed.Select and Address bytes are acknowledged,Data bytes are not acknowledged.M24C16, M24C08, M24C04, M24C02, M24C01Table 3. Device Select CodeDevice Type Identifier1Chip Enable2,3RWb7b6b5b4b3b2b1b0M24C01 Select Code1010E2E1E0RWM24C02 Select Code1010E2E1E0RWM24C04 Select Code1010E2E1A8RWM24C08 Select Code1010E2A9A8RWM24C16 Select Code1010A10A9A8RW Note: 1.The most significant bit, b7, is sent first.2.E0, E1 and E2 are compared against the respective external pins on the memory device.3.A10, A9 and A8 represent most significant bits of the address.5/25M24C16, M24C08, M24C04, M24C02, M24C016/25DEVICE OPERATIONThe device supports the I²C protocol. This is sum-marized in Figure 6.. Any device that sends data on to the bus is defined to be a transmitter, and any device that reads the data to be a receiver.The device that controls the data transfer is known as the bus master, and the other as the slave de-vice. A data transfer can only be initiated by the bus master, which will also provide the serial clock for synchronization. The M24Cxx device is always a slave in all communication.Start ConditionStart is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in the High state. A Start condition must precede any data transfer command. The device continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock (SCL) for a Start condition,and will not respond unless one is given.Stop ConditionStop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable and driv-en High. A Stop condition terminates communica-tion between the device and the bus master. A Read command that is followed by NoAck can be followed by a Stop condition to force the device into the Stand-by mode. A Stop condition at the end of a Write command triggers the internal Write cycle.Acknowledge Bit (ACK)The acknowledge bit is used to indicate a success-ful byte transfer. The bus transmitter, whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits of data. During the 9th clock pulse period, the receiver pulls Serial Data (SDA) Low to acknowledge the receipt of the eight data bits.Data InputDuring data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock (SCL).For correct device operation, Serial Data (SDA)must be stable during the rising edge of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock (SCL) is driv-en Low.Memory AddressingTo start communication between the bus master and the slave device, the bus master must initiate a Start condition. Following this, the bus master sends the Device Select Code, shown in Table 3.(on Serial Data (SDA), most significant bit first).The Device Select Code consists of a 4-bit Device Type Identifier, and a 3-bit Chip Enable “Address”(E2, E1, E0). To address the memory array, the 4-bit Device Type Identifier is 1010b.Each device is given a unique 3-bit code on the Chip Enable (E0, E1, E2) inputs. When the Device Select Code is received, the device only responds if the Chip Enable Address is the same as the val-ue on the Chip Enable (E0, E1, E2) inputs. How-ever, those devices with larger memory capacities (the M24C16, M24C08 and M24C04) need more address bits. E0 is not available for use on devices that need to use address line A8; E1 is not avail-able for devices that need to use address line A9,and E2 is not available for devices that need to use address line A10 (see Figure 3. and Table 3. for details). Using the E0, E1 and E2 inputs, up to eight M24C02 (or M24C01), four M24C04, two M24C08 or one M24C16 devices can be connect-ed to one I²C bus. In each case, and in the hybrid cases, this gives a total memory capacity of 16Kbits, 2KBytes (except where M24C01 devic-es are used).The 8th set to 1 for Read and 0 for Write operations.If a match occurs on the Device Select code, the corresponding device gives an acknowledgment on Serial Data (SDA) during the 9th bit time. If the device does not match the Device Select code, it deselects itself from the bus, and goes into Stand-by mode.Table 4. Operating ModesNote: 1.X = V IH or V IL .ModeRW bit WC 1Bytes Initial SequenceCurrent Address Read 1X 1START , Device Select, RW = 1Random Address Read 0X 1START , Device Select, RW = 0, Address 1X reST ART, Device Select, RW = 1Sequential Read 1X ≥ 1Similar to Current or Random Address Read Byte Write 0V IL 1START , Device Select, RW = 0Page WriteV IL≤ 16START , Device Select, RW = 0M24C16, M24C08, M24C04, M24C02, M24C01Figure 7. Write Mode Sequences with WC=1 (data write inhibited)Following a Start condition the bus master sends a Device Select Code with the Read/Write bit (RW) reset to 0. The device acknowledges this, as shown in Figure 8., and waits for an address byte. The device responds to the address byte with an acknowledge bit, and then waits for the data byte. When the bus master generates a Stop condition immediately after the Ack bit (in the “10th bit” time slot), either at the end of a Byte Write or a Page Write, the internal Write cycle is triggered. A Stop condition at any other time slot does not trigger the internal Write cycle.During the internal Write cycle, Serial Data (SDA) and Serial Clock (SCL) are ignored, and the de-vice does not respond to any requests.Byte WriteAfter the Device Select code and the address byte, the bus master sends one data byte. If the ad-dressed location is Write-protected, by Write Con-trol (WC) being driven High (during the period from byte), the device replies to the data byte with NoAck, as shown in Figure 7., and the location is not modified. If, instead, the addressed location is not Write-protected, the device replies with Ack. The bus master terminates the transfer by gener-ating a Stop condition, as shown in Figure 8.. Page WriteThe Page Write mode allows up to 16 bytes to be written in a single Write cycle, provided that they are all located in the same page in the memory: that is, the most significant memory address bits are the same. If more bytes are sent than will fit up to the end of the page, a condition known as ‘roll-over’ occurs. This should be avoided, as data starts to become overwritten in an implementation dependent way.The bus master sends from 1 to 16 bytes of data, each of which is acknowledged by the device if Write Control (WC) is Low. If the addressed loca-ing driven High (during the period from the Start7/25M24C16, M24C08, M24C04, M24C02, M24C018/25condition until the end of the address byte), the de-vice replies to the data bytes with NoAck, as shown in Figure 7., and the locations are not mod-ified. After each byte is transferred, the internalbyte address counter (the 4 least significant ad-dress bits only) is incremented. The transfer is ter-minated by the bus master generating a Stop condition.M24C16, M24C08, M24C04, M24C02, M24C01During the internal Write cycle, the device discon-nects itself from the bus, and writes a copy of the data from its internal latches to the memory cells. The maximum Write time (t w) is shown in Table 13. and Table 14., but the typical time is shorter. To make use of this, a polling sequence can be used by the bus master.The sequence, as shown in Figure 9., is:–Step 1: the bus master issues a Start condition followed by a Device Select Code (the firstbyte of the new instruction).–Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and thebus master goes back to Step 1. If the device has terminated the internal Write cycle, itresponds with an Ack, indicating that thedevice is ready to receive the second part of the instruction (the first byte of this instruction having been sent during Step 1).9/25M24C16, M24C08, M24C04, M24C02, M24C0110/25Read OperationsRead operations are performed independently of The device has an internal address counter which is incremented each time a byte is read.Random Address ReadA dummy Write is first performed to load the ad-dress into this address counter (as shown in Fig-ure 10.) but without sending a Stop condition.Then, the bus master sends another Start condi-tion, and repeats the Device Select Code, with the Read/Write bit (RW) set to 1. The device acknowl-edges this, and outputs the contents of the ad-dressed byte. The bus master must not acknowledge the byte, and terminates the transfer with a Stop condition.Current Address ReadFor the Current Address Read operation, following a Start condition, the bus master only sends a De-to 1. The device acknowledges this, and outputs the byte addressed by the internal address counter. The counter is then incremented. The bus master terminates the transfer with a Stop condi-tion, as shown in Figure 10., without acknowledg-ing the byte.Sequential ReadThis operation can be used after a Current Ad-dress Read or a Random Address Read. The bus master does acknowledge the data byte output, and sends additional clock pulses so that the de-vice continues to output the next byte in sequence. To terminate the stream of bytes, the bus master must not acknowledge the last byte, and must generate a Stop condition, as shown in Figure 10.. The output data comes from consecutive address-es, with the internal address counter automatically incremented after each byte output. After the last memory address, the address counter ‘rolls-over’, and the device continues to output data from memory address 00h.Acknowledge in Read ModeFor all Read commands, the device waits, aftereach byte read, for an acknowledgment during the 9th bit time. If the bus master does not drive Serial Data (SDA) Low during this time, the device termi-nates the data transfer and switches to its Stand-by mode.INITIAL DELIVERY STATEThe device is delivered with all bits in the memory array set to 1 (each byte contains FFh).11/2512/25MAXIMUM RATINGStressing the device outside the ratings listed in Table 5. may cause permanent damage to the de-vice. These are stress ratings only, and operation of the device at these, or any other conditions out-side those indicated in the Operating sections of this specification, is not implied. Exposure to Ab-solute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.Table 5. Absolute Maximum RatingsNote: pliant with JEDEC Std J-STD-020C (for small body, Sn-Pb or Pb assembly), the ST ECOPACK ® 7191395 specification, andthe European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU2.AEC-Q100-002 (compliant with JEDEC Std JESD22-A114A, C1=100pF, R1=1500Ω, R2=500Ω)Symbol ParameterMin.Max.Unit T A Ambient Operating Temperature –40125°C T STG Storage Temperature–65150°C T LEAD Lead T emperature during Soldering 1°C V IO Input or Output range –0.50 6.5V V CC Supply Voltage–0.50 6.5V V ESDElectrostatic Discharge Voltage (Human Body model) 2–40004000V13/25DC AND AC PARAMETERSThis section summarizes the operating and mea-surement conditions, and the DC and AC charac-teristics of the device. The parameters in the DC and AC Characteristic tables that follow are de-rived from tests performed under the Measure-ment Conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parame-ters.Table 6. Operating Conditions (M24Cxx-W)Table 7. Operating Conditions (M24Cxx-R)Table 8. DC Characteristics (M24Cxx-W, Device Grade 6)Note: 1.The voltage source driving only E0, E1 and E2 inputs must provide an impedance of less than 1kOhm.Symbol ParameterMin.Max.Unit V CC Supply Voltage2.5 5.5V T AAmbient Operating T emperature (Device Grade 6)–4085°C Ambient Operating T emperature (Device Grade 3)–40125°CSymbol ParameterMin.Max.Unit V CC Supply Voltage1.8 5.5V T AAmbient Operating T emperature–4085°CSymbol ParameterTest Condition(in addition to those in Table 6.)Min.Max.Unit I LI Input Leakage Current(SCL, SDA, E0, E1,and E2)V IN = V SS or V CC± 2µA I LO Output Leakage Current V OUT = V SS or V CC, SDA in Hi-Z ± 2µA I CCSupply CurrentV CC =5V , f c =400kHz (rise/fall time < 30ns)2mA V CC =2.5V , f c =400kHz (rise/fall time < 30ns)1mA I CC1Stand-by Supply Current V IN = V SS or V CC , V CC = 5V 1µA V IN = V SS or V CC , V CC = 2.5V0.5µA V IL Input Low Voltage (1)–0.450.3V CC V V IH Input High Voltage (1)0.7V CCV CC +1V V OLOutput Low VoltageI OL = 2.1mA, V CC = 2.5V0.4V14/25Table 9. DC Characteristics (M24Cxx-W, Device Grade 3)Note: 1.The voltage source driving only E0, E1 and E2 inputs must provide an impedance of less than 1kOhm.Table 10. DC Characteristics (M24Cxx-R)Note: 1.The voltage source driving only E0, E1 and E2 inputs must provide an impedance of less than 1kOhm.Table 11. AC Measurement ConditionsSymbol ParameterTest Condition(in addition to those in Table 6.)Min.Max.Unit I LI Input Leakage Current(SCL, SDA, E0, E1,and E2)V IN = V SS or V CC± 2µA I LO Output Leakage Current V OUT = V SS or V CC, SDA in Hi-Z ± 2µA I CCSupply CurrentV CC =5V , f C =400kHz (rise/fall time < 30ns)3mA V CC =2.5V , f C =400kHz (rise/fall time < 30ns)3mA I CC1Stand-by Supply Current V IN = V SS or V CC , V CC = 5V 5µA V IN = V SS or V CC , V CC = 2.5V2µA V IL Input Low Voltage (1)–0.450.3V CC V V IH Input High Voltage (1)0.7V CCV CC +1V V OLOutput Low VoltageI OL = 2.1mA, V CC = 2.5V0.4VSymbol ParameterTest Condition(in addition to those in Table 7.)Min.Max.Unit I LI Input Leakage Current(SCL, SDA, E0, E1,and E2)V IN = V SS or V CC± 2µA I LO Output Leakage Current V OUT = V SS or V CC, SDA in Hi-Z ± 2µA I CC Supply CurrentV CC =1.8V , f c =400kHz (rise/fall time < 30ns)0.8mA I CC1Stand-by Supply Current V IN = V SS or V CC , V CC = 1.8V0.3µA V IL Input Low Voltage (1) 2.5V ≤ V CC –0.450.3V CC V 1.8V ≤ V CC < 2.5V–0.450.25V CC V V IH Input High Voltage (1)0.7V CC V CC +1V V OLOutput Low VoltageI OL = 0.7mA, V CC = 1.8V 0.2VSymbol ParameterMin.Max.Unit C LLoad Capacitance 100pF Input Rise and Fall Times 50ns Input Levels0.2V CC to 0.8V CC V Input and Output Timing Reference Levels0.3V CC to 0.7V CCV15/25Table 12. Input ParametersNote: 1.T A = 25°C, f = 400kHz2.Sampled only, not 100% tested.Symbol Parameter 1,2Test ConditionMin.Max.Unit C IN Input Capacitance (SDA)8pF C IN Input Capacitance (other pins)6pF Z WCL WC Input Impedance V IN < 0.3V 1570k ΩZ WCH WC Input Impedance V IN > 0.7V CC 500k Ωt NSPulse width ignored(Input Filter on SCL and SDA)Single glitch100nsTable 13. AC Characteristics (M24Cxx-W)Test conditions specified in Table 6. and Table 11.Symbol Alt.Parameter Min.Max.Unitf C f SCL Clock Frequency400kHzt CHCL t HIGH Clock Pulse Width High600ns t CLCH t LOW Clock Pulse Width Low1300nst DL1DL2 2t F SDA Fall Time20300ns t DXCX t SU:DAT Data In Set Up Time100ns t CLDX t HD:DA T Data In Hold Time0ns t CLQX t DH Data Out Hold Time200ns t CLQV 3t AA Clock Low to Next Data Valid (Access Time)200900ns t CHDX 1t SU:ST A Start Condition Set Up Time600ns t DLCL t HD:ST A Start Condition Hold Time600ns t CHDH t SU:STO Stop Condition Set Up Time600ns t DHDL t BUF Time between Stop Condition and Next Start Condition1300ns t W 4t WR Write Time5ms Note: 1.For a reSTART condition, or following a Write cycle.2.Sampled only, not 100% tested.3.To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.4.Previous devices bearing the process letter “L” in the package marking guarantee a maximum write time of 10ms. For more infor-mation about these devices and their device identification, please ask your ST Sales Office for Process Change Notices PCN MPG/ EE/0061 and 0062 (PCEE0061 and PCEE0062).Table 14. AC Characteristics (M24Cxx-R)Test conditions specified in Table 7. and Table 10.Symbol Alt.Parameter Min. 4Max. 4Unitf C f SCL Clock Frequency400kHzt CHCL t HIGH Clock Pulse Width High600ns t CLCH t LOW Clock Pulse Width Low1300nst DL1DL2 2t F SDA Fall Time20300ns t DXCX t SU:DAT Data In Set Up Time100ns t CLDX t HD:DA T Data In Hold Time0ns t CLQX t DH Data Out Hold Time200ns t CLQV 3t AA Clock Low to Next Data Valid (Access Time)200900ns t CHDX 1t SU:ST A Start Condition Set Up Time600ns t DLCL t HD:ST A Start Condition Hold Time600ns t CHDH t SU:STO Stop Condition Set Up Time600ns t DHDL t BUF Time between Stop Condition and Next Start Condition1300ns t W t WR Write Time10ms Note: 1.For a reSTART condition, or following a Write cycle.2.Sampled only, not 100% tested.3.To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.4.This is preliminary information.16/2517/25PACKAGE MECHANICALTable 15. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Mechanical DataSymb.mm inchesTyp.Min.Max.Typ.Min.Max.A 5.330.210A10.380.015A2 3.30 2.92 4.950.1300.1150.195 b0.460.360.560.0180.0140.022 b2 1.52 1.14 1.780.0600.0450.070 c0.250.200.360.0100.0080.014 D9.279.0210.160.3650.3550.400 E7.877.628.260.3100.3000.325 E1 6.35 6.107.110.2500.2400.280e 2.54––0.100––eA7.62––0.300––eB10.920.430 L 3.30 2.92 3.810.1300.1150.15018/25Note:Drawing is not to scale.Table 16. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Mechanical DataSymb.mm inchesTyp.Min.Max.Typ.Min.Max.A 1.35 1.750.0530.069A10.100.250.0040.010B0.330.510.0130.020C0.190.250.0070.010D 4.80 5.000.1890.197E 3.80 4.000.1500.157e 1.27––0.050––H 5.80 6.200.2280.244h0.250.500.0100.020L0.400.900.0160.035α0°8°0°8°N88CP0.100.00419/25Note: 1.Drawing is not to scale.2.The central pad (the area E2 by D2 in the above illustration) is pulled, internally, to V SS. It must not be allowed to be connected toany other voltage or signal line on the PCB, for example during the soldering process.Table 17. UFDFPN8 (MLP8) 8-lead Ultra thin Fine pitch Dual Flat Package No lead 2x3mm², DataSymbolmm inchesTyp.Min.Max.Typ.Min.Max.A0.550.500.600.0220.0200.024 A10.000.050.0000.002 b0.250.200.300.0100.0080.012D 2.000.079D2 1.55 1.650.0610.065 ddd0.050.002E 3.000.118E20.150.250.0060.010 e0.50––0.020––L0.450.400.500.0180.0160.020 L10.150.006 L30.300.012N8820/25。

IS24C32C中文资料

Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.IS24C32C32K-bit2-WIRE SERIAL CMOS EEPROMJANUARY 2008DESCRIPTIONThe IS24C32C is electrically erasable PROM devices that use the standard 2-wire interface for communications. The IS24C32C contains amemory array of 32K-bits (4K x 8). Each device is organized into 32 byte pages for page write mode.This EEPROM operates in a wide voltage range of 1.8V to 5.5V to be compatible with most application voltages. ISSI designed this device family to be a practical, low-power 2-wire EEPROM solution.The devices are available in 8-pin PDIP, 8-pinSOIC, 8-pin TSSOP, 8-pad DFN, and 8-pin MSOP packages.The IS24C32C maintains compatibility with the popular 2-wire bus protocol, so it is easy to use in applications implementing this bus type. Thesimple bus consists of the Serial Clock wire (SCL)and the Serial Data wire (SDA). Using the bus, a Master device such as a microcontroller is usually connected to one or more Slave devices such as this device. The bit stream over the SDA line includes a series of bytes, which identifies aparticular Slave device, an instruction, an address within that Slave device, and a series of data, if appropriate. The IS24C32C has a Write Protect pin (WP) to allow blocking of any write instruction transmitted over the bus.FEATURES•Two-Wire Serial Interface, I 2C TM Compatible– Bi-directional data transfer protocol •Wide Voltage Operation– Vcc = 1.8V to 5.5V•400 KHz (2.5V) and 1MHz (5.0V) Compatible •Low Power CMOS Technology– Standby Current: 1 µA or less (1.8V)– Read Current: 2 mA or less (5.0V)– Write Current: 3 mA or less (5.0V)•Hardware Data Protection– protects entire array •Sequential Read Feature•Filtered Inputs for Noise Suppression •Self time write cycle with auto clear 5 ms max.@ 2.5V •Organization:– 4Kx8 (128 pages of 32 bytes)•32 Byte Page Write Buffer •High Reliability– Endurance: 1,000,000 Cycles – Data Retention: 100 Years•Automotive and Industrial temperature ranges •8-pin PDIP, 8-pin SOIC, 8-pin SOP, 8-pinTSSOP, 8-pad DFN, and 8-pin MSOP packages •Lead-free AvailableIS24C32CFUNCTIONAL BLOCK DIAGRAM2Integrated Silicon Solution, Inc.Rev.BIS24C32CPIN DESCRIPTIONSA0-A2Address InputsSDA Serial Address/Data I/O SCL Serial Clock Input WP Write Protect Input Vcc Power Supply GNDGroundSCLThis input clock pin is used to synchronize the data transfer to and from the device.SDAThe SDA is a Bi-directional pin used to transfer addresses and data into and out of the device. The SDA pin is an open drain output and can be wire-Ored with other open drain or open collector outputs. The SDA bus requires a pullup resistor to Vcc.A0, A1, A2The A0, A1 and A2 are the device address inputs that are hardwired or left not connected for hardware compatibility with the 24C16. When pins are hardwired, as many as eight 32K devices may be addressed on a single bus system.When the pins are not hardwired, the default values of A0,A1, and A2 are zero.WPWP is the Write Protect pin. The input level determines if all or none of the array is protected from modifications.PIN CONFIGURATION8-Pin DIP, SOIC, TSSOP, and MSOP12348765A0A1A2GNDVCC WP SCL SDAWrite ProtectionArray A ddresses P rotectedWPIS24C32C GND o r f loating N o n e VccEntire A rray8-pad DFN(Top View)12348765A0A1A2GND VCC WP SCL SDAIS24C32CDEVICE OPERATIONIS24C32C features serial communication and supports a bi-directional 2-wire bus transmission protocol called I2C TM. 2-WIRE BUSThe two-wire bus is defined as a Serial Data line (SDA), and a Serial Clock line (SCL).The protocol defines any device that sends data onto the SDA bus as a transmitter, and the receiving devices as receivers.The bus is controlled by a Master device that generates the SCL, controls the bus access, and generates the Stop and Start conditions.The IS24C32C is the Slave device on the bus.The Bus Protocol:–Data transfer may be initiated only when the bus is not busy–During a data transfer, the SDA line must remain stable whenever the SCL line is high.Any changes in the SDA line while the SCL line is high will be interpreted as a Start or Stop condition.The state of the SDA line represents valid data after a Start condition. The SDA line must be stable for the duration of the High period of the clock signal.The data on the SDA line may be changed during the Low period of the clock signal. There is one clock pulse per bit of data.Each data transfer is initiated with a Start condition and terminated with a Stop condition.Start ConditionThe Start condition precedes all commands to the device and is defined as a H igh to Low transition of SDA when SCL is H igh. The EEPROM monitors the SDA and SCL lines and will not respond until the Start condition is met.Stop ConditionThe Stop condition is defined as a Low to High transition of SDA when SCL is H igh. All operations must end with a Stop condition.Acknowledge (ACK)After a successful data transfer, each receiving device is required to generate an ACK.The Acknowledging device pulls down the SDA line.ResetThe IS24C32C contains a reset function in case the 2-wire bus transmission is accidentally interrupted (eg. a power loss), or needs to be terminated mid-stream. The reset is caused when the Master device creates a Start condition. To do this, it may be necessary for the Master device to monitor the SDA line while cycling the SCL up to nine times. (For each clock signal transition to High, the Master checks for a High level on SDA.)Standby ModePower consumption is reduced in standby mode. The IS24C32C will enter standby mode: a) At Power-up, and remain in it until SCL or SDA toggles; b) Following the Stop signal if a no write operation is initiated; or c) Following any internal write operation.4Integrated Silicon Solution, Inc.Rev.BIS24C32CWRITE OPERATION Byte WriteIn the Byte Write mode, the Master device sends the Start condition and the Slave address information (with the R/W set to Zero) to the Slave device.After the Slave generates an ACK, the Master sends the two byte address that is to be written into the address pointer of the IS24C32C.After receiving another ACK from the Slave, the Master device transmits the data byte to be written into the address memory location.The IS24C32C acknowledges once more and the Master generates the Stop condition, at which time the device begins its internal programming cycle.While this internal cycle is in progress, the device will not respond to any request from the Master device.Page WriteThe IS24C32C is capable of 32-byte Page-Write operation.A Page-Write is initiated in the same manner as a Byte Write,but instead of terminating the internal Write cycle after the first data word is transferred, the Master device can transmit up to 31 more bytes.After the receipt of each data word, the EEPROM responds immediately with an ACK on SDA line,and the five lower order data word address bits are internally incremented by one, while the higher order bits of the data word address remain constant. If a byte address is incremented from the last byte of a page, it returns to the first byte of that page. If the Master device should transmit more than 32 bytes prior to issuing the Stop condition, the address counter will “roll over,” and the previously written data will be overwritten.Once all 32 bytes are received and the Stop condition has been sent by the Master, the internal programming cycle begins. At this point, all received data is written to the IS24C32C in a single Write cycle. All inputs are disabled until completion of the internal Write cycle.Acknowledge (ACK) PollingThe disabling of the inputs can be used to take advantage of the typical Write cycle time.Once the Stop condition is issued to indicate the end of the host's Write operation, the IS24C32C initiates the internal Write cycle. ACK polling can be initiated immediately.This involves issuing the Start condition followed by the Slave address for a Write operation.If the EEPROM is still busy with the Write operation, no ACK will be returned.If the IS24C32C has completed the Write operation, an ACK will be returned and the host can then proceed with the next Read or Write operation.DEVICE ADDRESSINGThe Master begins a transmission by sending a Start condition.The Master then sends the address of the particular Slave devices it is requesting. The Slave device (Fig. 5) address is 8 bits.The four most significant bits of the Slave address are fixed as 1010 for the IS24C32C.The next three bits of the Slave address are A0, A1, and A2,and are used in comparison with the hard-wired input values on the A0, A1, and A2 pins. Up to eight IS24C32C units may share the 2-wire bus.The last bit of the Slave address specifies whether a Read or Write operation is to be performed. When this bit is set to 1, a Read operation is selected, and when set to 0, a Write operation is selected.After the Master transmits the Start condition and Slave address byte (Fig. 5), the appropriate 2-wire Slave,IS24C32C, will respond with ACK on the SDA line. The Slave will pull down the SDA on the ninth clock cycle,signaling that it received the eight bits of data. The selected EEPROM then prepares for a Read or Write operation by monitoring the bus.IS24C32CREAD OPERATIONRead operations are initiated in the same manner as Write operations, except that the (R/W) bit of the Slave address is set to “1”.There are three Read operation options: current address read, random address read and sequential read. Current Address ReadThe IS24C32C contains an internal address counter which maintains the address of the last byte accessed, incremented by one.For example, if the previous operation is either a Read or Write operation addressed to the address location n, the internal address counter would increment to address location n+1.When the EEPROM receives the Slave Addressing Byte with a Read operation (R/W bit set to “1”), it will respond an ACK and transmit the 8-bit data byte stored at address location n+1.The Master should not acknowledge the transfer but should generate a Stop condition so the IS24C32C discontinues transmission.If 'n' is the last byte of the memory, the data from location '0' will be transmitted. (Refer to Figure 8. Current Address Read Diagram.)Random Address ReadSelective Read operations allow the Master device to select at random any memory location for a Read operation.The Master device first performs a 'dummy' Write operation by sending the Start condition, Slave address and byte address of the location it wishes to read. After the IS24C32C acknowledges the byte address, the Master device resends the Start condition and the Slave address, this time with the R/W bit set to one.The EEPROM then responds with its ACK and sends the data requested.The Master device does not send an ACK but will generate a Stop condition.(Refer to Figure 9. Random Address Read Diagram.)Sequential ReadSequential Reads can be initiated as either a Current Address Read or Random Address Read.After the IS24C32C sends the initial byte sequence, the Master device now responds with an ACK indicating it requires additional data from the IS24C32C. The EEPROM continues to output data for each ACK received.The Master device terminates the sequential Read operation by pulling SDA High (no ACK) indicating the last data word to be read, followed by a Stop condition.The data output is sequential, with the data from address n followed by the data from address n+1, n+2 ... etc.The address counter increments by one automatically, allowing the entire memory contents to be serially read during sequential Read operation.When the memory address boundary of 8191 for IS24C32C is reached, the address counter “rolls over” to address 0, and the device continues to output data. (Refer to Figure 10. Sequential Read Diagram).6Integrated Silicon Solution, Inc.Rev.BIS24C32CFigure 1. Typical System Bus ConfigurationFigure 2. Output AcknowledgeFigure 3. START and STOP ConditionsIS24C32CFigure 4. Data Validity ProtocolFigure 6. Byte WriteFigure 7. Page Write8Integrated Silicon Solution, Inc.Rev.BIS24C32CFigure 8. Current Address Read ArrayFigure 9. Random Address ReadFigure 10. Sequential Read10Integrated Silicon Solution, Inc.Rev.BIS24C32CABSOLUTE MAXIMUM RATINGS (1)Symbol Parameter Value Unit V S Supply Voltage –0.5 to +6.5V V P Voltage on Any Pin–0.5 to Vcc + 0.5V T BIAS Temperature Under Bias –55 to +125°C T STG Storage Temperature –65 to +150°C I OUTOutput Current5mANotes:1.Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may causepermanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.OPERATING RANGE (IS24C32C-2)Range Ambient TemperatureV CCIndustrial–40°C to +85°C1.8V to 5.5VNote: ISSI offers Industrial grade for Commerical applications (0o C to +70o C).CAPACITANCE (1,2)Symbol ParameterConditions Max.Unit C IN Input Capacitance V IN = 0V 6pF C OUTOutput CapacitanceV OUT = 0V8pFNotes:1.Tested initially and after any design or process changes that may affect these parameters.2.Test conditions: T A = 25°C, f = 1 MHz, Vcc = 5.0V.OPERATING RANGE (IS24C32C-3)RangeAmbient Temperature V CCAutomotive–40°C to +125°C2.5V to 5.5VAC WAVEFORMSFigure 11. Bus TimingFigure 12. Write Cycle TimingDC ELECTRICAL CHARACTERISTICS Industrial (T A = -40o C to +85o C), Automotive (T A = -40o C to +125o C) Symbol Parameter Test Conditions Min.Max.Unit V OL1Output Low Voltage V CC = 1.8V, I OL = 0.15 mA—0.2V V OL2Output Low Voltage V CC = 2.5V, I OL = 3 mA—0.4V V IH Input High Voltage V CC X 0.7V CC + 0.5V V IL Input Low Voltage–1.0V CC X 0.3VI LI Input Leakage Current V IN = V CC max.—3µAI LO Output Leakage Current—3µA Notes:V IL min and V IH max are reference only and are not tested.POWER SUPPLY CHARACTERISTICS Industrial (T A = -40o C to +85o C), Automotive (T A = -40o C to +125o C) Symbol Parameter Test Conditions Min.Max.UnitI CC1Operating Current Read at 400 KHz (Vcc = 5V)— 2.0mAI CC2Operating Current Write at 400 KHz (Vcc = 5V)— 3.0mAI SB1Standby Current Vcc = 1.8V—1µAI SB2Standby Current Vcc = 2.5V—2µAI SB3Standby Current Vcc = 5.0V—6µAAC ELECTRICAL CHARACTERISTICS Industrial (T A = -40o C to +85o C)1.8V ≤Vcc <2.5V 2.5V ≤Vcc < 4.5V 4.5V ≤Vcc ≤ 5.5V(1) Symbol Parameter Min.Max.Min.Max.Min.Max.Unit f SCL SCL Clock Frequency0100040001000KHz T Noise Suppression Time(1)—100—50—50nst Low Clock Low Period 4.7— 1.2—0.6—µst High Clock H igh Period4—0.6—0.4—µst BUF Bus Free Time Before New Transmission(1) 4.7— 1.2—0.5—µst SU:STA Start Condition Setup Time4—0.6—0.25—µst SU:STO Stop Condition Setup Time4—0.6—0.25—µst HD:STA Start Condition H old Time4—0.6—0.25—µst HD:STO Stop Condition H old Time4—0.6—0.25—µst SU:DAT Data In Setup Time100—100—100—nst HD:DAT Data In H old Time0—0—0—nst SU:WP WP pin Setup Time4—0.6—0.6—µst HD:WP WP pin H old Time 4.7— 1.2— 1.2—µst DH Data Out H old Time100—50—50—ns (SCL Low to SDA Data Out Change)t AA Clock to Output10035005090050400ns (SCL Low to SDA Data Out Valid)t R SCL and SDA Rise Time(1)—1000—300—300nst F SCL and SDA Fall Time(1)—300—300—100nst WR Write Cycle Time—5—5—5ms Note:1. These parameters are characterized but not 100% tested.12Integrated Silicon Solution, Inc.Rev.BAC ELECTRICAL CHARACTERISTICS Automotive (T A = -40o C to +125o C)2.5V ≤Vcc < 4.5V 4.5V ≤Vcc ≤ 5.5V(1) Symbol Parameter Min.Max.Min.Max.Unit f SCL SCL Clock Frequency040001000KH z T Noise Suppression Time(1)—50—50ns t Low Clock Low Period 1.2—0.6—µs t High Clock High Period0.6—0.4—µs t BUF Bus Free Time Before New Transmission(1) 1.2—0.5—µs t SU:STA Start Condition Setup Time0.6—0.25—µs t SU:STO Stop Condition Setup Time0.6—0.25—µs t HD:STA Start Condition Hold Time0.6—0.25—µs t HD:STO Stop Condition Hold Time0.6—0.25—µs t SU:DAT Data In Setup Time100—100—ns t HD:DAT Data In Hold Time0—0—ns t SU:WP WP pin Setup Time0.6—0.6—µs t HD:WP WP pin Hold Time 1.2— 1.2—µs t DH Data Out Hold Time (SCL Low to SDA Data Out Change)50—50—ns t AA Clock to Output (SCL Low to SDA Data Out Valid)5090050550ns t R SCL and SDA Rise Time(1)—300—300ns t F SCL and SDA Fall Time(1)—300—100ns t WR Write Cycle Time—10—5ms Note:1. These parameters are characterized but not 100% tested.ORDERING INFORMATIONIndustrial Range: -40°C to +85°C, Lead-freeVoltageRange Part Number Package1.8V IS24C32C-2DLI*8-pad 2x3 mm DFNIS24C32C-2PLI*8-pin 300-mil Plastic DIPto 5.5V IS24C32C-2GLI8-pin 150-mil SOIC (JEDEC STD)IS24C32C-2ZLI8-pin 3x4.4 mm TSSOPIS24C32C-2SLI*8-pin 120-mil MSOPORDERING INFORMATIONAutomotive Range: -40°C to +125°C, Lead-freeVoltageRange Part Number Package2.5V IS24C32C-3PLA3*8-pin 300-mil Plastic DIPto 5.5V IS24C32C-3GLA38-pin 150-mil SOIC (JEDEC STD)IS24C32C-3ZLA38-pin 3x4.4 mm TSSOP* Please contact ISSI Sales Rep for availability.14Integrated Silicon Solution, Inc.Rev.BDual Flat No-Lead Package Code: D (8-pad)300-mil Plastic DIPPackage Code: N,P16Integrated Silicon Solution, Inc.Rev.B150-mil Plastic SOPThin Shrink Small Outline TSSOPPackage Code: Z (8 pin, 14 pin)18Integrated Silicon Solution, Inc.Rev.BPlastic M S OP Package Code: SREVISION HISTORYRev.Date DescriptionA April 2007Draft versionB January 2008Initial version for product launch20Integrated Silicon Solution, Inc.Rev.B。

Belling BL24CM1A 1M位 EEPROM 产品说明书

Features⚫Compatible with all I2C bidirectional data transfer protocol⚫Memory array:–1024 Kbits (128 Kbytes) of EEPROM–Page size: 256 bytes–Additional Write lockable page⚫Single supply voltage and high speed:–⚫Random and sequential Read modes⚫Write:–Byte Write within 5 ms–Page Write within 5 ms–Partial Page Writes Allowed⚫Write Protect Pin for Hardware Data Protection ⚫Schmitt Trigger, Filtered Inputs for Noise Suppression⚫High-reliability–Endurance: 4 Million Write Cycles–Data Retention: 100 Years⚫Enhanced ESD/Latch-up protection–HBM 8000V⚫8-lead PDIP/SOP/TSSOP/UDFN/WLCSP packagesDescription⚫The BL24CM1A provides 1048576 bits of serial electrically erasable and programmable read-only memory (EEPROM), organized as 131072 words of 8 bits each.⚫The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. ⚫The BL24CM1A offers an additional page, named the Identification Page (256 bytes). The Identification Page can be used to store sensitive application parameters which can be (later) permanently locked in Read-only mode.Pin ConfigurationNC A1 A2 GNDVCCWPNCA1A2GNDNCA1A2GNDVCCWPVCCWP １２３４8765１２３４１２３４87658765８-lead PDIP８-lead SOP８-lead TSSOPSCLSDASCLSDASCLSDAWLCSPSDA VccSCLA2A1NCGNDWPNCA1A2GNDVCCWP１２３４8765UDFNSCLSDAPin DescriptionsPin Name Type Functions A1-A2I Address Inputs SDA I/O Serial Data SCL I Serial Clock Input WP I Write ProtectGND P Ground VccPPower SupplyBlock DiagramSTART STOP LOGICSERIAL CONTROLLOGICSCL SDAGNDVcc DEVICE ADDRESS COMPARATORLOADCCMPDATA WORD ADRESS COUNTERLOADINCX DECODERY DECODER SERIAL MUXEEPROMENDATA RECOVERY HIGH VOLTAGE PUMP/TIMINGDOUT/ACKNOWLEDGEDINDOUTA1A2WPDEVICE/PAGE ADDRESSES (A2 and A1): The A2 and A1 pins are device address inputs that are hard wirefor the BL24CM1A. Four 1M devices may be addressed on a single bus system (device addressing is discussedin detail under the Device Addressing section).SERIAL DATA (SDA): The SDA pin is bi-directional for serial data transfer. This pin is open-drain driven and may be wire-ORed with any number of other open-drain or open- collector devices.SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device.WRITE PROTECT (WP): The BL24CM1A has a Write Protect pin that provides hardware data protection. The Write Protect pin allows normal read/write operations when connected to ground (GND). When the Write Protection pin is connected to Vcc, the write protection feature is enabled and operates as shown in the following Table 2.Table 1Figure 1WP Pin Status BL24CM1AAt VCC Full(1024K)ArrayAt GND Normal Read/Write OperationsTable 2Functional Description1. Memory OrganizationBL24CM1A, 1M SERIAL EEPROM: Internally organized with 512 pages of 256 bytes each, the 1M requires a 17-bit data word address for random word addressing.2. Device OperationCLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods (see Figure 2). Data changes during SCL high periods will indicate a start or stop condition as defined below.START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (see Figure 3).STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop command will place the EEPROM in a standby power mode (see Figure 3).ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a "0" to acknowledge that it has received each word. This happens during the ninth clock cycle.STANDBY MODE: The BL24CM1A features a low-power standby mode which is enabled: (a) upon power-up and (b) after the receipt of the STOP bit and the completion of any internal operations.MEMORY RESET: After an interruption in protocol, power loss or system reset, any two-wire part can be reset by following these steps:1. Clock up to 9 cycles.2. Look for SDA high in each cycle while SCL is high.3. Create a start condition.DATA STABLEDATA STABLEDATA CHANGESDASCLFigure 2. Data ValiditySDASCLSTARTSTOPFigure 3. Start and Stop DefinitionSCL DATA INDATA OUTSTARTACKNOWLEDGE189Figure 4. Output Acknowledge3. Device AddressingThe 1M EEPROM devices all require an 8-bit device address word following a start condition to enable the chip for a read or write operation (see Figure 5)The device address word consists of a mandatory "1", "0" sequence for the first four most significant bits as shown. This is common to all the Serial EEPROM devices.The 1M EEPROM uses A2 and A1 device address bits and one world address bit to allow as much as four devices on the same bus. These 2 device address bits must be compared to their corresponding hardwired input pins. The A2 and A1 pins use an internal proprietary circuit that biases them to a logic low condition if the pins are allowed to float.The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit is high and a write operation is initiated if this bit is low.Upon a compare of the device address, the EEPROM will output a "0". If a compare is not made, the chip will return to a standby state.MSB LSB1010A2A1B16R/WB15B14B13B12B11B10B9B8B7B6B5B4B3B2B1B0Figure 5. Device Address and two 8-bit data word addressDATA SECURITY: The BL24CM1A has a hardware data protection scheme that allows the user to write protect the entire memory when the WP pin is at VCC.4. Write OperationsBYTE WRITE: A write operation requires two 8-bit data word address following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a "0" and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a "0" and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condition. At this time the EEPROM enters an internally timed write cycle, tWR, to the nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will not respond until the write is complete (see Figure 6).SDA LINE STARTDEVICEADDRESSWRITEMSBLSBR/WACKFIRST WORDADDRESSSECOND WORDADDRESSACKLSBACKLSBACKLSBSTOPDATAFigure 6. Byte WritePAGE WRITE: The Page Write mode allows up to 256 bytes to be written in a single Write cycle. A page write is initiated the same as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller can transmit up to 255 more data words. The EEPROM will respond with a “0” after each data word received. The microcontroller must terminate the page write sequence with a stop condition (see Figure 7).ST A R TDEVICEADDRESSWRITEMSBLSBR/WACKFIRST WORDADDRESSSECOND WORDADDRESSACKLSBACKLSBACKSTOPDATA(n)ACKACKDATA(n+1)DATA(n+1)SDALINEFigure 7. Page WriteThe data word address lower eight bits are internally incremented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location. When the word address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than 256 data words are transmitted to the EEPROM, the data word address will "roll over" and previous data will be overwritten.WRITE IDENTIFICATION PAGE: The Identification Page (256 bytes) is an additional page which can be written and (later) permanently locked in Read-only mode. It is written by issuing the Write Identification Page instruction. This instruction uses the same protocol and format as Page Write (into memory array), except for the following differences:•Device type identifier = 1011b•MSB address bits B16/B8 are don't care except for address bit B10 which must be "0".LSB address bits B7/B0 define the byte address inside the Identification page.If the Identification page is locked, the data bytes transferred during the Write Identification Page instruction are not acknowledged (NoAck).ACKNOWLEDGE POLLING: Once the internally timed write cycle has started and the EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a start condition followed by the device address word. The read/write bit is representative of the operation desired. Only if the internal write cycle has completed will the EEPROM respond with a "0", allowing the read or write sequence to continue.5. Read OperationsRead operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to "1". There are three read operations: current address read, random address read and sequential read.CURRENT ADDRESS READ:The internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. This address stays valid between operations as long as the chip power is maintained. The address "roll over" during read is from the last byte of the last memory page to the first byte of the first page. The address "roll over" during write is from the last byte of the current page to the first byte of the same page. Once the device address with the read/write select bit set to "1" is clocked in and acknowledged by the EEPROM, the current address data word is serially clocked out. The microcontroller does not respond with an input "0" but does generate a following stop condition (see Figure 8).ST A R TDEVICEADDRESSREADMSBLSBR/WACKSTOPDATANOACKSDALINEFigure 8. Current Address ReadRANDOM READ:A random read requires a "dummy" byte write sequence to load in the data word address. Once the device address word and data word address are clocked in and acknowledged by the EEPROM, the microcontroller must generate another start condition. The microcontroller now initiates a current address read by sending a device address with the read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. The microcontroller does not respond with a "0" but does generate a following stop condition (see Figure 9)STA R TDEVICEADDRESSWRITEMSBLSBR/WACK1st,2nd WORDADDRESSACKLSBSTOPDATA(n)DEVICEADDRESSSTARTREADACKNOACK DUMMY WRITESDALINEFigure 9. Random ReadSEQUENTIAL READ: Sequential reads are initiated by either a current address read or a random address read. After the microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. When the memory address limit is reached, the data word address will "roll over" and the sequential read will continue. The sequential read operation is terminated when the microcontroller does not respond with a "0" but does generate a following stop condition (see Figure 10).DEVICE ADDRESS READR/WACKACKACKACKSTOP DATA(n)DATA(n+1)DATA(n+2)DATA(n+x)NOACKSDALINEFigure 10. Sequential ReadREAD IDENTIFICATION PAGE: The Identification Page (256 bytes) is an additional page which can be written and (later) permanently locked in Read-only mode.The Identification Page can be read by issuing an Read Identification Page instruction. This instruction uses the same protocol and format as the Random Address Read (from memory array) with device type identifier defined as 1011b. The MSB address bits B16/B8 are don't care, the LSB address bits B7/B0 define the byte address inside the Identification Page. The number of bytes to read in the ID page must not exceed the page boundary (e.g.: when reading the Identification Page from location 10d, the number of bytes should be less than or equal to 246, as the ID page boundary is 256 bytes)LOCK IDENTIFICATION PAGE: The Lock Identification Page instruction (Lock ID) permanently locks the Identification page in Read-only mode. The Lock ID instruction is similar to Byte Write (into memory array) with the following specific conditions:Device type identifier = 1011bAddress bit B10 must be ‘1’; all other address bits are don't careThe data byte must be equal to the binary value xxxx xx1x, where x is don't careElectrical CharacteristicsAbsolute Maximum Stress Ratings：⚫DC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V⚫Input / Output Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND-0.3V to VCC+0.3V⚫Operating Ambient Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40℃ to +85℃⚫Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65℃ to +150℃⚫Electrostatic pulse (Human Body model) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8000VComments：Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.DC Electrical CharacteristicsApplicable over recommended operating range from: TA = -40℃to +85℃, VCC = +2.0V to +5.5V (unless otherwise noted)Parameter Symbol Min Typ Max Unit Condition Supply Voltage V CC1 2.0- 5.5V-Supply Current VCC=5.0V I CC1-0.260.5mA READ at 400KHZSupply Current VCC=5.0V I CC2-0.280.5mA WRITE at 400KHZSupply Current VCC=5.0V I SB1-0.030.5μA V IN=V CC or V SSInput Leakage Current I L1-0.10 1.0μA V IN=V CC or V SSOutput Leakage Current I LO-0.05 1.0μA V OUT=V CC or V SSInput Low Level V IL1-0.3-V CC×0.3V V CC=1.7V to 5.5VInput High Level V IH1V CC×0.7-V CC+0.3V V CC=1.7V to 5.5VOutput Low Level VCC=1.7V V OL1--0.2V I OL=2.1mAOutput Low Level VCC=5.0V V OL2--0.4V I OL=3.0mATable 3Pin CapacitanceParameter Symbol Min Typ Max Unit ConditionInput/Output Capacitance(SDA)C I/O--8pF V IO=0VInput Capacitance(A1,A2,SCL)C IN--6pF V IN=0VTable 4AC Electrical CharacteristicsApplicable over recommended operating range from TA = -40℃ to +85℃, VCC = +2.0V to +5.5V, CL = 1 TTL Gate and 100 pF (unless otherwise noted)Min Typ Max Min Typ Max Clock Frequency,SCL f SCL --400--1000KHZ Clock Pulse Width Low t LOW 1.3--0.5--μs Clock Pulse Width High t HIGH 0.6--0.26--μs Noise Suppression Time t I --50--50ns Clock Low to Data Out Valid t AA --0.9--0.45μs Time the bus must be free before a new transmission can start t BUF 1.3--0.5--μs Start Hold Time t HD:STA 0.6--0.25--μs Start Setup Time t SU:STA 0.6--0.25--μs Data In Hold Time t HD:DAT 0--0--μs Data in Setup Time t SU:DAT 100--100--ns Input Rise Time(1)t R --0.3--0.12μs Input Fall Time(1)t F --0.3--0.12μs Stop Setup Time t Su:STO 0.6--0.25--μs Data Out Hold Time t DH 50--50--ns Write Cycle Time t WR - 3.55- 3.55ms 5.0V,25℃,Byte Mode(1)Endurance4M--4M--Write CycleParameterSymbol 2.0V ≤V CC ﹤2.5V 2.5V ≤V CC ﹤5.5V UnitsNotes:1. This parameter is characterized and is not 100% tested.2. AC measurement conditions: RL (connects to VCC): 1.3 kInput pulse voltages: 0.3 VCC to 0.7 VCC Input rise and fall time: 50 nsInput and output timing reference voltages: 0.5 VCCThe value of RL should be concerned according to the actual loading on the user's system.Table 5Bus TimingSCLSDA_INSDA_OUTt SU.STAt HD.STAt LOW t Ft HIGHt LOWt HD.DATt SU.DATt Rt SU.STOt BUFt DHt AAFigure 11. SCL: Serial Clock, SDA: Serial Data I/OWrite Cycle TimingtWR(1)ACKSTOP CONDITIONSTART CONDITIONSCLSDAWord nFigure 12. SCL: Serial Clock, SDA: Serial Data I/ONotes:The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.Package InformationPDIP Outline Dimensionsb2eLAA2ceA E1COMMON DIMENSIONS (Unit of Measure=mm)SYMBOL MIN NOM MAX A 3.60 3.80 4.00A2 3.20 3.30 3.40b 0.44-0.53b2c 0.24-0.32D 9.059.259.45E1 6.156.35 6.55e eA eB 7.62-9.30L2.54BSC 7.62BSC1.52BSC3.00BSCeBDEBe A A1DE1LΦSYMBOL MIN NOM MAXA 1.35- 1.75A10.10-0.23 B0.39-0.48 C0.21-0.26D 4.70 4.90 5.10E1 3.70 3.90 4.10E 5.80 6.00 6.20eL0.50-0.80Φ0"-8"1.27BSCCOMMON DIMENSIONS(Unit of Measure=mm)CE1E Top ViewD ebA1A Side ViewL1LEnd ViewSYMBOL MIN NOM MAXD 2.90 3.00 3.10E 6.20 6.40 6.60E1 4.30 4.40 4.50A-- 1.20A10.05-0.15b0.21-0.30eL0.450.600.75L10.65BSC1.00REFCOMMON DIMENSIONSUnit of Measure=mmPIN 1 DOT BY MARKINGTOP VIEWb eLD2E2ED A3AA1PIN #1 IDENTIFICATIONCHAMFERPKG REF MIN NOM MAX A 0.500.550.60A10.00-0.05A3D 1.95 2.00 2.05E 2.95 3.00 3.05b 0.200.250.30L 0.200.300.40D2 1.25 1.40 1.50E2 1.15 1.30 1.40eCOMMON DIMENSION(MM)UT:ULTRA THIN 0.15REF0.50BSCBOTTOM VIEWSIDE VIEWWLCSPEG GA2A A1be1FFe 2eSYMBOL MIN NOM MAX A 0.4250.4650.505A10.1700.1900.210A20.2550.2750.295D 1.944 1.964 1.984E 1.4801.500 1.520e e1e2e3b F 0.5290.5490.569G0.2300.2500.2700.500BSC 0.500BSC 1.000BSC 0.270BSC 0.866BSC DMarking DiagramSOPBL24CM1ASSSSSPSSSSS : Lot IDTSSOPBL24CM1ASSSSSSSSSS : Lot IDUDFNBLFAYYWWYY: yearWW :weekWLCSPAYWY:The last digits of the yearW:week code.Y1...345 (90)Year2011...201320142015 (20192020)W A…Y Z a…y zWeek1...252627 (5152)Ordering InformationBL 24C M1 A-PA R CFeatureS: Standard (default, Pb Free RoHS Std.)C: Green (Halogen Free)Packing typeR: Tape and ReelT: TubePackage TypePA: SOP-8LSF: TSSOP-8LNT: UDFN-8LCS: WLCSPDA: PDIP-8LGenerationA: A VersionDensityM1: 1MbitProduct Family24C: IIC Interface EEPROMRevision historyVersion 1.00 BL24CM1AInitial versionVersion 1.01 BL24CM1AAdd WLCSP and UDFN Package informationVersion 1.02 BL24CM1AUpdate the Package Information。

ATMEL AT24C01B 说明书

Features•Low-voltage and Standard-voltage Operation –1.8 (V CC = 1.8V to 5.5V)•Internally Organized 128 x 8 (1K)•Two-wire Serial Interface•Schmitt Trigger, Filtered Inputs for Noise Suppression •Bidirectional Data Transfer Protocol• 1 MHz (5V), 400 kHz (1.8V, 2.5V, 2.7V) Compatibility •Write Protect Pin for Hardware Data Protection •8-byte Page (1K) Write Modes •Partial Page Writes Allowed•Self-timed Write Cycle (5 ms max)•High-reliability–Endurance: 1 Million Write Cycles –Data Retention: 100 Years•8-lead PDIP , 8-lead JEDEC SOIC, 8-lead Ultra Thin Mini-MAP (MLP 2x3), 5-lead SOT23,8-lead TSSOP and 8-ball dBGA2 Packages •Lead-free/Halogen-free•Die Sales: Wafer Form and Tape and ReelDescriptionThe AT24C01B provides 1024 bits of serial electrically erasable and programmable read-only memory (EEPROM) organized as 128 words of 8 bits each. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. The AT24C01B is available in space-saving 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead Ultra Thin Mini-MAP (MLP 2x3), 5-lead SOT23, 8-lead TSSOP, and 8-ball dBGA2 packages and is accessed via a Two-wire serial interface. In addition, the AT24C01B is available in 1.8V (1.8V to 5.5V) version.Table 0-1.Pin ConfigurationTwo-wireSerial EEPROM1K (128 x 8)AT24C01B5156E–SEEPR–10/08BDTIC www.BDTIC .com/ATMEL25156E–SEEPR–10/08AT24C01BFigure 0-1.Block DiagramAbsolute Maximum RatingsOperating Temperature..................................–55°C to +125°C *NOTICE:Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent dam-age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.Storage Temperature.....................................–65°C to +150°C Voltage on Any Pinwith Respect to Ground....................................–1.0V to +7.0V Maximum Operating Voltage..........................................6.25V DC Output Current........................................................5.0 mA35156E–SEEPR–10/08AT24C01B1.Pin DescriptionSERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device.SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and may be wire-ORed with any number of other open-drain or open-collector devices.DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1 and A0 pins are device address inputs that are hard wired for the AT24C01B. As many as eight 1K devices may be addressed on a sin-gle bus system (device addressing is discussed in detail under the Device Addressing section).WRITE PROTECT (WP): The AT24C01B has a write protect pin that provides hardware data protection. The write protect pin allows normal read/write operations when connected to ground (GND). When the write protect pin is connected to V CC , the write protection feature is enabled and operates as shown in Table 1-1.Table 1-1.Write Protect2.Memory OrganizationAT24C01B, 1K SERIAL EEPROM: Internally organized with 16 pages of 8 bytes each, the 1K requires an 7-bit data word address for random word addressing. (See Figure 8-2 on page 10)WP Pin Status Part of the Array Protected24C01BAt V CC Full (1K) ArrayAt GNDNormal Read/Write Operations45156E–SEEPR–10/08AT24C01BNote:1.This parameter is characterized and is not 100% tested.Note:1.V IL min and V IH max are reference only and are not tested.Table 2-1.Pin Capacitance (1)Applicable over recommended operating range from T A = 25°C, f = 1.0 MHz, V CC = +1.8VSymbol Test ConditionMax Units Conditions C I/O Input/Output Capacitance (SDA)8pF V I/O = 0V C IN Input Capacitance (A 0, A 1, A 2, SCL)6pFV IN = 0VTable 2-2.DC CharacteristicsApplicable over recommended operating range from: T AI = –40°C to +85°C, V CC = +1.8V to +5.5V, V CC =+1.8V to +5.5V (unless otherwise noted)Symbol Parameter Test ConditionMin TypMax Units V CC1Supply Voltage 1.8 5.5V V CC2Supply Voltage 2.5 5.5V V CC3Supply Voltage 2.7 5.5V V CC4Supply Voltage4.55.5V I CC Supply Current V CC = 5.0V READ at 100 kHz 0.4 1.0mA I CC Supply Current V CC = 5.0V WRITE at 100 kHz 2.0 3.0mA I SB1Standby Current V CC = 1.8V V IN = V CC or V SS 0.6 3.0µA I SB2Standby Current V CC = 2.5V V IN = V CC or V SS 1.4 4.0µA I SB3Standby Current V CC = 2.7V V IN = V CC or V SS 1.6 4.0µA I SB4Standby Current V CC = 5.0V V IN = V CC or V SS 8.018.0µA I LI Input Leakage Current V IN = V CC or V SS 0.10 3.0µA I LO Output Leakage Current V OUT = V CC or V SS0.05 3.0µA V IL Input Low Level (1)–0.6V CC x 0.3V V IH Input High Level (1)V CC x 0.7V CC + 0.5V V OL2Output Low Level V CC = 3.0V I OL = 2.1 mA 0.4V V OL1Output Low Level V CC = 1.8VI OL = 0.15 mA 0.2V55156E–SEEPR–10/08AT24C01BNote:1.This parameter is ensured by characterization only.Table 2-3.AC CharacteristicsApplicable over recommended operating range from T AI = –40°C to +85°C, V CC = +1.8V to +5.5V, CL = 1 TTL Gate and 100pF (unless otherwise noted)Symbol Parameter1.8,2.5, 2.75.0-volt Units MinMax MinMax f SCL Clock Frequency, SCL 4001000kHz t LOW Clock Pulse Width Low 1.20.4µs t HIGH Clock Pulse Width High 0.60.4µs t I Noise Suppression Time 5040ns t AA Clock Low to Data Out Valid0.10.90.050.55µs t BUF Time the bus must be free before a new transmission can start 1.20.5µs t HD.STA Start Hold Time 0.60.25µs t SU.STA Start Setup Time 0.60.25µs t HD.DAT Data In Hold Time 00µs t SU.DAT Data In Setup Time 100100ns t R Inputs Rise Time (1)0.30.3µs t F Inputs Fall Time (1)300100ns t SU.STO Stop Setup Time 0.6.25µs t DH Data Out Hold Time 5050ns t WRWrite Cycle Time 55ms Endurance (1) 5.0V, 25°C, Byte Mode1 MillionWrite Cycles65156E–SEEPR–10/08AT24C01B3.Device OperationCLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods (see Figure 5-2 on page 8). Data changes during SCL high periods will indicate a start or stop condition as defined below.START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (see Figure 5-3 on page 8).STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop command will place the EEPROM in a standby power mode (see Fig-ure 5-3 on page 8).ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a zero to acknowledge that it has received each word. This happens during the ninth clock cycle.STANDBY MODE: The AT24C01B features a low-power standby mode which is enabled: (a)upon power-up and (b) after the receipt of the STOP bit and the completion of any internal operations.2-WIRE SOFTWARE RESET: After an interruption in protocol, power loss or system reset, any 2-wire part can be protocol reset by following these steps: (a) Create a start bit condition, (b)Clock 9 cycles, (c) Create another start bit followed by a stop bit condition as shown below. Thedevice is ready for next communication after above steps have been completed.75156E–SEEPR–10/08AT24C01B4.Bus TimingFigure 4-1.SCL: Serial Clock, SDA: Serial Data I/O ®5.Write Cycle TimingFigure 5-1.SCL: Serial Clock, SDA: Serial Data I/ONote:1.The write cycle time t WRis the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.85156E–SEEPR–10/08AT24C01BFigure 5-2.Data ValidityFigure 5-3.Start and Stop DefinitionFigure 5-4.Output Acknowledge95156E–SEEPR–10/08AT24C01B6.Device AddressingThe 1K EEPROM device requires an 8-bit device address word following a start condition to enable the chip for a read or write operation (refer to Figure 8-1).The device address word consists of a mandatory one, zero sequence for the first four most sig-nificant bits as shown. This is common to all the EEPROM devices.The next 3 bits are the A2, A1 and A0 device address bits for the 1K EEPROM. These 3 bits must compare to their corresponding hard-wired input pins.The eighth bit of the device address is the read/write operation select bit. A read operation is ini-tiated if this bit is high and a write operation is initiated if this bit is low.Upon a compare of the device address, the EEPROM will output a zero. If a compare is not made, the chip will return to a standby state.7.Write OperationsBYTE WRITE: A write operation requires an 8-bit data word address following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a zero and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a zero and the addressing device, such as a microcontroller,must terminate the write sequence with a stop condition. At this time the EEPROM enters an internally timed write cycle, t WR , to the nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will not respond until the write is complete (see Figure 8-2 on page 10).PAGE WRITE: The 1K EEPROM is capable of an 8-byte page write.A page write is initiated the same as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller can transmit up to seven data words. The EEPROM will respond with a zero after each data word received. The microcontroller must ter-minate the page write sequence with a stop condition (see Figure 8-3 on page 11).The data word address lower three bits are internally incremented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location. When the word address, internally generated, reaches the page boundary, the fol-lowing byte is placed at the beginning of the same page. If more than eight data words are transmitted to the EEPROM, the data word address will “roll over” and previous data will be overwritten.ACKNOWLEDGE POLLING: Once the internally timed write cycle has started and the EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a start condition followed by the device address word. The read/write bit is representative of the operation desired. Only if the internal write cycle has completed will the EEPROM respond with a zero allowing the read or write sequence to continue.105156E–SEEPR–10/08AT24C01B8.Read OperationsRead operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to one. There are three read operations:current address read, random address read and sequential read.CURRENT ADDRESS READ: The internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. This address stays valid between operations as long as the chip power is maintained. The address “roll over”during read is from the last byte of the last memory page to the first byte of the first page. The address “roll over” during write is from the last byte of the current page to the first byte of the same page.Once the device address with the read/write select bit set to one is clocked in and acknowledged by the EEPROM, the current address data word is serially clocked out. The microcontroller does not respond with an input zero but does generate a following stop condition (see Figure 8-4 on page 11).RANDOM READ: A random read requires a “dummy” byte write sequence to load in the data word address. Once the device address word and data word address are clocked in and acknowledged by the EEPROM, the microcontroller must generate another start condition. The microcontroller now initiates a current address read by sending a device address with the read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. The microcontroller does not respond with a zero but does generate a follow-ing stop condition (see Figure 8-5 on page 11).SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a ran-dom address read. After the microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. When the memory address limit is reached, the data word address will “roll over” and the sequential read will continue. The sequential read operation is terminated when the microcontroller does not respond with a zero but does generate a following stop condition (see Figure 8-6 on page 12).Figure 8-1.Device AddressFigure 8-2.Byte Write115156E–SEEPR–10/08AT24C01BFigure 8-3.Page WriteFigure 8-4.Current Address ReadFigure 8-5.Random Read125156E–SEEPR–10/08AT24C01BFigure 8-6.Sequential Read135156E–SEEPR–10/08AT24C01BNotes:1.“-B” denotes bulk.2.“-T” denotes tape and reel. SOIC = 4K per reel. TSSOP , Ultra Thin Mini MAP , SOT 23 and dBGA2 = 5K per reel.3.Available in tape and reel and wafer form; order as SL788 for inkless wafer form. Please contact Serial Interface Marketing.AT24C01B Ordering InformationOrdering CodePackage Voltage Range Operation RangeAT24C01B-PU (Bulk form only)8P3 1.8V to 5.5V Lead-free/Halogen-free/Industrial Temperature (–40°C to 85°C)AT24C01BN-SH-B (1) (NiPdAu Lead Finish)8S1 1.8V to 5.5V AT24C01BN-SH-T (2) (NiPdAu Lead Finish)8S1 1.8V to 5.5V AT24C01B-TH-B (1) (NiPdAu Lead Finish)8A2 1.8V to 5.5V AT24C01B-TH-T (2) (NiPdAu Lead Finish)8A2 1.8V to 5.5V AT24C01BY6-YH -T(2) (NiPdAu Lead Finish)8Y6 1.8V to 5.5V AT24C01B-TSU -T(2)5TS1 1.8V to 5.5V AT24C01BU3-UU -T(2)8U3-1 1.8V to 5.5V AT24C01B-W-11(3)Die Sale1.8V to 5.5VIndustrial Temperature (–40°C to 85°C)Package Type8P38-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)8S18-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)8A28-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP)8Y68-lead, 2.0 mm x 3.00 mm Body, 0.50 mm Pitch, Ultra Thin Mini-MAP , Dual No Lead Package (DFN), (MLP 2x3 mm)5TS15-lead, 2.90 mm x 1.60 mm Body, Plastic Thin Shrink Small Outline Package (SOT23)8U3-18-ball, die Ball Grid Array Package (dBGA2)145156E–SEEPR–10/08AT24C01B9.Part Marking Scheme8-PDIPSeal Year TOP MARK| Seal Week | | ||---|---|---|---|---|---|---|---| A T M L U Y W W |---|---|---|---|---|---|---|---| 0 1 B 1|---|---|---|---|---|---|---|---| * Lot Number|---|---|---|---|---|---|---|---| |Pin 1 Indicator (Dot)U = Material Set Y = Seal Year WW = Seal Week 01B = DeviceV = Voltage Indicator*Lot Number to Use ALL Characters in Marking BOTTOM MARKNo Bottom Mark155156E–SEEPR–10/08AT24C01B8-SOICSeal Year TOP MARK | Seal Week| | ||---|---|---|---|---|---|---|---| A T M L H Y W W |---|---|---|---|---|---|---|---| 0 1 B 1|---|---|---|---|---|---|---|---| * Lot Number|---|---|---|---|---|---|---|---| |Pin 1 Indicator (Dot)H = Material Set Y = Seal Year WW = Seal Week 01B = Device 1 = Voltage Indicator*Lot Number to Use ALL Characters in Marking BOTTOM MARKNo Bottom Mark8-TSSOPTOP MARKPin 1 Indicator (Dot) ||---|---|---|---| * H Y W W |---|---|---|---|---|01B 1 |---|---|---|---|---|H = Material Set Y = Seal Year WW = Seal Week 01B = Device 1 = Voltage Indicator165156E–SEEPR–10/08AT24C01BBOTTOM MARK|---|---|---|---|---|---|---| X X|---|---|---|---|---|---|---| A A A A A A A |---|---|---|---|---|---|---| <- Pin 1 IndicatorLot NumberXX = Country of Origin AAAAAA = Lot NumberSOT23TOP MARK|---|---|---|---|---|Line 1 -----------> 1 B 1 W U|---|---|---|---|---| *| Pin 1 Indicator (Dot)1B = Device1 = Voltage IndicatorW = Write Protect Feature U = Material SetBOTTOM MARK|---|---|---|---| Y M T C |---|---|---|---|Y = One Digit Year Code M = Seal Month TC = Trace Code175156E–SEEPR–10/08AT24C01BULTRA THIN MINI MAPTOP MARK|---|---|---| 0 1 B |---|---|---| H 1 |---|---|---|Y T C |---|---|---| * |Pin 1 Indicator (Dot) 01B = Device H = Material Set1 = Voltage Indicator Y = Year of Assembly TC = Trace CodedBGA2TOP MARKLINE 1-------> 01BU LINE 2-------> YMTC|<-- Pin 1 This Corner 01B = DeviceU = Material SetY = One Digit Year Code M = Seal Month TC = Trace Code185156E–SEEPR–10/08AT24C01B10.Packaging Information10.18P3 – PDIP195156E–SEEPR–10/08AT24C01B10.28S1 – JEDEC SOIC205156E–SEEPR–10/08AT24C01B10.38A2 – TSSOPAT24C01B12.5TS1 – SOT23AT24C01B 13.8U3-1 – dBGA2Revision HistoryDoc. Rev.Date Comments5156E10/2008Modified Ordering Information5156D8/2007Added Part Marking Scheme5156C4/2007Removed NC and GND from Pin Configuration; Removed Preliminary from page 1 and all headers/footers; Added 2-wire Software Reset; Removed LSB and MSB from figures; Removed waffle pack from die sale order information5156B5/2006Ordering information changed; added -B denotes bulk; added bulk ordering codes; added tape and reel ordering codes5156A4/2006Initial document release。

S-24CS01ADP资料

Rev.4.4_00
Table 1 Description Address input (No connection in S-24CS04A/08A*1) Address input (No connection in S-24CS08A*1) Address input Ground Serial data input / output Serial clock input Write protection input 7 WP Connected to VCC: Protection valid Connected to GND: Protection invalid 8 VCC Power supply *1. Connect to GND or VCC. Remark See Dimensions for details of the package drawings. Pin No. 1 2 3 4 5 6 Symbol A0 A1 A2 GND SDA SCL
Features
• Low power consumption Standby : 2.0 µA Max. (VCC=5.5 V) Read : 0.8 mA Max. (VCC=5.5 V) • Operating voltage range Read : 1.8 to 5.5 V (at −40 to +85°C) Write : 2.55 to 5.5 V (at −40 to +85°C) • Page write : 8 bytes / page (S-24CS01A/02A) 16 bytes / page (S-24CS04A/08A) • Sequential read • Operating Frequency : 400 kHz (VCC=5 V±10%, at −40 to +85°C) • Write disable function when power supply voltage is low • Endurance: 107 cycles/word*1 (at +25°C) write capable, 106 cycles/word*1 (at +85°C) 3 × 105 cycles/word*1 (at +105°C) *1. For each address (Word: 8 bits) • Data retention: 10 years (after rewriting 106 cycles/word at +85°C) • S-24CS01A : 1k bit • S-24CS02A : 2k bit • S-24CS04A : 4k bit • S-24CS08A : 8k bit • High-temperature operation : +105°C Max. supported (Only S-24CS0xAFJ-TBH-G, S-24CS0xAFT-TBH-G) • Write protection : 100% • Lead-free product

S-24C01BMFN-TB-F资料

CMOS 2-WIRE SERIAL EEPROMS-24C01B/02B/04BThe S-24C01B/02B/04B are series of 2-wire, low power 1K/2K/4K-bit EEPROMs with a wide operating range. They are organized as 128-word ×8-bit, 256-word ×8-bit, and 512-word ×8-bit, respectively. Each is capable of page write, and sequential read.Pin AssignmentNamePin Number FunctionDIP, SOPMSOPNC 18No Connection*NC 27No Connection*NC 36No Connection*GND 45GroundSDA 54Serial data input/output SCL 63Serial clock inputWP72Write Protection pinConnected to Vcc:Protection valid Connected to GND:Protection invalid V CC81Power supplyPin FunctionsEndurance:10 6cycles/word Data retention:10 yearsWrite protection:S-24C01B : 100%S-24C02B/04B : 50% S-24C01B: 1 Kbits S-24C02B: 2 Kbits S-24C04B:4 KbitsFeaturesLow power consumption Standby: 1.0 µA Max.(V CC =5.5 V)Operating:0.8 mA Max.(V CC =5.5 V)0.3 mA Max.(V CC =3.3 V)Wide operating voltage range 2.0 to 5.5 VPage write8 bytes (S-24C01B, S-24C02B)16 bytes (S-24C04B)Sequential read capable 400KHz (V CC =5V ±10%)S-24C01BMFN S-24C02BMFN S-24C04BMFN8pin MSOP Top view 12348765V CC WP SCL SDANC NC NC GND8-pin DIP Top viewV CC GNDWP SCL NC NC SDANC 12345678S-24C01BDP-1A S-24C02BDP-1A S-24C04BDP-1ANC NC 8-pin SOP Top view V CC SCL SDANC GND65873412WP S-24C01BFJ S-24C02BFJ S-24C04BFJFigure 1Table 1* These pins can be connected to either Vcc or GND.Rev. 2.2CMOS 2-WIRE SERIAL EEPROMS-24C01B/02B/04BTBlock DiagramTAbsolute Maximum RatingsParameter Symbol Ratings Unit Power supply voltageV CC -0.3 to +7.0V Input voltage V IN -0.3 to V CC +0.3V Output voltageV OUT -0.3 to V CC V Storage temperature under biasT bias -50 to +95°C Storage temperatureT stg-65 to +150°CFigure 2V CC GNSerial Clock ControllerDevice Address ComparatorAddress CounterY DecoderData Output ACK Output ControllerHigh-Voltage GeneratorStart/Stop DetectorData registerEEPROMX DecoderSelectorSCL SDAD IND OUTR / WLOADIN COMPLOADWPTable 2CMOS 2-WIRE SERIAL EEPROMS-24C01B/02B/04BT Recommended Operating ConditionsTable 3Parameter Symbol Conditions Min.Typ.Max.UnitPower supply voltage VCC Read Operation 2.0-- 5.5VHigh level input voltage V IH V CC=2.5 to 5.5VV CC=2.0 to 2.5V 0.7×V CC0.8×V CC----V CCV CCVVLow level input voltage V IL V CC=2.5 to 5.5VV CC =2.0 to 2.5V 0.00.0----0.3×V CC0.2×V CCVVOperating temperature T opr---40--+85°CT Pin CapacitanceTable 4(Ta=25 °C, f=1.0 MHz, V CC=5 V) Parameter Symbol Conditions Min.Typ.Max.Unit Input capacitance C IN V IN=0 V (SCL, WP)----10pF Input/output capacitance C I / O V I / O=0 V (SDA)----10pFT EnduranceTable 5Parameter Symbol Min.Typ.Max.UnitEndurance N W10 6----cycles/wordCMOS 2-WIRE SERIAL EEPROMS-24C01B/02B/04B T DC Electrical CharacteristicsTable 6Parameter Symbol Conditions VCC=4.5 to 5.5 V V CC=2.5 to 4.5 V V CC=2.0 to 2.5 V UnitMin.Typ.Max.Min.Typ.Max.Min.Typ.Max.Current consumption(READ)I CC1f=100 kHz----0.8*----0.3----0.2mACurrent consumption(PROGRAM)I CC2f=100 kHz---- 4.0---- 1.5---- 1.5mA* f = 400KHzTable 7Parameter Symbol Conditions V CC=4.5 V to 5.5 V V CC=2.5 to 4.5 V V CC=2.0 to 2.5 V UnitMin.Typ.Max.Min.Typ.Max.Min.Typ.Max.Standby current consumption I SB V IN=V CC or GND---- 1.0----0.6----0.4µAInput leakage current I LI V IN=GND to V CC--0.1 1.0--0.1 1.0--0.1 1.0µAOutput leakagecurrent I LO V OUT=GND to V CC--0.1 1.0--0.1 1.0--0.1 1.0µALow level outputvoltage V OL I OL=3.2 mA----0.4----0.4------VI OL=1.5 mA----0.3----0.3----0.5VCurrent address retention voltage V AH-- 1.5-- 5.5 1.5-- 4.5 1.5-- 2.5VCMOS 2-WIRE SERIAL EEPROMS-24C01B/02B/04BTAC Electrical CharacteristicsTable 9ParameterSymbolV CC =4.5V to 5.5V V CC =2.0V to 4.5V UnitMin.Typ.Max.Min.Typ.Max.SCL clock frequency f SCL 0--4000--100KHz SCL clock time “L”t LOW 1.0---- 4.7----µs SCL clock time “H”t HIGH 0.9---- 4.0----µs SDA output delay time t AA 0.1--0.90.1-- 3.5µs SDA output hold time t DH 50----100----ns Start condition setup time t SU.STA 0.6---- 4.7----µs Start condition hold time t HD.STA 0.6---- 4.0----µs Data input setup time t SU.DAT 100----200----ns Data input hold time t HD.DAT 0----0----ns Stop condition setup time t SU.STO 0.6---- 4.7----µs SCL • SDA rising time t R ----0.3---- 1.0µs SCL • SDA falling time t F ----0.3----0.3µs Bus release time t BUF 1.3---- 4.7----µs Noise suppression timet I----50----100ns Input pulse voltage0.1×V CC to 0.9×V CC Input pulse rising/falling time 20 ns Output judgment voltage 0.5×V CCOutput load100 pF+ Pullup resistance 1.0 K Ω¶Table 8 Measurement ConditionsV CCR=1.0KSDAC=100pFFigure 3 Output Load CircuitFigure 4 Bus TimingSCLSDA INSDA OUTt BUFt Rt SU.STOt SU.DATt HD.DATt DHt AAt HIGH t LOWt HD.STAt SU.STA t FCMOS 2-WIRE SERIAL EEPROMS-24C01B/02B/04BTable 10Item Symbol Min.Typ.Max.Unit Write timet WR-- 4.010.0msTPin Functions1.SDA (Serial Data Input/Output) PinThe SDA pin is used for bilateral transmission of serial data. It consists of a signal input pin and an Nch open-drain transistor output pin.Usually pull up the SDA line via resistance to the V CC , and use it with other open-drain or open-collector output devices connected in a wired OR configuration.2.SCL (Serial Clock Input) PinThe SCL pin is used for serial clock input. It is capable of processing signals at the rising and falling edges of the SCL clock input signal. Make sure the rising time and falling time conform to the specifications.3.WP PinThe WP pin is used for write protection. When there is no need for write protection, connect the pin to the GND; when there is a need for write protection, connect the pin to the Vcc.Please refer Application Note “S-24C series EEPROMs Tips, Tricks & Traps” for equivalent circuit of each pin.Figure 5 Write CycleSCLSDAD0Write dataAcknowledgeStop condition Start conditiont WRCMOS 2-WIRE SERIAL EEPROMS-24C01B/02B/04BOperation1.Start ConditionWhen the SCL line is “H” the SDA line changes from “H” to “L”. This allows the device to go to the start condition.All operations begin from the start condition.2.Stop ConditionWhen the SCL line is “H” the SDA line changes from “L” to “H”. This allows the device to go to the stop condition.When the device receives the stop condition signal during a read sequence, the read operation is interrupted,and the device goes to standby mode.When the device receives the stop condition signal during write sequence, the retrieval of write data is halted,and the EEPROM initiates rewrite.3.Data TransmissionChanging the SDA line while the SCL line is “L” allows the data to be transmitted. A start or stop condition is recognized when the SDA line changes while the SCL line is “H”.Figure 6 Start/Stop Conditionst SU.STAt HD.STAt SU.STOStartConditionStopConditionSCLSDAFigure 7 Data Transmission Timingt SU.DATt HD.DATSCLSDACMOS 2-WIRE SERIAL EEPROMS-24C01B/02B/04B4.AcknowledgmentThe unit of data transmission is 8 bits. By turning the SDA line “L” the slave device mounted on the system bus which receives the data during the 9th clock cycle outputs the acknowledgment signal verifying the data reception.When the EEPROM is rewriting, the device does not output the acknowledgment signal.5.Device AddressingTo perform data communications, the master device mounted on the system outputs the start condition signal to the slave device. Next, the master device outputs 7-bit length device address and a 1-bit length read/write instruction code onto the SDA bus.Upper 4 bits of the device address are called the “Device Code”, and set to “1010”. Successive 3 bits are “don’t care” bits.When the comparison results match, the slave device outputs the acknowledgment signal during the 9th clock cycle.In the S-24C04A, 7th bit becomes “P0”. “P0” is a page address bit and is equivalent to an additional uppermost bit of the word address. Accordingly, when P0=”0”, the former half area corresponding to 2 kbits (addresses from 000h to 0FFh) in the entire memory are selected; when P0=”1”, the latter half area corresponding to 2 kbits (addresses from 100h to 1FFh) in all areas of the memory are selected.Figure 8 Acknowledgment Output Timing189Acknow-ledgment Outputt AAt DHStartConditionSCL (EEPROMSDA(Master Output)SDA(EEPROM Output)Figure 9 Device AddressDon’t care11xxxR/WDevice CodeS-24C01BS-24C02BMSBLSBLSB1010x x x R/W 101xxP0R/W S-24C04BMSBDevice CodeDon’t carePage AddressCMOS 2-WIRE SERIAL EEPROMS-24C01B/02B/04B6.Write 6.1Byte WriteWhen the EEPROM receives a 7-bit length device address and a 1-bit read/write instruction code “0”,following the start condition signal, it outputs the acknowledgment signal. Next, when the EEPROM receives an 8-bit length word address, it outputs the acknowledgment signal.After the EEPROM receives 8-bit write data and outputs the acknowledgment signal, it receives the stop condition signal. Next, the EEPROM at the specified memory address starts to rewrite.When the EEPROM is rewriting, all operations are prohibited and the acknowledgment signal is not output.6.2Page WriteUp to 8 bytes per page can be written in the S-24C01B and S-24C02B.Up to 16 bytes per page can be written in the S-24C04B.Basic data transmission procedures are the same as those in the “Byte Write”. However, when the EEPROM receives 8-bit write data which corresponds to the page size, the page can be written.When the EEPROM receives a 7-bit length device address and a 1-bit read/write instruction code “0”,following the start condition signal, it outputs the acknowledgment signal. When the EEPROM receives an 8-bit length word address, it outputs the acknowledgment signal.After the EEPROM receives 8-bit write data and outputs the acknowledgment signal, it receives 8-bit write data corresponding to the next word address, and outputs the acknowledgment signal. The EEPROM repeats reception of 8-bit write data and output of the acknowledgment signal in succession. It is capable of receiving write data corresponding to the maximum page size.When the EEPROM receives the stop condition signal, it starts to rewrite, corresponding to the size of the page, on which write data, starting from the specified memory address, is received.Figure 10 Byte WriteS T A R T1010W R I T ES T O PDEVICE ADDRESS WORD ADDRESS DATAR /W M S BSDA LINEADR INC (ADDRESS INCREMENT)x x P0W7W6W5W4W3W2W1W0D7D6D5D4D3D2D1D0A C KL S B A C KA C KW7 is optional in the S-24C01B.P0 is ‘don’t care’in the S-24C01B/02B.CMOS 2-WIRE SERIAL EEPROMS-24C01B/02B/04BIn the S-24C01B or S-24C02B, the lower 3 bits of the word address are automatically incremented each when the EEPROM receives 8-bit write data.Even if the write data exceeds 8 bytes, the upper 5 bits at the word address remain unchanged, the lower 3 bits are rolled over and overwritten.In the S-24C04B, the lower 4 bits at the word address are automatically incremented each when the EEPROM receives 8 bit write data.Even when the write data exceeds 16 bytes, the upper 4 bits of the word address and page address P0 remain unchanged, and the lower 4 bits are rolled over and overwritten.6.3Acknowledgment PollingAcknowledgment polling is used to know when the rewriting of the EEPROM is finished.After the EEPROM receives the stop condition signal and once it starts to rewrite, all operations are prohibited.Also, the EEPROM cannot respond to the signal transmitted by the master device.Accordingly, the master device transmits the start condition signal and the device address read/write instruction code to the EEPROM (namely, the slave device) to detect the response of the slave device. This allows users to know when the rewriting of the EEPROM is finished.That is, if the slave device does not output the acknowledgment signal, it means that the EEPROM is rewriting;when the slave device outputs the acknowledgment signal, you can know that rewriting has been completed. It is recommended to use read instruction “1” for the read/write instruction code transmitted by the master device.6.4Write ProtectionThe S-24C01B/02B/04B are capable of protecting the memory. When the WP pin is connected to V CC ,writing to all memory area is prohibite in the S-24C01B, writing to 50% of the latter half of memory area isprohibited in the S-24C02B and S-24C04B. (prohibited adress are 080h to 0FFh in the S-24C02B; 100h to 1FFh in the S-24C04B) Even when writing is prohibited, since the controller inside the IC is operating, the response to the signal transmitted by the master device is not available during the time of writing (t WR ).When the WP pin is connected to GND, the write protection becomes invalid, and writing in all memory area becomes available. However, when there is no need for using write protection, always connect the WP pin to GND.Figure 11 Page WriteS T A R T1010W R I T E S T O PDEVICE ADDRES WORD ADDRESS (n)DATA (n)R /W M S BSDA LINEADR INCxx P0W7W6W5W4W3W2W1W0D7D6D5D4D3D2D1D0A C KL S B A C KA C K 0D7D0D7D0ADR INCA C K ADR INCA C KDATA (n+1)DATA (n+x)W7 is optional in the S-24C01B.P0 is ‘don’t care’ in the S-24C01B/02B.CMOS 2-WIRE SERIAL EEPROMS-24C01B/02B/04BSeiko Instruments Inc.117.Read7.1Current Address ReadThe EEPROM is capable of storing the last accessed memory address during both writing and reading. The memory address is stored as long as the power voltage is more than the retention voltage V AH .Accordingly, when the master device recognizes the position of the address pointer inside the EEPROM,data can be read from the memory address of the current address pointer without assigning a word address.This is called “Current Address Read”.“Current Address Read” is explained for when the address counter inside the EEPROM is an “n” address.When the EEPROM receives a 7-bit length device address and a 1-bit read/write instruction code “1”,following the start condition signal, it outputs the acknowledgment signal. However, in the S-24C04B, page address P0 becomes invalid, and the memory address of the current address pointer becomes valid.Next, 8-bit length data at an “n” address is output from the EEPROM, in synchronization with the SCL clock.The address counter is incremented at the falling edge of the SCL clock by which the 8th bit of data is output,and the address counter goes to address n+1.The master device does not output the acknowledgment signal and transmits the stop condition signal to finish reading.For recognition of the address pointer inside the EEPROM, take into consideration the following:The memory address counter inside the EEPROM is automatically incremented for every falling edge of the SCL clock by which the 8th bit of data is output during the time of reading. During the time of writing, upper bits of the memory address (upper 5 bits of the word address in the S-24C01B and S-24C02B; upper 4 bits of the word address and page address P0 in the S-24C04B) are left unchanged and are not incremented.Figure 12 Current Address ReadS T A R T1010R E A D S T O PDEVICE ADDRES R /W M S BSDA LINEADR INCx xP0D7D6D5D4D3D2D1D0A C KL S B 1DATANO ACK from Master Device(P0 is ‘don’t care’ in the S-24C01B/02B)CMOS 2-WIRE SERIAL EEPROMS-24C01B/02B/04BSeiko Instruments Inc.127.2Random ReadRandom read is a mode used when the data is read from arbitrary memory addresses.To load a memory address into the address counter inside the EEPROM, first perform a dummy write according to the following procedures:When the EEPROM receives a 7-bit length device address and a 1-bit read/write instruction code “0”,following the start condition signal, it outputs the acknowledgment signal.Next, the EEPROM receives an 8-bit length word address and outputs the acknowledgment signal. Last, the memory address is loaded into the address counter of the EEPROM.the EEPROM receives the write data during byte or page writing. However, data reception is not performed during dummy write.The memory address is loaded into the memory address counter inside the EEPROM during dummy write. After that, the master device can read the data starting from the arbitrary memory address by transmitting a new start condition signal and performing the same operation as that in the “Current Read”.That is, when the EEPROM receives a 7-bit length device address and a 1-bit read/write instruction code “1”,following the start condition signal, it outputs the acknowledgment signal.Next, 8-bit length data is output from the EEPROM, in synchronization with the SCL clock. The master device does not output an acknowledgment signal and transmits the stop condition signal to finish reading.Figure 13 Random ReadS T A R T1010W R I T ES T O PDEVICE ADDRES WORD ADDRESS (n)R /W M S BSDA LINExx P0W7W6W5W4W3W2W1W0A C KL S B A C KA C K1010xx P01D7D6D5D4D3D2D1D0DATA (n)DUMMY WRITEDEVICE ADDRES R E A DNO ACK from Master DeviceADRS T A R TW7 is optional in the S-24C01B.P0 is ‘don’t care’ in the S-24C01B/02B.CMOS 2-WIRE SERIAL EEPROMS-24C01B/02B/04BSeiko Instruments Inc.137.3Sequential ReadWhen the EEPROM receives a 7-bit length device address and a 1-bit read/write instruction code “1” in both current and random read operations, following the start condition signal, it outputs the acknowledgment signal.When 8-bit length data is output from the EEPROM, in synchronization with the SCL clock, the memory address counter inside the EEPROM is automatically incremented at the falling edge of the SCL clock, by which the 8th data is output.When the master device transmits the acknowledgment signal, the next memory address data is output.When the master device transmits the acknowledgment signal, the memory address counter inside the EEPROM is incremented and read data in succession. This is called “Sequential Read”.When the master device does not output an acknowledgement signal and transmits the stop condition signal, the read operation is finished.Data can be read in the “Sequential Read” mode in succession. When the memory address counter reaches the last word address, it rolls over to the first memory address.Figure 14 Sequential ReadR E A D S T O PDEVICE ADDRESR /W ADR INC D7D0A C KA C KA C K 1D7D0ADR INC A C K ADR INCSDA LINEDATA (n)D7D0D7D0DATA (n+1)DATA (n+2)DATA (n+x)NO ACK from Master DeviceADR INCCMOS 2-WIRE SERIAL EEPROMS-24C01B/02B/04BSeiko Instruments Inc.148.Address Increment TimingThe address increment timing is as follows. See Figures 15 and 16. During reading operation, the memory address counter is automatically incremented at the falling edge of the SCL clock (the 8th read data is output).During writing operation, the memory address counter is also automatically incremented at the falling edge of the SCL clock when the 8th bit write data is fetched.Figure 15 Address Increment Timing During ReadingSCLSDA R / W=1Address Increment89189D7 Output D0 OutputACK OutputFigure 16 Address Increment Timing During WritingSCLSDA R / W=089189D7 Input D0 Input ACK Output ACK OutputAddress IncrementPurchase of I 2C components of Seiko Instruments Inc. conveys a license under the Philips I 2C Patent Rights to use these components in an I 2C system, provided that the system conforms to the I 2C Standard Specification as defined by Philips.Please note that any product or system incorporating this IC may infringe upon the Philips I 2C Bus Patent Rights depending upon its configuration.In the event that such product or system incorporating the I 2C Bus infringes upon the Philips Patent Rights, Seiko Instruments Inc. shall not bear any responsibility for any matters with regard to and arising from such patent infringement.CMOS 2-WIRE SERIAL EEPROMS-24C01B/02B/04BSeiko Instruments Inc.15T Ordering InformationS-24C0xB yy - zz - wP code (Distincion for package process)None F S 1A Taping specification None (for DIP)TB Package codeDP :DIP FJ :SOP MFN:MSOPProduct nameS-24C01B :1k bits S-24C02B :2k bits S-24C04B :4k bitsProduct name Package code Taping specification P code Package/Tape/ReeldrawingsNone DP008-A -FDP008-E S-24C01B DPNone -S DP008-A DP008-E S-24C02B -1A DP008-C S-24C04BNoneFJ008-D FJ-TB -F FJ008-E -SFJ008-D FJ008-E MFN-TB NoneFN008-ANote1) Package dimensions of SOPs whose package codes are FJ and DFJ are the same in the range of deviation.2) Please contact an SII local office or a local representative for details.CMOS 2-WIRE SERIAL EEPROMS-24C01B/02B/04BSeiko Instruments Inc.16Characteristics1.DC Characteristics1.1Current consumption (READ) I CC1 --Ambient temperature Ta1.2Current consumption (READ) I CC1 --Ambient temperature Ta1.3Current consumption (READ) I CC1 --Ambient temperature Ta1.4Current consumption (READ) I CC1 --Power supply voltage V CC1.5Current consumption (READ) I CC1 -- Power supply voltage V CC1.6Current consumption (READ) I CC1 --Clock frequency fscl1.7Current consumption (PROGRAM) I CC2 --Ambient temperature Ta1.8Current consumption (PROGRAM) I CC2 --Ambient temperature TaTa (°C)200100V CC =5.5 V fscl=100 KHz DATA=0101-4085ICC1(µA)Ta (°C)200100V CC =3.3 V fscl=100 KHz DATA=0101-4085ICC1(µA)Ta (°C)4020V CC =1.8 V fscl=100 KHz DATA=0101-4085ICC1(µA)10050234567Ta=25 °C fscl=100 KHz DATA=0101V CC (V)ICC1(µA)200100234567Ta=25 °C fscl=400 KHz DATA=0101V CC (V)200100ICC1(µA)V CC =5.0 V Ta=25 °C100K 200K fscl(Hz)ICC1(µA)300K 400KTa ( °C)1.00.5V CC =5.5 V-40085ICC2(mA)Ta ( °C)1.00.5V CC =3.3 V-40085ICC2(mA)CMOS 2-WIRE SERIAL EEPROMS-24C01B/02B/04BSeiko Instruments Inc.171.10Current consumption (PROGRAM) I CC2 --Power supply voltage V CC1.11Standby current consumption I SB -- Ambient temperature Ta1.12Input leakage current I LI --Ambient temperature Ta1.13Input leakage current I LI --Ambient temperature Ta1.14Output leakage current I LO --Ambient temperature Ta1.15Output leakage current I LO --Ambient temperature Ta1.9Current consumption (PROGRAM) I CC2 --Ambient temperature TaTa ( °C)1.00.5V CC =2.5 V-40085ICC2(mA)1.00.5234567Ta=25 °C V CC (V)V CC (V)ICC2(mA)10-610-710-810-910-10V CC =5.5 V10-11Ta ( °C)-40085Ta ( °C)1.00.5V CC =5.5 VSDA, SCL, WP=0V 0-40085ILI (µA)ISB (A)Ta ( °C)1.00.5V CC =5.5 V SDA=0V-4085ILO (µA)Ta ( °C)1.00.5-40085V CC =5.5 VSDA,SCL,WP=5.5V ILI (µA)Ta ( °C)1.00.5V CC =5.5 V SDA=5.5 V-40085ILO (µA)1.16Low level output voltage V OL --Low level output current I OL0.20.1123456V CC =3.3 VV CC =5V Ta=25 °C VOL (V)CMOS 2-WIRE SERIAL EEPROMS-24C01B/02B/04BSeiko Instruments Inc.181.21High input inversion voltage VIH --Power supply voltageV CC1.17Low level output voltage V OL --Ambient temperature Ta1.18Low level output voltage V OL --Ambient temperature Ta1.19Low level output current I OL --Ambient temperature Ta1.20Low level output current I OL --Ambient temperature Ta1.22High input inversion voltage VIH --Ambient temperature Ta1.23Low input inversion voltage VIL --Power supply voltageV CC1.24Low input inversion voltage VIL --Ambient temperature TaTa ( °C)0.30.2V CC =4.5 V I OL =3.2 mA-40085VOL (V)0.1Ta ( °C)0.30.2V CC =1.8 V I OL =100 µA-40085VOL (V)0.1Ta ( °C)2010V CC =4.5 V V OL =0.45 V-40085IOL (mA)Ta ( °C)2.01.0V CC =1.8 V V OL =0.1 V-40085IOL (mA)Ta=25 °CSDA, SCL, WP 1.002.03.0VIH (V)1234567V CC (V)V CC =5.0 VSDA, SCL, WP1.002.03.0VIH (V)Ta ( °C)-40085Ta=25 °CSDA, SCL, WP 1.002.03.0VIL (V)1234567V CC (V)1.002.03.0VIL (V)Ta ( °C)-4085Ta=5.0VSDA, SCL, WPCMOS 2-WIRE SERIAL EEPROMS-24C01B/02B/04BSeiko Instruments Inc.192.AC Characteristics2.1 Maximum operating frequency fmax -- Power supply voltage V CC2.2Write time t WR --Power supply voltage V CC2.3Write time t WR --Ambient temperature Ta2.4Write time t WR --Ambient temperature Ta2.5SDA output delay time t AA --Ambient temperature Ta2.6SDA output delay time t AA --Ambient temperature Ta2.7Data output delay time t AA --Ambient temperature Ta10K2345Ta=25 °CV CC (V)fmax (Hz)142234567Ta=25 °CV CC (V)tWR (ms)1100K1M13Ta ( °C)64V CC =4.5 V-400852tWR (ms)Ta ( °C)64V CC =2.5 V-400852tWR (ms)Ta ( °C)1.51.0V CC =4.5 V-400850.5tAA (µs)Ta ( °C)1.51.0V CC =2.7 V-400850.5tAA (µs)Ta ( °C)3.02.0V CC =1.8 V-400851.0tAA (µs)。

24c01程序控制及原理图

/**************************************************;功能描述：;PC端发送3个数据n0,n1,n2;n0=0,写，将n1写入n2地址中;n0=1，读，读出n1地址中的数据，n2不起作用，但必须有;收到一个字节后，将其地址值显示在数码管第1、2位上，数值显示在第5、6位上;读出一个字节后，将其地址值显示在数码管第1、2位上，读出的值显示在第5、6位上;**************************************************/#include "pic.h"#define uchar unsigned char#define uint unsigned int#define Hidden 16__CONFIG(HS&WDTDIS&LVPDIS); //配置文件，设置为HS方式振荡，禁止看门狗,低压编程关闭ucharDispTab[]={0xC0,0xF9,0xA4,0xB0,0x99,0x92,0x82,0xF8,0x80,0x90,0x88,0x83,0xC6,0xA1,0x8 6,0x8E,0xFF};uchar BitTab[]={0xfb,0xfd,0xfe};uchar DispBuf[6];bit Rec; //接收到数据的标志uchar RecBuf[3]; //接收缓冲区#define SCL_CNT TRISC3#define SDA_CNT TRISC4void mDelay(uint DelayTime){ uint temp;for(;DelayTime>0;DelayTime--){ for(temp=0;temp<270;temp++){;}}}void interrupt Int_Process(){ static uchar dCount; //用作显示的计数器static uchar Count; //用作接收缓冲区计数if(TMR1IF==1&&TMR1IE==1) //定时器T1中断{TMR1H=-(12000/256);TMR1L=-(12000%256); //重置定时初值PORTA|=0x07; //关前面的显示PORTE|=0X07; //关前面的显示PORTD=DispTab[DispBuf[dCount]]; //显示第i位显示缓冲区中的内容if(dCount<3)PORTE&=BitTab[dCount]; //第1~3位是由PORTE控制的elsePORTA&=BitTab[dCount-3]; //第4~6位是由PORTA的低3位控制的dCount++;if(dCount==6)dCount=0;TMR1IF=0; //清中断标志}else if(TXIE&TXIF) //串行发送中断{if(TRMT)TXEN=0; //停止发送}else if(RCIE&RCIF) //串行接收中断{RecBuf[Count]=RCREG-0x30;Count++;if(Count>=3){ Count=0;Rec=1; //置位标志}}}void Idle(void) //I2C 空闲检测{while((SSPCON2 & 0x1F)|(STAT_RW))continue;}void WrToRom(uchar Data[], uchar Address,uchar Num){ uchar i;SEN = 1; //发送起始命令while(SEN); //SEN被硬件自动清零前循环等待SSPBUF = 0b10100000; //控制字送入SSPBUFIdle(); //空闲检测if(!ACKSTAT); //是否有应答？else //ACKSTA T=1从器件无应答，直接返回return ;SSPBUF=Address; //地址送入SSPBUFIdle(); //I2C空闲检测if(!ACKSTAT); //应答位检测，ACKSTAT＝0从器件有应答else //ACKSTA T=1从器件无应答，直接返回return ;for(i=0;i<Num;i++){SSPBUF = Data[i]; //数据送入SSPBUFIdle(); //空闲检测if(!ACKSTAT); //应答位检测，ACKSTAT＝0从器件有应答else //ACKSTA T=1从器件无应答，直接返回return ;}PEN = 1; //初始化重复停止位while(PEN); //PEN被硬件自动清零之前循环//EEPROM内部写周期一般为3ms~10ms,主机必须查询内部写入过程是否结束for(;;){ SEN=1; //发送起始位while(SEN); //SEN被硬件自动清零前循环等待SSPBUF=0b10100000; //控制字送入SSPBUFIdle(); //空闲检测PEN=1; //发送停止位while(PEN); //PEN被硬件自动清零前循环if(!ACKSTAT) //应答位检测，ACKSTAT＝0从器件有应答break; //ACKSTA T=1从器件无应答，直接返回}}void RdFromRom(uchar Data[],uchar Address,uchar Num){ uchar i;SEN = 1; //发送起始信号while(SEN); //SEN被硬件自动清零前循环等待SSPBUF = 0b10100000; //写控制字送入SSPBUFIdle(); //空闲检测if(!ACKSTAT); //应答位检测，ACKSTAT＝0从器件有应答else //ACKSTA T=1从器件无应答，直接返回return ;SSPBUF = Address; //地址送入SSPBUFIdle(); //空闲检测if(!ACKSTAT); //应答位检测，ACKSTAT＝0从器件有应答else //ACKSTA T=1从器件无应答，直接返回return ;for(i=0;i<Num;i++){RSEN = 1; //重复START状态while(RSEN); //等待START状态结束SSPBUF = 0b10100001; //读数据的控制字送入SSPBUFIdle(); //空闲检测if(!ACKSTAT); //应答位检测，ACKSTAT＝0从器件有应答else //ACKSTA T=1从器件无应答，直接返回return ;RCEN = 1; //允许接收while(RCEN); //等待接收结束ACKDT = 1; //接收结束后不发送应答位ACKEN = 1; //while(ACKEN); //ACKEN被硬件自动清零之前不断循环Data[i]= SSPBUF; //数据写入SSPBUF}PEN = 1; //发送停止位while(PEN); //PEN被硬件自动清零前循环}void Init_Ser(){ SYNC=0; //选择异步通信模式BRGH=1; //选择高速波特率发生模式SPEN=1; //串行通信端口打开CREN=1; //开启异步通信的接收功能RCIE=1; //允许接收中断SPBRG=38; //设置波特率为19.2K，12M，高速模式}void Init_IO(){ ADCON1=0x06; //设定为数字端口TRISA&=0xf8; //PORTA 0~2设为输出TRISE&=0xf8; //PORTE 0~2设为输出TRISD=0; //PORTD 设为输出TRISC&=0xbf; //RC6引脚为输出TRISC|=0x80; //RC7引脚作为输入//////////////////Timer1 设置TMR1CS=0; //将T1设为定时器TMR1ON=1; //启动T1TMR1IE=1;//////////////////中断控制GIE=1; //总中断允许PEIE=1; //外围部件中断允许}void main(){ uchar RomDat[4];Init_IO(); //初始化端口Init_Ser(); //初始化串行口DispBuf[2]=Hidden;DispBuf[3]=Hidden;SSPADD=29; //在晶振11.0592M时，波特率约为100K SSPIE=0; //禁止SSPIF中断SSPCON=0B00101000; //SSPEN＝1，I2C主模式for(;;){DispBuf[0]=RecBuf[1]/16;DispBuf[1]=RecBuf[1]%16;if(Rec) //接收到数据{ Rec=0; //清除标志if(RecBuf[0]==0) //第一种功能，写入{ RomDat[0]=RecBuf[2];DispBuf[4]=RomDat[0]/16;DispBuf[5]=RomDat[0]%16;WrToRom(RomDat,RecBuf[1],1);TXREG=RomDat[0];TXEN=1; //启动发送}else{ RdFromRom(RomDat,RecBuf[1],1);DispBuf[4]=RomDat[0]/16;DispBuf[5]=RomDat[0]%16;TXREG=RomDat[0];TXEN=1; //启动发送}}}}。

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IS24C01IS24C02IS24C04IS24C08IS24C16ISSI®Copyright © 2004 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.1K-bit/2K-bit/4K-bit/8K-bit/16K-bit 2-WIRE SERIAL CMOS EEPROMMARCH 2004DESCRIPTIONThe IS24CXX (refers to IS24C01, IS24C02, IS24C04,IS24C08, IS24C16) family is a low-cost and low voltage 2-wire Serial EEPROM. It is fabricated using ISSI’s advanced CMOS EEPROM technology and provides a low power and low voltage operation. The IS24CXX family features a write protection feature, and is available in 8-pin DIP and 8-pin SOIC packages.The IS24C01 is a 1K-bit EEPROM; IS24C02 is a 2K-bit EEPROM; IS24C04 is a 4K-bit EEPROM; IS24C08 is a 8K-bit EEPROM; IS24C16 is a 16K-bit EEPROM.The IS24C01 and IS24C02 are available in 8-pin MSOP package. The IS24C01, IS24C02, IS24C04, and IS24C08are available in 8-Pin TSSOP package.Automotive data is preliminary.The devices IS24C04, IS24C08, and IS24C16 are not recommended for new designs. Please refer to IS24C04A,IS24C08A, and IS24C16A.FEATURES•Low Power CMOS Technology–Standby Current less than 8 µA (5.5V)–Read Current (typical) less than 1 mA (5.5V)–Write Current (typical) less than 3 mA (5.5V)•Flexible Voltage Operation–Vcc = 1.8V to 5.5V for –2 version –Vcc = 2.5V to 5.5V for –3 version •400 KHz (I 2C Protocol) Compatibility •Hardware Data Protection–Write Protect Pin •Sequential Read Feature•Filtered Inputs for Noise Suppression •8-pin PDIP and 8-pin SOIC packages •8-pin TSSOP (1K,2K, 4K & 8K only)•8-pin MSOP (1K,2K only)•Self time write cycle with auto clear 5 ms @ 2.5V •Organization:–IS24C01128x8(one block of 128 bytes)–IS24C02256x8(one block of 256 bytes)–IS24C04512x8(two blocks of 256 bytes)–IS24C081024x8(four blocks of 256 bytes)–IS24C162048x8(eight blocks of 256 bytes)•Page Write Buffer•Two-Wire Serial Interface–Bi-directional data transfer protocol •High Reliability–Endurance: 1,000,000 Cycles –Data Retention: 100 Years•Commercial, Industrial and Automotive tempera-ture ranges元器件交易网元器件交易网IS24C01IS24C02IS24C04IS24C08 IS24C16ISSI®FUNCTIONAL BLOCK DIAGRAM2Integrated Silicon Solution, Inc. — — 1-800-379-4774Rev.FIS24C01IS24C02IS24C04IS24C08 IS24C16ISSI®PIN DESCRIPTIONSA0-A2Address InputsSDA Serial Address/Data I/O SCL Serial Clock Input WP Write Protect Input Vcc Power Supply GNDGroundSCLThis input clock pin is used to synchronize the data transfer to and from the device.SDAThe SDA is a Bi-directional pin used to transfer addresses and data into and out of the device. The SDA pin is an open drain output and can be wire-Ored with other open drain or open collector outputs.The SDA bus requires a pullup resistor to Vcc.A0, A1, A2The A0, A1 and A2 are the device address inputs. The IS24C01 and IS24C02 use the A0, A1, and A2 for hardware addressing and a total of 8 devices may be used on a single bus system.PIN CONFIGURATION8-Pin DIP and SOIC8 Pin TSSOP (1K, 2K, 4K and 8K)8-Pin MSOP (1K, 2K)12348765A0A1A2GNDVCC WP SCL SDAThe IS24C04 uses A1 and A2 pins for hardwire addressing and a total of four devices may be addressed on a single bus system.The A0 pin is not used by IS24C04. This pin can be left floating or tied to GND or Vcc.The IS24C08 only use A2 input for hardwire addressing and a total of two devices may be addressed on a single bus system.The A0 and A1 pins are not used by IS24C08. They may be left floating or tied to either GND or Vcc.These pins are not used by IS24C16. A0 and A1 may be left floating or tied to either GND or Vcc. A2 should be tied to either GND or Vcc.WPWP is the Write Protect pin. On the 24C01, 24C02, IS24C04and 24C08, if the WP pin is tied to V CC the entire array becomes Write Protected (Read only). On the 24C16, if the WP pin is tied to Vcc the upper half array becomes Write Protected (Read only). When WP is tied to GND or left floating normal read/write operations are allowed to the device.元器件交易网IS24C01IS24C02IS24C04IS24C08 IS24C16ISSI®DEVICE OPERATIONThe IS24CXX family features a serial communication and supports a bi-directional 2-wire bus transmission protocol. 2-WIRE BUSThe two-wire bus is defined as a Serial Data line(SDA), and a Serial Clock Line (SCL). The protocol defines any device that sends data onto the SDA bus as a transmitter, and the receiving devices as a receiver. The bus is controlled by MASTER device which generates the SCL, controls the bus access and generates the STOP and START conditions. The IS24CXX is the SLAVE device on the bus.THE BUS PROTOCOL:--Data transfer may be initiated only when the bus is not busy--During a data transfer, the data line must remain stable whenever the clock line is high. Any changes in the data line while the clock line is high will be interpreted as a START or STOP condition.The state of the data line represents valid data when after a START condition, the data line is stable for the duration of the HIGH period of the clock signal. The data on the line must be changed during the LOW period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a START condition and terminated with a STOP condition.START CONDITIONThe START condition precedes all commands to the devices and is defined as a HIGH to LOW transition of SDA when SCL is HIGH. The IS24CXX monitors the SDA and SCL lines and will not respond until the START condition is met.STOP CONDITIONThe STOP condition is defined as a LOW to HIGH transition of SDA when SCL is HIGH. All operations must end with a STOP condition.ACKNOWLEDGEAfter a successful data transfer, each receiving device is required to generate an acknowledge. The Acknowledging device pulls down the SDA line.DEVICE ADDRESSINGThe MASTER begins a transmission by sending a START condition. The MASTER then sends the address of the particular slave devices it is requesting. The SLAVE address is 8 bytes.The four most significant bytes of the address are fixed as 1010 for the IS24CXX.For the IS24C16, the bytes(B2, B1 and B0) are used for memory page addressing (the IS24C16 is organized as eight blocks of 256 bytes).For the IS24C04 out of the next three bytes, B0 is for Memory Page Addressing (the IS24C04 is organized as two blocks of 256 bytes) and A2 and A1 bytes are used as device address bytes and must compare to its hard-wire inputs pins (A2 and A1). Up to four IS24C04's may be individually addressed by the system. The page addressing bytes for IS24Cxx should be considered the most significant bytes of the data word address which follows.For the IS24C08 out of the next three bytes, B1 and B0 are for memory page addressing (the IS24C08 is organized as four blocks of 256 bytes) and the A2 bit is used as device address bit and must compare to its hard-wired input pin (A2). Up to two IS24C08 may be individually addressed by the system. The page addressing bytes for IS24CXX should be considered the most significant bytes of the data word address which follows.For the IS24C01 and IS24C02, the A0, A1, and A2 are used as device address bytes and must compare to its hard-wired input pins (A0, A1, and A2) Up to Eight IS24C01 and/ or IS24C02's may be individually addressed by the system. The last bit of the slave address specifies whether a Read or Write operation is to be performed. When this bit is set to 1, a Read operation is selected, and when set to 0, a Write operation is selected.After the MASTER sends a START condition and the SLAVE address byte, the IS24CXX monitors the bus and responds with an Acknowledge (on the SDA line) when its address matches the transmitted slave address. The IS24CXX pulls down the SDA line during the ninth clock cycle, signaling that it received the eight bytes of data. The IS24CXX then performs a Read or Write operation depending on the state of the R/W bit.WRITE OPERATIONBYTE WRITEIn the Byte Write mode, the Master device sends the START condition and the slave address information(with the R/W set to Zero) to the Slave device. After the Slave generates an acknowledge, the Master sends the byte address that is to be written into the address pointer of the IS24CXX. After receiving another acknowledge from the Slave, the Master device transmits the data byte to be written into the address memory location. The IS24CXX acknowledges once more and the Master generates the STOP condition, at which time the device begins its internal programming cycle. While this internal cycle is in progress, the device will not respond to any request from the Master device.元器件交易网4Integrated Silicon Solution, Inc. — — 1-800-379-4774Rev.FIS24C01IS24C02IS24C04IS24C08 IS24C16ISSI®condition and the IS24CXX discontinues transmission. If 'n' is the last byte of the memory, then the data from location '0' will be transmitted. (Refer to Current Address Read Diagram.)RANDOM ADDRESS READSelective READ operations allow the Master device to select at random any memory location for a READ operation.The Master device first performs a 'dummy' write operation by sending the START condition, slave address and word address of the location it wishes to read. After the IS24CXX acknowledge the word address, the Master device resends the START condition and the slave address, this time with the R/W bit set to one. The IS24CXX then responds with its acknowledge and sends the data requested. The master device does not send an acknowledge but will generate a STOP condition. (Refer to Random Address Read Diagram.)SEQUENTIAL READSequential Reads can be initiated as either a Current Address Read or Random Address Read. After the IS24CXX sends initial byte sequence, the master device now responds with an ACKnowledge indicating it requires additional data from the IS24CXX. The IS24CXX continues to output data for each ACKnowledge received. The master device terminates the sequential READ operation by pulling SDA HIGH (no ACKnowledge) indicating the last data word to be read, followed by a STOP condition.The data output is sequential, with the data from address n followed by the data from address n+1, ... etc.The address counter increments by one automatically,allowing the entire memory contents to be serially read during sequential read operation. When the memory address boundary (127 for IS24C01; 255 for IS24C02; 511 for IS24C04; 1023 for IS24C08; 2047 for IS24C16) is reached,the address counter “rolls over” to address 0, and the IS24CXX continues to output data for each ACKnowledge received. (Refer to Sequential Read Operation Starting with a Random Address READ Diagram.)PAGE WRITEThe IS24CXX is capable of page-WRITE (8-byte for 24C01/02 and 16-byte for 24C04/08/16) operation. A page-WRITE is initiated in the same manner as a byte write, but instead of terminating the internal write cycle after the first data word is transferred, the master device can transmit up to N more bytes (N=7 for 24C01/02 and N=15 for 24C04/08/16). After the receipt of each data word, the IS24CXX responds immediately with an ACKnowledge on SDA line, and the three lower (24C01/24C02) or four lower (24C04/24C08/24C16) order data word address bits are internally incremented by one, while the higher order bits of the data word address remain constant. If the master device should transmit more than N+1 (N=7 for 24C01/02 and N=15 for 24C04/08/16) words, prior to issuing the STOP condition,the address counter will “roll over,” and the previously written data will be overwritten. Once all N+1 (N=7 for 24C01/02 and N=15 for 24C04/08/16) bytes are received and the STOP condition has been sent by the Master, the internal programming cycle begins. At this point, all received data is written to the IS24CXX in a single write cycle. All inputs are disabled until completion of the internal WRITE cycle.ACKNOWLEDGE POLLINGThe disabling of the inputs can be used to take advantage of the typical write cycle time. Once the stop condition is issued to indicate the end of the host's write operation, the IS24CXX initiates the internal write cycle. ACK polling can be initiated immediately. This involves issuing the start condition followed by the slave address for a write operation.If the IS24CXX is still busy with the write operation, no ACK will be returned. If the IS24CXX has completed the write operation, an ACK will be returned and the host can then proceed with the next read or write operation.READ OPERATIONREAD operations are initiated in the same manner as WRITE operations, except that the read/write bit of the slave address is set to “1”. There are three READ operation options: current address read, random address read and sequential read.CURRENT ADDRESS READThe IS24CXX contains an internal address counter which maintains the address of the last byte accessed, incremented by one. For example, if the previous operation is either a read or write operation addressed to the address location n,the internal address counter would increment to address location n+1. When the IS24CXX receives the Device Addressing Byte with a READ operation (read/write bit set to “1”), it will respond an ACKnowledge and transmit the 8-bit data word stored at address location n+1. The master will not acknowledge the transfer but does generate a STOP元器件交易网元器件交易网IS24C01IS24C02IS24C04IS24C08 IS24C16ISSI®TYPICAL SYSTEM BUS CONFIGURATIONSTART AND STOP CONDITIONS6Integrated Silicon Solution, Inc. — — 1-800-379-4774Rev.F元器件交易网IS24C01IS24C02IS24C04IS24C08 IS24C16ISSI®DATA VALIDITY PROTOCOL元器件交易网IS24C01IS24C02IS24C04IS24C08 IS24C16ISSI®PAGE WRITE8Integrated Silicon Solution, Inc. — — 1-800-379-4774Rev.F元器件交易网IS24C01IS24C02IS24C04IS24C08 IS24C16ISSI®SEQUENTIAL READ元器件交易网IS24C01IS24C02IS24C04IS24C08 IS24C16ISSI®ABSOLUTE MAXIMUM RATINGS(1)Symbol Parameter Value UnitV S Supply Voltage0.5 to +6.25VV P Voltage on Any Pin–0.5 to Vcc + 0.5VT BIAS Temperature Under Bias–40 to +85°CT STG Storage Temperature–65 to +150°CI OUT Output Current5mANotes:1.Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may causepermanent damage to the device. This is a stress rating only and functional operation of thedevice at these or any other conditions above those indicated in the operational sections ofthis specification is not implied. Exposure to absolute maximum rating conditions forextended periods may affect reliability.OPERATING RANGE(IS24C01-2, IS24C02-2, IS24C04-2 IS24C08-2, & IS24C16-2)Range Ambient Temperature V CCCommercial0°C to +70°C 1.8V to 5.5VIndustrial–40°C to +85°C 1.8V to 5.5VOPERATING RANGE(IS24C01-3, IS24C02-3, IS24C04-3, IS24C08-3, & IS24C16-3)Range Ambient Temperature V CCCommercial0°C to +70°C 2.5V to 5.5VIndustrial–40°C to +85°C 2.5V to 5.5VAutomotive–40°C to +125°C 2.7V to 5.5VNote: Automotive data is preliminary.OPERATING RANGE(IS24C01-5, IS24C02-5, IS24C04-5 IS24C08-5, & IS24C16-5)Range Ambient Temperature V CCAuromotive–40°C to +125°C 4.5V to 5.5VNote: Automotive data is preliminary.10Integrated Silicon Solution, Inc. — — 1-800-379-4774Rev.FDC ELECTRICAL CHARACTERISTICSSymbol Parameter Test Conditions Min.Max.Unit V OL1Output LOW Voltage V CC = 1.8V, I OL = 0.15 mA—0.2V V OL2Output LOW Voltage V CC = 2.5V, I OL = 1.0 mA—0.4V V IH Input HIGH Voltage V CC X 0.7V CC + 0.5V V IL Input LOW Voltage–1.0V CC X 0.3VI LI Input Leakage Current V IN = V CC max.—3µAI LO Output Leakage Current—3µA Notes: V IL min and V IH max are reference only and are not tested.POWER SUPPLY CHARACTERISTICSSymbol Parameter Test Conditions Min.Max.UnitI CC1Vcc Operating Current READ at 100 KHz (Vcc = 5V)— 1.0mAI CC2Vcc Operating Current WRITE at 100 KHz (Vcc = 5V)— 3.0mAI SB1Standby Current Vcc = 1.8V— 4.0µAI SB2Standby Current Vcc = 5.5V—8.0µACAPACITANCE(1,2)Symbol Parameter Conditions Max.UnitC IN Input Capacitance V IN = 0V6pFC OUT Output Capacitance V OUT = 0V8pFNotes:1.Tested initially and after any design or process changes that may affect these parameters.2.Test conditions: T A = 25°C, f = 1 MHz, Vcc = 5.0V.12Integrated Silicon Solution, Inc. — — 1-800-379-4774Rev.F AC ELECTRICAL CHARACTERISTICS (Over Operating Range)Automotive (T A = –40°C to +125°C) 2.7V-5.5V 4.5V-5.5V Symbol Parameter Test ConditionsMin.Max.Min.Max.Unit f SCL SCL Clock Frequency 01000400KHz T Noise Suppression Time (1)—100—50ns t LOW Clock LOW Period 4.7— 1.2—µs t HIGH Clock HIGH Period4—0.6—µs t BUF Bus Free Time Before New Transmission 4.7— 1.2—µs t SU:STA Start Condition Setup Time 4.7—0.6—µs t SU:STO Stop Condition Setup Time 4.7—0.6—µs t HD:STA Start Condition Hold Time 4—0.6—µs t HD:STO Stop Condition Hold Time 4—0.6—µs t SU:DAT Data In Setup Time 200—100—ns t HD:DAT Data In Hold Time 0—0—ns t DH Data Out Hold Time SCL LOW to SDA Data Out Change 100—50—ns t AA Clock to Output SCL LOW to SDA Data Out Valid0.1 4.50.10.9µs t R SCL and SDA Rise Time(1)—1000—300ns t F SCL and SDA Fall Time (1)—300—300ns t WRWrite Cycle Time—10—10msNote:1. This parameter is characterized but not 100% tested.2. Automotive data is preliminary.AC ELECTRICAL CHARACTERISTICS (Over Operating Rnage)Commercial (T A = 0°C to +70°C) Industrial (T A = –40°C to +85°C) 1.8V-5.5V 2.5V-5.5V Symbol Parameter Test ConditionsMin.Max.Min.Max.Unit f SCL SCL Clock Frequency 01000400KHz T Noise Suppression Time (1)—100—50ns t LOW Clock LOW Period 4.7— 1.2—µs t HIGH Clock HIGH Period4—0.6—µs t BUF Bus Free Time Before New Transmission (1) 4.7— 1.2—µs t SU:STA Start Condition Setup Time 4.7—0.6—µs t SU:STO Stop Condition Setup Time 4.7—0.6—µs t HD:STA Start Condition Hold Time 4—0.6—µs t HD:STO Stop Condition Hold Time 4—0.6—µs t SU:DAT Data In Setup Time 200—100—ns t HD:DAT Data In Hold Time 0—0—ns t DH Data Out Hold Time SCL LOW to SDA Data Out Change 100—50—ns t AA Clock to Output SCL LOW to SDA Data Out Valid 0.1 4.50.10.9µs t R SCL and SDA Rise Time (1)—1000—300ns t F SCL and SDA Fall Time (1)—300—300ns t WRWrite Cycle Time—10—5msNote:1. This parameter is characterized but not 100% tested.AC WAVEFORMS BUS TIMINGWRITE CYCLE TIMINGORDERING INFORMATIONCommercial Range: 0°C to +70°CVol tageFrequency Range Part Number Package100 KHz 1.8V IS24C01-2P300-mil Plastic DIPto 5.5V IS24C01-2G Small Outline (JEDEC STD)IS24C01-2S MSOPIS24C01-2Z TSSOP100 KHz 1.8V IS24C02-2P300-mil Plastic DIPto 5.5V IS24C02-2G Small Outline (JEDEC STD)IS24C02-2S MSOPIS24C02-2Z TSSOP400 KHz 2.5V IS24C01-3P300-mil Plastic DIPto 5.5V IS24C01-3G Small Outline (JEDEC STD)IS24C01-3S MSOPIS24C01-3Z TSSOP400 KHz 2.5V IS24C02-3P300-mil Plastic DIPto 5.5V IS24C02-3G Small Outline (JEDEC STD)IS24C02-3S MSOPIS24C02-3Z TSSOPORDERING INFORMATIONIndustrial Range: –40°C to +85°CVoltageFrequency Range Part Number Package100 KHz 1.8V IS24C01-2PI300-mil Plastic DIPto 5.5V IS24C01-2GI Small Outline (JEDEC STD)IS24C01-2SI MSOPIS24C01-2ZI TSSOP100 KHz 1.8V IS24C02-2PI300-mil Plastic DIPto 5.5V IS24C02-2GI Small Outline (JEDEC STD)IS24C02-2SI MSOPIS24C02-2ZI TSSOP400 KHz 2.5V IS24C01-3PI300-mil Plastic DIPto 5.5V IS24C01-3GI Small Outline (JEDEC STD)IS24C01-3SI MSOPIS24C01-3ZI TSSOP400 KHz 2.5V IS24C02-3PI300-mil Plastic DIPto 5.5V IS24C02-3GI Small Outline (JEDEC STD)IS24C02-3SI MSOPIS24C02-3ZI TSSOP14Integrated Silicon Solution, Inc. — — 1-800-379-4774Rev.FORDERING INFORMATIONCommercial Range: 0°C to +70°CVol tageFrequency Range Part Number Package100 KHz 1.8V IS24C01-2PL300-mil Plastic DIP, Lead-freeto 5.5V IS24C01-2GL Small Outline (JEDEC STD), Lead-freeIS24C01-2SL MSOP, Lead-freeIS24C01-2ZL TSSOP, Lead-free100 KHz 1.8V IS24C02-2PL300-mil Plastic DIP, Lead-freeto 5.5V IS24C02-2GL Small Outline (JEDEC STD), Lead-freeIS24C02-2SL MSOP, Lead-freeIS24C02-2ZL TSSOP, Lead-free400 KHz 2.5V IS24C01-3PL300-mil Plastic DIP, Lead-freeto 5.5V IS24C01-3GL Small Outline (JEDEC STD), Lead-freeIS24C01-3SL MSOP, Lead-freeIS24C01-3ZL TSSOP, Lead-free400 KHz 2.5V IS24C02-3PL300-mil Plastic DIP, Lead-freeto 5.5V IS24C02-3GL Small Outline (JEDEC STD), Lead-freeIS24C02-3SL MSOP, Lead-freeIS24C02-3ZL TSSOP, Lead-freeORDERING INFORMATIONIndustrial Range: –40°C to +85°CVoltageFrequency Range Part Number Package100 KHz 1.8V IS24C01-2PLI300-mil Plastic DIP, Lead-freeto 5.5V IS24C01-2GLI Small Outline (JEDEC STD), Lead-freeIS24C01-2SLI MSOP, Lead-freeIS24C01-2ZLI TSSOP, Lead-free100 KHz 1.8V IS24C02-2PLI300-mil Plastic DIP, Lead-freeto 5.5V IS24C02-2GLI Small Outline (JEDEC STD), Lead-freeIS24C02-2SLI MSOP, Lead-freeIS24C02-2ZLI TSSOP, Lead-free400 KHz 2.5V IS24C01-3PLI300-mil Plastic DIP, Lead-freeto 5.5V IS24C01-3GLI Small Outline (JEDEC STD), Lead-freeIS24C01-3SLI MSOP, Lead-freeIS24C01-3ZLI TSSOP, Lead-free400 KHz 2.5V IS24C02-3PLI300-mil Plastic DIP, Lead-freeto 5.5V IS24C02-3GLI Small Outline (JEDEC STD), Lead-freeIS24C02-3SLI MSOP, Lead-freeIS24C02-3ZLI TSSOP, Lead-freeORDERING INFORMATIONAutomotive Range: –40°C to +125°CVoltageFrequency Range Part Number Package100 KHz 2.7V IS24C01-3PA300-mil Plastic DIPto 5.5V IS24C01-3GA Small Outline (JEDEC STD)IS24C01-3SA MSOPIS24C01-3ZA TSSOP100 KHz 2.7V IS24C02-3PA300-mil Plastic DIPto 5.5V IS24C02-3GA Small Outline (JEDEC STD)IS24C02-3SA MSOPIS24C02-3ZA TSSOP400 KHz 4.5V IS24C01-PA300-mil Plastic DIPto 5.5V IS24C01-GA Small Outline (JEDEC STD)IS24C01-SA MSOPIS24C01-ZA TSSOP400 KHz 4.5V IS24C02-PA300-mil Plastic DIPto 5.5V IS24C02-GA Small Outline (JEDEC STD)IS24C02-SA MSOPIS24C02-ZA TSSOPNote: Automotive data is preliminary.16Integrated Silicon Solution, Inc. — — 1-800-379-4774Rev.F。