计算机架构 资料 501W15_slideset11

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The same defective program, now with the threads running simultaneously in two cores . . .
Thread A:
while ( condition ) {
do some work counter++; }
Thread A:
while ( condition ) {
do some work counter++; }
Thread B:
while ( condition ) { do some work counter++;
}
Before considering the race condition in a multicore system, let’s address this question: What is the potential failure if this program is running in a uniprocessor system?
A race condition is a situation in which the evolution of the state of some system depends critically on the exact order of nearly-simultaneous events in two or more subsystems.
Thread A ...
LD
R8, 100(R28)
DADDIU R8, R8, 1
SD...
R8, 100(R28)
Thread B
...
LD R8, 100(R28)
DADDIU R8, R8, 1
SD...
R8, 100(R28)

Due to latency in a snoop-based implementation of MSI, Thread B could do its load before an invalidate command from Thread A’s store is processed.
Is that enough? Consider the MSI protocol again. What must happen either as a result of Thread A releasing the lock, or as a result of Thread B acquiring the lock?
Again the value of counter is supposed to increase by 2, but will actually increase by only 1.
A cache coherency protocol such as MSI will not prevent failure!
Thread B:
while ( condition ) {
do some work counter++; }
Again assume MIPS64, with 100(R28) being the address of counter . . .
ENCM 501 W15 Lectures Slide Set 11
ENCM 501 W15 Lectures Slide Set 11
TLP race condition example
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Two threads are running in the same loop, both reading and writing a global variable called counter . . .
Slide Set 11
for ENCM 369 Winter 2015 Lecture Section 01
Steve Norman, PhD, PEng
Electrical & Computer Engineering Schulich School of Engineering University of Calgary
An atomic instruction (or a sequence of instructions that is intended to provide the same kind of behaviour, such as MIPS LL/SC) typically works like this:
Winter Term, 2015
ENCM 501 W15 Lectures Slide Set 11
Contents
Race conditions Introduction to Pthreads programming Locks
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ENCM 501 W15 Lectures Slide Set 11
if two or more threads attempt the operation, such that the attempts overlap in time, one thread will succeed, and all the other threads will fail.
ENCM 501 W15 Lectures Slide Set 11
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ISA and microarchitecture support for concurrency
Instruction sets have to provide special atomic instructions to allow software implementation of synchronization facilities such as mutexes.
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The key aspects of atomic instructions are:
the whole operation succeeds or the whole operation fails, in a clean way that can be checked after the attempt was made;
Let’s make some notes about how this would work in a uniprocessor system.
ENCM 501 W15 Lectures Slide Set 11
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Thread A:
while ( condition ) {
do some work
ENCM 501 W15 Lectures Slide Set 11
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A memory-register ISA does not solve race condition problems
This x86-64 instruction . . . addq $1, (%rax)
ENCM 501 W15 Lectures Slide Set 11
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Imagine a uniprocessor MIPS64 system, with 100(R28) being the address of counter . . .
Thread A
LD
R8, 100(R28)
DADDIU R8, R8, 1
context switch [suspended]
context switch
SD
R8, 100(R28)
Thread B [suspended]
...
LD R8, 100(R28)
DADDIU R8, R8, 1
SD...
R8, 100(R28)
[suspended]
Outline of Slide Set 11
Race conditions Introduction to Pthreads programming Locks
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ENCM 501 W15 Lectures Slide Set 11
Race conditions
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Thread A ...
LD
R8, 100(R28)
DADDIU R8, R8, 1
SD...
R8, 100(R28)
Thread B
...
LD R8, 100(R28)
DADDIU R8, R8, 1
SD...
R8, 100(R28)
Thread A loses the race to write to counter before Thread B reads from counter.
. . . does a memory read, an addition, and a memory write.
Why can’t that be used to eliminate the problem we saw with MIPS64 instructions?
ENCM 501 W15 Lectures Slide Set 11
memory read is attempted at some location; some kind of write data is generated; memory write to the same location is attempted.
ENCM 501 W15 Lectures Slide Set 11
acquire lock counter++; release lock