开发板电路图
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单片机HC6800开发板资料原理图(电路图)
VCC
C23 104
C22 104
C8 104
RP5B
DSIO P34
Relay： 继电 器接 口 BEEP：蜂 鸣器接口
C21 GND PY1.2 PY1.1 PY1.0 PY1.3 Relay BEEP C4 16 15 14 13 12 11 10 U17 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 104 IN1 IN2 IN3 IN4 IN5 IN6 IN7 GND VCC ULN2003D
J-TXD 1 2 3 RXD-U RXD RXD_R
VCC a f e g d b c dp
VCC a f e g d
VCC a b f c e dp g d b c dp LED2
VCC a f e g d b c dp
VCC a f e g d b f c e dp
VCC a g d b c dp f e
VCC a g d b c dp J14
1 2 3 4 5 6 7 8
双 色点阵
D Pa-D Pd : 为74HC573 输出 端 R E1-R E2: 为点 阵红 色端 GR1-GR2: 为 点阵 绿 色端
VCC
138译码器
74HC573 动静LED 共阴极数码管
J16
74HC595锁 存器与共阳 极数码 管
Jp3 为 单位 数码 管的 接口 Jp2 595(传 入并 出)锁存 器输 出接 口， 这两 个接 口需 要用 排线 连接
稳压电 路
温度检 测
此 电路 的上 拉电 阻在 《中 央 控 制器 （CPU》 ）模 块中
红外接 收
此 电路 的上 拉电 阻在《中 央 控 制器 （CPU》 ）模 块中
KST-51开发板原理图
J5
J7
D
单片机电路
LED2 LED3 LED4 LED5 LED6 LED7 LED8 LED9 LEDC1 R41 1K Q11 9012 DB0 LED DB1 LED DB2 LED DB3 LED DB4 LED DB5 LED DB6 LED DB7 LED
+5
USB供电电路 单片机复位电路
LEDC4
R48 1K
ADDR0
ADDR1
ADDR2
74HC138 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 15 14 13 12 11 10 9 7 LEDC0 LEDC1 LEDC2 LEDC3 LEDC4 LEDC5 LEDC6 LEDC7
LEDC5
R49 1K
Q19 9012
1 7 2
+5 U11 11 12 R1 R2 R3 R4 DB9-TX DB9-RX C7 0.1uF C27 0.1uF C1 +5 0.1uF 2 16 10 9 1 3 T1IN R1OUT T2IN R2OUT C1+ C1V+ VCC MAX232 T1OUT R1IN T2OUT R2IN C2+ C2VGND 14 13 TO-PC-RX 7 8 4 5 6 15 TO-PC-TX C32 0.1uF C33 0.1uF 1 6 2 7 3 8 4 9 5 RS-232 J1 ADDR0 ADDR1 ADDR2 ADDR3
1 2 +5 3 ADDR0 4 ADDR1 5 ENLCD1 6 DB_0 7 DB_1 8 DB_2 9 DB_3 10 DB_4 11 DB_5 12 DB_6 13 DB_7 14 15 +5 16
单片机开发板电路图(原理图)
6 4 5
G1 G2A G2B 74LS138
J12 8 7 6 5 4 3 2 1 2 3 4 5 6 7 8 9 GND 1 LE 11 P10 VCC
U13 D0 D1 D2 D3 D4 D5 D6 D7 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 19 18 17 16 15 14 13 12 R20 R21 100R R22 R23 R24 R25 R26 R27 D11 D12 D13 D14 D15 D16 D17 D18
M2 B2 D2 C2 VCC A2 1 2 3 4 5 M1
RP4B
ISP XT1 C1 XT2 C2 33P P15 RST P17 P16 1 3 5 7 9 2 4 6 8 10 VCC GND GND GND GND
U15 IM1 4 3 2 1 1 2 3 4 5 6 7 8 GND IN1 IN2 IN3 IN4 IN5 IN6 IN7 GND ULN2003D VCC OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 COM 16 15 14 13 12 11 10 9 C2 D2 A1 B1 C1 D1
双色点阵
D Pa-D Pd : 为74HC573 输出 端 R E1-R E2: 为点 阵红 色端 GR1-GR2: 为 点阵 绿 色端
VCC
138译码器
74HC573 动静LED 共 阴极数 码管
J16
74HC595锁 存器与共阳 极数码 管
Jp3 为 单位 数码 管的 接口 Jp2 595(传 入并 出)锁存 器输 出接 口， 这两 个接 口需 要用 排线 连接
B1 D1 C1 VCC A1
1 2 3 4 5
P15
德飞莱开发板LY-51S V2.33电路图
S10
S13
S16
J26 1 2 3 4 5 6 7 8
SW-PB K6 SW-PB K7 SW-PB K8 SW-PB
LED LED9 R26 10K SCL SDA
RED
VCC R27 10K R28 390
J56 1 2 3 4 5 6 CON5 DTR TXD RXD VCCIN
C32 104
S6
S9
S12
S15 J24 1 2 3 4 5 6 7 8 CON8 J25 1 CON1
母口
J18 TXD 1 3 5 2 4 6 RXD
CON3X2
DB9 J21
D1 IN4148
D2 IN4148
D3 IN4148
D4 IN4148
CON8
ADJ
串口通讯
1 6 2 7 3 8 4 9 5
S7
U12A 1 U12B 3 U12C 5 6 U12D 9 U12E 11 U12F 13 CD4069 12 10 8 4 J6 1 2 3 4 5 6 7 8 CON8 3 VCC 8 C29 104 R1-R8 510 DS3 DPY_7-SEG_DP_2 DPY a a b c f b g d e e c d f dp g dp C C 2
8位共阴数码管
LG3641 DS1 DPY DPY a a a a b b c f c f b b g g d d e e c d f dp g dp com 12 e e c d f dp g dp com DPY a a b c f b g d e e c d f dp g dp com DPY a a b c f b g d e e c d f dp g dp com PDS1 11 PDS2 7 PDS3 4 PDS4 2 PDS5 1 PDS6 10 PDS7 5 PDS8 3 LG3641 DS2 DPY DPY a a a a b b c f c f b b g g d d e e c d f dp g dp com 12 e e c d f dp g dp com DPY a a b c f b g d e e c d f dp g dp com DPY a a b c f b g d e e c d f dp g dp com
AT89C51单片机开发板原理图电路
A
Revision
GND
P3.2
1
2
3
4
6
COM3 R9 120 P0.1 P0.2
D2 D3 D4 P0.3
+5V 1
RP2
D
3
Q3 8550
D1 P0.0
D
GND 7805 PWR GND D10 4001 1 CP1 100u 2 Vin Vout 3 +5V
E
E
+5V R6 1K
+5V P0.4
D5 D6 P0.5 D7 COM4 P0.6 P0.7 120
GND +5V VLCD RS R/W E DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 +5V 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
1602 VSS VDD VO RS R/W E DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 A K TG1602 GND
GND
JP2 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RST P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33
CN2 2 1 CN3 MAX232 1 C8 104 3 4 C9 104 5 P3.1 P3.0 11 10 12 9 C1+ C1C2+ GND C2T1IN T2IN R1OUT R2OUT T1OUT T2OUT R1IN R2IN VCC V+ V2 6 15 GND 14 7 13 8 GND C10 104 GND UART 1 6 2 7 3 8 4 9 5 D+ D+5V C5 4.7u R23 + C6 104 10K C7 1u GND 2 1 TXD P3.1 U11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 DCD RI GND D+ DVDD REGIN VBUS RST# NC SUSPEND# SUSPEND NC NC CP2102 DTR DSR TXD RXD RTX CTX NC NC NC NC NC NC NC NC 28 27 26 25 24 23 22 21 20 19 18 17 16 15 GND RXD1 TXD1 P3.0 P3.1 RXD P3.0 +5V
LM3S8962开发板电路原理图
Schematic page 1
1
2
3
4
5
6
Stellaris LM3S8962 Microcontroller
A PA0/U0Rx PA1/U0Tx PA2/SSI0CLK PA3/SSI0FSS PA4/SSI0RX PA5/SSI0TX PA6/CCP1 PA7 INT_TCK TMS/SWDIO PC2/TDI PC3/TDO TMS/SWDIO PC2/TDI PC3/TDO PC4/PhA0 PC5 PC6/PhB0 PC7 PE0/PWM4 PE1/PWM5 PE2/PhB1 PE3/PhA1 ADC0 ADC1 ADC2 ADC3 PG0 PG1/PWM1 MCURSTn 26 27 28 29 30 31 34 35 80 79 78 77 25 24 23 22 72 73 74 75 1 2 5 6 19 18 64 17 16 48 49 1 Y1 2 1 Y2 2 OSC32IN OSC32OUT 52 53 50 51 65 76 9 15 21 33 39 42 45 54 57 63 69 82 85 86 87 94 4 97 U1 U2 PA0/U0RX PA1/U0TX PA2/SSI0CLK PA3/SSI0FSS PA4/SSI0RX PA5/SSI0TX PA6/CCP1 PA7 PC0/TCK/SWCLK PC1/TMS/SWDIO PC2/TDI PC3/TDO/SWO PC4/PhA0 PC5 PC6/PhB0 PC7 PE0/PWM4 PE1/PWM5 PE2/PhB1 PE3/PhA1 ADC0 ADC1 ADC2 ADC3 PG0 PG1/PWM1 RST XTALNPHY XTALPPHY MOSCin MOSCout OSC32in OSC32out WAKE HIB CMOD0 CMOD1 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND AGND AGND LM3S8962 12.4K 1% resistor required on Pin 41 for compatibility with future LM3S8962 revisions See Product Change Notification PCN-08001 AVDD AVDD VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VBAT LDO VDD25 VDD25 VDD25 VDD25 ERBIAS TXON RXIP 46 40 C5 37 R8 49.9 R9 49.9 C6 10pF C7 10pF 0.1UF R7 330 +3.3V +3.3V 6 RXIN 8 2 1 9 10 C12 0.1UF C13 0.01UF
1
2
3
4
5
6
Stellaris LM3S8962 Microcontroller
A PA0/U0Rx PA1/U0Tx PA2/SSI0CLK PA3/SSI0FSS PA4/SSI0RX PA5/SSI0TX PA6/CCP1 PA7 INT_TCK TMS/SWDIO PC2/TDI PC3/TDO TMS/SWDIO PC2/TDI PC3/TDO PC4/PhA0 PC5 PC6/PhB0 PC7 PE0/PWM4 PE1/PWM5 PE2/PhB1 PE3/PhA1 ADC0 ADC1 ADC2 ADC3 PG0 PG1/PWM1 MCURSTn 26 27 28 29 30 31 34 35 80 79 78 77 25 24 23 22 72 73 74 75 1 2 5 6 19 18 64 17 16 48 49 1 Y1 2 1 Y2 2 OSC32IN OSC32OUT 52 53 50 51 65 76 9 15 21 33 39 42 45 54 57 63 69 82 85 86 87 94 4 97 U1 U2 PA0/U0RX PA1/U0TX PA2/SSI0CLK PA3/SSI0FSS PA4/SSI0RX PA5/SSI0TX PA6/CCP1 PA7 PC0/TCK/SWCLK PC1/TMS/SWDIO PC2/TDI PC3/TDO/SWO PC4/PhA0 PC5 PC6/PhB0 PC7 PE0/PWM4 PE1/PWM5 PE2/PhB1 PE3/PhA1 ADC0 ADC1 ADC2 ADC3 PG0 PG1/PWM1 RST XTALNPHY XTALPPHY MOSCin MOSCout OSC32in OSC32out WAKE HIB CMOD0 CMOD1 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND AGND AGND LM3S8962 12.4K 1% resistor required on Pin 41 for compatibility with future LM3S8962 revisions See Product Change Notification PCN-08001 AVDD AVDD VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VBAT LDO VDD25 VDD25 VDD25 VDD25 ERBIAS TXON RXIP 46 40 C5 37 R8 49.9 R9 49.9 C6 10pF C7 10pF 0.1UF R7 330 +3.3V +3.3V 6 RXIN 8 2 1 9 10 C12 0.1UF C13 0.01UF
Stratix V GX FPGA开发板电路图
8 8 8 8
C
8 8
8 8 8 8 8 8 8 8
PCIE_TX_CP4 PCIE_TX_CN4 PCIE_TX_CP5 PCIE_TX_CN5 PCIE_TX_CP6 PCIE_TX_CN6 PCIE_TX_CP7 PCIE_TX_CN7
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
REV
C1 C1.1 C1.2
DATE
09/27/2011 12/22/2011 03/15/2012
PAGES
All 26 07
DESCRIPTION
INITIAL REVISION C RELEASE BOM UPDATE FOR CAPACITOR C111 AND C127. ADD A NOTE ON SHEET 7 FOR DDR3 SPEED REQUIRMENTS.
HSMC Port B x2 (of 4 XCVRS) DisplayPort (x4)
XCVR BANK QR3
QSFP SDI
C
C
XCVR BANKS QR0, QR1
HSMC Port A x8 HSMC Port B x2 (of 4 XCVRS)
XCVR BANKS QR0, QR2
PCI Express x8
3.3V_PCIE
A
C74 0.1uF PCI BRACKET
C75 0.1uF
C76 0.1uF
C584 0.1uF
C585 0.1uF
C582 0.1uF
C583 0.1uF
C77 0.1uF
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
开发板电路原理图
8 VCC 7 6 5
C1 00 + 1 0U
WW 1 0K
5
液晶显示器接口电路
VCC A3 A4 A5 P37 P36 A9 P13
J P5 HEADER 8 X2
1
2
3
4
5
6
7
8
9
10
11 12
13 14
15 16
LIGHT LC D_A0 LC D_A1 LC D_A2 LC D_R D LCD_W R C S _LC D RST_ LCD
LED LED LED LED LED LED LED LED LED LED LED LED LED LED LED LED
DG5
VCC
DG6
DG7
1
J P1
D0
A
D1
1
2
B
D2
3
4
C
D3
5
6
D
D4
7
8
E
D5
9
10
F
D6
11 12
G
D7
13 14
DP
15 16
HEADER 8 X2
2
3
4
9
8
7
6
5
LC M_D0 7 LC M_D1 8 LC M_D2 9 LC M_D3 10 LC M_D4 11 LC M_D5 12 LC M_D6 13 LC M_D7 14
J 10 0 LCD16 0 2
VCC Vad j GND
LIGHT+ LIGHT-
R /W DATA CLK
D0 D1 D2 D3 D4 D5 D6 D7