MEMORY存储芯片MT47J64M16HR-5E中文规格书
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Electrical Specifications – I DD Specifications and Conditions
Within the following I DD measurement tables, the following definitions and conditions
are used, unless stated otherwise:
•LOW: V IN≤ V IL(AC)max; HIGH: V IN≥ V IH(AC)min.
•Midlevel: Inputs are V REF = V DD/2.
•R ON set to RZQ/7 (34Ω).
•R TT,nom set to RZQ/6 (40Ω).
•R TT(WR) set to RZQ/2 (120Ω).
•Q OFF is enabled in MR1.
•ODT is enabled in MR1 (R TT,nom) and MR2 (R TT(WR)).
•TDQS is disabled in MR1.
•External DQ/DQS/DM load resistor is 25Ω to V DDQ/2.
•Burst lengths are BL8 fixed.
•AL equals 0 (except in I DD7).
•I DD specifications are tested after the device is properly initialized.
•Input slew rate is specified by AC parametric test conditions.
•Optional ASR is disabled.
•Read burst type uses nibble sequential (MR0[3] = 0).
•Loop patterns must be executed at least once before current measurements begin. Table 8: Timing Parameters Used for I DD Measurements – Clock Units
Table 9: I DD0 Measurement Loop
Notes: 1.DQ, DQS, DQS# are midlevel.
2.DM is LOW.
3.Only selected bank (single) active.
Table 10: I DD1 Measurement Loop
Notes: 1.
DQ, DQS, DQS# are midlevel unless driven as required by the RD command.2.
DM is LOW.3.
Burst sequence is driven on each DQ signal by the RD command.4.Only selected bank (single) active.
8Gb: x4, x8, x16 DDR3L SDRAM Electrical Specifications – I DD Specifications and Conditions。