MEMORY存储芯片TMS320DM270GHK中文规格书

196TMS320C6745,TMS320C6747
SPRS377F –SEPTEMBER 2008–REVISED JUNE 2014
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Peripheral Information and Electrical Specifications Copyright ©2008–2014,Texas Instruments Incorporated
UHPI_HSTROBE refers to the following logical operation [NOT(UHPI_HDS1XOR UHPI_HDS2)]OR UHPI_HCS.B.
Depending on the type of write or read operation (HPID without auto-incrementing;HPIA,HPIC,or HPID with auto-incrementing)and the state of the FIFO,transitions on UHPI_HRDY may or may not occur.C.
UHPI_HCS reflects typical UHPI_HCS behavior when UHPI_HSTROBE assertion is caused by UHPI_HDS1or UHPI_HDS2.UHPI_HCS timing requirements are reflected by parameters for UHPI_HSTROBE.D.The diagram above assumes UHPI_HAS has been pulled high.Figure 6-67.UHPI Read Timing (UHPI_HAS Not Used,Tied High)
202TMS320C6745,TMS320C6747
SPRS377F –SEPTEMBER 2008–REVISED JUNE 2014
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Product Folder Links:TMS320C6745TMS320C6747
Peripheral Information and Electrical Specifications Copyright ©2008–2014,Texas Instruments Incorporated
6.28.1.1Power Domain States
A power domain can only be in one of the two states:ON or OFF,defined as follows:
•ON:power to the domain is on
•OFF:power to the domain is off
In the device,for both PSC0and PSC1,the Always ON domain,or PD0power domain,is always in the ON state when the chip is powered-on.This domain is not programmable to OFF state.
•On PSC0PD1/PD_DSP Domain:Controls the sleep state for DSP L1and L2Memories
•On PSC1PD1/PD_SHRAM Domain:Controls the sleep state for the 128K Shared RAM
6.28.1.2Module States
The PSC defines several possible states for a module.This states are essentially a combination of the module reset asserted or de-asserted and module clock on/enabled or off/disabled.The module states are defined in Table 6-104.
Table 6-104.Module States
Module State
Module Reset Module Clock Module State Definition Enable
De-asserted On A module in the enable state has its module reset de-asserted and it has its clock on.This is the normal operational state for a given module Disable De-asserted Off A module in the disabled state has its module reset de-asserted and it has its
module clock off.This state is typically used for disabling a module clock to
save power.The device is designed in full static CMOS,so when you stop a
module clock,it retains the module’s state.When the clock is restarted,the
module resumes operating from the stopping point.
SyncReset Asserted On A module state in the SyncReset state has its module reset asserted and it has
its clock on.Generally,software is not expected to initiate this state
SwRstDisable Asserted Off A module in the SwResetDisable state has its module reset asserted and it has
its clock disabled.After initial power-on,several modules come up in the
SwRstDisable state.Generally,software is not expected to initiate this state
Auto Sleep De-asserted Off A module in the Auto Sleep state also has its module reset de-asserted and its
module clock disabled,similar to the Disable state.However this is a special
state,once a module is configured in this state by software,it can
“automatically”transition to “Enable”state whenever there is an internal
read/write request made to it,and after servicing the request it will
“automatically”transition into the sleep state (with module reset re de-asserted
and module clock disabled),without any software intervention.The transition
from sleep to enabled and back to sleep state has some cycle latency
associated with it.It is not envisioned to use this mode when peripherals are
fully operational and moving data.
Auto Wake De-asserted Off
A module in the Auto Wake state also has its module reset de-asserted and its
module clock disabled,similar to the Disable state.However this is a special
state,once a module is configured in this state by software,it will
“automatically”transition to “Enable”state whenever there is an internal
read/write request made to it,and will remain in the “Enabled”state from then
on (with module reset re de-asserted and module clock on),without any
software intervention.The transition from sleep to enabled state has some
cycle latency associated with it.It is not envisioned to use this mode when
peripherals are fully operational and moving data.。