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元器件交易网ASAHI KASEI[AK4367]AK4367Low Power 24-Bit 2ch DAC with HP-AMP & Output MixerGENERAL DESCRIPTION The AK4367 is 24bit DAC with built-in Headphone Amplifier. The AK4367 features an analog mixing circuit that allows easy interfacing in mobile phone and portable communication designs. The integrated headphone amplifier features “pop-free” power-on/off, a mute control and delivers 50mW of power at 16Ω. The AK4367 is housed in a 20pin QFN package, making it suitable for portable applications. FEATURE Multi-bit ∆Σ DAC Sampling Rate: 8kHz∼48kHz 64x Oversampling On chip perfect filtering 8 times FIR interpolator - Passband: 20kHz - Passband Ripple: ±0.02dB - Stopband Attenuation: 54dB Digital De-emphasis Filter: 32kHz, 44.1kHz and 48kHz System Clock: 256fs/384fs/512fs - AC Couple Input Available Audio I/F Format: MSB First, 2’s Compliment - I2S, 24bit MSB justified, 24bit/20bit/16bit LSB justified Digital ATT Analog Mixing Circuit Mono Lineout µP Interface: 3-wire/I2C Bass Boost Function Headphone Amplifier - Output Power: 50mW x 2ch @16Ω, 3.3V - S/N: 92dB@2.4V - Pop Noise Free at Power-ON/OFF and Mute Power Supply: 2.2V ∼ 3.6V Power Supply Current: 2.8mA@2.4V (@HP-AMP no-output) Ta: −40 ∼ 85°C Small Package: 20pin QFNMS0247-E-02 -1-2005/10元器件交易网ASAHI KASEI[AK4367]MCLKLINMINVDDBICK LRCK SDATAAudio InterfaceClock Divider VCOM HDP AmpVCOMDAC(Lch)MUTEHPLATT & Bass BoostDEM & Digital Filter DAC(Rch)MOUTHDP AmpMUTEHPRPDN I2C CAD0/CSN SCL/CCLK SDA/CDTI RIN VSS Serial I/F HVDD MUTETFigure 1. AK4367 Block DiagramMS0247-E-02 -2-2005/10元器件交易网ASAHI KASEI[AK4367]Ordering GuideAK4367VN AKD4367 −40 ∼ +85°C 20pin QFN (0.5mm pitch) Evaluation board for AK4367Pin LayoutMUTET 12HPR HPL MIN RIN LIN11151413VCOMHVDDVDDVSS16 17 18 19 20 1 2 3 4 510MOUT I2C PDN MCLK BICKAK4367Top View9 8 7 6CAD0/CSNSCL/CCLKSDA/CDTISDATAMS0247-E-02 -3-LRCK2005/10元器件交易网ASAHI KASEI[AK4367]PIN/FUNCTIONNo. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Pin Name SDA CDTI SCL CCLK CAD0 CSN SDATA LRCK BICK MCLK PDN I2C MOUT VCOM MUTET VDD VSS HVDD HPR HPL MIN RIN LIN I/O I/O I I I I I I I I I I I O O O O O I I I Function Control Data Input/Output Pin (I2C pin = “H”) Control Data Input Pin (I2C pin = “L”) Control Data Clock Pin (I2C pin = “H”) Control Data Clock Pin (I2C pin = “L”) Chip Address 0 Select Pin (I2C pin = “H”) Control Data Chip Select Pin (I2C pin = “L”) Audio Serial Data Input Pin L/R Clock Pin This clock determines which audio channel is currently being input on SDATA pin. Serial Bit Clock Pin This clock is used to latch audio data. Master Clock Input Pin Power-down & Reset Pin When at “L”, the AK4367 is in power-down mode and is held in reset. The AK4367 should always be reset upon power-up. Control Mode Select Pin (Internal Pull-down Pin) “H”: I2C Bus, “L”: 3-wire Serial Mono Analog Output Pin Common Voltage Output Pin Normally connected to VSS pin with 0.1µF ceramic capacitor in parallel with a 2.2µF electrolytic capacitor. Mute Time Constant Control Pin Connected to VSS pin with a capacitor for mute time constant. Power Supply Pin Ground Pin Power Supply Pin for Headphone Amp Rch Headphone Amp Output Pin Lch Headphone Amp Output Pin Mono Analog Input Pin Rch Analog Input Pin Lch Analog Input PinNote: All digital input pins except analog input pins (MIN, RIN and LIN) and internal pull-down pin must not be left floating.Handling of Unused PinThe unused I/O pins should be processed appropriately as below. Classification Analog Digital Pin Name MOUT, MUTET, HPR, HPL, MIN, RIN, LIN CAD0 Setting These pins should be open. These pins should be connected to VSS.MS0247-E-02 -4-2005/10元器件交易网ASAHI KASEI[AK4367]ABSOLUATE MAXIMUM RATING (VSS=0V; Note 1) Parameter Symbol min Power Supplies Analog, Digital VDD −0.3 HP-AMP HVDD −0.3 Input Current (any pins except for supplies) IIN Input Voltage VIN −0.3 Ambient Temperature Ta −40 Storage Temperature Tstg −65 Note 1. All voltages with respect to ground.max 4.6 4.6 ±10 VDD+0.3 or 4.6 85 150Units V V mA V °C °CWARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.RECOMMEND OPERATING CONDITIONS (VSS=0V; Note 1) Parameter Symbol min typ Power Supplies Analog, Digital VDD 2.2 2.4 (Note 2) HP-AMP HVDD 2.2 2.4 Note 1. All voltages with respect to ground. Note 2. VDD should be same voltage as HVDD.* AKM assumes no responsibility for usage beyond the conditions in this datasheet.max 3.6 3.6Units V VMS0247-E-02 -5-2005/10元器件交易网ASAHI KASEI[AK4367]ANALOG CHARACTERISTICS (Ta=25°C; VDD=HVDD=2.4V, VSS=0V; fs=44.1kHz; BOOST OFF; Signal Frequency =1kHz; Measurement band width=10Hz ∼ 20kHz; Headphone-Amp: Load impedance is a serial connection with RL =16Ω and CL=220µF. (Refer to Figure 33); Mono output: RL =16Ω; unless otherwise specified) Parameter min typ max Units 24 bit DAC Resolution Headphone-Amp: (HPL/HPR pins) (Note 3) Analog Output Characteristics THD+N dB −4.8dBFS Output, Po=10mW@16Ω, 2.4V −55 −45 dB −3dBFS Output, Po=28mW@16Ω, 3.3V −55 dB −3dBFS Output, Po=14mW@32Ω, 3.3V −57 D-Range −60dBFS Output, A-weighted, 2.4V 84 92 dB 94 dB −60dBFS Output, A-weighted, 3.3V S/N A-weighted, 2.4V 84 92 dB A-weighted, 3.3V 94 dB Interchannel Isolation 60 80 dB DC Accuracy Interchannel Gain Mismatch 0.2 dB Gain Drift 200 ppm/°C Load Resistance (Note 4) 16 Ω Load Capacitance 300 Output Voltage (Note 5) 1.02 1.13 1.24 Vpp (−4.8dBFS Output) Max Output Power 26 mW RL=16Ω, 2.4V 50 mW RL=16Ω, 3.3V Mono Output: (MOUT pin) (Note 6) Analog Output Characteristics: THD+N (0dBFS Output) dB −60 −50 S/N (A-weighted) 84 92 dB DC Accuracy Gain Drift 200 ppm/°C Load Resistance (Note 4) 10 kΩ Load Capacitance 25 pF Output Voltage (Note 7) 1.42 1.58 1.74 Vpp Output Volume: (MOUT pin) Step Size 1 2 3 dB Gain Control Range 0 dB −30 Note 3. DACL=DACR bits = “1”, MINL=MINR=LINL=RINR bits = “0”, ATTL=ATTR=0dB. Note 4. AC Load Note 5. Output voltage is proportional to VDD voltage. Vout = 0.47 x VDD(typ)@−4.8dBFS. Note 6. DACM bit = “1”, DACL=DACR bits = “0”, LINM=RINM=MINM bits = “0”, ATTL=ATTR=ATTM=0dB, and common mode signal is input to L/Rch of DAC. Note 7. Output voltage is proportional to VDD voltage. Vout = 0.66 x VDD(typ).MS0247-E-02 -6-2005/10元器件交易网ASAHI KASEI[AK4367]Parameter min typ max LINEIN: (LIN/RIN/MIN pins) Analog Input Characteristics Input Resistance (See Figure 31 and Figure 32.) LIN pin LINL bit = “1”, LINM bit = “1” 23 33 LINL bit = “1”, LINM bit = “0” 40 LINL bit = “0”, LINM bit = “1” 200 RIN pin RINR bit = “1”, RINM bit = “1” 23 33 RINR bit = “1”, RINM bit = “0” 40 RINR bit = “0”, RINM bit = “1” 200 MIN pin MINL bit = “1”, MINR bit = “1”, MINM bit = “1” 11 17 MINL bit = “1”, MINR bit = “0”, MINM bit = “0” 40 MINL bit = “0”, MINR bit = “1”, MINM bit = “0” 40 MINL bit = “0”, MINR bit = “0”, MINM bit = “1” 100 Gain LIN/RIN→MOUT −7 −6 −5 0 +1 MIN→MOUT −1 +0.8 +1.8 +2.8 LIN/MIN→HPL, RIN/MIN→HPR Power Supplies Power Supply Current Normal Operation (PDN pin = “H”) (Note 8) VDD 1.8 3.0 HVDD 1.0 2.0 Power-Down Mode (PDN pin = “L”) (Note 9) 1 100 Note 8. PMDAC=PMHPL=PMHPR=PMMO bits = “1”, MUTEN bit = “1” and HP-Amp output is off. Note 9. All digital input pins including clock pins (MCLK, BICK and LRCK) are held at VSS.UnitskΩ kΩ kΩ kΩ kΩ kΩ kΩ kΩ kΩ kΩ dB dB dBmA mA µAMS0247-E-02 -7-2005/10元器件交易网ASAHI KASEI[AK4367]FILTER CHARACTERISTICS (Ta=25°C; VDD, HVDD=2.2 ∼ 3.6V; fs=44.1kHz; De-emphasis = “OFF”) Parameter Symbol min typ max Units DAC Digital Filter: (Note 10) Passband PB 0 20.0 kHz −0.05dB (Note 11) 22.05 kHz −6.0dB Stopband (Note 11) SB 24.1 kHz Passband Ripple PR dB ±0.02 Stopband Attenuation SA 54 dB Group Delay (Note 12) GD 20.8 1/fs Group Delay Distortion 0 µs ∆GD DAC Digital Filter + Analog Filter: (Note 10) (Note 13) Frequency Response FR dB 0 ∼ 20.0kHz ±0.5 Analog Filter: (Note 14) Frequency Response FR dB 0 ∼ 20.0kHz ±1.0 BOOST Filter: (Note 13) (Note 15) Frequency Response 20Hz FR dB 5.76 MIN 100Hz dB 2.92 1kHz dB 0.02 20Hz FR dB 10.80 MID 100Hz dB 6.84 1kHz dB 0.13 20Hz FR dB 16.06 MAX 100Hz dB 10.54 1kHz dB 0.37 Note 10. BOOST OFF (BST1-0 bit = “00”) Note 11. The passband and stopband frequencies scale with fs. For example, PB=0.4535*fs(@±0.05dB), SB=0.546*fs(@−54dB). Note 12. This is the calculated delay time caused by digital filtering. This time is measured from the setting of the 24bit data of both channels to the input registers to the output of the analog signal. Note 13. DAC HPL, HPR, MOUT Note 14. MIN HPL/HPR/MOUT, LIN HPL/MOUT, RIN HPR/MOUT Note 15. These frequency responses scale with fs. If high-level signal is input, the AK4367 clips at low frequency.Boost Filter (fs=44.1kHz) 20 15 Level [dB] MID 10 MIN 5 0 -5 10 100 Frequency [Hz] 1000 10000MAXFigure 2. Boost Frequency (fs=44.1kHz)MS0247-E-02 -8-2005/10元器件交易网ASAHI KASEI[AK4367]DC CHARACTERISTICS (Ta=25°C; VDD, HVDD=2.2 ∼ 3.6V) Parameter Symbol min High-Level Input Voltage VIH 70%DVDD Low-Level Input Voltage VIL Input Voltage at AC Coupling (Note 16) VAC 1.0 Low-Level Output Voltage (Iout = 3mA) VOL Input Leakage Current (Note 17) Iin Note 16. Only MCLK pin. (Figure 33) Note 17. I2C pin has internal pull-down device, nominally 100kΩ.typ -max 30%DVDD 0.4 ±10Units V V Vpp V µASWITCHING CHARACTERISTICS (Ta=25°C; VDD, HVDD=2.2 ∼ 3.6V; CL = 20pF) Parameter Symbol min typ max Units Master Clock Timing Frequency fCLK 2.048 24.576 MHz Pulse Width Low (Note 18) tCLKL 0.4/fCLK ns Pulse Width High (Note 18) tCLKH 0.4/fCLK ns AC Pulse Width (Note 21) tACW 20 ns LRCK Timing Frequency fs 8 44.1 48 kHz Duty Cycle: Duty 45 55 % Serial Interface Timing (Note 19) BICK Period tBCK 1/(64fs) ns BICK Pulse Width Low tBCKL 130 ns Pulse Width High tBCKH 130 ns (Note 20) tLRB 50 ns LRCK Edge to BICK “↑” (Note 20) tBLR 50 ns BICK “↑” to LRCK Edge SDATA Hold Time tSDH 50 ns SDATA Setup Time tSDS 50 ns Control Interface Timing (3-wire Serial mode) CCLK Period tCCK 200 ns CCLK Pulse Width Low tCCKL 80 ns Pulse Width High tCCKH 80 ns CDTI Setup Time tCDS 40 ns CDTI Hold Time tCDH 40 ns CSN “H” Time tCSW 150 ns tCSS 50 ns CSN “↑” to CCLK “↑” tCSH 50 ns CCLK “↑” to CSN “↑” Note 18. Except AC coupling. Note 19. Refer to “Serial Data Interface”. Note 20. BICK rising edge must not occur at the same time as LRCK edge. Note 21. Pulse width to ground level when MCLK is connected to a capacitor in series and a resistor is connected to ground. (Refer to Figure 3.)MS0247-E-02 -9-2005/10元器件交易网ASAHI KASEI[AK4367]Parameter Control Interface Timing (I2C Bus mode): (Note 22) SCL Clock Frequency Bus Free Time Between Transmissions Start Condition Hold Time (prior to first clock pulse) Clock Low Time Clock High Time Setup Time for Repeated Start Condition SDA Hold Time from SCL Falling (Note 23) SDA Setup Time from SCL Rising Rise Time of Both SDA and SCL Lines Fall Time of Both SDA and SCL Lines Setup Time for Stop Condition Pulse Width of Spike Noise Suppressed by Input Filter Power-down & Reset Timing PDN Pulse Width (Note 24)Symbol fSCL tBUF tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR tF tSU:STO tSP tPDmin 4.7 4.0 4.7 4.0 4.7 0.25 4.0 0 150typ -max 100 1.0 0.3 50 -Units kHz µs µs µs µs µs µs µs µs µs µs ns nsNote 22. I2C is a registered trademark of Philips Semiconductors. Note 23. Data must be held long enough to bridge the 300ns-transition time of SCL. Note 24. The AK4367 can be reset by bringing PDN pin = “L” to “H” only upon power up.Purchase of Asahi Kasei Microsystems Co., Ltd I2C components conveys a license under the Philips I2C patent to use the components in the I2C system, provided the system conform to the I2C specifications defined by Philips.MS0247-E-02 - 10 -2005/10ASAHI KASEI [AK4367]Timing DiagramMCLK Input Measurement PointVSS1000pFFigure 3. MCLK AC Coupling TimingVIHMCLKVILVIH LRCKVILVIH BICKVILFigure 4. Clock TimingLRCKVIH BICKVILVIH SDATAVIL VIH VILFigure 5. Serial Interface TimingASAHI KASEI [AK4367]CSNVIH CCLKVILVIH CDTI VILVIHVILFigure 6. WRITE Command Input TimingCSNVIH CCLKVILVIH CDTI VILVIHVILD3D2D1D0Figure 7. WRITE Data Input TimingVIHVILVIHVILFigure 8. I 2C Bus Mode TimingVILPDNFigure 9. Power-down & Reset TimingASAHI KASEI [AK4367]OPERATION OVERVIEWSystem ClockThe external clocks required to operate the AK4367 are MCLK(256fs/384fs/512fs), LRCK(fs) and BICK. The master clock (MCLK) should be synchronized with sampling clock (LRCK). The phase between these clocks does not matter. The frequency of MCLK is detected automatically, and the internal master clock becomes the appropriate frequency. Table 1 shows system clock example.LRCK MCLK (MHz) BICK (MHz) fs 256fs 384fs 512fs 64fs 8kHz 2.048 3.072 4.096 0.512 11.025kHz 2.8224 4.2336 5.6448 0.7056 12kHz 3.072 4.608 6.144 0.768 16kHz 4.096 6.144 8.192 1.024 22.05kHz 5.6448 8.4672 11.2896 1.4112 24kHz 6.144 9.216 12.288 1.536 32kHz 8.192 12.288 16.384 2.048 44.1kHz 11.2896 16.9344 22.5792 2.8224 48kHz 12.288 18.432 24.576 3.072Table 1. System Clock ExampleAll external clocks (MCLK, BICK and LRCK) should always be present whenever the DAC is in normal operation mode (PMDAC bit = “1”). If these clocks are not provided, the AK4367 may draw excess current and will not operate properly because it utilizes these clocks for internal dynamic refresh of registers. If the external clocks are not present, the DAC should be placed in power-down mode (PMDAC bit = “0”). When MCLK is input with AC coupling, the MCKAC bit should be set to “1”.For low sampling rates, DR and S/N degrade because of the outband noise. DR and S/N are improved by setting DFS1 bit to “1”. Table 2 shows S/N of DAC output for both the HP-amp and MOUT. When the DFS1 bit is “1”, MCLK needs 512fs.S/N (fs=8kHz, A-weighted) DFS1 DFS0 Over SampleRate fs MCLKHP-amp MOUT0 0 64fs 8kHz ∼48kHz 256fs/384fs/512fs 56dB 56dB Default 0 1 128fs 8kHz ∼24kHz 256fs/384fs/512fs 75dB 75dB 1 x 256fs 8kHz ∼12kHz512fs 92dB 90dB Table 2. Relationship among fs, MCLK frequency and S/N of HP-amp and MOUTASAHI KASEI [AK4367]Serial Data InterfaceThe AK4367 interfaces with external system via the SDATA, BICK and LRCK pins. Five data formats are available and are selected by setting DIF2, DIF1 and DIF0 bits (Table 3). Mode 0 is compatible with existing 16bit DACs and digital filters. Mode 1 is a 20bit version of Mode 0. Mode 4 is a 24bit version of Mode 0. Mode 2 is similar to AKM ADCs and many DSP serial ports. Mode 3 is compatible with the I 2S serial data protocol. In Modes 2 and 3 with BICK ≥48fs, the following formats are also valid: 16-bit data followed by eight zeros (17th to 24th bits) and 20-bit data followed by four zeros (21st to 24th bits). In all modes, the serial data is MSB first and 2’s complement format.DIF2 bit DIF1 bit DIF0 bit MODE BICK Figure 0 0 0 0: 16bit, LSB justified 32fs ≤ BICK ≤ 64fs Figure 10 0 0 1 1: 20bit, LSB justified 40fs ≤ BICK ≤ 64fs Figure 11 0 1 0 2: 24bit, MSB justified 48fs ≤ BICK ≤ 64fsFigure 12Default 0 1 1 3: I 2S Compatible BICK=32fs or 48fs ≤ BICK ≤ 64fs Figure 13 1 0 0 4: 24bit, LSB justified 48fs ≤ BICK ≤ 64fsFigure 11 Table 3. Audio Data FormatSDATA BICK LRCKSDATA BICK (32fs)Mode 0Mode 0Figure 10. Mode 0 TimingSDATA LRCK BICK Mode 1SDATA Mode 4Figure 11. Mode 1, 4 TimingASAHI KASEI [AK4367]LRCKBICK SDATA 16bitSDATA 20bit SDATA 24bitFigure 12. Mode 2 TimingLRCK BICKSDATA 16bit SDATA 20bit SDATA 24bit BICK SDATA 16bit(32fs) Figure 13. Mode 3 TimingASAHI KASEI [AK4367]Digital AttenuatorThe AK4367 has a channel-independent digital attenuator (256 levels, 0.5dB step). This digital attenuator is placed before the D/A converter. ATTL/R7-0 bits set the attenuation level (0dB to −127dB or MUTE) for each channel (Table 4). At DATTC bit = “1”, ATTL7-0 bits control both Lch and Rch attenuation levels. At DATTC bit = “0”, ATTL7-0 bits control the Lch level and ATTR7-0 bits control the Rch level. When HPM bit = “1”, (L+R)/2 summation is done after volume control.ATTL7-0AttenuationATTR7-0DefaultFFH 0dBFEH −0.5dBFDH −1.0dBFCH −1.5dB: :: :02H −126.5dB01H −127.0dB00H MUTE (−∞)Table 4. Digital Volume ATT valuesThe ATS bit sets the transition time between set values of ATT7-0 bits as either 1061/fs or 7424/fs (Table 5). When ATS bit = “0”, a soft transition between the set values occurs(1062 levels). It takes 1061/fs (24ms@fs=44.1kHz) from FFH(0dB) to 00H(MUTE). The ATTs are 00H when the PMDAC bit is “0”. When the PMDAC returns to “1”, the ATTs fade to their current value. Digital attenuator is independent of the soft mute function.ATT speedATS0dB to MUTE 1 stepDefault0 1061/fs 4/fs1 7424/fs 29/fsTable 5. Transition time between set values of ATT7-0 bitsMOUT volume is controlled by ATTM3-0 bits when MMUTE bit = “0” (Table 6). Pop noise occurs when ATT3-0 bits are changed.MMUTE ATTM3-0 Attenuation0FH 0dB0EH −2dB0DH −4dB0CH −6dB: :: :01H −28dB00H −30dBDefault1 x MUTETable 6. MOUT Volume ATT valuesASAHI KASEI [AK4367] Soft MuteSoft mute operation is performed at digital domain. When the SMUTE bit goes to “1”, the output signal is attenuated by −∞ during ATT_DATA×ATT transition time (Table 5) from the current ATT level. When the SMUTE bit is returned to “0”, the mute is cancelled and the output attenuation gradually changes to the ATT level during ATT_DATA×ATT transition time. If the soft mute is cancelled before attenuating to −∞ after starting the operation, the attenuation is discontinued and returned to ATT level by the same cycle. The soft mute is effective for changing the signal source without stopping the signal transmission.Attenuation-∞Analog OutputFigure 14. Soft Mute FunctionNotes:(1) ATT_DATA×ATT transition time (Table 5). For example, this time is 3712LRCK cycles (3712/fs) at ATS bit =“1” and ATT_DATA = “128”.(2) The analog output corresponding to the digital input has a group delay, GD.(3) If the soft mute is cancelled before attenuating to −∞ after starting the operation, the attenuation is discontinuedand returned to ATT level by the same cycle.ASAHI KASEI [AK4367] De-emphasis FilterThe AK4367 includes a digital de-emphasis filter (tc = 50/15µs) by IIR filter corresponding to three sampling frequencies (32kHz, 44.1kHz and 48kHz). The de-emphasis filter is enabled by setting DEM1-0 bits (Table 7).DEM1 bit DEM0 bit De-emphasis44.1kHz0 0Default0 1 OFF48kHz1 01 132kHzTable 7. De-emphasis Filter Frequency SelectBass Boost FunctionBy controlling BST1-0 bits, the low frequency boost signal can be output from DAC. The setting value is common in Lch and Rch (Table 8).BST1 bit BST0 bit BOOSTDefault0 0 OFF0 1 MIN1 0 MID1 1 MAXTable 8. Low Frequency Boost SelectSystem ResetThe AK4367 should be reset once by bringing PDN pin “L” upon power-up. After exiting reset, VCOM, DAC, HPL, HPR and MOUT switch to the power-down state. The contents of the control register are maintained until the reset is done.DAC exits reset and power down state by MCLK after PMDAC bit is changed to “1”, and then DAC is powered up and the internal timing starts clocking by LRCK “↑”. DAC is in power-down mode until MCLK and LRCK are input.ASAHI KASEI [AK4367]Headphone OutputPower supply voltage for the Headphone-amp is supplied from the HVDD pin and centered on the MUTET voltage. The Headphone-amp output load resistance is min.16Ω. When the MUTEN bit is “1” at PMHPL=PMHPR= “1”, the common voltage rises to 0.45 x VDD. When the MUTEN bit is “0”, the common voltage of Headphone-amp falls and the outputs (HPL and HPR pins) go to VSS.A capacitor between the MUTET pin and ground reduces pop noise at power-up/down. It isrecommended that the capacitor with small variation of capacitance and low ESR (Equivalent Series Resistance) over all temperature range, since the rise and fall time in Table 9 depend on the capacitance and ESR of the external capacitor at MUTET pin. In case only one path is connected, DAC or LIN/RIN/MIN. In case both paths are connected,DAC and LIN/RIN/MIN.t r : Rise Time up to VCOM/2 100k x C (typ) 120k x C (typ) t f : Fall Time down to 0V 200k x C (typ) 150k x C (typ)Table 9. Headphone-Amp Rise/Fall Time[Example] : A capacitor between the MUTET pin and ground = 1.0µF, and only DAC path is connected:Time constant of rise time: t r = 100k Ω x 1µF = 100ms(typ) Time constant of fall time: t f = 200k Ω x 1µF = 200ms(typ)When PMHPL and PMHPR bits are “0”, the Headphone-amp is powered-down, and the outputs (HPL and HPR pins) go to VSS.MUTEN bitPMHPL/R bitHPL/R pin(1) (2)(4)(3)t rt f VCOM/2VCOMFigure 15. Power-up/Power-down Timing for Headphone-amp(1) Headphone-amp power-up (PMHPL and PMHPR bits = “1”). The outputs are still VSS.(2) Headphone-amp common voltage rises up (MUTEN bit = “1”). Common voltage of Headphone-amp is rising. This rise time depends on the capacitor value connected with the MUTET pin. The rise time up to VCOM/2 is t r = 100k x C(typ) when the capacitor value on MUTET pin is “C”.(3) Headphone-amp common voltage falls down (MUTEN bit = “0”). Common voltage of Headphone-amp is falling to VSS. This fall time depends on the capacitor value connected with the MUTET pin. The fall time down to 0V is t f = 200k x C(typ) when the capacitor value on MUTET pin is “C”.(4) Headphone-amp power-down (PMHPL, PMHPR bits = “0”). The outputs are VSS. If the power supply is switched off or Headphone-amp is powered-down before the common voltage goes to VSS, some pop noise occurs.ASAHI KASEI [AK4367]The cut-off frequency of Headphone-amp output depends on the external resistor and capacitor used. Table 10 shows the cut off frequency and the output power for various resistor/capacitor combinations. The headphone impedance R L is 16Ω. Output powers are shown at HVDD = 2.4, 3.0 and 3.3V. The output voltage of headphone is 0.47 x VDD (Vpp) @−4.8dBFS.Figure 16. External Circuit Example of HeadphoneOutput Power [mW]R [Ω] C [µF] fc [Hz] BOOST=OFF fc [Hz] BOOST=MIN 2.4V 3.0V 3.3V220 45 170 100 100 43 15 24 28100 70 286.8 47 149 78 7 12 14100 50 191647 106 474 6 7Table 10. Relationship of external circuit, output power and frequency responseASAHI KASEI [AK4367]Power-Up/Down Sequence1) DAC → HP-ampPower Supply PDN pinPMVCM bitClock InputSDTI pin PMDAC bit DAC Internal State HPL/R pinPMHPL, PMHPR bit ATTL7-0 ATTR7-0 bitMUTEN bitDACL, DACR bitFigure 17. Power-up/down sequence of DAC and HP-amp(1) PDN pin should be set to “H” at least 150ns after the power is supplied.(2) PMVCM and PMDAC bits should be changed to “1” after PDN pin goes to “H”.(3) External clocks (MCLK, BICK, LRCK) are needed to operate DAC. When PMDAC bit = “0”, these clocks can bestopped. Headphone amp can operate without these clocks.(4) DACL and DACR bits should be changed to “1” after PMDAC bit is changed to “1”.(5) PMHPL, PMHPR and MUTEN bits should be changed to “1” at least 2ms (in case external capacitance at VCOM pinis 2.2µF) after DACL and DACR bits are changed to “1”.(6) Rise time of headphone amp is determined by external capacitor (C) of MUTET pin. The rise time up to VCOM/2 ist r = 100k x C(typ). When C=1µF, time constant is 100ms(typ).(7) Fall time of headphone amp is determined by external capacitor (C) of MUTET pin. The fall time down to 0V is t f =200k x C(typ). When C=1µF, time constant is 200ms(typ).PMHPL, PMHPR, DACL and DACR bits should be changed to “0” after HPL and HPR pins go to VSS. (8) Analog output corresponding to digital input has the group delay (GD) of 20.8/fs(=472µs@fs=44.1kHz). (9) ATS bit sets transition time of digital attenuator. Default value is 1061/fs(=24ms@fs=44.1kHz).(10) Power supply should be switched off after headphone amp is powered down (HPL/R pins become “L”).ASAHI KASEI [AK4367]2) DAC → MOUTPower SupplyPDN pinPMVCM bitClock InputSDTI pin PMDAC bit DAC Internal State PMMO bit ATTL/R7-0 bit MOUT pinMMUTE, ATTM3-0 bitDACM bitFigure 18. Power-up/down sequence of DAC and MOUT(1) PDN pin should be set to “H” at least 150ns after the power is supplied. (2) PMVCM bit should be changed to “1” after PDN pin goes to “H”.(3) DACM bit should be changed to “1” after PMVCM bit is changed to “1”.(4) PMDAC and PMMO bits should be changed to “1” after DACM bit is changed to “1”.(5)External clocks (MCLK, BICK, LRCK) are needed to operate DAC. When PMDAC bit = “0”, these clocks can be stopped. MOUT buffer can operate without these clocks.(6) When PMMO bit is changed, pop noise is output from MOUT pin.(7) Analog output corresponding to digital input has the group delay (GD) of 20.8/fs(=472µs@fs=44.1kHz). (8) ATS bit sets transition time of digital attenuator. Default value is 1061/fs(=24ms@fs=44.1kHz).ASAHI KASEI [AK4367]3) LIN/RIN/MIN → HP-ampPower SupplyPDN pinPMVCM bitHPL/R pinLIN/RIN/MIN pinPMHPL/R bitMUTEN bitFigure 19. Power-up/down sequence of LIN/RIN/MIN and HP-amp(1) PDN pin should be set to “H” at least 150ns after the power is supplied. MCLK, BICK and LRCK can be stoppedwhen DAC is not used.(2) PMVCM bit should be changed to “1” after PDN pin goes to “H”.(3) LINL, MINL, RINR and MINR bits should be changed to “1” after PMVCM bit is changed to “1”.(4) When LINL, MINL, RINR or MINR bit is changed to “1”, LIN, RIN or MIN pin is biased to 0.45 x VDD voltage. (5) PMHPL, PMHPR and MUTEN bits should be changed to “1” at least 2ms (in case external capacitance at VCOM pinis 2.2µF) after LINL, MINL, RINR and MINR bits are changed to “1”.(6) Rise time of headphone amp is determined by external capacitor (C) of MUTET pin. The rise time up to VCOM/2 ist r = 100k x C(typ). When C=1µF, time constant is 100ms(typ).(7) Fall time of headphone amp is determined by external capacitor (C) of MUTET pin. The fall time down to 0V is t f =200k x C(typ). When C=1µF, time constant is 200ms(typ).PMHPL, PMHPR, LINL, MINL, RINR and MINR bits should be changed to “0” after HPL and HPR pins go to VSS.ASAHI KASEI [AK4367]4) LIN/RIN/MIN → MOUTPower SupplyPDN pinPMVCM bitMOUT pinMMUTE, ATTM3-0 bitLIN/RIN/MIN pin MUTEN bitPMMO bitFigure 20. Power-up/down sequence of LIN/RIN/MIN and MOUT(1) PDN pin should be set to “H” at least 150ns after the power is supplied. MCLK, BICK and LRCK can be stoppedwhen DAC is not used.(2) PMVCM bit should be changed to “1” after PDN pin goes to “H”.(3) LINM, RINM and MINM bits should be changed to “1” after PMVCM bit is changed to “1”.(4) When LINM, RINM or MINM bit is changed to “1”, LIN, RIN or MIN pin is biased to 0.45 x VDD voltage.(5) MUTEN and PMMO bits should be changed to “1” at least 2ms (in case external capacitance at VCOM pin is 2.2µF)after LINM, RINM and MINM bits are changed to “1”.(6) When PMMO bit is changed, pop noise is output from MOUT pin.。

AKD4367中文资料

GENERAL DESCRIPTIONAKD4367 is an evaluation board for 24bit DAC with built-in Headphone Amplifier, AK4367. The AKD4367 has the interface with AKM’s ADC evaluation boards. Therefore, it’s easy to evaluate the AK4367. The AKD4367 also has the digital audio interface and can achieve the interface with digital audio systems via opt-connector.n Ordering guideAKD4367 --- Evaluation board for AK4367(Cable for connecting with printer port of IBM-AT compatible PC and controlsoftware are packed with this. This control software does not operate on Windows NT.)FUNCTION• Compatible with 2 types of interface- Direct interface with AKM’s A/D converter evaluation boards - On-board AK4116 as DIR which accepts optical input• 10pin header for serial control interfaceLIN RIN Opt In A/D Data 10pin HeaderHPRHPL MIN MOUTFigure 1. AKD4367 Block Diagram* Circuit diagram and PCB layout are attached at the end of this manual.Evaluation board Rev.B for AK4367AKD43671. Evaluation Board Manualn Operation sequence1) Set up the power supply lines.[+5V] (red) = 5V[AGND] (black) = 0V : for analog ground[DGND] (black) = 0V : for logic groundEach supply line should be distributed from the power supply unit.2) Set up the evaluation mode, jumper pins.(See the followings.)3) Power on.The AK4367 and AK4116 should be resets once bringing SW1 (DAC_PDN) and SW2 (DIR_PDN) “L” upon power-up.n Evaluation modeApplicable Evaluation Mode(1) In case of using DIR (Optical Link) <default>(2) In case of connecting AK4367 with a external DSP(1) In case of using DIR (Optical Link) <default>PORT1 (DIR) is used. DIR generates MCLK, BICK, LRCK and SDATA from the received data through optical connector (TORX141). Nothing should be connected to PORT3 (DSP).JP5 MCLKJP7LRCKJP84116_SDTO JP6BICKn How to evaluate AK4367 by connecting CD playerAKD4367 can evaluate tone quality easily by connecting CD Player (fs=44.1kHz).1). Connection Diagram2). Jumper and Switch SettingPORT1 (DIR) is used. DIR generates MCLK, BICK, LRCK and SDATA from the received data through optical connector (TORX141). Nothing should be connected to PORT3 (DSP).JP5MCLKJP7LRCKJP84116_SDTOJP6BICKCD Player(2) In case of connecting AK4367 with a external DSPAKD4367 can be connected with an external DSP through PORT3 (DSP).(1) When BICK, LRCK and SDATA are supplied from DSP, and MCLK is supplied from AK4116.JP5 MCLKJP7LRCKJP84116_SDTO JP6BICK(2) When MCLK, BICK, LRCK and SDATA are all supplied from DSP.JP5 MCLKJP7LRCKJP84116_SDTO JP6BICKn The function of the toggle SWUpper-side is “H” and lower-side is “L”.[SW1] (DAC_PDN) : Resets the AK4367. Keep “H” during normal operation.[SW2] (DIR_PDN) : Resets the AK4116. Keep “H” during normal operation.n Indication for LED[LED1] (ERF): Monitor INT0 pin of the AK4116. LED turns on when unlock or parity error occurs.n Serial ControlThe AK4367 can be controlled via the printer port (parallel port) of IBM-AT compatible PC. Connect PORT2 (uP-I/F) with PC by 10 wire flat cable packed with the AKD4367.ConnectCSNCCLKCDTI10pin Header10pinConnector10 wireflat cablePC AKD4367CDTOFigure 2. Connection of 10 wire flat cablen Input / Output circuit & Set-up jumper pin for Input / Output circuits(1) Input CircuitExternal analog signal is fed through the BNC connector. R21 are resistors to terminate the signal source. This resistors is not assembled on the board.MIN, LIN, RIN Input circuitsFigure 3. MIN, LIN, RIN Input circuitsJP2 (AIN) : Input pins are selected for the signals from BNC (J1). MIN : Input to MIN pin. LIN : Input to LIN pin.RIN: Input to RIN pin.(2) Output Circuit(a) MOUT Output circuitFigure 4. MOUT Output circuitsJ1MINLINC18RINJP2MIN J5MOUTR24MOUT(b) HPL, HPR Output circuitFigure 5. HPL, HPR Output circuit1. Outputs of HPL and HPR pins are applied via J2 and J4.JP4HPRLINEHP JP3HPLHP LINE2. Outputs of HPL and HPR pins are applied via J3 (mini jack).JP4HPRLINEHP JP3HPLHP LINE(3) Other Jumper Pins(a) JP1 (GND) : Analog ground and digital ground open :separatedshort :common (The connector “DGND” can be open.) <default>* AKM assumes no responsibility for the trouble when using the circuit examples.HPLHPRJ2HPLJ3HP2. Control Software Manualn Set-up of evaluation board and control software1. Set up the AKD4367 according to previous term.2. Connect IBM-AT compatible PC with AKD4367 by 10-line type flat cable (packed with AKD4367). Take care of thedirection of 10pin header. (Please install the driver in the CD-ROM when this control software is used on Windows 2000/XP. Please refer “Installation Manual of Control Software Driver by AKM device control software”. In case of Windows95/98/ME, this installation is not needed. This control software does not operate on Windows NT.)3. Insert the CD-ROM labeled “AK4367 Evaluation Kit” into the CD-ROM drive.4. Access the CD-ROM drive and double-click the icon of “akd4367.exe” to set up the control program.5. Then please evaluate according to the follows.n Operation flowKeep the following flow.1. Set up the control program according to explanation above.2. Click “Port Setup” button.3. Click “Write default” button.Then set up the dialog and input data.n Explanation of each buttons1. [Port Setup] : Set up the printer port.2. [Write default] : Initialize the register of AK4367.3. [Function1] : Dialog to write data by keyboard operation.4. [Function2] : Dialog to evaluate ATT.5. [Write] : Dialog to write data by mouse operation.n Explanation of each dialog1. [Function1 Dialog] : Dialog to write data by keyboard operationAddress Box: Input register address in 2 figures of hexadecimal.Data Box: Input register data in 2 figures of hexadecimal.If you want to write the input data to AK4367, click “OK” button. If not, click “Cancel” button.2. [Function2 Dialog] : Dialog to evaluate ATTThis dialog corresponds to only addr=04H, 05H and 08H.Address Box: Input register address in 2 figures of hexadecimal.Start Data Box: Input start data in 2 figures of hexadecimal.End Data Box: Input end data in 2 figures of hexadecimal.Interval Box: Data is written to AK4367 by this interval.Step Box: Data changes by this step.Mode Select Box:If you check this check box, data reaches end data, and returns to start data.[Example] Start Data = 00, End Data = 09Data flow: 00 01 02 03 04 05 06 07 08 09 09 08 07 06 05 04 03 02 01 00If you do not check this check box, data reaches end data, but does not return to start data.[Example] Start Data = 00, End Data = 09Data flow: 00 01 02 03 04 05 06 07 08 09If you want to write the input data to AK4367, click “OK” button. If not, click “Cancel” button.3. [Write Dialog] : Dialog to write data by mouse operationThere are dialogs corresponding to each register.Click the “Write” button corresponding to each register to set up the dialog. If you check the check box, data becomes “H” or “1”. If not, “L” or “0”.If you want to write the input data to AK4367, click “OK” button. If not, click “Cancel” button.n Indication of dataInput data is indicated on the register map. Red letter indicates “H” or “1” and blue one indicates “L” or “0”. Blank is the part that is not defined in the datasheet.n Attention on the operationIf you set up Function1 or Function2 dialog, input data to all boxes. Attention dialog is indicated if you input data or address that is not specified in the datasheet or you click “OK” button before you input data. In that case set up the dialog and input data once more again. These operations does not need if you click “Cancel” button or check the check box.MEASUREMENT RESULTS[Measurement condition]• Measurement unit : Audio Precession System Two Cascade• MCLK : 12.2896MHz• BICK : 64fs• fs : 44.1kHz• Bit : 24bit• Power Supply : VDD = HVDD = 3.3V• Measurement Filter : 10Hz ∼ 20kHz• Temperature : RoomParameter Result (Lch / Rch) UnitDAC Analog Output CharacteristicsTHD+N (-3dBFS Output) 56.8 / 56.1 dBD-Range (-60dB Output, A-weighted) 93.0 / 93.0 dBS/N (A-weighted) 94.9 / 93.8 dBMonaural Output CharacteristicsTHD+N (0dBFS Output) 64.5 dBS/N (A-weighted) 95.4 dB[Plot of Headphone Amplifier]AKMAK4367 HP-Amp THD+N vs. Input Level (fs=44.1kHz, fIn=1kHz)d B r A-140+0-130-120-110-100-90-80-70-60-50-40-30-20-10dBFSFigure 1. THD+N vs. Input LevelAKMAK4367 HP-Amp THD+N vs. fin (fs=44.1kHz, Input Level=-3dB)d B r AHzFigure 2. THD+N vs. Input FrequencyAKMAK4367 HP-Amp Linearity (fs=44.1kHz, fin=1kHz)d B r A-140+0-130-120-110-100-90-80-70-60-50-40-30-20-10dBFSFigure 3. LinearityAKMAK4367 HP-Amp Frequency Response (fs=44.1kHz, Input Level=-3dB)d B r A2020k501002005001k 2k 5k 10k HzFigure 4. Frequency Response (Boost off)(including external HPF)AKMAK4367 HP-Amp FFT Out-of-band Noise-120-110-100-90-80d B r A20100k501002005001k2k 5k 10k 20k 50k HzFigure 5. Out-band NoiseAKMAK4367 HP-Amp FFT (fs=44.1kHz, fin=1kHz, Input Level=-3dB)+0-130-120-110-100-90-80-70-60-50-40-30-20-10d B r A2020k501002005001k2k5k10kHzFigure 6. FFT Plot-130-120-110-100-90-80-70-60d B r A2020k501002005001k 2k 5k 10k HzFigure 7. FFT PlotAKMAK4367 HP-Amp FFT Noise Floor (No data Input)-130-120d B r A2020k501002005001k2k5k10kHzFigure 8. FFT PlotUpper@1kHz:Lch-->Rch, Lower@1kHz:Rch-->LchdB2020k 501002005001k2k5k10kHzFigure 9. Crosstalk PlotIMPORTANT NOTICE• These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status.• AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein.• Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials.• AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here:(a) A hazard related device or system is one designed or intended for life support or maintenance ofsafety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property.(b) A critical component is one whose failure to function or perform may reasonably be expected toresult, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability.• It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification.。

AK4626VQP资料

ASAHI KASEI[AK4626]AK4626High Performance Multi-channel Audio CODECGENERAL DESCRIPTION The AK4626 is a single chip CODEC that includes two channels of ADC and six channels of DAC. The ADC outputs 24bit data and the DAC accepts up to 24bit input data. The ADC has the Enhanced Dual Bit architecture with wide dynamic range. The DAC introduces the newly developed Advanced Multi-Bit architecture, and achieves wider dynamic range and lower outband noise. An auxiliary digital audio input interface maybe used instead of the ADC for passing audio data to the primary audio output port. Control may be set directly by pins or programmed through a separate serial interface. The AK4626 has a dynamic range of 102dB for ADC, 106dB for DAC and is well suited for digital surround for home theater and car audio. An AC-3 system can be built with a IEC60958(SPDIF) receiver such as the AK4112B. The AK4626 is available in a small 44pin LQFP package which will reduce system space.*AC-3 is a trademark of Dolby Laboratories.FEATURES 2ch 24bit ADC - 64x Oversampling - Sampling Rate up to 96kHz - Linear Phase Digital Anti-Alias Filter - Single-Ended Input - S/(N+D): 92dB - Dynamic Range, S/N: 102dB - Digital HPF for offset cancellation - I/F format: MSB justified, I2S or TDM - Overflow flag 6ch 24bit DAC - 128x Oversampling - Sampling Rate up to 192kHz - 24bit 8 times Digital Filter - Single-Ended Outputs - On-chip Switched-Capacitor Filter - S/(N+D): 90dB - Dynamic Range, S/N: 106dB - I/F format: MSB justified, LSB justified(20bit,24bit), I2S or TDM - Individual channel digital volume with 128 levels and 0.5dB step - Soft mute - De-emphasis for 32kHz, 44.1kHz and 48kHz - Zero Detect Function High Jitter Tolerance TTL Level Digital I/F 3-wire Serial and I2C Bus µP I/F for mode setting Master clock:256fs, 384fs or 512fs for fs=32kHz to 48kHz 128fs, 192fs or 256fs for fs=64kHz to 96kHz 128fs for fs=120kHz to 192kHz Power Supply: 4.5 to 5.5V Power Supply for output buffer: 2.7 to 5.5V Small 44pin LQFP AK4628 Pin CompatibleMS0233- E-01 -1-2004/03ASAHI KASEI[AK4626]Block DiagramLINADC ADCHPF HPFAudio I/FRINRX1 RX2 RX3 RX4 XTILOUT1LPFDACDATTMCLK LRCK BICKMCLK LRCK BICK DAUXXTO MCKO LRCK BICK SDTODIR AK4112BROUT1LPFDACDATTLOUT2LPFDACDATTFormat ConverterROUT2LPFDACDATTSDOUT SDOS SDTO LRCK BICK SDIN SDOUT1 SDOUT2 SDOUT3AC3LOUT3LPFDACDATTSDIN1 SDIN2 SDIN3ROUT3LPFDACDATTSDTI1 SDTI2 SDTI3AK4626Block Diagram (DIR and AC-3 DSP are external parts)MS0233- E-01 -2-2004/03ASAHI KASEI[AK4626]Ordering GuideAK4626VQ AKD4626 -40 ∼ +85°C 44pin LQFP(0.8mm pitch) Evaluation Board for AK4626Pin LayoutLOOP0/SDA/CDTIDIF1/SCL/CCLKDIF0/CSNVREFH 35MCLK444143424037AVSSAVDDDZF1P/S3938SDOS I2C SMUTE BICK LRCK SDTI1 SDTI2 SDTI3 SDTO DAUX DFS01 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Top View3634 33 32 31VCOMTDM0DZF2/OVF RIN LIN NC TST5 ROUT1 LOUT1 ROUT2 LOUT2 ROUT3 LOUT3AK4626VQ30 29 28 27 26 25 24 23DVDDDVSSTVDDCAD1CAD0DZFETST1TST2TST3MS0233- E-01 -3-TST4PDN2004/03ASAHI KASEI[AK4626]Compatibility with AK4527B1. Functions Functions DAC Sampling frequency TDM128 (96kHz) Digital Attenuator Soft Mute Analog Input (ADC) 2. Pin Configurationpin# 11 12 18 19 20 21 22 29 30 31 32 44 AK4527B DFS NC TEST NC ADIF CAD1 CAD0 LINLIN+ RINRIN+ LOOP1 AK4626 DFS0 TST1 TST2 CAD1 CAD0 TST3 TST4 TST5 NC LIN RINAK4527B Up to 96kHz Not available 256 levels Soft mute function is independent of Digital attenuator. Differential inputAK4626 Up to 192kHz Available 128 levels Soft mute function is not independent of Digital attenuator. Single-ended InputTDM03. RegisterAddr 00H 00H 01H 01H 09H 0AH AK4527B Not available Not available DFS Not available Not available Not available AK4626 TDM0 TDM1 DFS0 DFS1 ATS1, ATS0 DZFM3MS0233- E-01 -4-2004/03ASAHI KASEI[AK4626]PIN/FUNCTIONNo. 1 Pin Name SDOS I/O I Function SDTO Source Select Pin (Note 1) “L”: Internal ADC output, “H”: DAUX input SDOS pin should be set to “L” when TDM= “1”. Control Mode Select Pin “L”: 3-wire Serial, “H”: I2C Bus Soft Mute Pin (Note 1) When this pin goes to “H”, soft mute cycle is initialized. When returning to “L”, the output mute releases. Audio Serial Data Clock Pin Input Channel Clock Pin DAC1 Audio Serial Data Input Pin DAC2 Audio Serial Data Input Pin DAC3 Audio Serial Data Input Pin Audio Serial Data Output Pin AUX Audio Serial Data Input Pin Double Speed Sampling Mode Pin (Note 1) “L”: Normal Speed, “H”: Double Speed Test Pin This pin should be connected to DVSS. Zero Input Detect Enable Pin “L”: mode 7 (disable) at parallel mode, zero detect mode is selectable by DZFM3-0 bits at serial mode “H”: mode 0 (DZF1 is AND of all six channels) Output Buffer Power Supply Pin, 2.7V∼5.5V Digital Power Supply Pin, 4.5V∼5.5V Digital Ground Pin, 0V Power-Down & Reset Pin When “L”, the AK4626 is powered-down and the control registers are reset to default state. If the state of P/S or CAD1-0 changes, then the AK4626 must be reset by PDN. Test Pin This pin should be connected to DVSS. Chip Address 1 Pin Chip Address 0 Pin Test Pin This pin should be left floating. Test Pin This pin should be left floating.2 3I2C SMUTEI I4 5 6 7 8 9 10 11 12 13BICK LRCK SDTI1 SDTI2 SDTI3 SDTO DAUX DFS0 TST1 DZFEI I I I I O I I I I14 15 16 17TVDD DVDD DVSS PDNI18 19 20 21 22TST2 CAD1 CAD0 TST3 TST4I I I O OMS0233- E-01 -5-2004/03ASAHI KASEI[AK4626]No. 23 24 25 26 27 28 29 30 31 32 33Pin Name LOUT3 ROUT3 LOUT2 ROUT2 LOUT1 ROUT1 TST5 NC LIN RIN DZF2I/O O O O O O O I I I OOVF 34 35 36 37 38 VCOM VREFH AVDD AVSS DZF1O O I O39 40 41MCLK P/S DIF0 CSN DIF1 SCL/CCLK LOOP0 SDA/CDTII I I I I I I I/O I424344TDM0Function DAC3 Lch Analog Output Pin DAC3 Rch Analog Output Pin DAC2 Lch Analog Output Pin DAC2 Rch Analog Output Pin DAC1 Lch Analog Output Pin DAC1 Rch Analog Output Pin Test pin (Internal pull-down pin) This pin should be left floating or connected to AVSS. No Connect No internal bonding. Lch Analog Input Pin Rch Analog Input Pin Zero Input Detect 2 Pin (Note 2) When the input data of the group 1 follow total 8192 LRCK cycles with “0” input data, this pin goes to “H”. And when RSTN bit is “0”, PWDAN pin is “0”, this pin goes to “H”. It always is in “L” when P/S is “H”. Analog Input Overflow Detect Pin (Note 3) This pin goes to “H” if the analog input of Lch or Rch overflows. Common Voltage Output Pin, AVDD/2 Large external capacitor around 2.2µF is used to reduce power-supply noise. Positive Voltage Reference Input Pin, AVDD Analog Power Supply Pin, 4.5V∼5.5V Analog Ground Pin, 0V Zero Input Detect 1 Pin (Note 2) When the input data of the group 1 follow total 8192 LRCK cycles with “0” input data, this pin goes to “H”. And when RSTN bit is “0”, PWDAN pin is “0”, this pin goes to “H”. Output is selected by setting DZFE pin when P/S is “H”. Master Clock Input Pin Parallel/Serial Select Pin “L”: Serial control mode, “H”: Parallel control mode Audio Data Interface Format 0 Pin in parallel control mode Chip Select Pin in 3-wire serial control mode This pin should be connected to DVDD at I2C bus control mode Audio Data Interface Format 1 Pin in parallel control mode Control Data Clock Pin in serial control mode I2C = “L”: CCLK (3-wire Serial), I2C = “H”: SCL (I2C Bus) Loopback Mode 0 Pin in parallel control mode Enables digital loop-back from ADC to 3 DACs. Control Data Input Pin in serial control mode I2C = “L”: CDTI (3-wire Serial), I2C = “H”: SDA (I2C Bus) TDM I/F Format Mode Pin (Note 1) “L”: Normal mode, “H”: TDM modeNotes: 1. SDOS, SMUTE, DFS0, and TDM0 pins are ORed with register data if P/S = “L”. 2. The group 1 and 2 can be selected by DZFM3-0 bits if P/S = “L” and DZFE = “L”. 3. This pin becomes OVF pin if OVFE bit is set to “1” at serial control mode. 4. All digital input pins except for pull-down should not be left floating.MS0233- E-01 -6-2004/03ASAHI KASEI[AK4626]ABSOLUTE MAXIMUM RATINGS (AVSS, DVSS=0V; Note 5) Parameter Symbol min AVDD -0.3 Power Supplies Analog DVDD -0.3 Digital TVDD -0.3 Output buffer |AVSS-DVSS| (Note 6) ∆GND Input Current (any pins except for supplies) IIN Analog Input Voltage VINA -0.3 Digital Input Voltage (Expect LRCK, BICK pins) VIND1 -0.3 (LRCK, BICK pins) VIND2 -0.3 Ambient Temperature (power applied) Ta -40 Storage Temperature Tstg -65Notes: 5. All voltages with respect to ground. 6. AVSS and DVSS must be connected to the same analog ground plane.max 6.0 6.0 6.0 0.3 ±10 AVDD+0.3 DVDD+0.3 TVDD+0.3 85 150Units V V V V mA V V V °C °CWARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.RECOMMENDED OPERATING CONDITIONS (AVSS, DVSS=0V; Note 5) Parameter Symbol min typ Power Supplies Analog AVDD 4.5 5.0 (Note 7) Digital DVDD 4.5 5.0 Output buffer TVDD 2.7 5.0max 5.5 5.5 5.5Units V V VNotes: 5. All voltages with respect to ground. 7. The power up sequence between AVDD, DVDD and TVDD is not critical. Do not turn off only the AK4626 under the condition that a surrounding device is powered on and the I2C bus is in use. WARNING: AKM assumes no responsibility for the usage beyond the conditions in this datasheet.MS0233- E-01 -7-2004/03ASAHI KASEI[AK4626]ANALOG CHARACTERISTICS (Ta=25°C; AVDD, DVDD, TVDD=5V; AVSS, DVSS=0V; VREFH=AVDD; fs=48kHz; BICK=64fs; Signal Frequency=1kHz; 24bit Data; Measurement Frequency=20Hz∼20kHz at 48kHz, 20Hz~40kHz at fs=96kHz, 20Hz~40kHz at fs=192kHz; unless otherwise specified) Parameter min typ max Units ADC Analog Input Characteristics Resolution 24 Bits S/(N+D) (-0.5dBFS) fs=48kHz 84 92 dB fs=96kHz 86 dB DR (-60dBFS) fs=48kHz, A-weighted 94 102 dB fs=96kHz 88 96 dB fs=96kHz, A-weighted 93 102 dB dB 102 94 S/N (Note 8) fs=48kHz, A-weighted dB 96 88 fs=96kHz dB 102 93 fs=96kHz, A-weighted Interchannel Isolation 90 110 dB DC Accuracy Interchannel Gain Mismatch 0.2 0.3 dB Gain Drift 20 ppm/°CInput Voltage AIN=0.62xVREFH 2.90 3.10 3.30 VppInput Resistance (Note 9) Power Supply Rejection (Note 10) DAC Analog Output Characteristics Resolution S/(N+D) fs=48kHz fs=96kHz fs=192kHz DR (-60dBFS) fs=48kHz, A-weighted fs=96kHz fs=96kHz, A-weightedfs=192kHz fs=192kHz, A-weighted1525 50 24kΩ dB Bits dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB ppm/°C Vpp kΩ dBS/N(Note 11)fs=48kHz, A-weighted fs=96kHz fs=96kHz, A-weightedfs=192kHz fs=192kHz, A-weightedInterchannel Isolation DC Accuracy Interchannel Gain Mismatch Gain Drift Output Voltage AOUT=0.6xVREFH Load Resistance Power Supply Rejection Notes:80 78 95 88 94 95 88 94 9090 88 88 106 100 106 100 106 106 100 106 100 106110 0.2 20 3.0 50 0.5 3.252.75 5 (Note 10)8. S/N measured by CCIR-ARM is 98dB(@fs=48kHz). 9. Input resistance is 16kΩ typically at fs=96kHz. 10. PSR is applied to AVDD, DVDD and TVDD with 1kHz, 50mVpp. VREFH pin is held a constant voltage. 11. S/N measured by CCIR-ARM is 102dB(@fs=48kHz).MS0233- E-01 -8-2004/03ASAHI KASEI[AK4626]Parameter Power SuppliesPower Supply Current (AVDD+DVDD+TVDD) Normal Operation (PDN = “H”) AVDD fs=48kHz,96kHz fs=192kHz DVDD+TVDD fs=48kHz fs=96kHz fs=192kHz Power-down mode (PDN = “L”) TST=”L”mintypmaxUnits(Note 12)(Note 13)45 34 18 24 27 8067 51 27 36 40 200mA mA mA mA mA µANotes: 12. TVDD=0.1mA(typ). 13. In the power-down mode. All digital input pins including clock pins (MCLK, BICK, LRCK) are held DVSS.MS0233- E-01 -9-2004/03ASAHI KASEI[AK4626]FILTER CHARACTERISTICS (Ta=25°C; AVDD, DVDD=4.5∼5.5V; TVDD=2.7∼5.5V; fs=48kHz) Parameter Symbol min ADC Digital Filter (Decimation LPF): PB 0 Passband (Note 14) ±0.1dB -0.2dB -3.0dB Stopband SB 28 Passband Ripple PR Stopband Attenuation SA 68 Group Delay (Note 15) GD Group Delay Distortion ∆GD ADC Digital Filter (HPF): Frequency Response (Note 14) -3dB FR -0.1dB DAC Digital Filter: Passband (Note 14) -0.1dB PB 0 -6.0dB Stopband SB 26.2 Passband Ripple PR Stopband Attenuation SA 54 Group Delay (Note 15) GD DAC Digital Filter + Analog Filter: FR Frequency Response: 0 ∼ 20.0kHz FR 40.0kHz (Note 16) FR 80.0kHz (Note 16)typmax 18.9 ±0.04Units kHz kHz kHz kHz dB dB 1/fs µs Hz Hz20.0 23.016 0 1.0 6.5 21.8 ±0.02 19.2±0.2 ±0.3 ±1.024.0kHz kHz kHz dB dB 1/fs dB dB dBNotes: 14. The passband and stopband frequencies scale with fs. For example, 21.8kHz at –0.1dB is 0.454 x fs. 15. The calculating delay time which occurred by digital filtering. This time is from setting the input of analog signal to setting the 24bit data of both channels to the output register for ADC. For DAC, this time is from setting the 20/24bit data of both channels on input register to the output of analog signal. 16. 40.0kHz; fs=96kHz , 80.0kHz; fs=192kHz.DC CHARACTERISTICS (Ta=25°C; AVDD, DVDD=4.5∼5.5V; TVDD=2.7∼5.5V) Parameter Symbol min High-Level Input Voltage VIH 2.2 Low-Level Input Voltage VIL High-Level Output Voltage (SDTO, LRCK, BICK pin: Iout=-100µA) VOH TVDD-0.5 (DZF1, DZF2/OVF pins: Iout=-100µA) VOH AVDD-0.5 Low-Level Output Voltage (SDTO, DZF1, DZF2/OVF pins: Iout= 100µA) VOL (SDA, LRCK, BICK pin: Iout= 3mA) VOL Input Leakage Current (Note 17) Iin Note 17: TST2 pin has an internal pull-down device, nominally 100kohm.typ -max 0.8 0.5 0.4 ±10Units V V V V V V µAMS0233- E-01 - 10 -2004/03SWITCHING CHARACTERISTICS(Ta=-40°C∼85°C; AVDD, DVDD=4.5∼5.5V; TVDD=2.7∼5.5V; C L=20pF)Parameter SymbolmintypmaxUnits Master Clock Timing256fsn, 128fsd: Pulse Width Low Pulse Width High 384fsn, 192fsd: Pulse Width Low Pulse Width High 512fsn, 256fsd: Pulse Width Low Pulse Width High fCLKtCLKLtCLKHfCLKtCLKLtCLKHfCLKtCLKLtCLKH8.192272712.288202016.384151512.28818.43224.576MHznsnsMHznsnsMHznsnsLRCK TimingNormal mode (TDM0= “0”, TDM1= “0”)Normal Speed Mode Double Speed Mode Quad Speed Mode Duty Cycle fsnfsdfsqDuty326412045489619255kHzkHzkHz%TDM256 mode (TDM0= “1”, TDM1= “0”)LRCK frequency “H” time“L” time fsntLRHtLRL321/256fs1/256fs48 kHznsnsTDM128 mode (TDM0= “1”, TDM1= “1”)LRCK frequency “H” time“L” timefsdtLRHtLRL641/128fs1/128fs96 kHznsnsAudio Interface TimingNormal mode (TDM0= “0”, TDM1= “0”)BICK PeriodBICK Pulse Width LowPulse Width HighLRCK Edge to BICK “↑” (Note 18) BICK “↑” to LRCK Edge (Note 18) LRCK to SDTO(MSB)BICK “↓” to SDTOSDTI1-3,DAUX Hold TimeSDTI1-3,DAUX Setup Time tBCKtBCKLtBCKHtLRBtBLRtLRStBSDtSDHtSDS813232202020204040nsnsnsnsnsnsnsnsnsnsTDM256 mode (TDM0= “1”, TDM1= “0”)BICK PeriodBICK Pulse Width LowPulse Width HighLRCK Edge to BICK “↑” (Note 18) BICK “↑” to LRCK Edge (Note 18) BICK “↓” to SDTOSDTI1 Hold TimeSDTI1 Setup Time tBCKtBCKLtBCKHtLRBtBLRtBSDtSDHtSDS8132322020101020nsnsnsnsnsnsnsnsnsTDM128 mode (TDM0= “1”, TDM1= “1”)BICK PeriodBICK Pulse Width LowPulse Width HighLRCK Edge to BICK “↑” (Note 18) BICK “↑” to LRCK Edge (Note 18) BICK “↓” to SDTOSDTI1-2 Hold TimeSDTI1-2 Setup Time tBCKtBCKLtBCKHtLRBtBLRtBSDtSDHtSDS8132322020101020nsnsnsnsnsnsnsnsnsNotes: 18. BICK rising edge must not occur at the same time as LRCK edge.Parameter SymbolmintypmaxUnitsControl Interface Timing (3-wire Serial mode):CCLK PeriodCCLK Pulse Width LowPulse Width High CDTI Setup Time CDTI Hold TimeCSN “H” TimeCSN “↓” to CCLK “↑” CCLK “↑” to CSN “↑” tCCKtCCKLtCCKHtCDStCDHtCSWtCSStCSH200808040401505050nsnsnsnsnsnsnsnsControl Interface Timing (I2C Bus mode):SCL Clock FrequencyBus Free Time Between TransmissionsStart Condition Hold Time (prior to first clock pulse) Clock Low TimeClock High TimeSetup Time for Repeated Start ConditionSDA Hold Time from SCL Falling (Note 19) SDA Setup Time from SCL RisingRise Time of Both SDA and SCL LinesFall Time of Both SDA and SCL LinesSetup Time for Stop ConditionPulse Width of Spike Noise Suppressed by Input Filter fSCLtBUFtHD:STAtLOWtHIGHtSU:STAtHD:DATtSU:DATtRtFtSU:STOtSP-4.74.04.74.04.70.25--4.0100-------1.00.3-50kHzµsµsµsµsµsµsµsµsµsµsnsPower-down & Reset TimingPDN Pulse Width (Note 20) PDN “↑” to SDTO valid (Note 21) tPDtPDV150522ns1/fsNotes: 19. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.20. The AK4626 can be reset by bringing PDN “L” to “H” upon power-up.21. These cycles are the number of LRCK rising from PDN rising.22. I2C is a registered trademark of Philips Semiconductors.Purchase of Asahi Kasei Microsystems Co., Ltd I2C components conveys a license under the Philips I2C patent to use the components in the I2C system, provided the system conform to the I2Cspecifications defined by Philips.Timing DiagramVIHMCLKVILLRCKVIH VILVIH BICKVILClock Timing (TDM= “0”)VIH MCLKVILLRCKVIH VILVIH BICKVILClock Timing (TDM= “1”)LRCKVIH BICKVILSDTO50%TVDDVIH VILSDTIVIH VILAudio Interface Timing (TDM= “0”)LRCKVIH BICKVILSDTO50%TVDDVIH VILSDTIVIH VILAudio Interface Timing (TDM= “1”)CSNVIH CCLKVILVIH CDTI VILVIHVILWRITE Command Input Timing (3-wire Serial mode)CSNVIH CCLKVILVIH CDTI VILVIHVILD3D2D1D0WRITE Data Input Timing (3-wire Serial mode)VIHVILVIHVILI 2C Bus mode TimingVILPDNSDTO 50%TVDDVIHPower-down & Reset TimingOPERATION OVERVIEWSystem ClockThe external clocks, which are required to operate the AK4626, are MCLK, LRCK and BICK. MCLK should be synchronized with LRCK but the phase is not critical. There are two methods to set MCLK frequency. In Manual Setting Mode (ACKS = “0”: Default), the sampling speed is set by DFS0, DFS1 (Table 1). The frequency of MCLK at each sampling speed is set automatically. (Table 2, 3, 4). In Auto Setting Mode (ACKS = “1”), as MCLK frequency is detected automatically (Table 5), and the internal master clock becomes the appropriate frequency (Table 6), it is not necessary to set DFS.External clocks (MCLK, BICK) should always be present whenever the AK4626 is in normal operation mode (PDN = “H”). If these clocks are not provided, the AK4626 may draw excess current because the device utilizes dynamic refreshed logic internally. If the external clocks are not present, the AK4626 should be in the power-down mode (PDN = “L”) or in the reset mode (RSTN = “0”). After exiting reset at power-up etc., the AK4626 is in the power-down mode until MCLK and LRCK are input.(fs)SpeedDFS1 DFS0 SamplingDefaultMode 32kHz~48kHzSpeed0 0 Normal0 1 DoubleMode 64kHz~96kHzSpeedMode 120kHz~192kHz1 0 QuadSpeedTable 1. Sampling Speed (Manual Setting Mode)(MHz) BICK(MHz) LRCK MCLKfs 256fs 384fs 512fs 64fs32.0kHz 8.1920 12.2880 16.3840 2.048044.1kHz 11.2896 16.9344 22.5792 2.822448.0kHz 12.2880 18.4320 24.5760 3.0720Table 2. System Clock Example (Normal Speed Mode @Manual Setting Mode)LRCK MCLK (MHz) BICK (MHz)fs 128fs 192fs 256fs 64fs88.2kHz 11.2896 16.9344 22.5792 5.644896.0kHz 12.2880 18.4320 24.5760 6.1440Table 3. System Clock Example (Double Speed Mode @Manual Setting Mode)(Note: At Double speed mode(DFS1= “0”, DFS0 = “1”), 128fs and 192fs are not available for ADC.)LRCK MCLK (MHz) BICK (MHz)fs 128fs 192fs 256fs 64fs176.4kHz 22.5792 - - 11.2896192.0kHz 24.5760 - - 12.2880Table 4. System Clock Example (Quad Speed Mode @Manual Setting Mode)(Note: At Quad speed mode(DFS1= “1”, DFS0 = “0”) are not available for ADC.)MCLK Sampling Speed512fs Normal 256fs Double 128fs QuadTable 5. Sampling Speed (Auto Setting Mode)LRCK MCLK (MHz) fs 128fs 256fs 512fs Sampling Speed 32.0kHz - - 16.384044.1kHz - - 22.579248.0kHz - - 24.5760 Normal 88.2kHz - 22.5792 -96.0kHz - 24.5760 - Double176.4kHz 22.5792 - -192.0kHz 24.5760 - -QuadTable 6. System Clock Example (Auto Setting Mode)De-emphasis FilterThe AK4626 includes the digital de-emphasis filter (tc=50/15µs) by IIR filter. De-emphasis filter is not available in Double Speed Mode and Quad Speed Mode. This filter corresponds to three sampling frequencies (32kHz, 44.1kHz, 48kHz). De-emphasis of each DAC can be set individually by register data of DEMA1-C0 (DAC1: DEMA1-0, DAC2: DEMB1-0, DAC3: DEMC1-0, see “Register Definitions”).Mode Sampling Speed DEM1 DEM0 DEM 0 Normal Speed 0 0 44.1kHz 1 Normal Speed 0 1 OFF2 Normal Speed 1 0 48kHz3 Normal Speed 1 1 32kHzDefaultTable 7. De-emphasis controlDigital High Pass FilterThe ADC has a digital high pass filter for DC offset cancel. The cut-off frequency of the HPF is 1.0Hz at fs=48kHz and scales with sampling rate (fs).Audio Serial Interface FormatWhen TDM= “L”, four modes can be selected by the DIF1-0 as shown in Table 8. In all modes the serial data is MSB-first, 2’s compliment format. The SDTO is clocked out on the falling edge of BICK and the SDTI/DAUX are latched on the rising edge of BICK.Figures 1∼4 shows the timing at SDOS = “L”. In this case, the SDTO outputs the ADC output data. When SDOS = “H”, the data input to DAUX is converted to SDTO’s format and output from SDTO. Mode 2, 3, 6, 7, 10, 11 in SDTI input formats can be used for 16-20bit data by zeroing the unused LSBs.LRCK BICK ModeTDM 1TDM0 DIF1 DIF0SDTOSDTI1-3, DAUXI/O I/O0 0 0 0 024bit, Left justified 20bit, Rightjustified H/L I ≥ 48fs I 1 0 0 0 1 24bit, Left justified 24bit, Rightjustified H/LI ≥ 48fs I 2 0 0 1 0 24bit, Left justified 24bit, LeftjustifiedH/LI≥ 48fsI Default 3 0 0 1 1 24bit, I 2S 24bit, I 2S L/HI ≥ 48fsITable 8. Audio data formats (Normal mode)The audio serial interface format becomes the TDM mode if TDM0 pin is set to “H”. In the TDM256 mode, the serial data of all DAC (six channels) is input to the SDTI1 pin. The input data to SDTI2-3 pins are ignored. BICK should be fixed to 256fs. “H” time and “L” time of LRCK should be 1/256fs at least. Four modes can be selected by the DIF1-0 as shown in Table 9. In all modes the serial data is MSB-first, 2’s compliment format. The SDTO is clocked out on the falling edge of BICK and the SDTI1 are latched on the rising edge of BICK. SDOS and LOOP1-0 should be set to “0” at the TDM mode. TDM128 Mode can be set by TDM1 as show in Table10. In Double Speed Mode, the serial data of DAC (four channels; L1, R1, L2, R2) is input to the SDTI1 pin. Other two data (L3, R3) are input to the SDTI2. TDM0 pin and TDM0 register should be set to “H” if TDM256 Mode is selected. TDM0 pin and TDM0 register, TDM1 register should be set to “H” if Double Speed Mode is selected in TDM128 Mode.LRCK BICKMode TDM 1 TDM0 DIF1 DIF0SDTOSDTI1I/O I/O4 0 1 0 024bit, Left justified 20bit, Rightjustified ↑ I 256fs I5 0 1 0 124bit, Left justified 24bit, Rightjustified ↑ I 256fs I 6 0 1 1 024bit, Left justified 24bit, Leftjustified↑ I 256fs I 7 0 1 1 1 24bit, I 2S 24bit, I 2S↓I 256fs ITable 9. Audio data formats (TDM256 mode)LRCK BICK Mode TDM 1 TDM0 DIF1 DIF0SDTOSDTI1,SDTI2I/O I/O8 1 1 0 024bit, Left justified 20bit, Rightjustified ↑ I 128fs I9 1 1 0 124bit, Left justified 24bit, Rightjustified ↑ I 128fs I 10 1 1 1 024bit, Left justified 24bit, Leftjustified↑ I 128fs I 11 1 1 1 1 24bit, I 2S 24bit, I 2S↓I 128fs ITable 10. Audio data formats (TDM128 mode)BICK(64fs)SDTO(o)SDTI(i)Figure 1. Mode 0 Timing Array LRCKBICK(64fs)SDTO(o)SDTI(i)Figure 2. Mode 1 TimingLRCKSDTO(o)SDTI(i)Figure 3. Mode 2 Timing ArrayLRCKSDTO(o)SDTI(i)Figure 4. Mode 3 TimingLRCKBICK(256fs)SDTO(o)SDTI1(i)Figure 5. Mode 4 TimingLRCKBICK(256fs)SDTO(o)SDTI1(i)Figure 6. Mode 5 TimingLRCKBICK(256fs)SDTO(o)SDTI1(i)Figure 7. Mode 6 TimingLRCKBICK(256fs)SDTO(o)SDTI1(i)Figure 8. Mode 7 TimingLRCKBICK(128fs)SDTO(o)SDTI1(i)SDTI2(i)Figure 9. Mode 8 TimingLRCKBICK(128fs)SDTI1(i)SDTI2(i)Figure 10. Mode 9 TimingLRCKBICK(128fs)SDTO(o)SDTI1(i)SDTI2(i)Figure 11. Mode 10 TimingBICK(128fs)SDTO(o)SDTI1(i)SDTI2(i)Figure 12. Mode 11 TimingOverflow DetectionThe AK4626 has overflow detect function for analog input. Overflow detect function is enable if OVFE bit is set to “1” at serial control mode. OVF pin goes to “H” if analog input of Lch or Rch overflows (more than -0.3dBFS). OVF output for overflowed analog input has the same group delay as ADC (GD = 16/fs = 333µs @fs=48kHz). OVF is “L” for 522/fs (=11.8ms @fs=48kHz) after PDN = “↑”, and then overflow detection is enabled.Zero DetectionThe AK4626 has two pins for zero detect flag outputs. Channel grouping can be selected by DZFM3-0 bits if P/S = “L” and DZFE = “L” (Table 11). DZF1 pin corresponds to the group 1 channels and DZF2 pin corresponds to the group 2 channels. However DZF2 pin becomes OVF pin if OVFE bit is set to “1”. Zero detection mode is set to mode 0 if DZFE= “H” regardless of P/S pin. DZF1 is AND of all six channels and DZF2 is disabled (“L”) at mode 0. Table 12 shows the relation of P/S, DZFE, OVFE and DZF.When the input data of all channels in the group 1(group 2) are continuously zeros for 8192 LRCK cycles, DZF1(DZF2) pin goes to “H”. DZF1(DZF2) pin immediately goes to “L” if input data of any channels in the group 1(group 2) is not zero after going DZF1(DZF2) “H”.DZFM AOUT Mode3 2 1 0 L1 R1 L2 R2 L3 R3 0 0 0 0 0 DZF1DZF1DZF1DZF1DZF1DZF1 1 0 0 0 1 DZF1DZF1DZF1DZF1DZF1DZF2 2 0 0 1 0 DZF1DZF1DZF1DZF1DZF2DZF2 3 0 0 1 1 DZF1DZF1DZF1DZF2DZF2DZF24 0 1 0 0 DZF1DZF1DZF2DZF2DZF2DZF25 0 1 0 1 DZF1DZF2DZF2DZF2DZF2DZF26 0 1 1 0 DZF2DZF2DZF2DZF2DZF2DZF27 0 1 1 1 disable (DZF1=DZF2 = “L”)8 1 0 0 09 1 0 0 1 Not Available10 1 0 1 0 11 1 0 1 1 12 1 1 0 013 1 1 0 1 14 1 1 1 0 15 1 1 1 1disable (DZF1=DZF2 = “L”)DefaultTable 11. Zero detect controlP/S pin DZFE pin OVFE bit DZF mode DZF1 pin DZF2/OVF pin “L” disable Mode 7 “L” “L”“H” (parallel mode) “H” disable Mode 0 AND of 6ch “L”“0” Selectable Selectable Selectable“L” “1” Selectable Selectable OVF output “0” Mode 0 AND of 6ch “L” “L” (serial mode) “H”“1” Mode 0 AND of 6ch OVF outputTable 12. DZF1-2 pins outputs。

TP4366同步四灯显1A移动电源方案_TP4366规格书_TP4366 PDF

注：上表中电池电压是 Typical 情况下标准电压。
Ver1.0
TPOWER Semiconductor
5
TP4366 1A 同步移动电源方案
封装外形尺寸
SOP8L
符号 A A1 A2 b c D E E1 e L
最小值 1.35 0.08 1.20 0.33 0.17 4.70 5.80 3.70 0.38 0
极限参数（注 1）
参数所有引脚对 GND 储存环境温度工作结温范围 HBM MM 额定值 -0.3~+7 -50~+150 -40~150 3000 300 单位 V ℃ ℃ V V
推荐工作范围
符号 VDD TOP 参数充电输入电压工作环境温度参数范围 4.5~5.5 -20~85 单位 V ℃
毫米标准值 1.60 0.15 1.40 4.90 6.00 3.90 1.27BSC. 0.60 -
最大值 1.77 0.28 1.65 0.51 0.26 5.10 6.20 4.10 1.27 8
注明:本公司对本文档有修改的权利,本公司对本文档的修改恕不另行通知。
Ver1.0
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公司名：深圳市升邦科技（TPOWER一级代理商）联系人：胡先生 Q Q: 13322930472
应用
移动电源
2355540888 0755-85298367
电话:
典型应用电路
Ver1.0
TPOWER Semiconductor
1
TP4366 1A 同步移动电源方案
管脚
管脚描述
管脚号 1 2 3 4 5 6 7 8 管脚名称 OUT BAT SW GND SWT VDD LED2 LED1 描述升压输出正极端以及输出电压采样端锂离子电池正极升压功率 NMOS 的漏极芯片地接按键和手电筒 LED 灯，短按按键显示电量，长按按键 2S 手电筒打开或关闭电源输入端 LED 驱动端 LED 驱动端

AK4556VT中文资料

- Slave mode: 256fs, 384fs, 512fs or 768fs (Normal Speed)
256fs or 384fs
(Double Speed)
128fs or 192fs
(Quad Speed)
- Master mode: 256fs or 512fs
(Normal Speed)
Input/Output Voltage: ADC = 2.1Vpp @ VA=3.0V
Master/Slave mode Sampling Rate:
DAC = 2.1Vpp @ VA=3.0V
- Normal Speed: 8kHz to 54kHz
(256fs or 512fs)
8kHz to 48kHz
5 VD
- Digital Power Supply Pin
6 DEM0
I De-emphasis Control Pin
7 DEM1
I De-emphasis Control Pin
8 SDTO
9 CKS0 10 CSK1 11 CSK2
Audio Serial Data Output Pin O
1
20
ROUT
LIN
2
19
LOUT
VSS
3
18
VCOM
VA
4
Top
17
PDN
View
VDBiblioteka 516BCLK
DEM0
6
15
MCLK
DEM1
7
14
LRCK
SDTO
8
13
SDTI
CKS0
9
12

LTC4366高压浪涌抑制器详细学习资料大全

LTC4366高压浪涌抑制器详细学习资料大全LTC4366浪涌抑制器可保护负载免遭高压瞬变的损坏。

通过控制一个外部N沟道MOSFET的栅极，LTC4366可在过压瞬变过程中调节输出。

在MOSFET两端承载过压的情况下，负载可以保持运作状态。

在返回线路中布设一个电阻器可隔离LTC4366，并允许其随电源向上浮动；因此，输出电压的上限仅取决于高值电阻器的可用性和MOSFET的额定规格。

一个可调的过压定时器能在浪涌期间避免损坏MOSFET，而一个附加的9s定时器则为MOSFET提供了冷却周期。

停机引脚负责在停机期间将静态电流减小至14A以下。

在一个故障发生之后，LTC4366-1将锁断，而LTC4366-2则将执行自动重试操作。

1、LTC4366浪涌抑制器入门简介一个可调的过压定时器能在浪涌期间避免损坏MOSFET，而一个附加的9s定时器则为MOSFET提供了冷却周期。

停机引脚负责在停机期间将静态电流减小至14A以下。

在一个故障发生之后，LTC4366-1将锁断，而LTC4366-2则将执行自动重试操作。

2、LTC4366浪涌抑制器工作原理详解引脚功能：BASE：用于外部PNP并联稳压器的基极驱动器输出。

该引脚连接至一个内部6.2V齐纳二极管(其负极接至OUT引脚)的正极。

在期望较低的静态电流但禁止使用一个较大的V SS电阻器时，将一个外部PNP的基极连接至该引脚(此PNP的集电极接地，而发射极则连接至V SS)。

不用时把该引脚连接至V SS。

裸露焊盘：裸露衬垫可以置于开路状态或连接至V SS。

FB：过压调节放大器反馈输入。

把该引脚连接至一个位于OUT和地之间的外部阻性分压器。

过压调节放大器负责控制外部N沟道MOSFET的栅极，以把FB引脚电压调节在OUT以下1.23V。

在发生快速过压的情况下，过压放大器将启动GATE引脚上的一个200mA下拉电流源。

LTC4366引脚图3、LTC4366高压浪涌抑制器应用深入讲解应用信息LTC4366的典型应用是一种需要过压保护的系统，该系统可在过压瞬变期间安全地向负载分配功率。

AK4365中文资料

ASAHI KASEI[AK4368]AK4368PLL & HP-AMP DACAK4368 PLL & I/F 1624bit D/A AK4368 3D Stereo Enhancement ON/OFF 41pin BGAPLL50mW∆ΣDAC- 8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz FIR : 20kHz : ±0.02dB : 54dB : 32kHz, 44.1kHz, 48kHz PLL: : 27MHz, 26MHz, 19.8MHz, 19.68MHz, 19.2MHz, 15.36MHz, 14.4MHz, 13MHz, 12MHz, 11.2896MHz AC I/F : MSB First, 2’s Compliment 2 - I S, 24bit , 24bit/20bit/16bit : LR, LL, RR, (L+R)/2 ALC 83D Stereo Enhancement :3 /I2C: 50mW x 2ch @16Ω, 3.3V - S/N: 92dB@3.3V ON/OFF : 1.6V ∼ 3.6V : 4.0mA @2.4V (HP-AMP ) Ta: −30 ∼ 85°C : 41pin BGA (4mm x 4mm, 0.5mm pitch)MS0409-J-01 -1-2005/08ASAHI KASEI[AK4368]PVDDPVSSMCKOMCLKVCOCLINMINBICK LRCK SDATA DVDD DVSSAVDD Audio Interface PLL VCOM AVSS VCOMDAC(Lch)HDP AmpMUTEHPLALC DEM ATT Bass Boost Digital Filter 3D Stereo Enhancement LOUT 3DCAP1 3DCAP2 3DCAP3 ROUT HDP AmpPDN I2C CAD0/CSN SCL/CCLK SDA/CDTI Serial I/FDAC(Rch)MUTEHPRHVDD HVSS MUTET RINFigure 1.MS0409-J-01 -2-2005/08ASAHI KASEI[AK4368]AK4368VG AKD4368−30 ∼ +85°C AK436841pin BGA (0.5mm pitch)7 6 5AK4368VG4 3 2 1 Top ViewABCDEFG7 6 5 4 3 2 1NC HPL MIN RIN VCOC PVDD NC AHPR HVSS NC NC LIN PVSS MCKO BHVDD AVSSAVDD MUTETVCOM ROUTLOUTNC3DCAP2 3DCAP3 NC 3DCAP1 NC CAD0/ CSN SCL/ CCLK NC GTop View NC DVSS DVDD C I2C MCKI D LRCK BICK EPDN NC SDATA SDA/ CDTI FMS0409-J-01 -3-2005/08ASAHI KASEI[AK4368]AK4365, AK4367AK4365 PLL PLL I/F 19.8/19.68/19.2/15.36/ 14.4/13/12/11.2896MHz 8/11.025/16/22.05/24/32/ 44.1/48kHz 20bit 16/20bit I2S Available N/A N/A Mono 3-wire +6dB (L+R)/2 10mW 2.7 ∼ 3.3V 28QFN(5.2mm x 5.2mm) AK4367 N/A N/A 24bit 16/20/24bit I2S N/A N/A N/A Mono 3-wire/I2C +16dB (L+R)/2 50mW 2.2 ∼ 3.6V 20QFN(4.2mm x 4.2mm) AK4368 27/26/19.8/19.68/19.2/ 15.36/14.4/13/12/11.2896 MHz 8/11.025/12/16/22.05/24/ 32/44.1/48kHzALC 3D Stereo EnhancementAvailable Available Available StereoLL, RR, (L+R)/2 50mW 1.6 ∼ 3.6V 41BGA(4mm x 4mm)MS0409-J-01 -4-2005/08ASAHI KASEI[AK4368]No. B1 C2 C1 D2 D1 E2 E1 F2 F1 G2 G3 MCKO DVSS DVDD I2C MCKI LRCK BICK SDATA SDA CDTI SCL CCLK CAD0 CSN PDN 3DCAP1 3DCAP2 3DCAP3 LOUT ROUT VCOM AVDD AVSS MUTET HVDD HVSS HPR HPL MIN RIN LIN VCOC PVSS PVDDI/O O I I I/O I/O I I/O I I I I I I O O O O O O O O O I I I O HVSS pin L/R “H”: I2C , “L”: 30 & “L”(I2C pin = “H”) (I2C pin = “L”) (I2C pin = “H”) (I2C pin = “L”) (I2C pin = “H”) (I2C pin = “L”)F4 G5 F6 G6 F7 E6 E7 D7 C6 D6 C7 B6 B7 A6 A5 A4 B3 A3 B2 A2“L” 3D Stereo Enhancement 3DCAP2 pin 4.7nF 3D Stereo Enhancement 3DCAP1 pin 4.7nF 470nF 3D Stereo Enhancement 3DCAP3 pin 470nF Lch Rch AVSS pin 2.2µF1 2 3DCAP3 pin 3Rch HP-Amp Lch HP-Amp Rch Lch PLL PVSS PLL PLLAVSS AVDDMS0409-J-01 -5-2005/08ASAHI KASEI[AK4368]No. A1 A7 B4 B5 C3 F3 F5 G1 G4 G7 Note:NCI/O -No Connect Pin No internal bonding. These pins should be connected to ground(I2C, SDA/CDTI, SCL/CCLK, CAD0/CSN, SDATA, LRCK, BICK, MCKI, PDN) PDN pin = “L”Note: MCKI pinAnalog DigitalLOUT, ROUT, MUTET, HPR, HPL, MIN, RIN, LIN CAD0 MCKODVSSMS0409-J-01 -6-2005/08ASAHI KASEI[AK4368](AVSS, DVSS, HVSS, PVSS=0V; Note 1) Parameter Symbol min max Power Supplies Analog AVDD 4.6 −0.3 Digital DVDD 4.6 −0.3 PLL PVDD 4.6 −0.3 HP-Amp HVDD 4.6 −0.3 |AVSS – DVSS| (Note 2) 0.3 ∆GND1 |AVSS – HVSS| (Note 2) 0.3 ∆GND2 |AVSS – PVSS| (Note 2) 0.3 ∆GND3 Input Current (any pins except for supplies) IIN ±10 Analog Input Voltage (Note 3) VINA AVDD+0.3 or 4.6 −0.3 Digital Input Voltage (Note 4) VIND DVDD+0.3 or 4.6 −0.3 Ambient Temperature Ta 85 −30 Storage Temperature Tstg 150 −65 Note 1. Note 2. AVSS, DVSS, HVSS PVSS Note 3. MIN, LIN, RIN pins. Note 4. SDA/CDTI, SCL/CCLK, CAD0/CSN, SDATA, LRCK, BICK, MCLK, PDN, I2C pins.Units V V V V V V V mA V V °C °C:(AVSS, DVSS, HVSS, PVSS=0V; Note 1) Parameter Symbol Power Supplies Analog AVDD Digital DVDD PLL PVDD HP-Amp HVDD Difference1 AVDD−PVDD Difference2 AVDD−HVDD Note 1.min 1.6 1.6 1.6 1.6 −0.3 −0.3typ 2.4 2.4 2.4 2.4 0 0Max 3.6 AVDD 3.6 3.6 +0.3 +0.3Units V V V V V V:MS0409-J-01 -7-2005/08ASAHI KASEI[AK4368]( Ta=25°C; AVDD=PVDD=DVDD=HVDD=2.4V, AVSS=PVSS=DVSS=HVSS=0V; fs=44.1kHz; EXT mode; BOOST OFF; Slave Mode; Signal Frequency =1kHz; Measurement band width=20Hz ∼ 20kHz; Headphone-Amp: RL =16Ω, CL=220µF (Figure 45 )) Parameter min typ Max Units 24 bit DAC Resolution Headphone-Amp: (HPL/HPR pins) (Note 5) Analog Output Characteristics THD+N dB −3dBFS Output, 2.4V, Po=10mW@16Ω −50 −40 −4.8dBFS Output, 3.3V, dB −20 Po=50mW@16Ω HPG bit= “1” 82 90 dB D-Range −60dBFS Output, A-weighted, 2.4V 92 dB −60dBFS Output, A-weighted, 3.3V S/N A-weighted, 2.4V 82 90 dB A-weighted, 3.3V 92 dB Interchannel Isolation 60 80 dB DC Accuracy Interchannel Gain Mismatch Gain Drift Load Resistance (Note 6) Load Capacitance Output Voltage −3dBFS Output (Note 7) −4.8dBFS Output, 3.3V, Po=50mW@16Ω HPG bit= “1” Stereo Line Output: (LOUT/ROUT pins, RL=10kΩ) (Note 8) Analog Output Characteristics: THD+N 0dBFS Output S/N A-weighted DC Accuracy Gain Drift Load Resistance (Note 6) Load Capacitance Output Voltage 0dBFS Output (Note 9) Output Volume: (LOUT/ROUT pins) Step Size Gain Control Range 16 1.01 0.3 200 1.13 0.89 0.5 300 1.25 dB ppm/°C Ω pF Vpp Vrms80 10 1.32 1 −30−60 87 200 1.47 2 -−50 25 1.61 3 0dB dB ppm/°C kΩ pF Vpp dB dBNote 5. DACHL=DACHR bits = “1”, MINHL=MINHR=LINHL=RINHR bits = “0” Note 6. AC Note 7. AVDD Vout = 0.47 x AVDD(typ)@−3dBFS. Note 8. DACL=DACR bits = “1”, MINL=MINR=LINL=RINR bits = “0” Note 9. AVDD Vout = 0.61 x AVDD(typ)@0dBFS.MS0409-J-01 -8-2005/08ASAHI KASEI[AK4368]Parameter LINEIN: (LIN/RIN/MIN pins) Analog Input Characteristics Input Resistance (Figure 23, Figure 24 ) LIN pin LINHL bit = “1”, LINL bit = “1” LINHL bit = “1”, LINL bit = “0” LINHL bit = “0”, LINL bit = “1” RIN pin RINHR bit = “1”, RINR bit = “1” RINHR bit = “1”, RINR bit = “0” RINHR bit = “0”, RINR bit = “1” MIN pin MINHL=MINHR=MINL=MINR bits = “1” MINHL bit = “1”, MINHR=MINL=MINR bits = “0” MINHR bit = “1”, MINHL=MINL=MINR bits = “0” MINL bit = “1”, MINHL=MINHR=MINR bits = “0” MINR bit = “1”, MINHL=MINHR=MINL bits = “0” Gain LIN/MIN→LOUT, RIN/MIN ROUT LIN/MIN→HPL, RIN/MIN HPR Power Supplies Power Supply Current Normal Operation (PDN pin = “H”) (Note 10) AVDD+PVDD+DVDD HVDD Power-Down Mode (PDN pin = “L”) (Note 11)mintypmaxUnits35 35 17 −1 −0.2450 100 100 50 100 100 25 100 100 100 100 0 +0.76+1 +1.76kΩ kΩ kΩ kΩ kΩ kΩ kΩ kΩ kΩ kΩ kΩ dB dB-3.8 1.2 15.5 2.5 100mA mA µANote 10. PMDAC=PMHPL=PMHPR=PMLO bits = “1”, MUTEN bit = “1”, MCKO bit = “0”, HP-Amp PMDAC=PMHPL=PMHPR= “1”,PMLO bit= “0” , AVDD+PVDD+DVDD+HVDD= 4.0mA. Note 11. (MCKI, BICK, LRCK) DVSSMS0409-J-01 -9-2005/08ASAHI KASEI[AK4368](Ta=25°C; AVDD, DVDD, PVDD, HVDD=1.6 ∼ 3.6V; fs=44.1kHz; De-emphasis = “OFF”) Parameter Symbol min typ DAC Digital Filter: (Note 12) Passband (Note 13) PB 0 −0.05dB 22.05 −6.0dB Stopband (Note 13) SB 24.1 Passband Ripple PR Stopband Attenuation SA 54 Group Delay (Note 14) GD 22 Group Delay Distortion 0 ∆GD DAC Digital Filter + Analog Filter: (Note 12) (Note 15) Frequency Response FR 0 ∼ 20.0kHz ±0.5 Analog Filter: (Note 16) Frequency Response FR 0 ∼ 20.0kHz ±1.0 BOOST Filter: (Note 15) (Note 17) Frequency Response 20Hz FR 5.76 MIN 100Hz 2.92 1kHz 0.02 20Hz FR 10.80 MID 100Hz 6.84 1kHz 0.13 20Hz FR 16.06 MAX 100Hz 10.54 1kHz 0.37 Note 12. BOOST OFF (BST1-0 bit = “00”) Note 13. fs ( ) PB=0.4535fs(@−0.05dB) SB=0.546fs(@−54dB) Note 14. Note 15. DAC Note 16. MIN Note 17. HPL, HPR, LOUT, ROUT HPL/HPR/LOUT/ROUT, LIN fsmax 20.0 ±0.02 -Units kHz kHz kHz dB dB 1/fs µs dB dB dB dB dB dB dB dB dB dB dBHPL/LOUT, RINHPR/ROUTBoost Filter (fs=44.1kHz) 20 15 Level [dB] MID 10 MIN 5 0 -5 10 100 Frequency [Hz] 1000 10000MAXFigure 2. Boost Frequency (fs=44.1kHz)MS0409-J-01 - 10 -2005/08DC(Ta=25°C; AVDD, DVDD, PVDD, HVDD=1.6 ∼ 3.6V)UnitsmaxtypParameter Symbol minVHigh-Level Input Voltage 2.2V≤DVDD≤3.6V VIH 70%DVDD- -V1.6V≤DVDD<2.2V VIH 80%DVDD- -Low-Level Input Voltage 2.2V≤DVDD≤3.6V VIL - - 30%DVDD V1.6V≤DVDD<2.2V VIL - - 20%DVDD VInput Voltage at AC Coupling (Note 18) VAC 0.4 - - VppVHigh-Level Output Voltage (Iout=−200µA)VOH DVDD−0.2- -Low-Level Output VoltageV (Except SDA pin: Iout=200µA)VOL - - 0.2(SDA pin: Iout=3mA)VOL - - 0.4 VInput Leakage Current Iin - - ±10 µANote 18. MCKI pin (Figure 45 )(Ta=25°C; AVDD, DVDD, PVDD, HVDD=1.6 ∼ 3.6V; C L = 20pF)maxtypUnitsminParameter SymbolMaster Clock Input TimingFrequency (PLL mode)fCLK 11.2896 - 27 MHz(EXT mode) fCLK 2.048 - 12.288 MHzPulse Width Low (Note 19) tCLKL 0.4/fCLK- - nsPulse Width High (Note 19) tCLKH 0.4/fCLK- - nsAC Pulse Width (Note 20) tACW 18.5 - - nsLRCK TimingkHz Frequency fs 8 44.1 48Duty Cycle: Slave Mode Duty 45 - 55 %MasterMode Duty - 50 - %MCKO Output Timing (PLL mode)Frequency fCLKO 0.256 - 12.288 MHzDuty Cycle (Except fs=32kHz, PS1-0= “00”) dMCK 40 - 60 %(fs=32kHz, PS1-0= “00”) dMCK - 33 - %Serial Interface Timing (Note 21)Slave Mode (M/S bit = “0”):Period tBCK 312.5 - - nsBICKBICK Pulse Width Low tBCKL 100 - - nsPulse Width High tBCKH 100 - - nsLRCK Edge to BICK “↑” (Note 22) tLRB 50 - - nsBICK “↑” to LRCK Edge (Note 22) tBLR 50 - - nsSDATA Hold Time tSDH 50 - - nsSDATA Setup Time tSDS 50 - - nsMaster Mode (M/S bit = “1”):BICK Frequency (BF bit = “1”)fBCK - 64fs - Hz(BF bit = “0”) fBCK - 32fs - HzDuty dBCK - 50 - %BICKBICK “↓” to LRCK tMBLR −50 - 50 nsSDATA Hold Time tSDH 50 - - nsSDATA Setup Time tSDS 50 - - nsControl Interface Timing (3-wire Serial mode)CCLK Period tCCK 200 - - nsCCLK Pulse Width Low tCCKL 80 - - nsPulse Width High tCCKH 80 - - nsCDTI Setup Time tCDS 40 - - nsCDTI Hold Time tCDH 40 - - nsCSN “H” Time tCSW 150 - - nsCSN “↑” to CCLK “↑” tCSS 50 - - nsCCLK “↑” to CSN “↑” tCSH 50 - - nsNote 19. ACNote 20. MCKI(Figure 3 )Note 21.Note 22. LRCK BICK “↑”UnitsmaxtypminParameter SymbolControl Interface Timing (I2C Bus mode): (Note 23)SCL Clock Frequency fSCL - - 400 kHzBus Free Time Between Transmissions tBUF 1.3 - - µsStart Condition Hold Time (prior to first clock pulse) tHD:STA0.6 - - µsClock Low Time tLOW 1.3 - - µsClock High Time tHIGH 0.6 - - µsSetup Time for Repeated Start Condition tSU:STA0.6 - - µsSDA Hold Time from SCL Falling (Note 24) tHD:DAT0 - - µsSDA Setup Time from SCL Rising tSU:DAT0.1 - - µsRise Time of Both SDA and SCL Lines tR - - 0.3 µsFall Time of Both SDA and SCL Lines tF - - 0.3 µsSetup Time for Stop Condition tSU:STO0.6 - - µsPulse Width of Spike Noise Suppressed by Input Filter tSP 0 - 50 nsPower-down & Reset TimingPDN Pulse Width(Note 25)tPD 150 - - nsNote 23. I2C Philips SemiconductorsNote 24. 300ns (SCL )Note 25. PDN pin “L” “H”MeasurementPointDVSS1000pFFigure 3. MCKI AC Coupling TimingVIHMCKIVILVIH LRCKVILVIHBICKVIL50%DVDD MCKOFigure 4. Clock TimingLRCKVIH BICKVILVIHSDATAVILVIH VILFigure 5. Serial Interface Timing (Slave Mode)LRCK50%DVDDBICKVIH SDATAVIL50%DVDDFigure 6. Serial Interface Timing (Master mode)CSNVIH CCLKVILVIH CDTI VILVIHVILFigure 7. WRITE Command Input TimingCSNVIH CCLKVILVIH CDTI VILVIHVILD3D2D1D0Figure 8. WRITE Data Input TimingVIHVILVIHVILFigure 9. I 2C Bus Mode TimingVILPDNFigure 10. Power-down & Reset Timing1) PLL (PMPLL bit = “1”)PLL PLL3-0 bits, FS3-0 bits (Table 1, Table 2) MCKO PS1-0 bits (Table 3) MCKO bit ON/OFF PLL Table 1 (PMDAC bit = “1”) 0”M/S bit “1” “0” AK4368 (PDN pin = “L”) M/S bit “1”11.2896MHz, 12MHz, 13MHz, 14.4MHz, 15.36MHz, 19.2MHz, 19.68MHz, 19.8MHz, 26MHz, 27MHz PLL MCKO, BICK, LRCK (Figure 11)Figure 11. PLL Master ModeM/S bit “1” AK4368 LRCK, BICK pin AK4368 LRCK, BICK pin 100kΩ(M/S bit = “1”) PMPLL bit = “0” Æ “1” PMDAC bit = “0” Æ “1” PLL LRCK BICK “L” MCKO bit = “1” MCKO pin MCKO bit = “0” MCKO pin “L” PLL LRCK BICK AK4368 (Table 4)BICK, LRCK pin PLL AK4368 MCKO BICK, LRCKFigure 12. PLL Slave Mode(M/S bit = “0”) PMPLL bit = “0” Æ “1” PMDAC bit = “0” Æ “1” PLL MCKO bit = “1” MCKO pin PLL MCKO pin Table 3 (PMDAC bit = “1”) LRCK BICK (PMDAC bit = “0”)VCOC R,CMode PLL3 PLL2 PLL1 PLL0 MCKI fs[kHz] R[Ω]C[F] PLL (typ 0 0 0 0 0 11.2896MHz 44.1, 48 10k 22n 20ms Default 1 0 0 0 1 14.4MHz 44.1, 48 10k 22n 20ms 2 0 0 1 0 12MHz 44.1, 48 10k 47n 20ms 3 0 0 1 1 19.2MHz 44.1, 48 10k 22n 20ms 4 0 1 0 0 15.36MHz 44.1, 48 10k 22n 20ms 5 0 1 0 1 13MHz 44.1, 48 15k 330n 100ms 6 0 1 1 0 19.68MHz 44.1, 48 10k 47n 20ms 7 0 1 1 1 19.8MHz 44.1, 48 10k 47n 20ms 8 1 0 0 0 26MHz 44.1, 48 15k 330n 100ms 9 1 0 0 1 27MHz 44.1, 48 10k 47n 20ms 10 1 0 1 0 13MHz 44.0995 48.000710k 22n 20ms11 1 0 1 1 26MHz 44.0995 48.000710k 22n 20ms12 1 1 0 0 19.8MHz 44.0995 47.999210k 22n 20ms13 1 1 0 1 27MHz 44.0995 47.999710k 22n 20ms14-15 Others N/A N/A N/A N/A -Table 1. MCKI (PLL mode)Mode FS3 FS2 FS1 FS0 fs0 0 0 0 0 48kHz1 0 0 0 1 24kHz2 0 0 1 0 12kHz4 0 1 0 0 32kHz5 0 1 0 1 16kHz6 0 1 1 0 8kHz8 1 0 0 0 44.1kHz Default9 1 0 0 1 22.05kHz10 1 0 1 0 11.025kHz3, 7,11-15Others N/ATable 2. (PLL mode)PS1 PS0 MCKO0 0 256fsDefault0 1 128fs1 0 64fs1 1 32fsTable 3. MCKO (PLL mode, MCKO bit = “1”)Master Mode (M/S bit = “1”)Power Up(PMDAC bit= PMPLL bit= “1”) Power Down(PMDAC bit= PMPLL bit= “0”)PLL UnlockMCKI pin Refer to Table 1. Input orfixed to “L” or “H”Refer to Table 1.MCKO pin MCKO bit = “0”: “L”MCKO bit = “1”: Output “L” MCKO bit = “0”: “L”MCKO bit = “1”: UnsettlingBICK pin BF bit = “1”: 64fs outputBF bit = “0”: 32fs output“L” “L” LRCK pin Output “L” “L”Table 4. Clock Operation in Master mode (PLL mode)Slave Mode (M/S bit = “0”)Power Up(PMDAC bit= PMPLL bit= “1”) Power Down(PMDAC bit= PMPLL bit= “0”)PLL UnlockMCKI pin Refer to Table 1. Input orfixed to “L” or “H”Refer to Table 1.MCKO pin MCKO bit = “0”: “L”MCKO bit = “1”: Output “L” MCKO bit = “0”: “L”MCKO bit = “1”: UnsettlingBICK pin Input Fixed to “L” or “H” externally Input orFixed to “L” or “H”externallyLRCK pin Input Fixed to “L” or “H” externally Input orFixed to “L” or “H”externallyTable 5. Clock Operation in Slave mode (PLL mode)2) (PMPLL bit = “0”: Default)PMPLL bit “0” (EXT mode) MCKI pin PLL DAC FS3-0 bits Table 6 PLL3-0 bits MCKO MCKO bit ON/OFF PS1-0 bit DAC (PMDAC bit = “1”) “0”(M/S bit = “1”) LRCK BICK AK4368 (Figure 13) (PMDAC bit = “1”) MCKI pin DAC (PMDAC bit = “0”)AK4368Figure 13. EXT Master Mode(M/S bit = “0”) MCKI, BICK, LRCK (Figure 14) MCKI LRCK DAC (PMDAC bit = “1”) (MCKI, BICK, LRCK) DAC (PMDAC bit = “0”)AK4368Figure 14. EXT Slave ModeMode FS3 FS2 FS1 FS0 fs MCKI0 0 0 0 0 8kHz ∼ 48kHz 256fs1 0 0 0 1 8kHz ∼ 24kHz 512fs2 0 0 1 0 8kHz ∼ 12kHz 1024fs4 0 1 0 0 8kHz ∼ 48kHz 256fs5 0 1 0 1 8kHz ∼ 24kHz 512fs6 0 1 1 0 8kHz ∼ 12kHz 1024fs8 1 0 0 0 8kHz ∼ 48kHz 256fs Default9 1 0 0 1 8kHz ∼ 24kHz 512fs10 1 0 1 0 8kHz ∼ 12kHz 1024fs3, 7,Others N/A N/A 11-15Table 6. MCKI (EXT mode)PS1 PS0 MCKODefault0 0 256fs0 1 128fs1 0 64fs1 1 32fsTable 7. MCKO (EXT mode, MCKO bit = “1”)Master Mode (M/S bit = “1”)Power Up (PMDAC bit = “1”) Power Down (PMDAC bit = “0”)MCKI pin Refer to Table 6. Input orfixed to “L” or “H”“L”MCKO pin MCKO bit = “0”: “L”MCKO bit = “1”: OutputBICK pin BF bit = “1”: 64fs output“L”BF bit = “0”: 32fs outputLRCK pin Output “L”Table 8. Clock Operation in Master mode (EXT mode)Slave Mode (M/S bit = “0”)Power Up (PMDAC bit = “1”) Power Down (PMDAC bit = “0”)MCKI pin Refer to Table 6. Input orfixed to “L” or “H”MCKO pin MCKO bit = “0”: “L”“L”MCKO bit = “1”: OutputBICK pin Input Fixed to “L” or “H” externallyLRCK pin Input Fixed to “L” or “H” externallyTable 9. Clock Operation in Slave mode (EXT mode)DR, S/N MCKIDR, S/N Table 10 DAC DR,S/NDR, S/N (BW=20kHz, A-weight)MCKIfs=8kHz fs=16kHz256fs 56dB 75dB512fs 75dB 90dB1024fs 90dB N/ATable 10. MCKI DR, S/N (2.4V)SDATA, BICK, LRCK 3pin 5 (Table 11) DIF2-0 bits Mode 0 16bitDAC Mode 1 Mode 0 20bit Mode 4 Mode 0 24bit Mode 2 ADC DSP Mode 3 I 2S BICK ≥48fs Mode 2 3 16bit LSB 17∼24bit 8 “0” 20bit LSB 21∼24bit 4 “0”BICK=32fs(BF bit = “0”) Mode 1, 2Mode DIF2 DIF1 DIF0 BICK0 0 0 0 0: 16bit, 32fs ≤ BICK ≤ 64fsFigure 15 1 0 0 1 1: 20bit, 40fs ≤ BICK ≤ 64fsFigure 16 2 0 1 0 2: 24bit, 48fs ≤ BICK ≤ 64fsFigure 17Default 3 0 1 1 3: I 2SBICK=32fs or 48fs ≤ BICK ≤ 64fs Figure 18 4 1 0 0 4: 24bit, 48fs ≤ BICK ≤ 64fsFigure 16 Table 11.SDATABICKLRCKSDATABICK(32fs)Mode 0Mode 0Figure 15. Mode 0 (LRP = BCKP bits = “0”)SDATALRCKBICKMode 1SDATAMode 4Figure 16. Mode 1, 4 (LRP = BCKP bits = “0”)LRCK BICKSDATA16bitSDATA20bitSDATA24bitFigure 17. Mode 2 (LRP = BCKP bits = “0”)LRCKBICKSDATA16bitSDATA20bitSDATA24bitBICKSDATA16bit (32fs)Figure 18. Mode 3 (LRP = BCKP bits = “0”)ALCALC bit = “1” ALC ALC bit = “0” ALC 0dB[1] ALCALC DAC L/R ALC (−6.0dBFS) ALC ATT (LMAT1-0 bits, Table 13) ALC L/R ROTM1-0 bits (Table 12)ALC ,ROTM1 ROTM0fs=16kHzfs=22.05kHz fs=24kHzfs=32kHz fs=44.1kHz fs=48kHz0 0 1024/fs 64ms 46ms 43ms 32ms 23ms 21ms0 1 2048/fs128ms 93ms 85ms 64ms 46ms 43msDefault1 0 4096/fs 256ms 186ms 171ms 128ms 93ms 85ms11Reserved- - - - - - Table 12. ALC ,ALC ATTLMAT1 LMAT0 ALC Output ≥−6.0dBFS ALC Output ≥0dBFSALC Output ≥+6dBFSALC Output ≥+12dBFS0 1 1 1 1Default 01 2 2 2 210 2 2 4 411 2 4 4 8Table 13. ALC ATT[2] ALCALC ALC ROTM1-0 bits DAC (−8.5dBFS) ALC ALC ROTM1-0 bits (Table 12) (L/R ) (REF7-0 bits, Table 15) RATT bit (Table 14) ALC ROTM1-0 bits ROTM1-0 bits ROTM1-0 bitsALC DAC L/R ALC (−6.0dBFS) ALCALC(ALC ) ≤ (DAC ) < (ALC )(ALC ) > (DAC )ROTM1-0 bitsSTEPRATT GAINDefault0 11 2Table 14. ALCREF7-0GAIN(dB)FFH: ReservedC2HC1H +18.0C0H +17.625BFH +17.25: :92H +0.375Default91H 090H −0.375: :73H −11.2572H −11.62571H −12.070H: Reserved00HTable 15. ALC[3] ALCfs=16kHz fs=44.1kHzRegister Name CommentData Operation Data Operation ROTM1-0 Zero crossing timeout period 00 64ms 01 46msREF7-0 Maximum gain at recovery operation C1H +18dB C1H+18dBLMAT1-0Limiter ATT step 00 1 step 001 stepRATT Recovery GAIN step 0 1 step 0 1 stepALC ALC enable 1 Enable 1 EnableTable 16. ALCALC ALC (ALC bit = “0” PMDAC bit = “0”)LMAT1-0, ROTM1-0, RATT, REF7-0Note: WR: WriteFigure 19. ALCAK4368 MUTE 0.5dB 256 (DATT) DAC 0dB −127dB (Table 17) DATTC bit “1” ATTL7-0 bit Lch, Rch DATTC bit “0” Lch, RchATTL7-0AttenuationATTR7-0FFH 0dBFEH −0.5dBFDH −1.0dBFCH −1.5dB: :: :02H −126.5dB01H −127.0dB00H MUTE (−∞) DefaultTable 17. Digital Volume ATTATT7-0 ATS bit 1061/fs 7424/fs (Table 18) ATS bit = “0” ATT 1062 FFH(0dB) 00H(MUTE) 1061/fs (24ms @fs=44.1kHz) PDN pin “L” ATT7-0 00H ATT7-0 PMDAC bit “0” 00H PMDAC bit “1”ATT speedATS0dB to MUTE 1 stepDefault0 1061/fs 4/fs1 7424/fs 29/fsTable 18. ATT7-0SMUTE bit “1” ATT ATT ×ATT (Table 18) −∞ (“0”) SMUTE bit “0” −∞ ATT ×ATT ATT −∞ ATTAttenuation-Analog OutputFigure 20.Notes:(1) ATT ×ATT (Table 18) ATS bit = “1” ATT “128”(−63.5dB)3712/fs(2) (GD)(3) −∞ATTIIR 3 (32kHz, 44.1kHz, 48kHz) (50/15µs ) DEM1-0 bit (Table 19)DEM1 bit DEM0 bit De-emphasis44.1kHz0 0Default0 1 OFF48kHz1 032kHz1 1Table 19.BST1-0 bit DAC (Table 20)BST1 bit BST0 bit BOOSTDefault0 0 OFF0 1 MIN1 0 MID1 1 MAXTable 20.MONO1-0 bit DAC Lch/Rch (Table 21)MONO1 bit MONO0 bit Lch RchDefault0 0 L R0 1 L L1 0 R R(L+R)/2(L+R)/21 1Table 21.PDN pin “L” VCOM, DAC, HPL, HPR, LOUT, ROUT PDN pinDAC PMDAC bit “1” MCKI MCKI(HPL, HPR pins)HVDD MUTET pin 16Ω PMHPL=PMHPR bits = “1” MUTEN bit “1” VCOM(=0.475 x AVDD) MUTEN bit “0” HVSS t r : (VCOM/2 )70k x C (typ) t f : (VCOM/2 )60k x C (typ) Table 22.: MUTET pin C=1µF(VCOM/2 ): t r = 70k x 1µ = 70ms(typ)(VCOM/2 ): t f = 60k x 1µ = 60ms(typ)PMHPL, PMHPR bits “0” HPL, HPR pins HVSSMUTEN bitPMHPL/R bitHPL/R pin (1) (2)(4) (3)t r t fVCOM/2VCOMFigure 21.(1) (PMHPL, PMHPR bits = “1”) HVSS(2) (MUTEN bit = “1”) MUTET MUTET pin “C” VCOM/2 (t r ) 70k x C(typ)(3) (MUTEN bit = “0”) MUTET HVSS MUTET pin “C” VCOM/2 (t f ) 60k x C(typ)(4) (PMHPL, PMHPR bits = “1”) HVSS(fc) Table 23 (fc) R L 16Ω AVDD=2.4, 3.0, 3.3V 0.47 x AVDD (Vpp) @−3dBFSFigure 22.Output Power [mW]HPG=0, 0dBHPG=1,4.8dBR [Ω] C [µF]fc [Hz] BOOST=OFFfc [Hz] BOOST=MIN2.4V3.0V 3.3V 3.3V220 45 170 100 100 43 20 31 38 50100 70286.8 47 149 78 10 15 18 25100 50 191647 106 475 8 9 13Table 23. , fON/OFF DACHL, LINHL, MINHL, DACHR, RINHR, MINHR bits HPG bit = “0” (R 1=100k) +0.76dB(typ) HPG bit = “1” (R 1= 50k) DAC +6.76dB(typ)Figure 23. (HPG bit = “0” )(LOUT, ROUT pins)0.475 x AVDD 10kΩ PMLO bit = “1” ON/OFF DACL, LINL, MINL, DACR, RINR, MINR bits LOG bit = “0”(R1=100k), ATTS3-0 bits = “0FH”(0dB) 0dB(typ) LOG bit = “1” (R1= 50k) DAC +6dBFigure 24. LOUT/ROUT (LOG bit = “0” )LOUT/ROUT LMUTE bit = “0” ATTS3-0 bit (0dB ∼−30dB, 2dB step, Table 24) LOUT/ROUTLMUTE ATTS3-0 Attenuation0FH 0dB0EH −2dB0DH −4dB0CH −6dB: :: :01H −28dB00H −30dBDefault1 x MUTETable 24. LOUT/ROUT Volume ATT (x: Don’t care)3D Stereo EnhancementAK4368 3D (3D Stereo Enhancement) 3D1-0 bits 3D (Table 25) 3D DP1-0 bits (Table 26) 3D1-0 bits 50ms 3D1-0 bits MUTEN bit3DCAP1, 3DCAP2, 3DCAP3 pins Figure 25 4.7nF 470nF ±20% 3DCAP1, 3DCAP2, 3DCAP3 pins 20pFDefaultDP1 bit DP0 bit 3D Depth 0 0 0% Default 0 1 50% 1 0 70% 1 1 100%Table 26. 3D4.7nF470nFFigure 25. 3D(EXT mode)1) DAC → HP-AmpPower Supply PDN pinPMVCM bitClock InputSDTI pin PMDAC bit DAC Internal State HPL/R pinPMHPL, PMHPR bits ATTL7-0 ATTR7-0 bitsMUTEN bitDACHL, DACHR bits3D1-0 bitsFigure 26. DAC HP-amp (Don’t care: Hi-Z )(1) 150ns PDN pin “H” (2) PDN pin “H” PMVCM, PMDAC bit “1” (3) DAC (MCKI, BICK, LRCK) PMDAC bit = “0”(4) PMVCM, PMDAC bits “1” DACHL, DACHR bits “1”(5) 3D DACHL, DACHR bits “1” 3D1-0 bits “10”(6) 3D DACHL, DACHR bits “1” 2ms (VCOM pin2.2µF ) PMHPL, PMHPR, MUTEN bits “1” 3D 3D1-0bits “10” 50ms PMHPL, PMHPR, MUTEN bits “1”(7) MUTET pin (C) VCOM/2(t r ) 70k x C(typ) C=1µF t r 70ms(typ)(8) MUTET pin (C) VCOM/2(t f ) 60k x C(typ) C=1µF t f 60ms(typ)PMHPL, PMHPR “0” DACL, DACR bits “0” 3D1-0bits “00”(9) 22/fs(=499µs@fs=44.1kHz) (GD)(10) ATS bit 1061/fs(=24ms@fs=44.1kHz) (11) OFF2) DAC → LineoutPower SupplyPDN pinPMVCM bitClock InputSDTI pin PMDAC bit DAC Internal State PMLO bit ATTL/R7-0 bits LMUTE,ATTS3-0 bitsDACL, DACR bits3D1-0 bitsFigure 27. DAC Lineout (Don’t care: Hi-Z )(1) 150ns PDN pin “H” (2) PDN pin “H” PMVCM bit “1” (3) PMVCM bit “1” DACL, DACR bits “1”(4) 3D DACL, DACR bits “1” 3D1-0 bits “01”(5) 3D DACL, DACR bits “1” PMDAC, PMLO bits “1”3D 3D1-0bits “01” PMDAC, PMLO bits “1”(6) DAC (MCKI, BICK, LRCK) PMDAC bit = “0”LOUT/ROUT (7) PMLO bit LOUT, ROUT pins(8) 22/fs(=499µs@fs=44.1kHz) (GD)(9) ATS bit 1061/fs(=24ms@fs=44.1kHz)3) LIN/RIN/MIN → HP-Amp, LineoutPower SupplyPDN pinPMVCM bitHPL/R pinsMOUT pinLMUTE,ATTM3-0 bitsLIN/RIN/MIN pinsPMHPL/R bitsMUTEN bitPMLO bit3D1-0 bitsFigure 28. LIN/RIN/MIN, HP-amp LOUT/ROUT(Don’t care: Hi-Z )(1) 150ns PDN pin “H” DAC(MCLK, BICK, LRCK) (2) PDN pin “H” PMVCM bit “1” (3) PMVCM bit “1” LINHL, MINHL, RINHR, MINHR, LINL, MINL, RINR, MINR bits “1”(4) LINHL, MINHL, RINHR, MINHR, LINL, MINL, RINR, MINR bits “1” LIN, RIN, MIN pin0.475 x AVDD(5) 3D LINHL, MINHL, RINHR, MINHR, LINL, MINL, RINR, MINR bits “1”3D1-0bits “01”, “10” “11” (Refer to Table 25)(6) 3D LINHL, MINHL, RINHR, MINHR, LINL, MINL, RINR, MINR bits “1”2ms (VCOM pin 2.2µF ) PMHPL, PMHPR, MUTEN, PMLO bits “1” 3D 3D1-0bits “01”, “10” “11” 50ms PMHPL, PMHPR, MUTEN, PMLO bits “1”(7) MUTET pin (C) VCOM/2(t r ) 70k x C(typ) C=1µF t r 70ms(typ)(8) MUTET pin (C) VCOM/2(t f ) 60k x C(typ) C=1µF t f 60ms(typ)PMHPL, PMHPR bits “0” LINHL, MINHL, RINHR, MINHR, LINL, MINL, RINR, MINR bits “0” (9) PMLO bit LOUT, ROUT pins(PLL Slave mode)1) DAC → HP-AmpPower Supply PDN pinMCKI pinSDTI pin DAC Internal State HPL/R pinPMHPL, PMHPR bits ATTL7-0 ATTR7-0 bitsMUTEN bitDACHL, DACHR bits3D1-0 bits MCKO pinBICK,LRCK pinsFigure 29. DAC HP-amp (Don’t care: Hi-Z )(1) 150ns PDN pin “H” (2) PDN pin “H” PMVCM, PMPLL, PMDAC, MCKO bits “1” (3) MCKI pin PLL(4) PLL Table 1 PLL MCKO pin (5) DAC MCKO (BICK, LRCK) PMDAC bit = “0”(6) PLL DACHL, DACHR bits “1”(7) 3D DACHL, DACHR bits “1” 3D1-0 bits “10”(8) 3D DACHL, DACHR bits “1” 2ms (VCOM pin2.2µF ) PMHPL, PMHPR, MUTEN bits “1” 3D 3D1-0bits “10” 50ms PMHPL, PMHPR, MUTEN bits “1”(9) MUTET pin (C) VCOM/2(t r ) 70k x C(typ) C=1µF t r 70ms(typ)(10) MUTET pin (C) VCOM/2(t f ) 60k x C(typ) C=1µF t f 60ms(typ)PMHPL, PMHPR “0” DACL, DACR bits “0” 3D1-0bits “00”(11) 22/fs(=499µs@fs=44.1kHz) (GD)(12) ATS bit 1061/fs(=24ms@fs=44.1kHz) (13) OFF2) DAC → LineoutMCKO pinBICK, LRCK pinsPower SupplyPDN pinMCKI pinSDTI pin DAC Internal State PMLO bit ATTL/R7-0 bits LMUTE,ATTS3-0 bitsDACL, DACR bits3D1-0 bitsFigure 30. DAC Lineout (Don’t care: Hi-Z )(1) 150ns PDN pin “H” (2) PDN pin “H” PMVCM, PMPLL, PMDAC, MCKO bits “1” (3) MCKI pin PLL(4) PLL Table 1 PLL MCKO pin (5) DAC MCKO (BICK, LRCK) PMDAC bit = “0”LOUT/ROUT (6) PLL DACL, DACR bits “1”(7) 3D DACL, DACR bits “1” 3D1-0 bits “01”(8) PMLO bit “1” (9) PMLO bit LOUT, ROUT pins(10) 22/fs(=499µs@fs=44.1kHz) (GD)(11) ATS bit 1061/fs(=24ms@fs=44.1kHz)3) LIN/RIN/MIN → HP-Amp, LineoutPower SupplyPDN pinPMVCM bitHPL/R pinsMOUT pinLMUTE,ATTM3-0 bitsLIN/RIN/MIN pinsPMHPL/R bitsMUTEN bitPMLO bit3D1-0 bitsFigure 31. LIN/RIN/MIN, HP-amp LOUT/ROUT(Don’t care: Hi-Z )(1) 150ns PDN pin “H” DAC(MCLK, BICK, LRCK) (2) PDN pin “H” PMVCM bit “1” (3) PMVCM bit “1” LINHL, MINHL, RINHR, MINHR, LINL, MINL, RINR, MINR bits “1”(4) LINHL, MINHL, RINHR, MINHR, LINL, MINL, RINR, MINR bits “1” LIN, RIN, MIN pin0.475 x AVDD(5) 3D LINHL, MINHL, RINHR, MINHR, LINL, MINL, RINR, MINR bits “1”3D1-0bits “01”, “10” “11” (Refer to Table 25)(6) 3D LINHL, MINHL, RINHR, MINHR, LINL, MINL, RINR, MINR bits “1”2ms (VCOM pin 2.2µF ) PMHPL, PMHPR, MUTEN, PMLO bits “1” 3D 3D1-0bits “01”, “10” “11” 50ms PMHPL, PMHPR, MUTEN, PMLO bits “1”(7) MUTET pin (C) VCOM/2(t r ) 70k x C(typ) C=1µF t r 70ms(typ)(8) MUTET pin (C) VCOM/2(t f ) 60k x C(typ) C=1µF t f 60ms(typ)PMHPL, PMHPR bits “0” LINHL, MINHL, RINHR, MINHR, LINL, MINL, RINR, MINR bits “0” (9) PMLO bit LOUT, ROUT pins。

AP436中文资料

Synchronous Rectifier MOSFET DriverFeatures- V OUT slew-rate minimum 100V/uS @ CL=3000pF - I OUT (sink & source)=1.2 / 0.9 A - Safety considered.- Reduce power system thermal & increase system efficiency.- Pb-free packages: SOT89-5L, SOP-8LApplication- Power Adapter.（50~120W for LCD Monitor & NB…etc.）General DescriptionsThe AP436 is a high-speed controller designed to drive N-channel power MOSFET used as synchronous rectifiers in high current, high frequency fly-back converters. The circuit does not require any ties to the primary side and derives its operating power directly from the secondary. The circuit functions are structured by anticipating transformer output transitions then turns the power MOSFET on or off before the transitions of the transformer to minimize body drain diode conduction and reduce associated losses.Pin Assignment( Top View )GND TABV DC V CCV GND GND V R V OUT SOP-8L GND V CC GNDPin DescriptionsName Description V CC Operating voltage inputV R Reference input voltage V DC Duty cycle input voltageV OUTOutput voltage for driving N channelMOSFETGND GroundOrdering InformationS : SOP-8L Y : SOT89-5LBlank: Tube A : TapingSynchronous Rectifier MOSFET Driver Block DiagramsVDCVROUTVGNDAbsolute Maximum RatingsSymbol Parameter Rating UnitV CC SupplyVoltage 14 V V R Referenceinputvoltage -0.3≦V≦2.5 V V DC Duty cycle input voltage -0.3≦V≦V CC-2.1 VV OUT Output voltage to Ground -0.7 VP D Powerdissipation 1 W T ST Storage temperature range -65 to 150 o CT OP Operating temperature range -40 to +125 o CV OP Operating voltage range 7.2 to 14 VSynchronous Rectifier MOSFET DriverElectrical CharacteristicsUnless otherwise specified, guaranteed for Tj=25OC, V CC =12V.Symbol Parameter Conditions Min. Typ. Max. Units V CC Supply Voltage 7.2 12 14 V I B1 Input Bias Current (Pin V R ) V R =0.7V,V CC =12V -74 -103 -150 uA I B2 Input Bias Current (Pin V DC ) V DC =0.7V,V CC =12V -74 -103 -150 uA V R Reference Pin Voltage Range 0.3 0.7 1.5 V V DCL Minimum Input Signal Voltage -0.3 V V OH Output High Vcc-1.5 V V OL Output LowCL=3000pFR L =2K 0.8 0.9 V V DC Detection Voltage V R V R +6 mV V CM Common Mode Range 0.7 1.5 V I S Supply Current (Average Value) V CC =12V,No Load 5.5 6 mAI SOURCE Sourcing Current (Transient Value) 1250 mAI SINK Sinking Current (Transient Value) V CC =12V,C L =3000pFR L =2K,Cin=47uF,F Vdc =200KHz 900 mA I OP Operation Current (Average Value)14 mA Output Delay Time(Low to High)80 100 nS T PDOutput Delay Time(High to Low) 60100nST ROutput Rise Time (10% ~ 90% Rise Edge)35 100 nS T FOutput Fall Time (10% ~ 90% FallEdge)V CC =12V,C L =3000pFR L =2K,Cin=47uF, F Vdc =60KHz60 100 nS F OP Maximum Operation Frequency 200 KHz P D Power Dissipation SOT89-5L, SOP-8L1WI SD (Icc Shutdown Current)V CC =5V, C L =3000pFR L =2K,Cin=47uF, F Vdc =60KHz0.2 0.43 mASynchronous Rectifier MOSFET DriverTypical Application Circuit（1）（2）Marking Information(1)SOP-8L( Top View )~AP436YY WW (2)SOT89-5LXX : Identification code (See Appendix)Y : Year: 0-9M : Month: A~L(Top View)Appendix Part Number Package Identification CodeAP436 SOT89-5L FMSynchronous Rectifier MOSFET DriverPackage Information(1) Package Type: SOP-8LDimensions In Millimeters Dimensions In InchesSymbolMin. Nom. Max. Min. Nom. Max.A 1.40 1.60 1.75 0.055 0.063 0.069A1 0.10 - 0.25 0.040 - 0.100A2 1.30 1.45 1.50 0.051 0.057 0.059B 0.33 0.41 0.51 0.013 0.016 0.0200.008 0.010C 0.19 0.20 0.25 0.0075D 4.80 5.05 5.30 0.189 0.199 0.209E 3.70 3.90 4.10 0.146 0.154 0.161e - 1.27 - - 0.050 -H 5.79 5.99 6.20 0.228 0.236 0.244L 0.38 0.71 1.27 0.015 0.028 0.050y - - 0.10 - - 0.004θ0O - 8O0O - 8OSynchronous Rectifier MOSFET DriverPackage Information (Continued)(2) Package Type: SOT89-5LDimensions In Millimeters Dimensions In InchesSymbolMin. Nom. Max. Min. Nom. Max.A 4.40 4.50 4.60 0.173 0.177 0.181B 4.05 4.15 4.25 0.159 0.163 0.167C 1.50 1.60 1.70 0.059 0.063 0.067D 1.30 1.40 1.50 0.051 0.055 0.059E 2.40 2.50 2.60 0.094 0.098 0.102F 0.80 - - 0.031 - -G 3.00 Ref. 0.118 Ref.H 1.50 Ref. 0.059 Ref.I 0.40 0.46 0.52 0.016 0.018 0.020J 1.40 1.50 1.60 0.055 0.059 0.063K 0.35 0.39 0.43 0.014 0.015 0.017L 5o Typ. 5o Typ.。

AK4386VTP中文资料

Units V
MS0280-E-00 -4-
2003/12
元器件交易网
ASAHI KASEI
[AK4386]
ANALOG CHARACTERISTICS
(Ta=25°C; VDD=3.0V; VSS=0V; fs=44.1kHz, 96kHz; BICK=64fs; Signal Frequency=1kHz; 24bit Data; Measurement frequency=20Hz ∼ 20kHz at fs=44.1kHz, 20Hz ∼ 40kHz at fs=96kHz; unless otherwise specified)
I/O Function
I Master Clock Input Pin
I Audio Serial Data Clock Pin
I Audio Serial Data Input Pin
I Input Channel Clock Pin
I
Full Power Down Mode Pin “L” : Power down, “H” : Power up
FR
-
∼ 40kHz (Note 7)
-
typ
22.05
24.0 ±0.5 ±1.0
max
20.0 -
±0.01
-
-
Units
kHz kHz kHz dB dB 1/fs
dB dB
Note 5. The passband and stopband frequencies scale with fs (system sampling rate). Note 6. The calculating delay time which occurred by digital filtering. This time is from setting the 16/24bit data

AK4385VT资料

ASAHI KASEI [AK4385]GENERAL DESCRIPTIONThe AK4385 offers the perfect mix for cost and performance based audio systems. Using AKM's multi bit architecture for its modulator the AK4385 delivers a wide dynamic range while preserving linearity for improved THD+N performance. The AK4385 has full differential SCF outputs, removing the need for AC coupling capacitors and increasing performance for systems with excessive clock jitter. The 24 Bit word length and 192kHz sampling rate make this part ideal for a wide range of applications including DVD-Audio. The AK4385 is offered in a space saving 16pin TSSOP package.FEATURESSampling Rate Ranging from 8kHz to 192kHz 128 times Oversampling (Normal Speed Mode) 64 times Oversampling (Double Speed Mode) 32 times Oversampling (Quad Speed Mode) 24-Bit 8 times FIR Digital Filter On chip SCFDigital de-emphasis for 32k, 44.1k and 48kHz sampling Soft muteDigital Attenuator (Linear 256 steps)I/F format: 24-Bit MSB justified, 24/20/16-Bit LSB justified or I 2SMaster clock: 256fs, 384fs, 512fs, 768fs or 1152fs (Normal Speed Mode)128fs, 192fs, 256fs or 384fs (Double Speed Mode) 128fs, 192fs (Quad Speed Mode)THD+N: -94dBDynamic Range: 108dBHigh Tolerance to Clock Jitter Power supply: 4.75 to 5.25VVery Small Package: 16pin TSSOP (6.4mm x 5.0mm) AK4381 Pin CompatibleLRCK BICK SDTIPDNAOUTL+AOUTR+VDDVSS CSN CCLK CDTIDZFRAOUTL-AOUTR-DZFLASAHI KASEI [AK4385] Ordering GuideAK4385ET -20 ∼ +85°C 16pin TSSOP (0.65mm pitch)AK4385VT -40 ∼ +85°C 16pin TSSOP (0.65mm pitch)AKD4385 Evaluation Board for AK4385Pin LayoutMCLK LRCK BICKCSN CCLK CDTI DZFL DZFRVSS VDD AOUTL+AOUTL-AOUTR+ AOUTR-PDNSDTIPIN/FUNCTIONNo. PinName I/O Function1 MCLK I Master Clock Input PinAn external TTL clock should be input on this pin.2 BICK I Audio Serial Data Clock Pin3 SDTI I Audio Serial Data Input Pin4 LRCK I L/RClockPin5 PDN I Power-DownModePinWhen at “L”, the AK4385 is in the power-down mode and is held in reset.The AK4385 must be reset once upon power-up.6 CSN I ChipSelectPin7 CCLK I Control Data Input Pin8 CDTI I Control Data Input Pin in serial mode9 AOUTR- O Rch Negative Analog Output Pin10 AOUTR+ O Rch Positive Analog Output Pin11 AOUTL- O Lch Negative Analog Output Pin12 AOUTL+ O Lch Positive Analog Output Pin13 VSS - GroundPin14 VDD - Power Supply Pin15 DZFR O Rch Data Zero Input Detect Pin16 DZFL O Lch Data Zero Input Detect PinNote: All input pins should not be left floating.ASAHI KASEI [AK4385]ABSOLUTE MAXIMUM RATINGS(VSS=0V; Note 1)maxUnitsminParameter SymbolPower Supply VDD -0.3 6.0 VInput Current (any pins except for supplies) IIN - ±10 mAInput Voltage VIND -0.3 VDD+0.3 VAmbient Operating TemperatureAK4385ET Ta -20 85 °C(Powered applied) AK4385VT Ta -40 85 °CStorage Temperature Tstg -65 150 °CNote: 1. All voltages with respect to ground.WARNING: Operation at or beyond these limits may results in permanent damage to the device.Normal operation is not guaranteed at these extremes.RECOMMENDED OPERATING CONDITIONS(VSS=0V; Note 1)maxUnitsmintypParameter SymbolSupply VDD 4.75 5.0 5.25 VPower*AKM assumes no responsibility for the usage beyond the conditions in this datasheet.ASAHI KASEI [AK4385]ANALOG CHARACTERISTICS(Ta=25°C; VDD=5.0V; fs=44.1kHz; BICK=64fs; Signal Frequency=1kHz; 24bit Input Data;Measurement frequency=20Hz ∼ 20kHz; R L ≥4kΩ; unless otherwise specified)Parameter mintypmaxUnits Resolution24Bits Dynamic Characteristics (Note 3)fs=44.1kHz BW=20kHz 0dBFS-60dBFS-94-44-84-dBdBfs=96kHz BW=40kHz 0dBFS-60dBFS-92-41--dBdBTHD+Nfs=192kHz BW=40kHz 0dBFS-60dBFS-92-41--dBdBDynamic Range (-60dBFS with A-weighted) (Note 4) 100 108 dB S/N (A-weighted) (Note 5) 100 108 dB Interchannel Isolation (1kHz) 90 110 dB Interchannel Gain Mismatch 0.2 0.5 dB DC AccuracyGain Drift 100 - ppm/°C Output Voltage (Note 6) ±2.55 ±2.75 ±2.95 Vpp Load Resistance (Note 7) 4 kΩPower SuppliesPower Supply Current (VDD)Normal Operation (PDN = “H”, fs≤96kHz)Normal Operation (PDN = “H”, fs=192kHz)Power-Down Mode (PDN = “L”) (Note 8) 1720102732100mAmAµANotes: 3. Measured by Audio Precision (System Two). Refer to the evaluation board manual.4. 100dB at 16bit data.5. S/N does not depend on input bit length.6. Full-scale voltage (0dB). Output voltage scales with the voltage of VREF,AOUT (typ.@0dB)=(AOUT+)-(AOUT-)=±2.75Vpp × VREF/5.7. For AC-load. 4kΩ for DC-load.8. All digital inputs including clock pins (MCLK, BICK and LRCK) are held VDD or VSS.ASAHI KASEI [AK4385]SHARP ROLL-OFF FILTER CHARACTERISTICS(Ta = 25°C; VDD = 4.75 ∼ 5.25V; fs = 44.1kHz; DEM = OFF; SLOW = “0”)Parameter SymbolmintypmaxUnits Digital filterPassband ±0.05dB (Note 9) -6.0dB PB 0- 22.0520.0-kHzkHzStopband (Note 9) SB 24.1 kHz Passband Ripple PR ± 0.02 dB Stopband Attenuation SA 54 dB Group Delay (Note 10) GD - 19.3 - 1/fs Digital Filter + SCFFrequency Response 20.0kHz40.0kHz80.0kHz fs=44.1kHzfs=96kHzfs=192kHzFRFRFR---± 0.2± 0.3+0.1/-0.6---dBdBdBNotes: 9. The passband and stopband frequencies scale with fs(system sampling rate).For example, PB=0.4535×fs (@±0.05dB), SB=0.546×fs.10. The calculating delay time which occurred by digital filtering. This time is from setting the 16/24bit dataof both channels to input register to the output of analog signal.SLOW ROLL-OFF FILTER CHARACTERISTICS(Ta = 25°C; AVDD, DVDD = 4.75~5.25V; fs = 44.1kHz; DEM = OFF; SLOW = “1”)Parameter Symbol min typ max Units Digital FilterPassband ±0.04dB (Note 11) -3.0dB PB 0- 18.28.1-kHzkHzStopband (Note 11) SB 39.2 kHz Passband Ripple PR ± 0.005 dB Stopband Attenuation SA 72 dB Group Delay (Note 10) GD - 19.3 - 1/fs Digital Filter + SCFFrequency Response 20.0kHz40.0kHz80.0kHz fs=44.kHzfs=96kHzfs=192kHzFRFRFR---+0/-5+0/-4+0.1/-5---dBdBdBNote: 11. The passband and stopband frequencies scale with fs.For example, PB = 0.185×fs (@±0.04dB), SB = 0.888×fs.DC CHARACTERISTICS(Ta=25°C; VDD=4.75 ∼ 5.25V)Parameter SymbolmintypmaxUnitsHigh-Level Input Voltage Low-Level Input Voltage VIHVIL2.2----0.8VVHigh-Level Output Voltage (Iout=-80µA) Low-Level Output Voltage (Iout=80µA) VOHVOLVDD-0.4-- -0.4VVInput Leakage Current Iin - - ± 10 µAASAHI KASEI [AK4385]SWITCHING CHARACTERISTICS(Ta=25°C; VDD=4.75 ∼ 5.25V)Parameter SymbolmintypmaxUnitsMaster Clock FrequencyDuty Cycle fCLKdCLK2.0484011.2896 36.86460MHz%LRCK FrequencyNormal Speed Mode Double Speed Mode Quad Speed Mode Duty CyclefsnfsdfsqDuty86012045489619255kHzkHzkHz%Audio Interface Timing BICK PeriodNormal Speed ModeDouble/Quad Speed ModeBICK Pulse Width LowPulse Width HighBICK rising to LRCK Edge (Note 12) LRCK Edge to BICK rising (Note 12) SDTI Hold TimeSDTI Setup TimetBCKtBCKtBCKLtBCKHtBLRtLRBtSDHtSDS1/128fs1/64fs303020202020nsnsnsnsnsnsnsnsControl Interface TimingCCLK PeriodCCLK Pulse Width Low Pulse Width High CDTI Setup TimeCDTI Hold TimeCSN “H” TimeCSN “↓” to CCLK “↑” CCLK “↑” to CSN “↑” tCCKtCCKLtCCKHtCDStCDHtCSWtCSStCSH200808040401505050nsnsnsnsnsnsnsnsReset TimingPDN Pulse Width (Note 13)tPD 150 ns Notes: 12. BICK rising edge must not occur at the same time as LRCK edge.13. The AK4385 can be reset by bringing PDN= “L”.ASAHI KASEI [AK4385]Timing DiagramVIHMCLKVILVIH LRCKVILVIH BICKVILClock TimingLRCKVIH BICKVILVIH SDTIVIL VIH VILSerial Interface TimingASAHI KASEI [AK4385]CSNVIH CCLKVILVIH CDTI VILVIHVILWRITE Command Input TimingCSNVIH CCLKVILVIH CDTI VILVIHVILD3D2D1D0WRITE Data Input TimingVILPDNPower-down TimingASAHI KASEI [AK4385]OPERATION OVERVIEWSystem ClockThe external clocks, which are required to operate the AK4385, are MCLK, LRCK and BICK. The master clock (MCLK)should be synchronized with LRCK but the phase is not critical. The MCLK is used to operate the digital interpolationfilter and the delta-sigma modulator. There are two methods to set MCLK frequency. In Manual Setting Mode (ACKS =“0”: Register 00H), the sampling speed is set by DFS0/1(Table 1). The frequency of MCLK at each sampling speed is setautomatically. (Table 2~4).After exiting reset (PDN = “↑”), the AK4385 is in Auto Setting Mode. In Auto Setting Mode(ACKS = “1”: Default), as MCLK frequency is detected automatically (Table 5), and the internal master clock becomesthe appropriate frequency (Table 6), it is not necessary to set DFS0/1.All external clocks (MCLK,BICK and LRCK) should always be present whenever the AK4385 is in the normal operationmode (PDN= ”H”). If these clocks are not provided, the AK4385 may draw excess current and may fall into unpredictableoperation. This is because the device utilizes dynamic refreshed logic internally. The AK4385 should be reset by PDN=“L” after threse clocks are provided. If the external clocks are not present, the AK4385 should be in the power-downmode (PDN= “L”). After exiting reset at power-up etc., the AK4385 is in the power-down mode until MCLK and LRCKare input.(fs)RateDFS1 DFS0 Sampling0 0 Normal Speed Mode 8kHz~48kHz Default0 1 Double Speed Mode 60kHz~96kHzMode 120kHz~192kHzSpeedQuad1 0Table 1. Sampling Speed (Manual Setting Mode)LRCK MCLK BICK fs 256fs 384fs 512fs 768fs 1152fs 64fs32.0kHz 8.1920MHz 12.2880MHz16.3840MHz24.5760MHz36.8640MHz 2.0480MHz44.1kHz 11.2896MHz 16.9344MHz22.5792MHz33.8688MHz N/A 2.8224MHz48.0kHz 12.2880MHz 18.4320MHz24.5760MHz36.8640MHz N/A 3.0720MHzTable 2. System Clock Example (Normal Speed Mode @Manual Setting Mode)LRCK MCLK BICKfs 128fs 192fs 256fs 384fs 64fs88.2kHz 11.2896MHz 16.9344MHz22.5792MHz33.8688MHz 5.6448MHz96.0kHz 12.2880MHz 18.4320MHz24.5760MHz36.8640MHz 6.1440MHzTable 3. System Clock Example (Double Speed Mode @Manual Setting Mode)LRCK MCLK BICKfs 128fs 192fs 64fs176.4kHz 22.5792MHz33.8688MHz11.2896MHz192.0kHz 24.5760MHz36.8640MHz12.2880MHzTable 4. System Clock Example (Quad Speed Mode @Manual Setting Mode)ASAHI KASEI [AK4385]MCLK Sampling Speed 512fs 768fs Normal 256fs 384fs Double 128fs 192fs QuadTable 5. Sampling Speed (Auto Setting Mode: Default)LRCK MCLK (MHz)fs 128fs 192fs 256fs 384fs 512fs 768fs Sampling Speed32.0kHz - - - - 16.3840 24.576044.1kHz - - - - 22.5792 33.868848.0kHz - - - - 24.5760 36.8640 Normal 88.2kHz - - 22.5792 33.8688 - -96.0kHz - - 24.5760 36.8640 - - Double176.4kHz 22.5792 33.8688 - - - -192.0kHz 24.5760 36.8640 - - - -QuadTable 6. System Clock Example (Auto Setting Mode)Audio Serial Interface FormatData is shifted in via the SDTI pin using BICK and LRCK inputs. The DIF0-2 as shown in Table 7 can select five serial data modes. In all modes the serial data is MSB-first, 2’s compliment format and is latched on the rising edge of BICK. Mode 2 can be used for 16/20 MSB justified formats by zeroing the unused LSBs.Mode DIF2 DIF1 DIF0SDTI Format BICK Figure 0 0 0 0 16bit LSB Justified ≥32fs Figure 1 1 0 0 1 20bit LSB Justified ≥40fs Figure 2 2 0 1 0 24bit MSB Justified ≥48fs Figure 3 Default 3 0 1 1 24bit I 2S Compatible ≥48fs Figure 4 4 1 0 0 24bit LSB Justified ≥48fs Figure 2Table 7. Audio Data FormatsSDTI BICKLRCKSDTI BICK (32fs)(64fs)Mode 0Mode 0ASAHI KASEI [AK4385]Figure 1. Mode 0 TimingSDTI LRCK BICK (64fs)Mode 1SDTI Mode 4Figure 2. Mode 1,4 TimingLRCKBICK (64fs)SDTIFigure 3. Mode 2 TimingLRCKBICK (64fs)SDTIFigure 4. Mode 3 TimingASAHI KASEI [AK4385]De-emphasis FilterA digital de-emphasis filter is available for 32, 44.1 or 48kHz sampling rates (tc = 50/15µs) and is enabled or disabled with DEM0 and DEM1. In case of double speed and quad speed mode, the digital de-emphasis filter is always off.DEM1DEM0Mode44.1kHz0 0Default0 1 OFF1 0 48kHz1 1 32kHzTable 8. De-emphasis Filter Control (Normal Speed Mode)Output VolumeThe AK4385 includes channel independent digital output volumes (ATT) with 256 levels at linear step including MUTE. These volumes are in front of the DAC and can attenuate the input data from 0dB to –48dB and mute. When changing levels, transitions are executed via soft changes; thus no switching noise occurs during these transitions. The transition time of 1 level and all 256 levels is shown in Table 9.Transition TimeSampling Speed1 Level 255 to 0Normal Speed Mode 4LRCK 1020LRCKDouble Speed Mode 8LRCK 2040LRCKQuad Speed Mode 16LRCK 4080LRCKTable 9. ATT Transition TimeASAHI KASEI [AK4385] Zero DetectionThe AK4385 has channel-independent zeros detect function. When the input data at each channel is continuously zeros for 8192 LRCK cycles, DZF pin of each channel goes to “H”. DZF pin of each channel immediately goes to “L” if input data of each channel is not zero after going DZF “H”. If RSTN bit is “0”, DZF pins of both channels go to “H”. DZF pin of both channels go to “L” at 2~3/fs after RSTN bit returns to “1”. If DZFM bit is set to “1”, DZF pins of both channels go to “H” only when the input data at both channels are continuously zeros for 8192 LRCK cycles. Zero detect function can be disabled by DZFE bit. In this case, DZF pins of both channels are always “L”. DZFB bit can invert the polarity of DZF pin.Soft Mute OperationSoft mute operation is performed at digital domain. When the SMUTE bit goes to “1”, the output signal is attenuated by -∞ during ATT_DATA×ATT transition time (Table 9) from the current ATT level. When the SMUTE bit is returned to “0”, the mute is cancelled and the output attenuation gradually changes to the ATT level during ATT_DATA×ATT transition time. If the soft mute is cancelled before attenuating to -∞ after starting the operation, the attenuation is discontinued and returned to ATT level by the same cycle. The soft mute is effective for changing the signal source without stopping the signal transmission.SMUTE bit AttenuationDZF pin-AOUTNotes:(1) ATT_DATA×ATT transition time (Table 9). For example, in Normal Speed Mode, this time is 1020LRCK cycles(1020/fs) at ATT_DATA=255.(2) The analog output corresponding to the digital input has a group delay, GD.(3) If the soft mute is cancelled before attenuating to -∞ after starting the operation, the attenuation is discontinued andreturned to ATT level by the same cycle.(4) When the input data at each channel is continuously zeros for 8192 LRCK cycles, DZF pin of each channel goes to“H”. DZF pin immediately goes to “L” if input data are not zero after going DZF “H”.Figure 5. Soft Mute and Zero DetectionASAHI KASEI [AK4385]System ResetThe AK4385 should be reset once by bringing PDN= ”L” upon power-up. The AK4385 is powered up and the internal timing starts clocking by LRCK “↑” after exiting reset and power down state by MCLK. The AK4385 is in the power-down mode until MCLK and LRCK are input.Power-downThe AK4385 is placed in the power-down mode by bringing PDN pin “L” and the anlog outputs are floating (Hi-Z). Figure 6 shows an example of the system timing at the power-down and power-up.Internal State PDN D/A Out (Analog)D/A In (Digital)Clock InDZFL/DZFR External MUTE(5)Mute ONNotes:(1) The analog output corresponding to digital input has the group delay (GD). (2) Analog outputs are floating (Hi -Z) at the power-down mode.(3) Click noise occurs at the edge of PDN signal. This noise is output even if “0” data is input.(4) The external clocks (MCLK, BICK and LRCK) can be stopped in the power-down mode (PDN = “L”). (5) Please mute the analog output externally if the click noise (3) influences system application.The timing example is shown in this figure.(6) DZF pins are “L” in the power-down mode (PDN = “L”).Figure 6. Power-down/up Sequence ExampleASAHI KASEI [AK4385]Reset FunctionWhen RSTN=0, DAC is powered down but the internal register values are not initialized. The analog outputs go to VCOM voltage and DZF pin goes to “H”. Figure 7 shows the example of reset by RSTN bit.Internal State RSTN bitD/A Out (Analog)D/A In (Digital)Clock InMCLK,LRCK,BICKDZFInternal RSTN bitNotes:(1) The analog output corresponding to digital input has the group delay (GD). (2) Analog outputs go to VCOM voltage (VDD/2).(3) Click noise occurs at the edges(“↑ ↓”) of the internal timing of RSTN bit. This noise is output even if “0” data isinput.(4) The external clocks (MCLK, BICK and LRCK) can be stopped in the reset mode (RSTN = “L”).(5) DZF pins go to “H” when the RSTN bit becomes “0”, and go to “L” at 2/fs after RSTN bit becomes “1”.(6) There is a delay, 3~4/fs from RSTN bit “0” to the internal RSTN bit “0”, and 2~3/fs from RSTN bit “1” to theinternal RSTN “1”.Figure 7. Reset Sequence ExampleASAHI KASEI [AK4385]Mode Control InterfaceInternal registers may be written by 3-wire µP interface pins, CSN, CCLK and CDTI. The data on this interface consists of Chip Address (2bits, C1/0; fixed to “01”), Read/Write (1bit; fixed to “1”, Write only), Register Address (MSB first, 5bits) and Control Data (MSB first, 8bits). AK4385 latches the data on the rising edge of CCLK, so data should clocked in on the falling edge. The writing of data becomes valid by CSN “↑”. The clock speed of CCLK is 5MHz (max).PDN = “L” resets the registers to their default values. The internal timing circuit is reset by RSTN bit, but the registers are not initialized.CDTICCLKCSN123456789101112131415C1-C0: Chip Address (Fixed to “01”)R/W: READ/WRITE (Fixed to “1”, Write only) A4-A0: Register Address D7-D0: Control DataFigure 8. Control I/F Timing*AK4385 does not support the read command and chip address. C1/0 and R/W are fixed to “011”*When the AK4385 is in the power down mode (PDN = “L”) or the MCLK is not provided, writing into the control register is inhibited.Register MapAddr Register NameD7D6D5D4D3D2D1D000H Control 1 ACKS 0 0 DIF2 DIF1 DIF0 PW RSTN 01H Control 2 DZFE DZFM SLOW DFS1 DFS0 DEM1 DEM0 SMUTE 02H Control 3 0 0 0 0 0 DZFB 0 0 03H Lch ATT ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 04H Rch ATT ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 Notes:For addresses from 05H to 1FH, data must not be written.When PDN pin goes “L”, the registers are initialized to their default values.When RSTN bit goes “0”, the only internal timing is reset and the registers are not initialized to their default values.All data can be written to the register even if PW or RSTN bit is “0”.ASAHI KASEI [AK4385]Register DefinitionsName D7 D6 D5 D4 D3 D2 D1 D0Addr Register00H Control 1 ACKS 0 0 DIF2 DIF1 DIF0 PW RSTN111default 1RSTN: Internal timing reset control0: Reset. All registers are not initialized.1: Normal OperationWhen MCLK frequency or DFS changes, the click noise can be reduced by RSTN bit.PW: Power down control0: Power down. All registers are not initialized.1: Normal OperationDIF2-0: Audio data interface formats (see Table 7)Initial: “010”, Mode 2ACKS: Master Clock Frequency Auto Setting Mode Enable0: Disable, Manual Setting Mode1: Enable, Auto Setting ModeMaster clock frequency is detected automatically at ACKS bit “1”. In this case, the setting of DFS1-0are ignored. When this bit is “0”, DFS1-0 set the sampling speed mode.Name D7 D6 D5 D4 D3 D2 D1 D0Addr Register01H Control 2 DZFE DZFM SLOW DFS1 DFS0 DEM1 DEM0 SMUTE1default 0SMUTE: Soft Mute Enable0: Normal operation1: DAC outputs soft-mutedDEM1-0: De-emphasis Response (see Table 8)Initial: “01”, OFFDFS1-0: Sampling speed control00: Normal speed01: Double speed10: Quad speedWhen changing between Normal/Double Speed Mode and Quad Speed Mode, some click noiseoccurs.SLOW: Slow Roll-off Filter Enable0: Sharp Roll-off Filter1: Slow Roll-off FilterDZFE: Data Zero Detect Enable0: Disable1: EnableZero detect function can be disabled by DZFE bit “0”. In this case, the DZF pins of both channels arealways “L”.ASAHI KASEI [AK4385]DZFM: Data Zero Detect Mode0: Channel Separated Mode 1: Channel ANDed ModeIf the DZFM bit is set to “1”, the DZF pins of both channels go to “H” only when the input data at both channels are continuously zeros for 8192 LRCK cycles.Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 02H Control 3DZFBdefault 0 0 0 0 0 0 0 0DZFB: Inverting Enable of DZF0: DZF goes “H” at Zero Detection 1: DZF goes “L” at Zero DetectionAddr Register Name D7 D6 D5 D4 D3 D2 D1 D0 03H Lch ATT ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 04H Rch ATT ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0default 1 1 1 1 1 1 11ATT = 20 log 10 (ATT_DATA / 255) [dB] 00H: MuteSYSTEM DESIGNFigure 9 shows the system connection diagram. An evaluation board (AKD4385) is available in order to allow an easy study on the layout of a surrounding circuit.Notes:- LRCK = fs, BICK = 64fs.- When AOUT drives some capacitive load, some resistor should be added in series between AOUT and capacitive load.- All input pins should not be left floating.ASAHI KASEI [AK4385]1. Grounding and Power Supply DecouplingVDD and VSS are supplied from analog supply and should be separated from system digital supply. Decoupling capacitor, especially 0.1µF ceramic capacitor for high frequency should be placed as near to VDD as possible. The differential Voltage between VDD and VSS pins set the analog output range.2. Analog OutputsThe analog outputs are full-differential outputs and 0.55 x VDD Vpp (typ) centered around the internal common voltage (about AVDD/2). The differential outputs are summed externally, V AOUT =(AOUT+)-(AOUT-) between AOUT+ and AOUT-. If the summing gain is 1, the output range is 5.5Vpp (typ @VREFH=5V). The bias voltage of the external summing circuit is supplied externally. The input data format is 2’s complement. The output voltage (V AOUT ) is a positive full scale for 7FFFFF (@24bit) and a negative full scale for 800000H (@24bit). The ideal V AOUT is 0V for 000000H (@24bit).The internal switched-capacitor filter and external low pass filter attenuate the noise generated by the delta-sigma modulator beyond the audio passband. DC offset on AOUT+/- is eliminated without AC coupling since the analogoutputs are differential. Figure 10 and 11 show the example of external op-amp circuit summing the differential outputs.47uBIASAnalogOutFigure 10. External 2nd order LPF Circuit Example (using op-amp with single power supply)AOUT-AOUT+When R1=200ΩWhen R1=180Ωfc=93.2kHz, Q=0.712, g=-0.1dB at 40kHz fc=98.2kHz, Q=0.681, g=-0.2dB at 40kHzAnalog OutFigure 11. External 2nd order LPF Circuit Example (using op-amp with dual power supplies)ASAHI KASEI [AK4385]PACKAGE16pin TSSOP (Unit: mm)Package & Lead frame materialPackage molding compound: EpoxyLead frame material: CuLead frame surface treatment: Solder(Pb free) plateASAHI KASEI [AK4385]MARKING (AK4385VT)AKM4385VTXXYYY1) Pin #1 indication2) Date Code : XXYYY (5 digits)XX: Lot#YYY: Date Code3) Marketing Code : 4385VT4) Asahi Kasei LogoASAHI KASEI [AK4385]MARKING (AK4385ET)AKM4385ETXXYYY5) Pin #1 indication6) Date Code : XXYYY (5 digits)XX: Lot#YYY: Date Code7) Marketing Code : 4385ET8) Asahi Kasei LogoASAHI KASEI [AK4385]Revision HistoryDate (YY/MM/DD) Revision Reason Page Contents03/07/02 00 First Edition2 Ordering GuideAK4385ET was added.06/01/11 01 Spec Addition 22 MARKINGAK4385ET was added.IMPORTANT NOTICE• These products and their specifications are subject to change without notice. Before consideringany use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office orauthorized distributor concerning their current status.• AKM assumes no liability for infringement of any patent, intellectual property, or other right in theapplication or use of any information contained herein.• Any export of these products, or devices or systems containing them, may require an export licenseor other official approval under the law and regulations of the country of export pertaining to customsand tariffs, currency exchange, or strategic materials.• AKM products are neither intended nor authorized for use as critical components in any safety, lifesupport, or other hazard related device or system, and AKM assumes no responsibility relating toany such use, except with the express written consent of the Representative Director of AKM. Asused here:(a) A hazard related device or system is one designed or intended for life support or maintenance ofsafety or for applications in medicine, aerospace, nuclear energy, or other fields, in which itsfailure to function or perform may reasonably be expected to result in loss of life or in significantinjury or damage to person or property.(b) A critical component is one whose failure to function or perform may reasonably be expected toresult, whether directly or indirectly, in the loss of the safety or effectiveness of the device orsystem containing it, and which must therefore meet very high standards of performance andreliability.• It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, orotherwise places the product with a third party to notify that party in advance of the above contentand conditions, and the buyer or distributor agrees to assume any and all responsibility and liabilityfor and hold AKM harmless from any and all claims arising from the use of said product in theabsence of such notification.。

AK4396中文资料

ASAHI KASEI [AKD4396-SBW]AKD4396-SBWEvaluation boardGeneral DescriptionThe AKD4396-SBW is an evaluation board for AK4396, which is 192kHz sampling 24Bit ∆Σ DAC. The AKD4396-SBW includes a LPF which can add differential analog outputs from the AK4396 and also has a digital interface. Therefore, it is easy to evaluate the AK4396.Ordering GuideAKD4396-SBW --- Evaluation board for AK4396FunctionOn-board Analog output buffer circuitOn-board digital audio interface. (AK4113)Figure 1 Block diagram* Circuit diagram and PCB layout are attached at the end of this manual.COAX is recommended for an evaluation of the Sound quality.ASAHI KASEI [AKD4396-SBW]Operation sequence1) Set up the power supply lines. (See “Other jumpers set-up”.)Name Color Voltage Comments Attention+15V Red +12∼+15V Regulator,Power supply for Op-amp.This jack is always needed. Power line-15V Blue -12∼-15V Regulator,Power supply for Op-amp.This jack is always needed. Power lineAGND Black 0V GND This jack is always needed.Table 1 Set up of power supply linesEach supply line should be distributed from the power supply unit.2) Set-up the jumper pins3) Set-up the DIP switches. (See the followings.)4) Power onThe AK4396 should be reset once bringing SW1 (PDN) “L” upon power-up.ASAHI KASEI [AKD4396-SBW]Evaluation mode1. DIR(COAX) (default)J1 is used for the evaluation using such as CD test disk. The DIR generates MCLK, BICK and LRCK SDATA from the received data through BNC connector (J1). Setting of jumper is shown below.COAX is recommended for an evaluation of the Sound quality.JP1OPT COAXBNC (Default)Figure 2 Jumper setting, when using DIR2. DIR(Optical Link)PORT1 is used for the evaluation using such as CD test disk. The DIR generates MCLK, BICK and LRCK SDATA from the received data through optical connector (PORT2: TORX176). Setting of jumper is shown below.JP1OPT COAXPORT2Figure 3 Jumper setting, when using DIR3. All clocks are fed through the PORT1.-R9, R12, R13, R14 : open-R10, R15, R19, R20 : 100Ω or short (0 Ω)DIP Switch setting[SW2]: AK4113 settingNo. Pin OFFONDefault 1 OCKS1ON2 OCKS0AK4113 Master Clock setting Refer to Table4OFFTable 2 SW2 setting[SW3]: AK4396 settingNo. PinOFFONDefault1- 2 P/S Serial mode (Note) Parallel modeONNote : When using the serial mode, R5 and R17 should be removed.Table 3 SW3 settingASAHI KASEI [AKD4396-SBW]The frequency of the master clock output is set by OCKS0 and OCKS1 as shown in Table 4.FrequencyOCKS1 OCKS0 MCLK@fs=88.2/96kHz0 0 256fs@32/44.1/48kHz1 0 512fsDefault1 1 128fs@176.4/192kHzTable 4 MCLK ClockSW1 setting[SW1](PDN): Reset of AK4396. Select “H” during operation.External Analog CircuitThe differential output circuit and LPF is implemented on board. The differential outputs of AK4396 is buffered by non-inverted circuit(2nd order LPF, fc=182k, Q=0.637, G=+3.9dB). LPF adds differential outputs(1st order LPF, fc=284k, G=-0.84dB). NJM5534D is used for op-amp on this board that has low noise and high voltage torelance characteristics. Analog signal is output via BNC connectors on the board. The output level is about 2.8Vrms (typ@VREF=5.0V) by BNC.Figure 4External Analog Filter40kHz (Double)80kHz (quad)AKD4396-SBWFilterInternal Filter -0.3dB -1dBExternal LPF -0.19dB -0.85dBTotal -0.49dB -1.85dBThis table shows typical value.Table 5 Frequency ResponsesASAHI KASEI [AKD4396-SBW]2. Control Software ManualSet-up of evaluation board and control software1. Set up the AKD4396-SBW according to previous term.2. Connect IBM-AT compatible PC with AKD4396-SBW by 10-line type flat cable (packed with AKD4396-SBW).Take care of the direction of 10pin header. (Please install the driver in the CD-ROM when this control software is used on Windows 2000/XP. Please refer “Installation Manual of Control Software Driver by AKM device control software”. In case of Windows95/98/ME, this installation is not needed. This control software does not operate on Windows NT.)3. Insert the CD-ROM labeled “AKD4396-SBW Evaluation Kit” into the CD-ROM drive.4. Access the CD-ROM drive and double-click the icon of “akd4396.exe” to set up the control program.5. Then please evaluate according to the follows.Operation flowKeep the following flow.1. Set up the control program according to explanation above.2. Click “Port Reset” button.Explanation of each buttons1. [Port Reset] : Set up the USB interface board (AKDUSBIF-A) .2. [Write default] : Initialize the register of AK4396.3. [All Write] : Write all registers that is currently displayed.4. [Function1] : Dialog to write data by keyboard operation.5. [Function2] : Dialog to write data by keyboard operation.6. [Function3] : The sequence of register setting can be set and executed.7. [Function4] : The sequence that is created on [Function3] can be assigned to buttons andexecuted.8. [Function5]: The register setting that is created by [SAVE] function on main window canbe assigned to buttons and executed.9. [SAVE] : Save the current register setting.10. [OPEN] : Write the saved values to all register.11. [Write] : Dialog to write data by mouse operation.Indication of dataInput data is indicated on the register map. Red letter indicates “H” or “1” and blue one indicates “L” or “0”. Blank is the part that is not defined in the datasheet.ASAHI KASEI [AKD4396-SBW] Explanation of each dialog1. [Write Dialog]: Dialog to write data by mouse operationThere are dialogs corresponding to each register.Click the [Write] button corresponding to each register to set up the dialog. If you check the check box, databecomes “H” or “1”. If not, “L” or “0”.If you want to write the input data to AK4396, click [OK] button. If not, click [Cancel] button.2. [Function1 Dialog] : Dialog to write data by keyboard operationAddress Box: Input registers address in 2 figures of hexadecimal.Data Box: Input registers data in 2 figures of hexadecimal.If you want to write the input data to AK4396, click [OK] button. If not, click [Cancel] button.3. [Function2 Dialog] : Dialog to evaluate ATTAddress Box: Input registers address in 2 figures of hexadecimal.Start Data Box: Input starts data in 2 figures of hexadecimal.End Data Box: Input end data in 2 figures of hexadecimal.Interval Box: Data is written to AK4642 by this interval.Step Box: Data changes by this step.Mode Select Box:If you check this check box, data reaches end data, and returns to start data.[Example] Start Data = 00, End Data = 09Data flow: 00 01 02 03 04 05 06 07 08 09 09 08 07 06 05 04 03 02 01 00If you do not check this check box, data reaches end data, but does not return to start data.[Example] Start Data = 00, End Data = 09Data flow: 00 01 02 03 04 05 06 07 08 09If you want to write the input data to AK4396, click [OK] button. If not, click [Cancel] button.ASAHI KASEI [AKD4396-SBW] 4. [Save] and [Open]4-1. [Save]Save the current register setting data. The extension of file name is “akr”.(Operation flow)(1) Click [Save] Button.(2) Set the file name and push [Save] Button. The extension of file name is “akr”.4-2. [Open]The register setting data saved by [Save] is written to AK4396. The file type is the same as [Save]. (Operation flow)(1) Click [Open] Button.(2) Select the file (*.akr) and Click [Open] Button.ASAHI KASEI [AKD4396-SBW]5. [Function3 Dialog]The sequence of register setting can be set and executed.(1) Click [F3] Button.(2) Set the control sequence.Set the address, Data and Interval time. Set “-1” to the address of the step where the sequence should be paused. (3) Click [Start] button. Then this sequence is executed.The sequence is paused at the step of Interval="-1". Click [START] button, the sequence restarts from the paused step. This sequence can be saved and opened by [Save] and [Open] button on the Function3 window. The extension of file name is “aks”.Figure 5. Window of [F3]ASAHI KASEI [AKD4396-SBW] 6. [Function4 Dialog]The sequence that is created on [Function3] can be assigned to buttons and executed. When [F4] button is clicked, the window as shown in Figure 6 opens.Figure 6. [F4] windowASAHI KASEI [AKD4396-SBW]6-1. [OPEN] buttons on left side and [START] buttons(1) Click [OPEN] button and select the sequence file (*.aks).The sequence file name is displayed as shown in Figure 7.Figure 7. [F4] window(2)(2) Click [START] button, then the sequence is executed.3-2. [SAVE] and [OPEN] buttons on right side[SAVE] : The sequence file names can assign be saved. The file name is *.ak4.[OPEN] : The sequence file names assign that are saved in *.ak4 are loaded.3-3. Note(1) This function doesn't support the pause function of sequence function.(2) All files need to be in same folder used by [SAVE] and [OPEN] function on right side.(3) When the sequence is changed in [Function3], the file should be loaded again in order to reflect the change.ASAHI KASEI [AKD4396-SBW] 7. [Function5 Dialog]The register setting that is created by [SAVE] function on main window can be assigned to buttons and executed.When [F5] button is clicked, the following window as shown in Figure 8opens.Figure 8. [F5] window7-1. [OPEN] buttons on left side and [WRITE] button(1) Click [OPEN] button and select the register setting file (*.akr).(2) Click [WRITE] button, then the register setting is executed.7-2. [SAVE] and [OPEN] buttons on right side[SAVE] : The register setting file names assign can be saved. The file name is *.ak5.[OPEN] : The register setting file names assign that are saved in *.ak5 are loaded.7-3. Note(1) All files need to be in same folder used by [SAVE] and [OPEN] function on right side.(2) When the register setting is changed by [Save] Button in main window, the file should be loaded again inorder to reflect the change.ASAHI KASEI [AKD4396-SBW]Measurement Results[Measurement condition]• Measurement unit : Audio Precision System two Cascade (AP2) • MCLK : 512fs (44.1kHz), 256fs (96kHz), 128fs (192kHz) • BICK : 64fs• fs : 44.1kHz, 96kHz, 192kHz • Bit : 24bit• Power Supply : AVDD= DVDD=5V• Interface: Internal DIR (48kHz, 96kHz, 192kHz) • Temperature: Roomfs=44.1kHzParameter Input signal Measurement filter ResultsS/(N+D) 1kHz, 0dB 20kLPF 99.4 dB DR 1kHz, -60dB 22kLPF, A-weighted 119.0 dB S/N “0” data 22kLPF, A-weighted119.0 dBfs=96kHzParameter Input signal Measurement filter ResultsS/(N+D) 1kHz, 0dB 40kLPF 99.0 dB DR 1kHz, -60dB 40kLPF 114.0 dB DR 1kHz, -60dB 22kLPF, A-weighted 119.3 dBS/N “0” data 40kLPF 114.0 dB S/N “0” data 22kLPF, A-weighted119.3 dBfs=192kHzParameter Input signal Measurement filter ResultsS/(N+D) 1kHz, 0dB 40kLPF 98.7 dB DR 1kHz, -60dB 40kLPF 111.2 dB DR 1kHz, -60dB 22kLPF, A-weighted 116.4 dBS/N “0” data 40kLPF 113.6 dB S/N “0” data 22kLPF, A-weighted119.0 dBASAHI KASEI [AKD4396-SBW]Plots(fs=44.1kHz)AKMAK4396 FFT fs=44.1kHz AVDD=DVDD=5V, 0dBFS input2020k501002005001k2k5k10kHzd B r AFigure 9 FFT (fin=1kHz, Input Level=0dBFS)AKMAK4396 FFT plot fs=44.1kHz AVDD=DVDD=5V, -60dBFS inputd B r AHzFigure 10 FFT (fin=1kHz, Input Level=-60dBFS)ASAHI KASEI [AKD4396-SBW](fs=44.1kHz)AKM AK4396 FFT plot fs=44.1kHzAVDD=DVDD=5V, No signal inputdBrA501002005001k2k5k10k 2020kHzFigure 11FFT (Noise Floor)AKM AK4396 FFT fs=44.1kHzAVDD=DVDD=5V, 0dBFS input, outband noizedBrA501002005001k2k5k10k20k50k 20100kHzFigure 12FFT (Out of band noise)ASAHI KASEI [AKD4396-SBW](fs=44.1kHz)AKMAK4396 THD+N vs Input Level fs=44.1kHzAVDD=DVDD=5V, 0dBFS-140+0-130-120-110-100-90-80-70-60-50-40-30-20-10dBFSd B r AFigure 13 THD+N vs. Input level (fin=1kHz)AKMAK4396 THD+N vs Input Frequency fs=44.1kHzAVDD=DVDD=5V, 0dBFS input2020k501002005001k 2k 5k 10kHzd B r AFigure 14 THD+N vs. Input Frequency (Input level=0dBFS)ASAHI KASEI [AKD4396-SBW](fs=44.1kHz)AKMAK4396 Linearity fs=44.1kHz AVDD=DVDD=5V, 0dBFS input-150+0-140-130-120-110-100-90-80-70-60-50-40-30-20-10dBFSd B r AFigure 15 Linearity (fin=1kHz)AKMAK4396 Frequency Respons fs=44.1kHzAVDD=DVDD=5V, 0dBFS input2k20k4k6k8k10k 12k14k16k18kHzd B r AFigure 16 Frequency Response (Input level=0dBFS)ASAHI KASEI [AKD4396-SBW](fs=44.1kHz)AKMAK4396 Crosstalk (Red:Lch, Blue:Rch) fs=44.1kHzAVDD=DVDD=5V, 0dBFS input2020k501002005001k 2k 5k 10k Hzd BFigure 17 Crosstalk (Input level=0dBFS)ASAHI KASEI [AKD4396-SBW](fs=96kHz)AKMAK4396 FFT fs=96kHz AVDD=DVDD=5V, 0dBFS input4040k501002005001k2k5k10k20kHzd B r AFigure 18 FFT (fin=1kHz, Input Level=0dBFS)AKMAK4396 FFT fs=96kHzAVDD=DVDD=5V, 0dBFS input, notch4040k501002005001k2k5k10k20kHzd B r AFigure 19 FFT(fin=1kHz, Input Level=0dBFS, Notch)ASAHI KASEI [AKD4396-SBW](fs=96kHz)AKMAK4396 FFT fs=96kHzAVDD=DVDD=5V, -60dBFS input4040k501002005001k2k 5k 10k 20k Hzd B r AFigure 20 FFT (fin=1kHz, Input Level=-60dBFS)AKMAK4396 FFT fs=96kHzAVDD=DVDD=5V, No signal inputHzd B r AFigure 21 FFT (Noise Floor)ASAHI KASEI [AKD4396-SBW](fs=96kHz)AKMAK4396 THD+N vs Input Level fs=96kHzAVDD=DVDD=5V, 0dBFS input-140+0-130-120-110-100-90-80-70-60-50-40-30-20-10dBFSd B r AFigure 22 THD+N vs. Input level (fin=1kHz)AKMAK4396 THD+N vs Input Frequency fs=96kHzAVDD=DVDD=5V, 0dBFS input4040k501002005001k2k 5k 10k 20kHzd B r AFigure 23 THD+N vs. Input Frequency (Input level=0dBFS)ASAHI KASEI [AKD4396-SBW](fs=96kHz)AKMAK4396 Linearity fs=96kHz AVDD=DVDD=5V, 0dBFS input-150+0-140-130-120-110-100-90-80-70-60-50-40-30-20-10dBFSd B r AFigure 24 Linearity (fin=1kHz)AKMAK4396 Frequency Respons fs=96kHzAVDD=DVDD=5V, 0dBFS input2.5k40k5k7.5k10k12.5k15k17.5k20k 22.5k25k27.5k30k32.5k35k37.5kHzd B r AFigure 25 Frequency Response (Input level=0dBFS)ASAHI KASEI [AKD4396-SBW](fs=96kHz)AKMAK4396 Crosstalk (Red:Lch, Blue:Rch) fs=96kHzAVDD=DVDD=5V, 0dBFS input4040k501002005001k2k 5k 10k 20k Hzd BFigure 26 Crosstalk (Input level=0dBFS)ASAHI KASEI [AKD4396-SBW](fs=192kHz)AKMAK4396 FFT fs=192kHz AVDD=DVDD=5V, 0dBFS input9080k2005001k2k5k10k20k50kHzd B r AFigure 27 FFT (fin=1kHz, Input Level=0dBFS)AKMAK4396 FFT fs=192kHzAVDD=DVDD=5V, 0dBFS input, notch9080k2005001k2k5k10k20k50kHzd B r AFigure 28 FFT(fin=1kHz, Input Level=0dBFS, Notch)ASAHI KASEI [AKD4396-SBW](fs=192kHz)AKMAK4396 FFT fs=192kHzAVDD=DVDD=5V, -60dBFS inputd B r A9080k2005001k2k5k10k20k50kHzFigure 29 FFT (fin=1kHz, Input Level=-60dBFS)AKMAK4396 FFT fs=192kHzAVDD=DVDD=5V, No signal inputd B r A9080k2005001k2k5k10k20k50kHzFigure 30 FFT (Noise Floor)ASAHI KASEI [AKD4396-SBW](fs=192kHz)AKMAK4396 THD+N vs Input Level fs=192kHzAVDD=DVDD=5V, 0dBFS input-140+0-130-120-110-100-90-80-70-60-50-40-30-20-10dBFSd B r AFigure 31 THD+N vs. Input level (fin=1kHz)AKMAK4396 THD+N vs Input Frequency fs=192kHzAVDD=DVDD=5V, 0dBFS input9080k2005001k 2k5k 10k 20k 50kHzd B r AFigure 32 THD+N vs. Input Frequency (Input level=0dBFS)ASAHI KASEI [AKD4396-SBW](fs=192kHz)AKMAK4396 Linearity fs=192kHz AVDD=DVDD=5V, 0dBFS input-150+0-140-130-120-110-100-90-80-70-60-50-40-30-20-10dBFSd B r AFigure 33 Linearity (fin=1kHz)AKMAK4396 Frequency Respons fs=192kHzAVDD=DVDD=5V, 0dBFS input5k80k10k15k20k25k30k35k40k 45k50k55k60k65k70k75kHzd B r AFigure 34 Frequency Response (Input level=0dBFS)ASAHI KASEI [AKD4396-SBW]AKMAK4396 Cross talk (Red:Lch, Blue:Rch) fs=192kHzAVDD=DVDD=5V, 0dBFS input9080k2005001k 2k5k 10k 20k 50k Hzd BFigure 35 Crosstalk (Input level=0dBFS)ASAHI KASEI [AKD4396-SBW]Revision HistoryIMPORTANT NOTICE• These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status.• AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein.• Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials.• AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here:(a) A hazard related device or system is one designed or intended for life support or maintenanceof safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property.(b) A critical component is one whose failure to function or perform may reasonably be expectedto result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability.• It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification.Date (YY/MM/DD) Manual Revision Board Revision Reason Contents 05/03/14 KM078100 0 First edition05/03/23 KM078101 1 Modification Change of circuit 05/06/23 KM078102 2Modification Change of circuit元器件交易网元器件交易网。

山特产品速查手册说明书

山特产品速查手册SANTAK PRODUCT QUICK REFERENCE 全面保护用心为安全2 | 山特产品速查手册目录Contents后备式UPSTG-E1000/500, TG1000/500, ET1100/550, K500/K1000 PRO, MT500/1000, TG-BOX 600/850, SP-BOX 在线式UPS塔式C1-3K, 塔式C6-10K, 3C 10-20K, 机架式C1-3kVA Rack, 机架式C6-10kVA Rack, 3C3 Pro (20-200kVA), 3C3 Pro ISO (15 -200kVA), 3C3 HD (20-80kVA), 3C3 HD (400-600kVA),SPU1-20K 电力行业专用 UPS, SIU 10-200K 山特工业级 UPS 灵霄系列PT 3000 (1-3kVA), PT 3000 (6-20kVA)模块式UPSARRAY 3A3 Pro 系列 (15～150kVA), ARRAY 3A3 PT 系列 (25～200kVA), ARRAY 3A3 PT 系列 (60～600kVA)蓄电池C12系列电池, G 系列胶体蓄电池, ARRAY 系列蓄电池, SBC-A 电池柜微模块灵聚2.0微模块产品系列, 灵聚 2.0 Aisle 配电机柜配电单元 (PDU)精密空调全变频小型精密空调 (7.5-20kW), 定频小型精密空调(7.5-20kW), 双轴流小型机房空调, 机房专用空调(25-100kW), 列间精密空调 (SMCRC 系列)机柜S 系列机柜移动电站3-1314-3839-4546-4950-5455-606162-7273 74-75山特后备式TG-E系列UPS⸺美观时尚的“设备守护神”。

TG-E500/1000 UPS功能强大，集智慧、安全、可靠于一身，提升消费者在产品品质、观感、质感方面的使用体验。

AK5366VR资料

Power Down & Reset Control Input Selector Control Clock & Format Control Timer Select Lch IPGA Control Rch IPGA Control ALC Mode Control 1 ALC Mode Control 2 Lch DATT Control Rch DATT Control Lch Peak Hold Low Byte Lch Peak Hold High Byte Rch Peak Hold Low Byte Rch Peak Hold High Byte
-
No internal bonding. Connect to GND.
- Analog Power Supply Pin, 4.75 ∼ 5.25V
- Analog Ground Pin
O
Common Voltage Output Pin, AVDD/2 Bias voltage of ADC input.
FEATURES 1. 24bit Stereo ADC
• 5ch Stereo Inputs Selector • Input PGA from +18dB to 0dB, 0.5dB Step • Peak Hold Function • Auto Level Control (ALC) Circuit • Digital HPF for offset cancellation (fc=1.0Hz@fs=48kHz) • Digital Attenuator from +8dB to −63dB, Mute • Soft Mute • Single-end Inputs • S/(N+D) : 94dB • DR, S/N : 103dB • Audio I/F Format : 24bit MSB justified, I2S

AK4396VF中文资料

FEATURES
• 128x Oversampling
• Sampling Rate: 30kHz ∼ 216kHz
• 24Bit 8x Digital Filter (Slow-roll-off option)
Ripple: ±0.005dB, Attenuation: 75dB
• High Tolerance to Clock Jitter
AK4393/4/5
CKS0 DFS0=0
0
256fs
1
256fs
0
384fs
1
384fs
0
512fs
1
512fs
0
768fs
1
768fs
AK4396
DFS0=1 ACKS DFS0=0 DFS0=1
128fs
0
256fs
128fs
256fs
0
256fs
256fs
192fs
0
384fs
192fs
384fs
• Low Distortion Differential Output
• DSD data input available
• Digital de-emphasis for 32, 44.1, 48kHz sampling
• Soft Mute
• Digital Attenuator (Linear 256 steps)
元器件交易网
ASAHI KASEI
[AK4396]
AK4396
Advanced Multi-Bit 192kHz 24-Bit ∆Σ DAC
GENERAL DESCRIPTION The AK4396 is a high performance stereo DAC for the 192kHz sampling mode of DVD-Audio including a 24bit digital filter. Using AKM's multi bit architecture for its modulator the AK4396 delivers a wide dynamic range while preserving linearity for improved THD+N performance. The AK4396 has full differential SCF outputs, removing the need for AC coupling capacitors and increasing performance for systems with excessive clock jitter. The AK4396 accepts 192kHz PCM data and 1-bit DSD data, ideal for a wide range of applications including DVD-Audio and SACD. The AK4396 has a fully functional compatibility with the AK4393/4/5 and lower power dissipation.

近接垂直内联泵系列4360和4380的产品说明书

4380Close Coupled Vertical In-Line Pumpsf Series 4380JM Frame MotorsFrame 56C Motor18763312244360 43801Easy to service. A radially split casing permits removal of the motor and pump rotating assembly,without removing the pump casing from the line.2Easy removal of complete pump from the line when necessary, due to companion flanges, supplied with the pump.3Inside type mechanical seal serviceable without breaking pipe connections.4Flush and vent connection removes entrained air and ensures liquid at seal face at all times.5Equal suction and discharge connections result in simplified piping design and installation.6Fewer maintenance and servicing problems due to bearing-free pump design.f Series 4360f D e s ig n F e a t u r e sf D e s ig n F e a t u r e s453f Cooling and heating systems.f Pressure boosting systems.f Industrial applications requiring a compact pump. f OEM (Cooling tower, spray washer, fountain, etc.).f Typical Applicationsf Materials of ConstructionSeries 4360 & 4380f Pressure/Temperature Chart Series 4360/4380A Cast Iron - 125 psig Standard seal.Series 4360 & 4380.BDuctile Iron - 250 psig flanges Carbide seal.Series 4380 only.Notes:f Hydrostatic test pressure at ambient temperature is 150% maximum working pressure.f All values are based on clear, clean water. Values may change with other liquids.1.0PUMPS - CLOSE COUPLED VERTICAL IN-LINE.2.0Provide Armstrong single stage, single suctionVertical In-Line type pumps, with rising head to shut off pump characteristics.Refer to the schedule for pump flows and heads and motor speed, efficiency, enclosure and power requirements.3.0The pumps shall be Armstrong Series 4360 or Series 4380motor mounted Vertical In-Line.4.0Pump Construction:Series 4360:4.1Pump casing shall be cast iron, suitable for 175 psi(12.06 bar) working pressure at 140°F (60°C). The casing shall be hydrostatically tested to 150% maximum working pressure.The casing shall be radially split to allow removal of the rotating element without disturbing the pipe connections.The casing shall be provided with NPT threaded companionflanges, for the appropriate pump size, with gaskets and hardware.4.2Pump impeller shall be fully enclosed type. The impeller shall bekeyed and secured to the pump shaft by stainless steel fittings.4.3The pump shaft shall be a stainless steel stub shaft for frame56 motors. The steel motor shaft shall be enclosed by a bronze shaft sleeve, on other motor frame sizes.4.4Mechanical seal shall be single spring inside type with carbon andceramic (4360B) / carbon and silicone carbide (4360D) faces,EPDM elastomer, stainless steel spring and hardware. Provide factory installed seal vent line, piped from the seal area to the pump suction connection.Series 4380:4.1Pump casing shall be cast iron, suitable for 175 psi(12.06 bar) working pressure at 140°F (60°C). Ductile iron pump casings are suitable for pressures to 250 psi(17.24 bar). The casing shall be hydrostatically tested to 150%maximum working pressure.The casing shall be radially split to allow removal of the rotating element without disturbing the pipe connections.The casing suction and discharge connections shall be the same size and shall be provided with drilled and tapped seal vent and pressure gauge connections.4.2Pump impeller shall be bronze, fully enclosed type. Impeller shallbe dynamically balanced.4.3A bronze shaft sleeve, extending the full length of themechanical seal area, shall be provided.4.4Mechanical seal shall be single spring inside type with carbonagainst silicone carbide faces. EPDM elastomer with stainless steel spring and hardware shall be provided. Seal vent line shall be factory installed and shall be piped from the seal area to the pump suction connection.5.0Motor power requirements shown on the pump schedule arethe minimum acceptable and have been sized for continuous operation without exceeding the full load nameplate rating over the entire pump curve, exclusive of service factor.f Typical SpecificationsS . A . A r m s t r o n g L i m i t e d 23 Bertrand Avenue T oronto, Ontario Canada, M1L 2P3T : (416) 755-2291F (Main): (416) 759-9101A r m s t r o n g P u m p s I n c .93 East AvenueNorth T onawanda, New Y ork U.S.A., 14120-6594T : (716) 693-8813F : (716) 693-8970A r m s t r o n g H o l d e n B r o o k e P u l l e n Wenlock Way ManchesterUnited Kingdom, M12 5JL T : +44 (0) 161 223 2223F : +44 (0) 161 220 9660© S.A. Armstrong Limited 1996, 2003, 2007Other Armstrong ProductsFor even greater space savings, ease of installation and flexibility of use:Specify Armstrong dualArm Vertical In-Line pump.f Two (2) Armstrong time proven Vertical In-Line pumps in one (1) casing.f Eliminates a complete set of piping and fittings.f Stand-by or two pump parallel operation with no loss of single pump efficiency.f Remove one pump for repair while the second pump continues to operate.Armstrong Model SG Suction Guide StrainerArmstrong dualArm Vertical In-Line PumpArmstrong FTV-A Flo-Trex Combination Valve。

4316cpu参数

超线程技术
支持
虚拟化技术
Intel VT-x，Intel VT-D
指令集
TSX-NI，SSE4.2，AVX，AVX2，A度学习提升：是
英特尔资源导向技术：是
英特尔Speed Shift Technology：是
英特尔VT-x with Extended Page Tables(EPT)：是
AVX-512 FMA单元数：2
英特尔Volume Management Device(VMD)：是
英特尔AES新指令：是
英特尔Software Guard Extensions：Yes with Intel SPS
英特尔Trusted Execution Technology：是
执行禁用位：是
基于模式的执行控制(MBE)：是
Intel Xeon Silver 4316参数
重要参数
声明：仅供参考，以当地实际销售信息为准
核心数量：二十核心
主频：2.3GHz
制作工艺：10纳米
插槽类型：LGA 4189
基本参数
CPU系列
第三代Intel Xeon Silver系列
制作工艺
10纳米
核心代号
Ice Lake
性能参数
核心数量
二十核心
线程数量
四十线程
CPU主频
2.3GHz
动态加速频率
3.4GHz
L3缓存
30MB
热设计功耗(TDP)
150W
内存规格
支持最大内存容量
6TB
内存类型
DDR4 2667MHz
内存描述
最大内存通道数：8
ECC内存支持：是
封装规格
插槽类型

AKD4356资料

n External analog circuitThe 2nd order LPF (fc=93.2kHz, Q=0.712) which adds differential outputs of AK4356 is implemented on the board.When the further attenuation of the out-band noise is needed, some additional LPF is required. Analog signal is output through BNC connectors on the board. And the output level of AK4356 is 5.5Vpp@5V.The AK4356 detects input signal “zero” conditions and assert high on DZFL/DZFR pins. As shown on Figure 2, analog output is muted externally with this signal.LOUT-(ROUT-)DZFL*(DZFR*)LOUT-(ROUT-)R1R2R3C1C24.7k4.7k 2003300p 470pTable 1. The value of R,C on this boardfin 20kHz 40kHz80kHz Frequency Response -0.004dB -0.123dB-1.823dBTable 2. Frequency Response of LPF <Calculation>f C =ω02π,ω0=12*C1*C2*R2*R3,Q=2*C1*ω0.+1R1+1R21R3n Operation sequence1) Set up the power supply lines.[AVDD](orange)= 4.5∼5.25V [DVDD](orange)= 4.5∼5.25V [VD](red)= 3.4∼5.0V [VP+](green)= +12V ∼+15V [VP-](blue)= -12V ∼-12V [AGND](black)= 0V [DGND](black)= 0VEach supply line should be distributed from the power supply unit.2) Set-up the evaluation modes, jumper pins and DIP switches (See the followings.)3) Power on.The AK4356 should be reset once bringing SW1(-PD) “L” upon power-up.n Evaluation modeApplicable evaluation modes1) DIR (Optical Link and RCA) (default)2) Using ROM data (AK43XX)3) Using AKM’s evaluation board for ADC 4) Feeding all signals from external1) DIR (Optical Link and RCA) <default>PORT4(TORX174) or J1(RCA) is used. All clock are supplied from CS8414(DIR). DIR generates MCLK,BICK, LRCK and SDATA from the received data through optical connector (TORX174) or RCA ed for the evaluation using CD test disk. Nothing should be connected to PORT2,3. In case of using optical connector (TORX174), select “OPT” on JP17(RCA/OPT). In case of using RCA connector, select “RCA”.JP15XTIJP14DIRJP4LRCKDIR ADC JP7BICKJP16XTEJP13SDATADIRADC D I RB N CX TLGNDVD 2) Ideal sine wave generated by ROM dataConnect the AKD43XX with PORT3(AD/ROM). AKD4356 sends MCLK to AKD43XX, and receives LRCK,BICK and SDATA. In case of using external master clock through a BNC connector, select “BNC” on JP15(XTI)and short JP16(XTE).JP15XTIJP14DIRJP4LRCKDIR ADC JP7BICKJP16XTEJP13SDATADIRADC D I RB N CX TLGNDVD3) Using AKM’s evaluation board for ADCTo evaluate AK4356 with analog input, the AKM’s evaluation board for ADC can be used. MCLK, BICK and LRCK are supplied from clock generator on the AKD4356, and analog signal is A/D converted and send to AKD4356 through PORT3(AD/ROM). In case of using external master clock through a BNC connector, select “BNC” on JP15(XTI) and short JP16(XTE).JP15XTIJP14DIRJP4LRCKDIR ADC JP7BICKJP16XTEJP13SDATADIRADC D I RB N CX TLGNDVD 4) Feeding all signals from externalUnder the following set-up, all external signals can be fed through POTR3.JP15XTIJP14DIRJP4LRCKDIR ADC JP7BICKJP16XTEJP13SDATADIRADC D I RB N CX TLGNDVD n BICK frequency[JP9]:When BICK is fed from 74HC4040 on board,it’s frequency is selected with JP9.128fs:BICK = 128fs64fs:BICK = 64fs (Figure 3)32fs:BICK = 32fsFigure 3. BICK frequencyJP9X_BICK128fs 64fs 32fsn DIP switch set upUpper side is “ON”(“H”), lower side is “OFF”(”L”).[SW3](MODE1): No.1 to 5 set the mode of AK4356 and No.6 to 8 set the mode of CS8412.No.Pin OFF ON1CAD1 2CAD0Chip address (2bit) <default=”00”>3DIF0 4DIF1 5DIF2Digital interface format of AK4356(See table 2.)6M2 7M1 8M0Digital interface format of CS8414(See table 2.)(Note)Table 3. SW3 set-up(Note:M2-0 should be selected at only evaluation mode 1.In other mode, these should be “OFF”.)345678JP6 Mode Format DIF0DIF1DIF2M2M1M0BICK2016bit, LSB justified000101THR120bit, LSB justified100----224bit, MSB justified010000INV3I2S110010THR default424bit, LSB justified001----Table 4. Digital interface format set-up (1=ON, 0=OFF)(CS8414 does not correspond to 20/24bit LSB justified format.)[SW4](MODE2): Set the mode of AK4356.No.Pin OFF <default>ON1DFS0Normal speed Double speed2DZFE Zero detect disable Zero detect enable3CKS2 4CKS1 5CKS0Clock select(See the datasheet of AK4356.JP5 and 8 should be selected as table 4.) Table 5. SW4 set-up[JP5, 8]: Set the dividing rate corresponding to CKS2-0. This set up is needed only for the evaluation mode 3.JP5JP8Mode FS2FS1128fs x1/2x1256fs x1x1512fs x1x2Table 6. JP5 and 8 set up(For 192fs/384fs/768fs mode, use the external divider.)PORT1CR-I/F12910-CS CCLK CDTIPORT2AC312910SDTI1SDTI2SDTI3MCLK BICK LRCKn Other jumpers set up[JP1](GND): Analog ground and digital groundOpen:Separated <default>Short:Common (The connector “DGND” can be open.)[JP2](DVDD): DVDD of AK4356DVDD:Independent of AVDD <default>AVDD:Same as AVDD (The connector “DVDD” can be open.)[JP3](REG): AVDD of AK4356Open:Supplied from “AVDD” connectorShort:Supplied from the regulator (The connector “AVDD” should be open.)[JP10-12](SDTI1-3): SDTI of AK4356DATA:Serial data <default>GND:“0” datan The function of the toggle SWUpper-side is “H” and lower-side is “L”.[SW1](-PD):Resets the AK4356. Keep “H” during normal operation.[SW2](SMUTE):Soft mute of AK4356. Bring “H” when using soft mute.n The indication content for LED[D2] (VERF):Monitors VERF pin of the CS8414. LED turns on when some error has occurred to CS8414.[D3] (PREM):Indicates whether the input data is pre-emphasized or not. LED turns on when the data is pre-emphasized.n Serial control modeThe AK4356 can be controlled via the printer port (parallel port) of IBM-AT compatible PC. Connect PORT1(CR-I/F) with PC by 10-line flat cable packed with the AKD4356.Chip address can be selected by SW3(MODE1)-No.1(CAD1) and No.2(CAD0).Take care of the direction of connector. There is a mark at 1pin.The pin layout of PORT1 is as Figure 4.Figure 4. PORT1 pin layoutn Interface with AC3 decoderPORT2(AC3) is used for interface with AC3 decoder.MCLK, BICK, LRCK and 3-line serial data can be input from the decoder via PORT2.Pin layout of PORT2 is as Figure5.In this case, JP4(LRCK), JP7(BICK), JP15(XTI), JP16(XTE),JP14(DIR) and JP13(SDATA) should be set up as evaluation mode 4.Figure 5. PORT2 pin layoutMEASUREMENT RESULTS[Measurement condition]• Measurement unit: ROHDE & SCHWARZ, UPD04• MCLK: 256fs• BICK: 64fs• fs: 44.1kHz, 96kHz, 192kHz• BW: 20Hz∼20kHz (fs=44.1kHz), 20Hz∼40kHz (fs=96kHz), 20Hz∼80kHz (fs=192kHz)• Bit: 24bit• Power Supply: AVDD=DVDD=5V• Interface: DIR (fs=44.1kHz), Serial Multiplex (fs=96kHz, 192kHz)• Temperature: RoomParameter Input signal Measurement filter fs=44.1kHzS/(N+D)1kHz, 0dB20kLPF 97.5dBDR1kHz, -60dB20kLPF110.0dB20kLPF, A-weighted113.2dBS/N no signal20kLPF110.1dB20kLPF, A-weighted113.5dBParameter Input signal Measurement filter fs=96kHzS/(N+D)1kHz, 0dB40kLPF 94.4dBDR1kHz, -60dB40kLPF106.2dB20kLPF, A-weighted112.3dBS/N no signal40kLPF106.4dB20kLPF, A-weighted112.8dBParameter Input signal Measurement filter fs=192kHzS/(N+D)1kHz, 0dB80kLPF 90.0dBDR1kHz, -60dB80kLPF 92.6dB20kLPF, A-weighted112.8dBS/N no signal80kLPF 93.3dB20kLPF, A-weighted112.8dB[Measurement condition]• Measurement unit: Audio Precision, System two, Cascade• MCLK: 256fs• BICK: 64fs• fs: 44.1kHz• BW: 20Hz∼20kHz• Bit: 24bit• Power Supply: AVDD=DVDD=5V• Interface: DIR• Temperature: RoomParameter Input signal Measurement filter ResultsS/(N+D)1kHz, 0dB20kLPF 98.8dBDR1kHz, -60dB22kLPF, A-weighted112.2dBS/N no signal22kLPF, A-weighted112.6dBn Plots[Measurement condition]• Measurement unit: Audio Precision, System two, Cascade (fs=48kHz),ROHDE & SCHWARZ, UPD04 (fs=96kHz)• MCLK: 256fs• BICK: 64fs• fs: 44.1kHz, 96kHz, 192kHz• BW: 20Hz∼20kHz (fs=44.1kHz), 20Hz∼40kHz (fs=96kHz), 20Hz∼80kHz (fs=192kHz)• Bit: 24bit• Power Supply: VA=VD=5V• Interface: DIR (fs=48kHz, 96kHz), Serial Multiplex (fs=192kHz)• Temperature: Roomfs=44.1kHzFigure 6. THD+N vs Input Level (fin=1kHz)Figure 7. THD+N vs fin (0dBFS input)Figure 8. Linearity (fin=1kHz)Figure 9. Frequency Response (0dBFS input)Figure 10. Cross-talk (0dBFS input)Figure 11. FFT (1kHz, 0dBFS input)Figure 12. FFT (1kHz, -60dBFS input)Figure 13. FFT (noise floor)Figure 14. FFT (outband noise)fs=96kHzFigure 15. THD+N vs Input Level (fin=1kHz)Figure 16. THD+N vs fin (0dBFS input)Figure 17. Linearity (fin=1kHz)Figure 18. Frequency Response (0dBFS input)fs=192kHzFigure 19. THD+N vs Input Level (fin=1kHz)Figure 20. THD+N vs fin (0dBFS input)Figure 21. Linearity (fin=1kHz)Figure 22. Frequency Response (0dBFS input)AKMAK4356 THD+N vs Input Level (fs=44.1kHz, fin=1kHz)-120+0-110-100-90-80-70-60-50-40-30-20-10dBFSd B r AFigure 6. THD+N vs Input Level (fs=44.1kHz; fin=1kHz)AKMAK4356 THD+N vs fin (fs=44.1kHz, 0dBFS input)2020k501002005001k 2k 5k 10k Hzd B r AFigure 7. THD+N vs fin (fs=44.1kHz; 0dBFS input)AKMAK4356 Linearity (fs=44.1kHz, fin=1kHz)-140+0-130-120-110-100-90-80-70-60-50-40-30-20-10dBFSd B r AFigure 8. Linearity (fs=44.1kHz; fin=1kHz)AKMAK4356 Frequency Response (fs=44.1kHz, 0dBFS input)2k 20k4k 6k 8k 10k12k 14k 16k 18k Hzd B r AFigure 9. Frequency Response (fs=44.1kHz; 0dBFS input)* including output 2nd order LPF ResponseAKMAK4356 Cross-talk (fs=44.1kHz, 0dBFS input)2020k501002005001k 2k 5k 10k Hzd BFigure 10. Cross-talk (fs=44.1kHz; 0dBFS input)AKMAK4356 FFT (fs=44.1kHz; 1kHz, 0dBFS input)2020k501002005001k 2k 5k 10k Hzd B r AFigure 11. FFT (fs=44.1kHz; 1kHz, 0dBFS input)FFT point=16384, Avg=8AKMAK4356 FFT (fs=44.1kHz; 1kHz, -60dBFS input)2020k501002005001k 2k 5k 10k Hzd B r AFigure 12. FFT (fs=44.1kHz; 1kHz, -60dBFS input)FFT point=16384, Avg=8AKMAK4356 FFT (noise floor; fs=44.1kHz, no signal input)2020k501002005001k 2k 5k 10k Hzd B r AFigure 13. FFT (noise floor: fs=44.1kHz; no signal input)FFT point=16384, Avg=8AKMAK4356 FFT (outband noise: ~130kHz; fs=44.1kHz, no signal input)200100k5001k 2k 5k 10k 20k 50k Hzd B r AFigure 14. FFT (outband noise: fs=44.1kHz; no signal input)FFT point=16384, Avg=8AKMAK4356 THD+N vs Input Level (fs=96kHz, fin=1kHz)-120+0-110-100-90-80-70-60-50-40-30-20-10dBFSd B r AFigure 15. THD+N vs Input Level (fs=96kHz; fin=1kHz)AKMAK4356 THD+N vs fin (fs=96kHz, 0dBFS input)2040k501002005001k 2k 5k 10k 20k Hzd B r AFigure 16. THD+N vs fin (fs=96kHz; 0dBFS input)AKMAK4356 Linearity (fs=96kHz, fin=1kHz)-140+0-130-120-110-100-90-80-70-60-50-40-30-20-10dBFSd B r AFigure 17. Linearity (fs=96kHz; fin=1kHz)AKMAK4356 Frequency Response (fs=96kHz, 0dBFS input)2.5k 40k5k 7.5k 10k 12.5k 15k 17.5k 20k 22.5k 25k 27.5k 30k32.5k 35k 37.5k Hzd B r AFigure 18. Frequency Response (fs=96kHz; 0dBFS input)including external 2nd order LPF responseFigure 19. THD+N vs Input Level (fs=192kHz; fin=1kHz)Figure 20. THD+N vs fin (fs=192kHz; 0dBFS input)Figure 21. Linearity (fs=192kHz; fin=1kHz)Figure 22. Frequency Response (fs=192kHz; 0dBFS input) * including external 2nd order LPF responseAKD4356 Control Program ver 1.0 operation manual 1.Connect IBM-A T compatible PC with AKD4356 by 10-line type flat cable (packed with AKD4356).Take care of the direction of 10pin Header (Refer to manual of AKD4356).2.Start up “WINDOWS 95” or “WINDOWS 98”.3.Insert the floppy-disk labeled “AKD4356 Control Program ver 1.0” into the floppy-disk drive.4.Set up “MS-DOS” from start menu.5.Change directory to the floppy-disk drive(ex.a:) at MS-DOS prompt.6.Type “ak4356”.7.Then follow the displayed comment (See the following).==================== <<Operating flow>> =====================Input Chip Address (2bit)Write data/ Display register map/ Reset etc.à loop=========================================================At first the following message is displayed:****** AK4356 Control Program ver 1.0 , '99/3 ******copyright(c) 1999, Asahi Kasei Microsystems co.,ltd.All rights reserved.Input Chip Address(CAD1,CAD0) (2 figure, binary) =Input chip address in 2 figures of binary.Set CAD1 and CAD0 before the AKD4356 is powered up.When hanging CAD1 and CAD0, set SW1(-PD) “L”, then “H” after that.After chip address is defined, the following default register map is displayed (Loop starts from here): CAD1-0=00 ---------------------------------------------------------------- ADDR = 00 : 01 <Control 1> ( 0 SLOW DZFM DZFE DIF2 DIF1 DIF0 RSTN ) ADDR = 01 : 01 <Control 2> ( 0 0 0 CKS2 CKS1 CKS0 SMUTE RSTN ) ADDR = 02 : 0F <Speed & PD> ( 0 0 DFS1 DFS0 PW3 PW2 PW1 RSTN ) ADDR = 03 : 15 <DEM control>( 0 0 DEMC1 DEMC0 DEMB1 DEMB0 DEMA1 DEMA0) ADDR = 04 : FF <LOUT1 ATT> ( ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 ) ADDR = 05 : FF <ROUT1 ATT> ( ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 ) ADDR = 06 : FF <LOUT2 ATT> ( ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 ) ADDR = 07 : FF <ROUT2 ATT> ( ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 ) ADDR = 08 : FF <LOUT3 ATT> ( ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 ) ADDR = 09 : FF <ROUT3 ATT> ( ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 ) ADDR = 0A : 00 <Test> ( TEST7 TEST6 TEST5 TEST4 TEST3 TEST2 TEST1 TEST0) Input 1(Write), R(Reset), T(Table), I(Increment), D(Decrement) or S(Stop) :1) If you input “1”, you can write data to AK4356.You can write data to AK4356Input Register Address (2 figure, hex) (00-0A) =Input register address in 2 figures of hexadecimal.Then current data of this address is displayed:ADDR = 00 : 01 <Control 1> ( 0 SLOW DZFM DZFE DIF2 DIF1 DIF0 RSTN )0 0 0 0 0 0 0 1Input Register Data (2 figure, hex) (00-FF) =You can write control data to this address. Input control data in 2 figures of hexadecimal.Refer to datasheet of AK4356.Then the data written to this address is displayed:ADDR = 00 : 07 <Control 1> ( 0 SLOW DZFM DZFE DIF2 DIF1 DIF0 RSTN )0 0 0 0 0 1 1 12) If you input “R” or “r”, this program writes default data to all register addresses.3) If you input “T” or “t”, current register map is displayed.4) If you input “I” or “i”, this program increment data of current address by 1 (only for addr=04H to 09H). You can increment A TT value by 1step.5) If you input “D” or “d”, this program decrement data of current address by 1 (only for addr=04H to 09H). You can decrement A TT value by 1step.6) If you input “S” or “s”, this program is terminated.元器件交易网元器件交易网元器件交易网元器件交易网IMPORTANT NOTICE• These products and their specifications are subject to change without notice. Beforeconsidering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM)sales office or authorized distributor concerning their current status.• AKM assumes no liability for infringement of any patent, intellectual property, or other rightin the application or use of any information contained herein.• Any export of these products, or devices or systems containing them, may require an exportlicense or other official approval under the law and regulations of the country of exportpertaining to customs and tariffs, currency exchange, or strategic materials.• AKM products are neither intended nor authorized for use as critical components in anysafety, life support, or other hazard related device or system, and AKM assumes noresponsibility relating to any such use, except with the express written consent of theRepresentative Director of AKM. As used here:(a) A hazard related device or system is one designed or intended for life support ormaintenance of safety or for applications in medicine, aerospace, nuclear energy, orother fields, in which its failure to function or perform may reasonably be expected toresult in loss of life or in significant injury or damage to person or property.(b) A critical component is one whose failure to function or perform may reasonably beexpected to result, whether directly or indirectly, in the loss of the safety or effectivenessof the device or system containing it, and which must therefore meet very high standardsof performance and reliability.• It is the responsibility of the buyer or distributor of an AKM product who distributes, disposesof, or otherwise places the product with a third party to notify that party in advance of theabove content and conditions, and the buyer or distributor agrees to assume any and allresponsibility and liability for and hold AKM harmless from any and all claims arising fromthe use of said product in the absence of such notification.。