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2M X 8 Bit / 1M X 16 Bit CMOS 3.3 Volt-only,Boot Sector Flash MemoryDocument Title2M X 8 Bit / 1M X 16 Bit CMOS 3.3 Volt-only, Boot Sector Flash MemoryRevision HistoryDate Remark Rev. No. History Issue0.0 Initial issue April 1, 2005 Preliminary0.1 Change Vcc_min from 2.7V to 3.0V May 12, 20052M X 8 Bit / 1M X 16 Bit CMOS 3.3 Volt-only,Boot Sector Flash Memory FeaturesSingle power supply operation- Regulated voltage range: 3.0 to 3.6 volt read and write operations for compatibility with high performance 3.3 volt microprocessorsAccess times:- 70/90 (max.)Current:- 9 mA typical active read current- 20 mA typical program/erase current- 200 nA typical CMOS standby- 200 nA Automatic Sleep Mode currentFlexible sector architecture- 16 Kbyte/ 8 KbyteX2/ 32 Kbyte/ 64 KbyteX31 sectors- 8 Kword/ 4 KwordX2/ 16 Kword/ 32 KwordX31 sectors- Any combination of sectors can be erased- Supports full chip erase- Sector protection:A hardware method of protecting sectors to prevent anyinadvertent program or erase operations within that sector. Temporary Sector Unprotect feature allows code changes in previously locked sectorsUnlock Bypass Program Command- Reduces overall programming time when issuingmultiple program command sequenceTop or bottom boot block configurations availableEmbedded Algorithms- Embedded Erase algorithm will automatically erase the entire chip or any combination of designated sectors and verify the erased sectors - Embedded Program algorithm automatically writes and verifies data at specified addressesTypical 100,000 program/erase cycles per sector20-year data retention at 125°C- Reliable operation for the life of the systemCFI (Common Flash Interface) compliant- Provides device-specific information to the system, allowing host software to easily reconfigure for different Flash devicesCompatible with JEDEC-standards- Pinout and software compatible with single-power-supply Flash memory standard- Superior inadvertent write protectionData Polling and toggle bits- Provides a software method of detecting completion of program or erase operationsReady / BUSY pin (RY / BY)- Provides a hardware method of detecting completion of program or erase operations (not available on 44-pin SOP)Erase Suspend/Erase Resume- Suspends a sector erase operation to read data from, or program data to, a non-erasing sector, then resumes the erase operationHardware reset pin (RESET)- Hardware method to reset the device to reading array dataPackage options- 44-pin SOP or 48-pin TSOP (I) or 48-ball TFBGAGeneral DescriptionThe A29L160A is a 16Mbit, 3.3 volt-only Flash memory organized as 2,097,152 bytes of 8 bits or 1,048,576 words of 16 bits each. The 8 bits of data appear on I/O0 - I/O7; the 16 bits of data appear on I/O0~I/O15. The A29L160A is offered in 48-ball FBGA,44-pin SOP and 48-Pin TSOP packages. This device is designed to be programmed in-system with the standard system 3.3 volt VCC supply. Additional 12.0 volt VPP is not required for in-system write or erase operations. However, the A29L160A can also be programmed in standard EPROM programmers.The A29L160A has the first toggle bit, I/O6, which indicates whether an Embedded Program or Erase is in progress, or it is in the Erase Suspend. Besides the I/O6 toggle bit, the A29L160A has a second toggle bit, I/O2, to indicate whether the addressed sector is being selected for erase. The A29L160A also offers the ability to program in the Erase Suspend mode. The standard A29L160A offers access times of 70 and 90ns, allowing high-speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable (CE), write enable (WE) and output enable (OE) controls.The device requires only a single 3.3 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations.The A29L160A is entirely software command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices.Device programming occurs by writing the proper program command sequence. This initiates the Embedded Program algorithm - an internal algorithm that automatically times the program pulse widths and verifies proper program margin.A29L160A SeriesDevice erasure occurs by executing the proper erase command sequence. This initiates the Embedded Erase algorithm - an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper erase margin. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four.The host system can detect whether a program or erase operation is complete by observing the RY / BY pin, or by reading the I/O 7 (Data Polling) and I/O 6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command.The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The A29L160A is fully erased when shipped from the factory.The hardware sector protection feature disables operations for both program and erase in any combination of the sectors of memory. This can be achieved via programming equipment.The Erase Suspend/Erase Resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any other sector that is not selected for erasure. True background erase can thus be achieved. The hardware RESET pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory.The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both these modes.Pin ConfigurationsSOPTSOP (I)A18A17A7A6A5A4A3A2A1A0CE VSS OE I/O 0I/O 14I/O 8I/O 7I/O 15(A-1)VSS BYTE A16A15A14A12A11A10A19A8A9A13A 29L 160A M1234567891011121314151629303132333435363738394041424344RESET WE 171819202122282726252423I/O 1I/O 9I/O 2I/O 10I/O 3I/O 11I/O 6I/O 13I/O 5I/O 12I/O 4VCCPin Configurations (continued)TFBGABlock DiagramPin DescriptionsAbsolute Maximum Ratings*Storage Temperature Plastic Packages. . . -65°C to + 150°C Ambient Temperature with Power Applied. -55°C to + 125°C Voltage with Respect to GroundVCC (Note 1) . . . . . . . . . . . . . . . . . . . . ……. . -0.5V to +4.0V A9, OE & (Note 2) . . . . . . . . . . . …. -0.5 to +12.5V All other pins (Note 1) . . . . . . . . . . …. . -0.5V to VCC + 0.5V Output Short Circuit Current (Note 3) . . . . . . . …. . 200mANotes:1. Minimum DC voltage on input or I/O pins is -0.5V. Duringvoltage transitions, input or I/O pins may undershoot VSS to -2.0V for periods of up to 20ns. Maximum DC voltage on input and I/O pins is VCC +0.5V. During voltage transitions, input or I/O pins may overshoot to VCC +2.0V for periods up to 20ns.2. Minimum DC input voltage on A9,OE and RESET is -0.5V. During voltage transitions, A9,OE and RESET may overshoot VSS to -2.0V for periods of up to 20ns.Maximum DC input voltage on A9 is +12.5V which may overshoot to 14.0V for periods up to 20ns.3. No more than one output is shorted at a time. Duration ofthe short circuit should not be greater than one second.*CommentsStresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of these specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.Operating RangesCommercial (C) DevicesAmbient Temperature (T A ) . . . . . . . . . . . ….. . . 0°C to +70°CExtended Range DevicesAmbient Temperature (T A )For –I series. . . . . . . . . . . . . . . . . . . . . . . . . . -25°C to +85°C For –U series . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°CVCC Supply VoltagesVCC for all devices . . . . . . . . . . . . . . . . . …...+3.0V to +3.6V Operating ranges define those limits between which the functionally of the device is guaranteed.Device Bus OperationsThis section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is composed of latches that store the commands, along with the address and data information needed toexecute the command. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. The appropriate device bus operations table lists the inputs and control levels required, and the resulting output. The following subsections describe each of these operations in further detail.Table 1. A29L160A Device Bus OperationsL = Logic Low = V IL , H = Logic High = V IH , V ID = 12.0 ± 0.5V, X = Don't Care, D IN = Data In, D OUT = Data Out, A IN = Address In Notes:1. Addresses are A19:A0 in word mode (BYTE =V IH ), A19: A -1 in byte mode (BYTE =V IL ).2. See the “Sector Protection/Unprotection” section and Temporary Sector Unprotect for more information.Word/Byte ConfigurationThe BYTE pin determines whether the I/O pins I/O15-I/O0 operate in the byte or word configuration. If the BYTE pin is set at logic ”1”, the device is in word configuration, I/O15-I/O0 are active and controlled by CE and OE.If the BYTE pin is set at logic “0”, the device is in byte configuration, and only I/O0-I/O7 are active and controlled by CE and OE. I/O8-I/O14 are tri-stated, and I/O15 pin is used as an input for the LSB(A-1) address function. Requirements for Reading Array DataTo read array data from the outputs, the system must drive the CE and OE pins to V IL. CE is the power control and selects the device. OE is the output control and gates array data to the output pins. WE should remain at V IH all the time during read operation. The BYTE pin determines whether the device outputs array data in words and bytes. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered.See "Reading Array Data" for more information. Refer to the AC Read Operations table for timing specifications and to the Read Operations Timings diagram for the timing waveforms, l CC1 in the DC Characteristics table represents the active current specification for reading array data.Writing Commands/Command SequencesTo write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive WE and CE to V IL, and OE to V IH. For program operations, the BYTE pin determines whether the device accepts program data in bytes or words, Refer to “Word/Byte Configuration” for more information. The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are required to program a word or byte, instead of four. The “Word / Byte Program Command Sequence” section has details on programming data to the device using both standard and Unlock Bypass command sequence. An erase operation can erase one sector, multiple sectors, or the entire device. The Sector Address Tables indicate the address range that each sector occupies. A "sector address" consists of the address inputs required to uniquely select a sector. See the "Command Definitions" section for details on erasing a sector or the entire chip, or suspending/resuming the erase operation.After the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on I/O7 - I/O0. Standard read cycle timings apply in this mode. Refer to the "Autoselect Mode" and "Autoselect Command Sequence" sections for more information.I CC2 in the DC Characteristics table represents the active current specification for the write mode. The "AC Characteristics" section contains timing specification tables and timing diagrams for write operations.Program and Erase Operation StatusDuring an erase or program operation, the system may check the status of the operation by reading the status bits on I/O7 - I/O0. Standard read cycle timings and I CC read specifications apply. Refer to "Write Operation Status" for more information, and to each AC Characteristics section for timing diagrams.Standby ModeWhen the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE input.The device enters the CMOS standby mode when the CE & RESET pins are both held at VCC ± 0.3V. (Note that this is a more restricted voltage range than V IH.) If CE and RESET are held at V IH, but not within VCC ± 0.3V, the device will be in the standby mode, but the standby current will be greater. The device requires the standard access time (t CE) before it is ready to read data.If the device is deselected during erasure or programming, the device draws active current until the operation is completed.I CC3 and I CC4 in the DC Characteristics tables represent the standby current specification.Automatic Sleep ModeThe automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when addresses remain stable for t ACC +30ns. The automatic sleep mode is independent of the CE,WE and OE control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. I CC4 in the DC Characteristics table represents the automatic sleep mode current specification.Output Disable ModeWhen the OE input is at V IH, output from the device is disabled. The output pins are placed in the high impedance state.RESET: Hardware Reset PinThe RESET pin provides a hardware method of resetting the device to reading array data. When the system drives the RESET pin low for at least a period of t RP, the device immediately terminates any operation in progress, tristates all data output pins, and ignores all read/write attempts for the duration of the RESET pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity.Current is reduced for the duration of the RESET pulse. When RESET is held at VSS ± 0.3V, the device draws CMOS standby current (I CC4 ). If RESET is held at V IL but not within VSS ± 0.3V, the standby current will be greater.The RESET pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory.If RESET is asserted during a program or erase operation, the RY/BY pin remains a “0” (busy) until the internal reset operation is complete, which requires a time t READY (during Embedded Algorithms). The system can thus monitor RY/BYto determine whether the reset operation is RESET is asserted when a program or eraseoperation is not executing (RY/BYpin is “1”), the reset operation is completed within a time of t READY (not during Embedded Algorithms). The system can read data t RH after the RESET pin return to V IH .Refer to the AC Characteristics tables for RESET parameters and diagram.Table 2. A29L160A Top Boot Block Sector Address TableAddress Range (in hexadecimal) Sector A19 A18 A17 A16 A15 A14A13A12Sector Size (Kbytes/ Kwords) Byte Mode (x8)Word Mode (x16)SA0 0 0 0 0 0 X X X 64/32 000000 - 00FFFF 00000 - 07FFF SA1 0 0 0 0 1 X X X 64/32 010000 - 01FFFF 08000 - 0FFFF SA2 0 0 0 1 0 X X X 64/32 020000 - 02FFFF 10000 - 17FFF SA3 0 0 0 1 1 X X X 64/32 030000 - 03FFFF 18000 - 1FFFF SA4 0 0 1 0 0 X X X 64/32 040000 - 04FFFF 20000 - 27FFF SA5 0 0 1 0 1 X X X 64/32 050000 - 05FFFF 28000 - 2FFFF SA6 0 0 1 1 0 X X X 64/32 060000 - 06FFFF 30000 - 37FFF SA7 0 0 1 1 1 X X X 64/32 070000 - 07FFFF 38000 - 3FFFF SA8 0 1 0 0 0 X X X 64/32 080000 - 08FFFF 40000 - 47FFF SA9 0 1 0 0 1 X X X 64/32 090000 - 09FFFF 48000 - 4FFFF SA10 0 1 0 1 0 X X X 64/32 0A0000 - 0AFFFF 50000 - 57FFF SA11 0 1 0 1 1 X X X 64/32 0B0000 - 0BFFFF 58000 - 5FFFF SA12 0 1 1 0 0 X X X 64/32 0C0000 - 0CFFFF 60000 - 67FFF SA13 0 1 1 0 1 X X X 64/32 0D0000 - 0DFFFF 68000 - 6FFFF SA14 0 1 1 1 0 X X X 64/32 0E0000 - 0EFFFF 70000 - 77FFF SA15 0 1 1 1 1 X X X 64/32 0F0000 - 0FFFFF 78000 - 7FFFF SA16 1 0 0 0 0 X X X 64/32 100000 - 10FFFF 80000 - 87FFF SA17 1 0 0 0 1 X X X 64/32 110000 - 11FFFF 88000 - 8FFFF SA18 1 0 0 1 0 X X X 64/32 120000 - 12FFFF 90000 - 97FFF SA19 1 0 0 1 1 X X X 64/32 130000 - 13FFFF 98000 - 9FFFF SA20 1 0 1 0 0 X X X 64/32 140000 - 14FFFF A0000 - A7FFF SA21 1 0 1 0 1 X X X 64/32 150000 - 15FFFF A8000 - AFFFF SA22 1 0 1 1 0 X X X 64/32 160000 - 16FFFF B0000 - B7FFF SA23 1 0 1 1 1 X X X 64/32 170000 - 17FFFF B8000 - BFFFF SA24 1 1 0 0 0 X X X 64/32 180000 - 18FFFF C0000 - C7FFF SA25 1 1 0 0 1 X X X 64/32 190000 - 19FFFF C8000 - CFFFF SA26 1 1 0 1 0 X X X 64/32 1A0000 - 1AFFFF D0000 - D7FFF SA27 1 1 0 1 1 X X X 64/32 1B0000 - 1BFFFF D8000 - DFFFF SA28 1 1 1 0 0 X X X 64/32 1C0000 - 1CFFFF E0000 - E7FFF SA29 1 1 1 0 1 X X X 64/32 1D0000 - 1DFFFF E8000 - EFFFF SA30 1 1 1 1 0 X X X 64/32 1E0000 - 1EFFFF F0000 - F7FFF SA31 1 1 1 1 1 0 X X 32/16 1F0000 - 1F7FFF F8000 - FBFFF SA32 1 1 1 1 1 1 0 0 8/4 1F8000 - 1F9FFF FC000 - FCFFF SA3311111118/41FA000 - 1FBFFFFD000 - FDFFF SA34 1 1 1 1 1 1 1 X 16/8 1FC000 - 1FFFFF FE000 - FFFFFNote:Address range is A19 : A -1 in byte mode and A19 : A0 in word mode. See “Word/Byte Configuration” section.Table 3. A29L160A Bottom Boot Block Sector Address TableSector A19 A18 A17 A16 A15 A14A13A12Sector SizeAddress Range (in hexadecimal)(Kbytes/Kwords) Byte Mode (x8) Word Mode (x16) SA0 0 0 0 0 0 0 0 X 16/8 000000 - 003FFF 00000 - 01FFF SA1 0 0 0 0 0 0 1 0 8/4 004000 - 005FFF 02000 - 02FFF SA2 0 0 0 0 0 0 1 1 8/4 006000 - 007FFF 03000 - 03FFF SA3 0 0 0 0 0 1 X X 32/16 008000 - 00FFFF 04000 - 07FFF SA4 0 0 0 0 1 X X X 64/32 010000 - 01FFFF 08000 - 0FFFF SA5 0 0 0 1 0 X X X 64/32 020000 - 02FFFF 10000 - 17FFF SA6 0 0 0 1 1 X X X 64/32 030000 - 03FFFF 18000 - 1FFFF SA7 0 0 1 0 0 X X X 64/32 040000 - 04FFFF 20000 - 27FFF SA8 0 0 1 0 1 X X X 64/32 050000 - 05FFFF 28000 - 2FFFF SA9 0 0 1 1 0 X X X 64/32 060000 - 06FFFF 30000 - 37FFF SA10 0 0 1 1 1 X X X 64/32 070000 - 07FFFF 38000 - 3FFFF SA11 0 1 0 0 0 X X X 64/32 080000 - 08FFFF 40000 - 47FFF SA12 0 1 0 0 1 X X X 64/32 090000 - 09FFFF 48000 - 4FFFF SA13 0 1 0 1 0 X X X 64/32 0A0000 - 0AFFFF 50000 - 57FFF SA14 0 1 0 1 1 X X X 64/32 0B0000 - 0BFFFF 58000 - 5FFFF SA15 0 1 1 0 0 X X X 64/32 0C0000 - 0CFFFF 60000 - 67FFF SA16 0 1 1 0 1 X X X 64/32 0D0000 - 0DFFFF 68000 - 6FFFF SA17 0 1 1 1 0 X X X 64/32 0E0000 - 0EFFFF 70000 - 77FFF SA18 0 1 1 1 1 X X X 64/32 0F0000 - 0FFFFF 78000 - 7FFFF SA19 1 0 0 0 0 X X X 64/32 100000 - 10FFFF 80000 - 87FFF SA20 1 0 0 0 1 X X X 64/32 110000 - 11FFFF 88000 - 8FFFF SA21 1 0 0 1 0 X X X 64/32 120000 - 12FFFF 90000 - 97FFF SA22 1 0 0 1 1 X X X 64/32 130000 - 13FFFF 98000 - 9FFFF SA23 1 0 1 0 0 X X X 64/32 140000 - 14FFFF A0000 - A7FFF SA24 1 0 1 0 1 X X X 64/32 150000 - 15FFFF A8000 - AFFFF SA25 1 0 1 1 0 X X X 64/32 160000 - 16FFFF B0000 – B7FFF SA26 1 0 1 1 1 X X X 64/32 170000 - 17FFFF B8000 - BFFFF SA27 1 1 0 0 0 X X X 64/32 180000 - 18FFFF C0000 - C7FFF SA28 1 1 0 0 1 X X X 64/32 190000 - 19FFFF C8000 - CFFFF SA29 1 1 0 1 0 X X X 64/32 1A0000 - 1AFFFF D0000 - D7FFF SA30 1 1 0 1 1 X X X 64/32 1B0000 - 1BFFFF D8000 - DFFFF SA31 1 1 1 0 0 X X X 64/32 1C0000 - 1CFFFF E0000 - E7FFF SA32 1 1 1 0 1 X X X 64/32 1D0000 - 1DFFFF E8000 - EFFFF SA33 1 1 1 1 0 X X X 64/32 1E0000 - 1EFFFF F0000 - F7FFF SA34 1 1 1 1 1 X X X 64/32 1F0000 - 1FFFFF F8000 - FFFFF Note:Address range is A19 : A-1 in byte mode and A19 : A0 in word mode. See “Word/Byte Configuration” section.Autoselect ModeThe autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on I/O7 - I/O0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed in-system through the command register. When using programming equipment, the autoselect mode requires V ID (11.5V to 12.5 V) on address pin A9. Address pins A6, A1, and A0 must be as shown in Autoselect Codes (High Voltage Method) table. In addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits. Refer to the corresponding Sector Address Tables. The Command Definitions table shows the remaining address bits that are don't care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on I/O7 - I/O0.To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in the Command Definitions table. This method does not require V ID. See "Command Definitions" for details on using the autoselect mode.Table 4. A29L160A Autoselect Codes (High Voltage Method)L=Logic Low= V IL, H=Logic High=V IH, SA=Sector Address, X=Don’t Care.Note: The autoselect codes may also be accessed in-system via command sequences.Sector Protection/UnprotectionThe hardware sector protection feature disables both program and erase operations in any sector. The hardware sector unprotection feature re-enables both program and erase operations in previously protected sectors.It is possible to determine whether a sector is protected or unprotected. See “Autoselect Mode” for details.Sector protection / unprotection can be implemented via two methods. The primary method requires VID on the RESET pin only, and can be implemented either in-system or via programming equipment. Figure 2 shows the algorithm and the Sector Protect / Unprotect Timing Diagram illustrates the timing waveforms for this feature. This method uses standard microprocessor bus cycle timing. For sector unprotect, all unprotected sectors must first be protected prior to the first sector unprotect write cycle. The alternate method must be implemented using programming equipment. The procedure requires a high voltage (V ID) on address pin A9 and the control pins.The device is shipped with all sectors unprotected.It is possible to determine whether a sector is protected or unprotected. See "Autoselect Mode" for details.Hardware Data ProtectionThe requirement of command unlocking sequence for programming or erasing provides data protection against inadvertent writes (refer to the Command Definitions table). In addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during V CC power-up transitions, or from system noise. The device is powered up to read array data to avoid accidentally writing data to the array.Write Pulse "Glitch" ProtectionNoise pulses of less than 5ns (typical) on OE, CE or WEdo not initiate a write cycle.Logical InhibitWrite cycles are inhibited by holding any one of OE=V IL, CE = V IH or WE = V IH. To initiate a write cycle, CE and WE must be a logical zero while OE is a logical one.Power-Up Write InhibitIf WE = CE = V IL and OE = V IH during power up, the device does not accept commands on the rising edge of WE. The internal state machine is automatically reset to reading array data on the initial power-up. Temporary Sector UnprotectThis feature allows temporary unprotection of previous protected sectors to change data in-system. The Sector Unprotect mode is activated by setting the RESET pin to V ID. During this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. Once V ID is removed from the RESET pin, all the previously protected sectors are protected again. Figure 1 shows the algorithm, and the Temporary Sector Unprotect diagram shows the timing waveforms, for this feature.Notes:1. All protected sectors unprotected.2. All previously protected sectors are protected once again.Figure 1. Temporary Sector Unprotect OperationFigure 2. In-System Sector Protect/Unprotect AlgorithmsCommon Flash Memory Interface (CFI)The Common Flash Interface (CFI) specification outlines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. Software support can then be device-independent, JEDEC ID-independent, and forward- and backward-compatible for the specified flash device families. Flash vendors can standardize their existing interface for long-term compatibility.This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address 55h in word mode (or address AAh in byte mode), any time the device is ready to read array data. The system can read CFI information at the addresses given in Table 5-8. In word mode, the upper address bits (A7-MSB) must be all zeros. To terminate reading CFI data, the system must write the reset command.The system can also write the CFI query command when the device is in the autoselect mode. The device enters the CFI query mode, and the system can read CFI data at the addresses given in Table 5-8. The system must write the reset command to return the device to the autoselect mode.Table 5. CFI Query Identification StringAddresses (Word Mode)Addresses(Byte Mode)Data Description10h 11h 12h 20h22h24h0051h0052h0059hQuery Unique ASCII string “QRY”13h 14h 26h28h0002h0000hPrimary OEM Command Set15h 16h 2Ah2Ch0040h0000hAddress for Primary Extended Table17h 18h 2Eh30h0000h0000hAlternate OEM Command Set (00h = none exists)19h 1Ah 32h34h0000h0000hAddress for Alternate OEM Extended Table (00h = none exists) Table 6 System Interface StringAddresses (Word Mode)Addresses(Byte Mode)Data Description1Bh 36h 0027h VCC Min. (write/erase)I/O7- I/O4 : volt, I/O3- I/O0: 100 millivolt1Ch 38h 0036h VCC Max. (write/erase)I/O7- I/O4: volt, I/O3- I/O0: 100 millivolt1Dh 3Ah 0000h Vpp Min. voltage (00h = no Vpp pin present)1Eh 3Ch 0000h Vpp Max. voltage (00h = no Vpp pin present)1Fh 3Eh0004hTypical timeout per single byte/word write 2Nµs20h 40h0000hTypical timeout for Min. size buffer write 2Nµs (00h = not supported) 21h 42h 000Ah Typical timeout per individual block erase 2N ms22h 44h 0000h Typical timeout for full chip erase 2N ms (00h = not supported)23h 46h 0005h Max. timeout for byte/word write 2N times typical24h 48h 0000h Max. timeout for buffer write 2N times typical25h 4Ah 0004h Max. timeout per individual block erase 2N times typical26h 4Ch 0000h Max. timeout for full chip erase 2N times typical (00h = not supported)。

AS29LV400T-70TI中文资料

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[ . î &026 )ODVK ((3520)HDWXUHV•Organization: 512Kx8/256Kx16•Sector architecture-One 16K; two 8K; one 32K; and seven 64K byte sectors -One 8K; two 4K; one 16K; and seven 32K word sectors -Boot code sector architecture—T (top) or B (bottom)-Erase any combination of sectors or full chip•Single 2.7-3.6V power supply for read/write operations •Sector protection•High speed 70/80/90/120 ns address access time •Automated on-chip programming algorithm-Automatically programs/verifies data at specified address •Automated on-chip erase algorithm-Automatically preprograms/erases chip or specifiedsectors•Hardware RESET pin-Resets internal state machine to read mode •Low power consumption-200 nA typical automatic sleep mode current-200 nA typical standby current-10 mA typical read current•JEDEC standard software, packages and pinouts -48-pin TSOP-44-pin SO; availability TBD•Detection of program/erase cycle completion-DQ7 DATA polling-DQ6 toggle bit-DQ2 toggle bit-RY/BY output•Erase suspend/resume-Supports reading data from or programming data to a sector not being erased•Low V CC write lock-out below 1.5V•10 year data retention at 150C•100,000 write/erase cycle endurance/RJLF EORFN GLDJUDP6HOHFWLRQ JXLGH29LV400-7029LV400-8029LV400-9029LV400-120Unit Maximum access time t AA708090120ns Maximum chip enable access time t CE708090120ns Maximum output enable access time t OE30303550ns48-pin TSOP44-pin SO (availability TBD)A8A9A10A11A12A13A14A15A16BYTE V SS DQ15/A-1DQ7DQ14NC NC WE NCNC RY/BY NC DQ2DQ10DQ3DQ11V CC DQ4DQ12DQ5DQ6DQ131234567891011121314484746454443424140393837363515163433A17A7A6A5A4A3A2A1A0V SS DQ0DQ8DQ1DQ917181920212232313029282723242625AS29LV400RESETCE OE 567891011121314151617181920A14A15A16V SSDQ15/A-1DQ7DQ14DQ6DQ13DQ5DQ12DQ4V CCA6A5A4A3A2A1A0CE V SS OE DQ0DQ8DQ1DQ9DQ2DQ102122DQ3DQ11A10A11A12A132NC 3A174A71BY /RY 40393837363534333231302928272625242343424144WE A8A9RESET A S 29L V 400BYTE3LQ DVVLJQPHQWV)XQFWLRQDO GHVFULSWLRQThe AS29LV400 is an 4 megabit, 3.0 volt Flash memory organized as 512Kbyte of 8 bits/256Kbytes of 16 bits each. For flexible Erase and Program capability, the 4 megabits of data is divided into eleven sectors: one 16K, two 8K, one 32K, and seven 64k byte sectors; or one 8K, two 4K, one 16K, and seven 32K word sectors. The ×8 data appears on DQ0–DQ7; the ×16 data appears on DQ0–DQ15. The AS29LV400 is offered in JEDEC standard 48-pin TSOP and 44-pin SO. This device is designed to be programmed and erased with a single 3.0V V CC supply. The device can also be reprogrammed in standard EPROM programmers. The AS29LV400 offers access times of 70/80/90/120 ns, allowing 0-wait state operation of high speed microprocessors. To eliminate bus contention the device has separate chip enable (CE), write enable (WE), and output enable (OE) controls. Word mode (×16 output) is selected by BYTE = high. Byte mode (×8 output) is selected by BYTE = low.The AS29LV400 is fully compatible with the JEDEC single power supply Flash standard. The device uses standard microprocessor write timings to send Write commands to the register. An internal state-machine uses register contents to control the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the Programming and Erase operations. Data is read in the same manner as other Flash or EPROM devices. Use the Program command sequence to invoke the on-chip programming algorithm that automatically times the program pulse widths, and verifies proper cell margin. Use the Erase command sequence to invoke the automated on-chip erase algorithm that preprograms the sector when it is not already programmed before executing the erase operation. The Erase command also times the erase pulse widths and verifies the proper cell margins.Boot sector architecture enables the system to boot from either the top (AS29LV400T) or the bottom (AS29LV400B) sector. Sector erase architecture allows specified sectors of memory to be erased and reprogrammed without altering data in other sectors. A sector typically erases and verifies within 1.0 seconds. Hardware sector protection disables both the Program and the Erase operations in all, or any combination of the eleven sectors. The device provides true background erase with Erase Suspend, which puts erase operations on hold to either read data from, or program data to, a sector that is not being erased. The Chip Erase command will automatically erase all unprotected sectors.When shipped from the factory, AS29LV400 is fully erased (all bits = 1). The programming operation sets bits to 0. Data is programmed into the array one byte at a time in any sequence and across sector boundaries. A sector must be erased to change bits from 0 to 1. Erase returns all bytes in a sector to the erased state (all bits = 1). Each sector is erased individually with no effect on other sectors.The device features a single 3.0V power supply operation for Read, Write, and Erase functions. Internally generated and regulated voltages are provided for the Program and Erase operations. A low V CC detector automatically inhibits write operations during power transtitions. The RY/BY pin, DATA polling of DQ7, or toggle bit (DQ6) may be used to detect the end of the program or to erase operations. The device automatically resets to the Read mode after the Program or Erase operations are completed. DQ2 indicates which sectors are being erased.The AS29LV400 resists accidental erasure or spurious programming signals resulting from power transitions. The Control register architecture permits alteration of memory contents only when successful completion of specific command sequences has occured. During power up, the device is set to Read mode with all Program/Erase commands disabled if V CC is less than V LKO (lockout voltage). The command registers are not affected by noise pulses of less than 5 ns on OE, CE, or WE. To initiate Write commands, CE and WE must be a logical zero and OE a logical 1.When the device’s hardware RESET pin is driven low, any Program/Erase operation in progress is terminated and the internal state machine is reset to Read mode. If the RESET pin is tied to the system reset circuitry and a system reset occurs during an automated on-chip Program/Erase algorithm, the operating data in the address locations may become corrupted and require rewriting. Resetting the device enables the system’s microprocessor to read boot-up firmware from the Flash memory.The AS29LV400 uses Fowler-Nordheim tunnelling to electrically erase all bits within a sector simultaneously. Bytes are programmed one at a time using the EPROM programming mechanism of hot electron injection.2SHUDWLQJ PRGHVL = Low (<V IL ) = logic 0; H = High (>V IH ) = logic 1; V ID = 10.0 ± 1.0V; X = don’t care.In ×16 mode, BYTE = V IH . In ×8 mode, BYTE = V IL with DQ8-DQ14 in high Z and DQ15 = A-1.†Verification of sector protect/unprotect during A9 = V ID .ModeCEOEWEA0A1A6A9RESETDQ ID read MFR code L L H L L L V ID H Code ID read device code L L H H L L V ID H Code Read L L H A0A1A6A9H D OUT StandbyH X X X X X X H HighZ Output disable L H H X X X X H High Z WriteL H L A0A1A6A9H D IN Enable sector protect L V ID Pulse/L L H L V ID H X Sector unprotect L V ID Pulse/L L H H V ID H X Temporary sector unprotectX X X X X X X V ID X Verify sector protect †L L H L H L V ID H Code Verify sector unprotect †L L H L H H V ID H Code Hardware ResetXXXXXXXLHighZ0RGH GHILQLWLRQVItem DescriptionID MFR code, device code Selected by A9 = V ID(9.5V–10.5V), CE = OE = A1 = A6 = L, enabling outputs.When A0 is low (V IL) the output data = 52h, a unique Mfr. code for Alliance Semiconductor Flash products. When A0 is high (V IH), D OUT represents the device code for the AS29LV400.Read mode Selected with CE = OE = L, WE = H. Data is valid in t ACC time after addresses are stable, t CE after CE is low and t OE after OE is low.Standby Selected with CE = H. Part is powered down, and I CC reduced to <1.0 µA when CE = V CC ± 0.3V = RESET. If activated during an automated on-chip algorithm, the device completes the operation before entering standby.Output disable Part remains powered up; but outputs disabled with OE pulled high.Write Selected with CE = WE = L, OE = H. Accomplish all Flash erasure and programming through the command register. Contents of command register serve as inputs to the internal state machine. Address latching occurs on the falling edge of WE or CE, whichever occurs later. Data latching occurs on the rising edge WE or CE, whichever occurs first. Filters on WE prevent spurious noise events from appearing as write commands.Enable sector protect disable program and erase operations for specified sectors. For in-system sector protection, refer to Sector protect algorithm on page12.Sector unprotect protected prior to sector unprotection. For in-system sector unprotection, refer to Sector unprotect algorithm on page12.Verify sector protect/ unprotect Verifies write protection for sector. Sectors are protected from program/erase operations on commercial programming equipment. Determine if sector protection exists in a system by writing the ID read command sequence and reading location XXX02h, where address bits A12–17 select the defined sector addresses. A logical 1 on DQ0 indicates a protected sector; a logical 0 indicates an unprotected sector.Temporary sector unprotect Temporarily disables sector protection for in-system data changes to protected sectors. Apply +10V to RESET to activate temporary sector unprotect mode. During temporary sector unprotect mode, program protected sectors by selecting the appropriate sector address. All protected sectors revert to protected state on removal of +10V from RESET.RESET Resets the interal state machine to read mode. If device is programming or erasing when RESET = L, data may be corrupted.power downHold RESET low to enter deep power down mode (<1 µA). Recovery time to start of first read cycle is 50ns.Automatic sleep mode Enabled automatically when addresses remain stable for 300ns. Typical current draw is 1 µA. Existing data is available to the system during this mode. If an address is changed, automatic sleep mode is disabled and new data is returned within standard access times.)OH[LEOH VHFWRU DUFKLWHFWXUHIn word mode, there are one 8K word, two 4K word, one 16K word, and seven 32K word sectors. Address range is A17–A-1 if BYTE = V IL ; address range isA17–A0 if BYTE = V IH .,' 6HFWRU DGGUHVV WDEOH5($' FRGHVKey: L =Low (<V IL ); H = High (>V IH ); X =Don’t careSector Bottom boot sector architecture (AS29LV400B)Top boot sector architecture (AS29LV400T)×8×16Size (Kbytes)×8×16Size (Kbytes)00000h–03FFFh 00000h–01FFFh 1600000h–0FFFFh 00000h–07FFFh 6404000h–05FFFh 02000h–02FFFh 810000h–1FFFFh 08000h–0FFFFh 64206000h–07FFFh 03000h–03FFFh 820000h–2FFFFh 10000h–17FFFh 64308000h–0FFFFh 04000h–07FFFh 3230000h–3FFFFh 18000h–1FFFFh 6410000h–1FFFFh 08000h–0FFFFh 6440000h–4FFFFh 20000h–27FFFh 6420000h–2FFFFh 10000h–17FFFh 6450000h–5FFFFh 28000h–2FFFFh 64630000h–3FFFFh 18000h–1FFFFh 6460000h–6FFFFh 30000h–37FFFh 64740000h–4FFFFh 20000h–27FFFh 6470000h–77FFFh 38000h–3BFFFh 3250000h–5FFFFh 28000h–2FFFFh 6478000h–79FFFh 3C000h–3CFFFh 860000h–6FFFFh 30000h–37FFFh 647A000h–7BFFFh 3D000h–3DFFFh 81070000h–7FFFFh 38000h–3FFFFh 647C000h–7FFFFh 3E000h–3FFFFh 16Sector Bottom boot sector address(AS29LV400B)Top boot sector address(AS29LV400T)A17A16A15A14A13A12A17A16A15A14A13A12000000X 000X X X 1000010001X X X 2000011010X X X 30001X X 011X X X 4001X X X 100X X X 5010X X X 101X X X 6011X X X 110X X X 7100X X X 1110X X 8101X X X 1111009110X X X 11110110111X X X11111XModeA17–A12A6A1A0CodeMFR code (Alliance Semiconductor)X L L L 52h Device code×8 T bootX L L H B9h ×8 B boot X L L H BAh ×16 T boot X L L H 22B9h ×16 B bootX L L H 22BAhSector protectionSector addressLHL01h protected 00h unprotected&RPPDQG IRUPDW1Bus operations defined in "Mode definitions," on page 3.2Reading from and programming to non-erasing sectors allowed in Erase Suspend mode.3Address bits A11-A17 = X = Don’t Care for all address commands except where Program Address and Sector Address are required.4Data bits DQ15-DQ8 are don’t care for unlock and command cycles.5The Unlock Bypass command must be initiated before the Unlock Bypass Program command.6The Unlock Bypass Reset command returns the device to reading array data when it is in the unlock bypass mode.Command sequenceRequired bus writecycles 1st bus cycle 2nd bus cycle 3rd bus cycle 4th bus cycle 5th bus cycle 6th bus cycleAddress Data Address DataAddress DataAddressDataAddress Data Address DataReset/Read 1XXXh F0h Read Address Read Data Reset/Read×163555h AAh2AAh 55h555h F0h Read Address Read Data ×8AAAh 555h AAAh AutoselectID Read×163555hAAh2AAh55h 555h90h01h Device code 22B9h (T) 22BAh (B)×8AAAh 555h AAAh 02h Device code B9h(T) BAh(B)×16555hAAh2AAh 55h555h 90h00h MFR code 0052h ×8AAAh 555h AAAh 52h×16555hAAh 2AAh55h555h90hXXX02h Sector protection 0001h = protected 0000h = unprotected ×8AAAh 555h AAAh XXX04h Sector protection 0001h=protected 0000h=unprotected Program ×164555h AAh 2AAh 55h 555h A0h Program AddressProgram Data×8AAAh 555h AAAh Unlock bypass ×163555AAh 2AA 55h 55520h×8AAA 555AAAUnlock bypass program 2XXX A0h Program address Program data Unlock bypass reset 2XXX 90h XXX 00h Chip Erase ×166555h AAh 2AAh 55h 555h 80h 555h AAh 2AAh 55h 555h 10h ×8AAAh 555h AAAh AAAh 555h AAAh Sector Erase×166555h AAh 2AAh 55h555h 80h555h AAh2AAh 55hSector Address30h×8AAAh 555hAAAhAAAh555hSector Erase Suspend 1XXXh B0h Sector Erase Resume1XXXh30h&RPPDQG GHILQLWLRQVItem DescriptionReset/Read Initiate read or reset operations by writing the Read/Reset command sequence into the command register. This allows the microprocessor to retrieve data from the memory. Device remains in read mode until command register contents are altered.Device automatically powers up in read/reset state. This feature allows only reads, therefore ensuring no spurious memory content alterations during power up.ID Read AS29LV400 provides manufacturer and device codes in two ways. External PROM programmers typically access the device codes by driving +10V on A9. AS29LV400 also contains an ID Read command to read the device code with only +3V, since multiplexing +10V on address lines is generally undesirable.Initiate device ID read by writing the ID Read command sequence into the command register. Follow with a read sequence from address XXX00h to return MFR code. Follow ID Read command sequence with a read sequence from address XXX01h to return device code.To verify write protect status on sectors, read address XXX02h. Sector addresses A17–A12 produce a 1 on DQ0 for protected sector and a 0 for unprotected sector.Exit from ID read mode with Read/Reset command sequence.Hardware Reset Holding RESET low for 500 ns resets the device, terminating any operation in progress; data handled in the operation is corrupted. The internal state machine resets 20 µs after RESET is driven low. RY/BY remains low until internal state machine resets. After RESET is set high, there is a delay of 50 ns for the device to permit read operations.Byte/word Programming Programming the AS29LV400 is a four bus cycle operation performed on a byte-by-byte or word-by-word basis. Two unlock write cycles precede the Program Setup command and program data write cycle. Upon execution of the program command, no additional CPU controls or timings are necessary. Addresses are latched on the falling edge of CE or WE, whichever is last; data is latched on the rising edge of CE or WE, whichever is first. The AS29LV400’s automated on-chip program algorithm provides adequate internally-generated programming pulses and verifies the programmed cell margin.Check programming status by sampling data on the RY/BY pin, or either the DATA polling (DQ7) or toggle bit (DQ6) at the program address location. The programming operation is complete if DQ7 returns equivalent data, if DQ6 = no toggle, or if RY/BY pin = high.The AS29LV400 ignores commands written during programming. A hardware reset occurring during programming may corrupt the data at the programmed location.AS29LV400 allows programming in any sequence, across any sector boundary. Changing data from 0 to 1 requires an erase operation. Attempting to program data 0 to 1 results in either DQ5 = 1 (exceeded programming time limits); reading this data after a read/reset operation returns a 0. When programming time limit is exceeded, DQ5 reads high, and DQ6 continues to toggle. In this state, a Reset command returns the device to read mode.Unlock Bypass Command Sequence The unlock bypass feature increases the speed at which the system programs bytes or words to the device because it bypasses the first two unlock cycles of the standard program command sequence. To initiate the unlock bypass command sequence, two unlock cycles must be written, then followed by a third cycle which has the unlock bypass command, 20h.The device then begins the unlock bypass mode. In order to program in this mode, a two cycle unlock bypass program sequence is required. The first cycle has the unlock bypass program command, A0h. It is followed by a second cycle which has the program address and data. To program additional data, the same sequence must be followed.The unlock bypass mode has two valid commands, the Unlock Bypass Program command and the Unlock Bypass Reset command. The only way the system can exit the unlock bypass mode is by issuing the unlock bypass reset command sequence. This sequence involves two cycles. The first cycle contains the data, 90h. The second cycle contains the data 00h. Addresses are don’t care for both cycles. The device then returns to reading array data.Chip Erase Chip erase requires six bus cycles: two unlock write cycles; a setup command, two additional unlock write cycles; and finally the Chip Erase command.Chip erase does not require logical 0s to be written prior to erasure. When the automated on-chip erase algorithm is invoked with the Chip Erase command sequence, AS29LV400 automatically programs and verifies the entire memory array for an all-zero pattern prior to erase. The 29LV400 returns to read mode upon completion of chip erase unless DQ5 is set high as a result of exceeding time limit.Sector Erase Sector erase requires six bus cycles: two unlock write cycles, a setup command, two additional unlock write cycles, and finally the Sector Erase command. Identify the sector to be erased by addressing any location in the sector. The address is latched on the falling edge of WE; the command, 30h is latched on the rising edge of WE. The sector erase operation begins after a sector erase time-out.To erase multiple sectors, write the Sector Erase command to each of the addresses of sectors to erase after following the six bus cycle operation above. Timing between writes of additional sectors must be less than the erase time-out period, or the AS29LV400 ignores the command and erasure begins. During the time-out period any falling edge of WE resets the time-out. Any command (other than Sector Erase or Erase Suspend) during time-out period resets the AS29LV400 to read mode, and the device ignores the sector erase command string. Erase such ignored sectors by restarting the Sector Erase command on the ignored sectors.The entire array need not be written with 0s prior to erasure. AS29LV400 writes 0s to the entire sector prior to electrical erase; writing of 0s affects only selected sectors, leaving non-selected sectors unaffected. AS29LV400 requires no CPU control or timing signals during sector erase operations.Automatic sector erase begins after sector erase time-out from the last rising edge of WE from the sector erase command stream and ends when the DATA polling (DQ7) is logical 1. DATA polling address must be performed on addresses that fall within the sectors being erased. AS29LV400 returns to read mode after sector erase unless DQ5 is set high by exceeding the time limit.Item DescriptionErase Suspend Erase Suspend allows interruption of sector erase operations to read data from or program data to a sector not being erased. Erase suspend applies only during sector erase operations, including the time-out period. Writing an Erase Suspend command during sector erase time-out results in immediate termination of the time-out period and suspension of erase operation.AS29LV400 ignores any commands during erase suspend other than Read/Reset, Program or Erase Resume commands. Writing the Erase Resume Command continues erase operations. Addresses are Don’t Care when writing Erase Suspend or Erase Resume commands.AS29LV400 takes 0.2–15 µs to suspend erase operations after receiving Erase Suspend command. To determine completion of erase suspend, either check DQ6 after selecting an address of a sector not being erased, or poll RY/BY. Check DQ2 in conjunction with DQ6 to determine if a sector is being erased. AS29LV400 ignores redundant writes of Erase Suspend.While in erase-suspend mode, AS29LV400 allows reading data (erase-suspend-read mode) from or programming data (erase-suspend-program mode) to any sector not undergoing sector erase; these operations are treated as standard read or standard programming mode. AS29LV400 defaults to erase-suspend-read mode while an erase operation has been suspended.Write the Resume command 30h to continue operation of sector erase. AS29LV400 ignores redundant writes of the Resume command. AS29LV400 permits multiple suspend/resume operations during sector erase.Sector Protect When attempting to write to a protected sector, DATA polling and Toggle Bit 1 (DQ6) are activated for about <1 µs. When attempting to erase a protected sector, DATA polling andToggle Bit 1 (DQ6) are activated for about <5 µs. In both cases, the device returns to read mode without altering the specified sectors.Ready/Busy RY/BY indicates whether an automated on-chip algorithm is in progress (RY/BY = low) or completed (RY/BY = high). The device does not accept Program/Erase commands whenRY/BY = low. RY/BY= high when device is in erase suspend mode. RY/BY = high when device exceeds time limit, indicating that a program or erase operation has failed. RY/BY is an open drain output, enabling multiple RY/BY pins to be tied in parallel with a pull up resistor to V CC.Item Description6HFWRU SURWHFW DOJRULWKP 6HFWRU XQSURWHFW DOJRULWKPSTART PLSCNT = 1RESET# = V ID Wait 1 µsFirst Write Cycle=60h?Temporary sector unprotect modeNoSet up sector Sector protect:addresswrite 60h to sector address with A6=0, A1=1,A0=0Wait 150 µs Verify sector protect; write 40h to sector address with A6=0,A1=1, A0=0Read from sector address with A6=0,A1=1, A0=0Data=01h?Protect sector?PLSCNT=25?NoIncrement PLSCNTNoDevice failedYesYes YesNoSTART PLSCNT = 1RESET# = V ID Wait 1 µsFirst Write Cycle=60h?Temporary sector unprotect modeNoYesAll sectors protected?Set up first Sector unprotect:sector address write 60h to sector address with A6=1, A1=1,A0=0Wait 15 ms Verify sector unprotect; write 40h to sector address with A6=1,A1=1, A0=0Read from sector address with A6=1,A1=1, A0=0Data=00h?Last sector verified?NoYesYesRemove V ID from RESET#Write reset command Sector unprotectcompleteRemove V ID from RESET#Write reset command Sector protect completePLSCNT Increment PLSCNTNoDevice failedYes=1000?Set up next sector addressNoProtect all sectors:The shaded portion of the sector protct initiated for all unprotected sectors before calling the sector unprotectNoYesYesalgorithm must be another6WDWXV RSHUDWLRQV:ULWH RSHUDWLRQ VWDWXVDQ2 toggles when an erase-suspended sector is read repeatedly . DQ6 toggles when any address is read repeatedly .DQ2 = 1 if byte address being programmed is read during erase-suspend program mode.†DQ2 toggles when the read address applied points to a sector which is undergoing erase, suspended erase, or a failure to erase.DATA polling (DQ7)Only active during automated on-chip algorithms or sector erase time outs. DQ7 reflectscomplement of data last written when read during the automated on-chip program algorithm (0 during erase algorithm); reflects true data when read after completion of an automated on-chip program algorithm (1 after completion of erase agorithm).Toggle bit 1 (DQ6)Active during automated on-chip algorithms or sector erase time outs. DQ6 toggles when CE or OE toggles, or an Erase Resume command is invoked. DQ6 is valid after the rising edge of the fourth pulse of WE during programming; after the rising edge of the sixth WE pulse during chip erase; after the last rising edge of the sector erase WE pulse for sector erase. For protected sectors, DQ6 toggles for <1 µs during program mode writes, and <5 µs during erase (if all selected sectors are protected).Exceeding time limit (DQ5)Indicates unsuccessful completion of program/erase operation (DQ5 = 1). DATA polling remains active. If DQ5 = 1 during chip erase, all or some sectors are defective; during byte programming or sector erase, the sector is defective (in this case, reset the device and execute a program or erase command sequence to continue working with functional sectors). Attempting to program 0 to 1 will set DQ5 = 1.Sector erase timer (DQ3)Checks whether sector erase timer window is open. If DQ3 = 1, erase is in progress; no commands will be accepted. If DQ3 = 0, the device will accept sector erase commands. Check DQ3 before and after each Sector Erase command to verify that the command was accepted.Toggle bit 2 (DQ2)During sector erase, DQ2 toggles with OE or CE only during an attempt to read a sector being erased. During chip erase, DQ2 toggles with OE or CE for all addresses. If DQ5 = 1, DQ2 toggles only at sector addresses where failure occurred, and will not toggle at other sector addresses. Use DQ2 in conjunction with DQ6 to determine whether device is in auto erase or erase suspend mode.StatusDQ7DQ6DQ5DQ3DQ2RY/BY Standard modeAuto programmingDQ7Toggle 0N/A No toggle 0Program/erase in auto erase 0Toggle 01Toggle †0Erase suspend modeRead erasing sector 1No toggle 0N/A Toggle 1Read non-erasing sector Data Data Data Data Data 1Program in erase suspend DQ7Toggle 0N/A Toggle †0Exceeded time limitsAuto programming (byte)DQ7Toggle 1N/A No toggle 1Program/erase in auto erase 0Toggle 1N/A Toggle †1Program in erase suspend (non-erase suspended sector)DQ7Toggle1N/ANo toggle1$XWRPDWHG RQ FKLS SURJUDPPLQJ DOJRULWKP$XWRPDWHG RQ FKLS HUDVH DOJRULWKP†The system software should check the status of DQ3 prior to and following eachsubsequent sector erase command to ensure command completion. The device may not have accepted the command if DQ3 is high on second status check.START555h/AAh2AAh/55h555h/A0hProgram address/program dataProgram command sequence ×16 mode (address/data):Write program command sequence(see below)DATA polling or toggle bit successfully completedLast address?Programming completedYESIncrement addressNO555h/AAh2AAh/55h555h/80herase command sequence 555h/AAh2AAh/55hSector address/30hErase complet e×16 mode (address/data):DATA polling or toggle bit successfully completedWrite erase command sequence(see below)555h/AAh2AAh/55h 555h/80h Chip erase command sequence 555h/AAh 2AAh/55h 555h/10h×16 mode (address/data):Individual sector/multiple sectorSector address/30hSector address/30hoptional sector erase commandsSTART。

唯特利（Victaulic）HDPE管道连接卡箍905型说明书

如需產品安裝、維護或支援資訊，請參閱本文件末的資訊。

1.0 產品描述供貨尺寸• 2 – 14 英吋 IPS 管道尺寸• 63 – 355 公釐 ISO 管道尺寸管道材料• 符合 ASTM D3035 和 ASTM F714 或 ISO 4427-2 (SDR 7 – 26) 的 HDPE 管道• PE-RT 管道符合 ASTM D3035、單元分類 PE445574C、ASTM F2619 和 ASTM F714 (SDR 7 – 26) 標準• 如需有關交聯聚乙烯 (PE-Xa) 管道的資訊，請參閱技術文件 36.01• 如需其他管道材料，請與 Victaulic（唯特利）聯絡最大工作壓力• 達到或超過 HDPE 或 PE-RT 管道的額定壓力工作溫度• 視管道製造商額定值和密封墊圈選用而定• 有關密封墊圈性能選項，請參閱第 3.0 節• 有關管道材料性能極限，請諮詢管道製造商功能• 連接平端HDPE管道• 採用 Installation-Ready™專利技術，無零散部件管道製備• 適用於平端 HDPE 或 PE-RT 管道註• 本文檔中對 HDPE 的所有引用都包括 PE-RT2.0 認證/列名註• 如需詳細資訊，請參見技術文件 10.01：Victaulic（唯特利）消防認證參考指南。

• 請參閱技術文件 02.06：Victaulic（唯特利）飲用水產品認證 – ANSI/NSF 61 和 ANSI/NSF 372。

• WaterMark™認證只適用於帶 “E” 級三元乙丙橡膠 (EPDM) 密封墊圈的熔融粘結環氧樹脂塗層卡箍。

有關進一步詳細資訊，請與 Victaulic（唯特利）聯絡。

用於 HDPE 管道的 Victaulic®（唯特利™）平端卡箍905 型19.07-TCH3.0 規格 – 材料殼體：符合 ASTM A536之65-45-12 等級要求的球墨鑄鐵。

殼體塗層：（請指明選項）ANSI 尺寸和 355 毫米 ISO 為橙色瓷漆。

S29C51004T70P中文资料

Featuress 512Kx8-bit Organizations Address Access Time: 70, 90, 120 ns s Single 5V ± 10% Power Supply s Sector Erase Mode Operation s 16KB Boot Block (lockable)s1K bytes per Sector, 512 Sectors–Sector-Erase Cycle Time: 10ms (Max)–Byte-Write Cycle Time: 35 µ s (Max) s Minimum 10,000 Erase-Program Cycles sLow power dissipation–Active Read Current: 20mA (Typ)–Active Program Current: 30mA (Typ)–Standby Current: 100 µ A (Max) s Hardware Data Protections Low V CC Program Inhibit Below 3.5VsSelf-timed write/erase operations with end-of-cy-cle detection –DATA Polling –Toggle Bits CMOS and TTL Interface sAvailable in one versions–S29C51004T (Top Boot Block)s Packages:–32-pin Plastic DIP –32-pin TSOP-I –32-pin PLCCDescriptionThe S29C51004T/S29C51004B is a high speed 524,288 x 8 bit CMOS flash memory. Writing or erasing the device is done with a single 5 Volt power supply. The device has separate chip enable CE, write enable WE, and output enable OE controls to eliminate bus contention.The S29C51004T/S29C51004B offers a combi-nation of: Boot Block with Sector Erase/Write Mode. The end of write/erase cycle is detected by DATA Polling of I/O 7 or by the Toggle Bit I/O 6 .TheS29C51004T/S29C51004B features a sector erase operation which allows each sector to be erased and reprogrammed without affecting data stored in other sectors. The device also supports full chip erase.Boot block architecture enables the device to boot from a protected sector located either at the top (S29C51004T) or the bottom (S29C51004B).All inputs and outputs are CMOS and TTL compatible.The S29C51004T/S29C51004B is ideal for applications that require updatable code and data storage.SyncMOS Technologies Inc. S 29C51004T/S 29C51004B4 MEGABIT (524,288 x 8 BIT)5 VOLT CMOS FLASH MEMORY元器件交易网Pin ConfigurationsPin NamesA 0 –A 18 Address Inputs I/O 0 –I/O 7Data Input/Output CE Chip Enable OE Output Enable WE Write EnableV CC5V ±10% Power SupplyGND Ground NCNo ConnectSyncMOS Technologies Inc. S 29C51004T/S 29C51004B4 MEGABIT (524,288 x 8 BIT)5 VOLT CMOS FLASH MEMORY元器件交易网Functional Block Diagram Capacitance (1,2)NOTE:1. Capacitance is sampled and not 100% tested.2. T A = 25 ° C, V CC = 5V ± 10%, f = 1 MHz.Latch Up Characteristics (1)NOTE:1. Includes all pins except V CC . Test conditions: V CC = 5V, one pin at a time.AC Test LoadSymbol Parameter Test Setup Typ. Max. UnitsC IN Input Capacitance V IN = 0 6 8 pF C OUT Output Capacitance V OUT = 0 8 12 pF C IN2Control Pin Capacitance V IN = 0 8 10 pFParameterMin. Max. UnitInput Voltage with Respect to GND on A 9 , OE-1 +13 VInput Voltage with Respect to GND on I/O, address or control pins -1 V CC + 1 V V CCCurrent -100 +100 mASyncMOS Technologies Inc. S 29C51004T/S 29C51004B4 MEGABIT (524,288 x 8 BIT)5 VOLT CMOS FLASH MEMORY元器件交易网Absolute Maximum Ratings (1)NOTE:1. Stress greater than those listed unders “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stressrating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.2. No more than one output maybe shorted at a time and not exceeding one second long.DC Electrical Characteristics(over the commercial operating range)Symbol Parameter Commercial Industrial UnitV IN Input Voltage (input or I/O pins) -2 to +7 -2 to +7 V V IN Input Voltage (A 9 pin, OE) -2 to +13 -2 to +13 V V CC Power Supply Voltage -0.5 to +5.5 -0.5 to +5.5 V T STG Storage Temerpature (Plastic) -65 to +125 -65 to +150 ° C T OPR Operating Temperature 0 to +70 -40 to + 85 ° CI OUTShort Circuit Current (2)200 (Max.) 200 (Max.) mAParameterName Parameter Test Conditions Min. Max. UnitV IL Input LOW Voltage V CC = V CC Min. — 0.8 V V IH Input HIGH Voltage V CC = V CC Max. 2 — V I IL Input Leakage Current V IN = GND to V CC , V CC = V CC Max. — ± 1 µ A I OL Output Leakage Current V OUT = GND to V CC , V CC = V CC Max. —± 10µ AV OL Output LOW Voltage V CC = V CC Min., I OL = 2.1mA — 0.4 V V OH Output HIGH Voltage V CC = V CC Min, I OH = -400 µ A 2.4 — V I CC1Read Current CE = OE = V IL , WE = V IH , all I/Os open,Address input = V IL /V IH , at f = 1/t RC Min.,V CC = V CC Max.— 30 mAI CC2 Write Current CE = WE = VIL, OE = V IH , V CC = V CC Max. — 40 mA I SBTTL Standby Current CE = OE = WE = V IH , V CC = VCC Max. — 1 mAI SB1 CMOS Standby Current CE = OE = WE = V CC – 0.3V, V CC = V CC Max. — 100 µA V H Device ID Voltage for A 9CE = OE = V IL , WE = V IH11.5 12.5 VI HDevice ID Current for A 9CE = OE = V IL , WE = V IH , A9 = V H Max. — 50 µASyncMOS Technologies Inc. S 29C51004T/S 29C51004B4 MEGABIT (524,288 x 8 BIT)5 VOLT CMOS FLASH MEMORY元器件交易网AC Electrical CharacteristicsRead CycleProgram (Erase/Program) CycleParameterName Parameter-70 -90 -12UnitMin. Max. Min. Max. Min. Max.t RC Read Cycle Time 70 — 90 — 120 — ns t AA Address Access Time — 70 — 90 — 120 ns t ACS Chip Enable Access Time — 70 — 90 — 120 ns t OE Output Enable Access Time — 35 — 45 — 60 ns t CLZ CE Low to Output Active 0 — 0 — 0 — ns t OLZ OE Low to Output Active 0 — 0 — 0 — ns t DF OE or CE High to Output in High Z 0 30 0 40 0 50 ns t OHOutput Hold from Address Change 0 — 0 — 0 — nsParameterName Parameter-70 -90 -12UnitMin. Typ. Max. Min. Typ. Max. Min. Typ. Max.t WC Write Cycle Time 70 — — 90 — — 120 — — ns t AS Address Setup Time 0 — — 0 — — 0 — — ns t AH Address Hold Time 45 — — 45 — — 50 — — ns t CS CE Setup Time 0 — — 0 — — 0 — — ns t CH CE Hold Time 0 — — 0 — — 0 — — ns t OES OE Setup Time 0 — — 0 — — 0 — — ns t OEH OE High Hold Time 0 — — 0 — — 0 — — ns t WP WE Pulse Width 35 — — 45 — — 50 — — ns t WPH WE Pulse Width High 20 — — 30 — — 35 — — ns t DS Data Setup Time 30 — — 30 — — 30 — — ns t DHData Hold Time 0 — — 0 — — 0 — — nst WHWH1 Programming Cycle — — 35 — — 35 — — 35 µ s t WHWH2Sector Erase Cycle — — 10 — — 10 — — 10 mst WHWH3 Chip Erase Cycle — — 3.0 — — 3.0— — 3.0 sec4 MEGABIT (524,288 x 8 BIT)5 VOLT CMOS FLASH MEMORYWaveforms of Read CycleWaveforms of WE Controlled-Program CycleNOTES:1. I/O 7: The output is the complement of the data written to the device.2. PA: The address of the memory location to be programmed.3. PD: The data at the byte address to be programmed.5 VOLT CMOS FLASH MEMORYWaveforms of CE Controlled-Program CycleWaveforms of Erase Cycle (1)NOTES:1. PA: The address of the memory location to be programmed.2. PD: The data at the byte address to be programmed.3. SA: The sector address for Sector Erase.5 VOLT CMOS FLASH MEMORYWaveforms of DATA Polling CycleWaveforms of Toggle Bit Cycle5 VOLT CMOS FLASH MEMORYFunctional DescriptionThe S29C51004T/S29C51004B consists of 512equally-sized sectors of 1K bytes each. The 16 KB lockable Boot Block is intended for storage of the system BIOS boot code. The boot code is the first piece of code executed each time the system is powered on or rebooted.The S29C51004 is available in two versions: the S29C51004T with the Boot Block address starting from 7C000H to 7FFFFH, and the S29C51004B with the Boot Block address starting from 00000H to 3FFFFH.Read CycleA read cycle is performed by holding both CE and OE signals LOW. Data Out becomes valid only when these conditions are met. During a read cycle WE must be HIGH prior to CE and OE going LOW.WE must remain HIGH during the read operation for the read to complete (see Table 1).Output DisableReturning OE or CE HIGH, whichever occurs first will terminate the read operation and place the l/O pins in the HIGH-Z state.StandbyThe device will enter standby mode when the CE signal is HIGH. The l/O pins are placed in the HIGH-Z, independent of the OE input state.Byte Write CycleThe S29C51004T/S29C51004B is programmed on a byte-by-byte basis. The byte write operation is initiated by using a specific four-bus-cycle sequence: two unlock program cycles, a program setup command and program data program cycles (see Table 2).During the byte write cycle, addresses are latched on the falling edge of either CE or WE,whichever is last. Data is latched on the rising edge of CE or WE, whichever is first. The byte write cycle can be CE controlled or WE controlled.Sector Erase CycleThe S29C51004T/S29C51004B features a sector erase operation which allows each sector to be erased and reprogrammed without affecting data stored in other sectors. Sector erase operation is initiated by using a specific six-bus-cycle sequence: Two unlock program cycles, a setup command, two additional unlock program cycles,and the sector erase command (see Table 2). A sector must be first erased before it can be re-written. While in the internal erase mode, the device ignores any program attempt into the device. The internal erase completion can be determined via DATA polling or toggle bit status.The S29C51004T/S29C51004B is shipped fully erased (all bits = 1).Table 1. Operation Modes DecodingNOTES:1. X = Don’t Care, V IH = HIGH, V IL = LOW, V H = 12.5V Max.2. PD: The data at the byte address to be programmed.Decoding Mode CEOE WEA 0A 1A 9I/ORead V IL V IL V IH A 0A 1A 9READ Byte Write V IL V IH V IL A 0A 1A 9PD Standby V IH X X X X X HIGH-Z Autoselect Device ID V IL V IL V IH V IH V IL V H CODE Autoselect Manufacture ID V IL V IL V IH V IL V IL V H CODE Enabling Boot Block Protection Lock V IL V H V IL X X V H X Disabling Boot Block Protection Lock V H V H V IL X X V H X Output Disable V ILV IH V IH X X X HIGH-ZSyncMOS Technologies Inc. S 29C51004T/S 29C51004B4 MEGABIT (524,288 x 8 BIT)5 VOLT CMOS FLASH MEMORY元器件交易网Table 2. Command CodesNOTES:1. RA: Read Address2. RD: Read Data3. PA: The address of the memory location to be programmed.4. PD: The data at the byte address to be programmed.5. SA(5): Sector AddressCommand SequenceFirst BusProgram CycleSecond Bus Program CycleThird BusProgram CycleFourth Bus Program CycleFifth BusProgram CycleSix BusProgram CycleAddress Data Address Data Address Data Address Data Address Data Address DataRead XXXXH F0HRead 5555H AAH 2AAAH 55H 5555H F0H RA(1) RD(2)Autoselect Mode 5555H AAH 2AAAH 55H 5555H 90HSee table 3 for detail.Byte Program5555H AAH 2AAAH 55H 5555H A0H PA PD(4)Chip Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H Sector Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H SA(5) 30H Chip Erase CycleThe S29C51004T/S29C51004B features a chip-erase operation. The chip erase operation is initiated by using a specific six-bus-cycle sequence: two unlock program cycles, a setup command, two additional unlock program cycles,and the chip erase command (see Table 2).The automatic erase begins on the rising edge of the last WE or CE pulse in the command sequence and terminates when the data on DQ7 is “1”.Program Cycle Status DetectionThere are two methods for determining the state of the S29C51004T/S29C51004B during a program (erase/write) cycle: DATA Polling (I/O 7)and Toggle Bit (I/O 6).DATA Polling (I/O 7)The S29C51004T/S29C51004B features DATA polling to indicate the end of a program cycle.When the device is in the program cycle, any attempt to read the device will received the complement of the loaded data on I/O 7. Once the program cycle is completed, I/O 7 will show true data, and the device is then ready for the next cycle.Toggle Bit (I/O 6)The S29C51004T/S29C51004B also features another method for determining the end of a program cycle. When the device is in the program cycle, any attempt to read the device will result in l/O 6 toggling between 1 and 0. Once the program is completed, the toggling will stop. The device is then ready for the next operation. Examining the toggle bit may begin at any time during a program cycle.Boot Block Protection Enabling/DisablingThe S29C51004T/S29C51004B features hardware Boot Block Protection. The boot block sector protection is enabled when high voltage (12.5V) is applied to OE and A9 pins with CE pin LOW and WE pin LOW. The sector protection is disabled when high voltage is applied to OE, CE and A9 pins with WE pin LOW. Other pins can be HIGH or LOW. This is shown in table 1.Autoselect ModeThe S29C51004T/S29C51004B features an Autoselect mode to identify boot block locking status, device ID and manufacturer ID .Entering Autoselect mode is accomplished by applying a high voltage (VH) to the A9 Pin, or through a sequence of commands (as shown in table 2). Device will exit this mode once high voltage on A9 is removed or another command is loaded into the device.SyncMOS Technologies Inc. S 29C51004T/S 29C51004B4 MEGABIT (524,288 x 8 BIT)5 VOLT CMOS FLASH MEMORY元器件交易网Boot Block Protection StatusIn Autoselect mode, performing a read at address location 3CXX2H (S29C51004T) or 0CXX2H (S29C51004B) will indicate boot bloc protection status. If the data is 01H, the boot block is protected. If the data is 00H, the boot block is unprotected. This is also shown is table 3.Device IDIn Autoselect mode, performing a read at address XXX1H will determine whether the device is a Top Boot Block device or a Bottom Boot Block device. If the data is 03H, the device is a Top Boot Block. If the data is A3H, the device is a Bottom Boot Block device (see Table 3).Manufacturer IDIn Autoselect mode, performing a read at address XXXX0H will determine the manufacturer ID.40H is the manufacturer code for SyncMOS Flash.Hardware Data ProtectionV CC Detection: the program operation is inhibited when VCC is less than 3.5V.Noise Protection: a CE or WE pulse of less than 5ns will not initiate a program cycle.Program Inhibit: holding any one of OE LOW, CE HIGH or WE HIGH inhibits a program cycle.Table 3. Autoselect DecodingNOTE:1. X = Don’t Care, V IH = HIGH, V IL = LOW.Decoding Mode Boot BlockAddressData I/O 0–I/O 7A 0A 1A 2–A 13A 14–A 17Boot Block Protection Top V ILV IH X V IH 01H: protected Bottom V ILV IH X V IL00H: unprotectedDevice ID Top V IHV ILX X 03HBottom A3HManufacture ID V IL V ILX X 40H5 VOLT CMOS FLASH MEMORYByte Program AlgorithmChip/Sector Erase Algorithm5 VOLT CMOS FLASH MEMORYDATA Polling AlgorithmToggle Bit AlgorithmNOTE:1. PBA: The byte address to be programmed.5 VOLT CMOS FLASH MEMORYPackage Diagrams32-pin Plastic DIP32-pin PLCC4 MEGABIT (524,288 x 8 BIT)5 VOLT CMOS FLASH MEMORY32-pin TSOP-I4 MEGABIT (524,288 x 8 BIT)5 VOLT CMOS FLASH MEMORYSales Office :4th Floor, No. 1, Creation Rd. 1,Science-Based Industrial Park,Hsinchu, Taiwan 30077Tel : 886-3-5792988Fax : 886-3-5792960S29C51004T/S29C51004B V1.0 May 2002164 MEGABIT (524,288 x 8 BIT)5 VOLT CMOS FLASH MEMORYNote :1. Publication date : November 1998 Rev. A , May 2002 Rev. B2. All data and specification are subject changed with Program (Erase/Program) Cycle as below description : a. Chip erase time : 2.0 sec →3.0 sec maximum. b. Byte program time : 20 usec → 35 usec maximum。

长虹电视机高压包代换资料

长虹电视机高压包代换资料长虹代换资料1. BSC73N无替代产品2. BSC60K可用BSC66J3. BSC68H可用BSC70E1和BSC69E4. BSC70E4可用BSC70C5. BSC69C可用BSC69P6. BSC68M可用BSC68M17. BSC62F可用BSC68J代替，需要将逆程电容由7N2加大到9NI8. BSC70P无可替代品。

9. G2985所用行变BSC68H2与BSC70E2可互换10. BSC70E可代用BSC70D1 TAD215HI可代用ST2310、D225311. BSC60J可代用BSC60H M52470P可代用M52472P12. BSC68H2可代用BSC68L TB1231N可代用TB1238AN13. BSC70G可代用TFB4143AD RU4A可代用RU4AM、Z588214. BSC73G可代用BSC73F1 ZSA105Y可代用ZPA1015Y15. BSC68F2可代用BSC68D 3DG388可代用KSC388C16. BSC62E可代用BSC68E D1651可代用D210217. BSC70Z可代用BSD69Z IRF1B5N6A可代用STPPNC65FD18. BSC68W可代用BSC68M1 88P8324N可代用CHT120219. PQ12RF11可代用BSC60T2/BSC60S PQ12RF11可代用BSC60T2、BSC60S20. BSC62A可代用BSC59A CH05T1603可代用CH08T060121. BSC60T2可代用BSC60S DVD5600碟架可代用DVD7100碟架22. BSC68Z可代用BSC68H3 STR-F6656可代用STR-F645423. BSC75W可代用BSC75S STR-F6454不能代用STR-F665624. BSC68H可代用BSC70E1 CH06001可代用CHT060525. BSC70C可代用BSD70B BY2S4可代用INS40826. BSC67A可代用BSC25-301B CH05T1606可代用CH05T160827. BSC73H可代用BSC73K CH05T1607可代用CH05T160428. BSC69E可代用BSC70E1、BSC68H CH05T1623可代用CH05T160929. BSC59J、BSC62J、BSC68J TA8427K(改进线路)可代用TDA365430. BSC70E4可代用BSC70C JUJ7.820.967-3变频板代JUJ7.820.459-331. BSC75M可代用BSC75I、BSC75M6 D1710可代用D528732. BSC68J可代用BSC62J C4706可代用C474533. QYW96E可代用DMV16 D2253可代用D155734. RG2可代用RU2(前能代后,但后不能代前) CH05T1609可代用CH05T162335. CH05T1602可代用CH05T1604/CH05T1607 CH08T0602可代用CH08T1060836. CH05T1601可代用CH05T1603 CH05T1611可代用CH05T162137. CHT0410可代用CHT0416/CIIT0410/CIIT04T1218。

EN29LV800BB-70TCP中文资料

FEATURES• Single power supply operation- Full voltage range: 2.7-3.6 volt read and write operations for battery-powered applications. - Regulated voltage range: 3.0-3.6 volt read and write operations and for compatibility with high performance 3.3 volt microprocessors.• High performance- Access times as fast as 55 ns• Low power consumption (typical values at 5 MHz)- 7 mA typical active read current- 15 mA typical program/erase current- 1 µA typical standby current (standard access time to active mode)• Flexible Sector Architecture:- One 16-Kbyte, two 8-Kbyte, one 32-Kbyte, and fifteen 64-Kbyte sectors (byte mode) - One 8-Kword, two 4-Kword, one 16-Kword and fifteen 32-Kword sectors (word mode)• High performance program/erase speed - Byte/Word program time: 8µs typical - Sector erase time: 500ms typical• Sector protection:- Hardware locking of sectors to preventprogram or erase operations within individual sectors- Additionally, temporary Sector Unprotect allows code changes in previously locked sectors.• JEDEC Standard Embedded Erase and Program Algorithms• JEDEC standard DATA# polling and toggle bits feature• Single Sector and Chip Erase • Sector Unprotect Mode• Erase Suspend / Resume modes:Read or program another Sector during Erase Suspend Mode• Low Vcc write inhibit < 2.5V • Minimum 100K endurance cycle• Package Options - 48-pin TSOP (Type 1) - 48-ball 6mm x 8mm FBGA• Commercial and industrial temperature RangeGENERAL DESCRIPTIONThe EN29LV800B is an 8-Megabit, electrically erasable, read/write non-volatile flash memory, organized as 1,048,576 bytes or 524,288 words. Any byte can be programmed typically in 8µs. The EN29LV800B features 3.0V voltage read and write operation, with access time as fast as 55ns to eliminate the need for WAIT statements in high-performance microprocessor systems.The EN29LV800B has separate Output Enable (OE#), Chip Enable (CE#), and Write Enable (WE#) controls, which eliminate bus contention issues. This device is designed to allow either single Sector or full chip erase operation, where each sector can be individually protected against program/erase operations or temporarily unprotected to erase or program. The device can sustain a minimum of 100K program/erase cycles on each sector.EN29LV800B 8 Megabit (1024K x 8-bit / 512K x 16-bit) Flash Memory Boot Sector Flash Memory, CMOS 3.0 Volt-onlyCONNECTION DIAGRAMSA6 A5 A4A1A3 A2 FBGATop View, Balls Facing DownA13A9 A3 RY/BY#WE# A7 B6 B5 B4B1 B3 B2 A12A8 A4NCRESET# A17 C6 C5 C4C1C3 C2 A14A10 A2A18NCA6 D6D5D4D1D3D2A15A11A1NC NCA5 E6E5E4E1E3E2A16DQ7A0DQ2DQ5DQ0F6F5F4F3F2BYTE#DQ14CE#DQ10DQ12DQ8G6G5G4G3G2DQ15/A-1DQ13OE#DQ11Vcc DQ9H6H5H3H2VssDQ6 VssDQ4DQ1 F1G1H4H1DQ312 34 5 67 89 10 11 12 1314 1516 17 18 19 2021 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 Standard TSOPA16 BYTE# VssDQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 Vcc DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# Vss CE# A0TABLE 1. PIN DESCRIPTION FIGURE 1. LOGIC DIAGRAMPin Name FunctionA0-A18 AddressesDQ0-DQ14 15 Data Inputs/OutputsDQ15 / A-1 DQ15 (data input/output, word mode), A-1 (LSB address input, byte mode)CE# ChipEnable OE# OutputEnable RESET# Hardware Reset PinRY/BY# Ready/BusyOutput WE# WriteEnableVcc Supply Voltage (2.7-3.6V)Vss GroundNC Not Connected to anything BYTE# Byte/WordModeEN29LV800BA0 - A18WE#CE#RY/BY# Reset#Byte#OE#TABLE 2A. TOP BOOT BLOCK SECTOR ARCHITECTUREADDRESS RANGESector(X16) (X8)SECTOR SIZE (Kbytes /Kwords)A18A17A16A15 A14 A13 A1218 7E000h-7FFFFh FC000h-FFFFFh 16/8 1 1 1 1 1 1 X 17 7D000h-7DFFFh FA000h-FBFFFh8/4 1 1 1 1 1 0 116 7C000h-7CFFFh F8000h-F9FFFh 8/4 1 1 1 1 1 0 0 15 78000h-7BFFFh F0000h – F7FFFh 32/16 1 1 1 1 0 X X 14 70000h-77FFFh E0000h - EFFFFh 64/32 1 1 1 0 X X X 13 68000h-6FFFFh D0000h - DFFFFh 64/32 1 1 0 1 X X X 12 60000h-6FFFFh C0000h - CFFFFh 64/32 1 1 0 0 X X X 11 58000h-5FFFFh B0000h - BFFFFh 64/32 1 0 1 1 X X X 10 50000h-57FFFh A0000h - AFFFFh 64/32 1 0 1 0 X X X 9 48000h-4FFFFh 90000h - 9FFFFh 64/32 1 0 0 1 X X X 8 40000h-47FFFh 80000h - 8FFFFh 64/32 1 0 0 0 X X X 7 38000h-3FFFFh 70000h - 7FFFFh 64/32 0 1 1 1 X X X 6 30000h-37FFFh 60000h - 6FFFFh 64/32 0 1 1 0 X X X 5 28000h-2FFFFh 50000h – 5FFFFh 64/32 0 1 0 1 X X X 4 20000h-27FFFh 40000h – 4FFFFh 64/32 0 1 0 0 X X X 3 18000h-1FFFFh 30000h – 3FFFFh 64/32 0 0 1 1 X X X 2 10000h-17FFFh 20000h - 2FFFFh 64/32 0 0 1 0 X X X 1 08000h-0FFFFh 10000h - 1FFFFh 64/32 0 0 0 1 X X X 000000h-07FFFh00000h - 0FFFFh64/32XXXTABLE 2B. BOTTOM BOOT BLOCK SECTOR ARCHITECTUREADDRESS RANGESector(X16) (X8)SECTOR SIZE (Kbytes/Kwords)A18A17A16A15 A14 A13 A1218 78000h-7FFFFh F0000h – FFFFFh 64/32 1 1 1 1 X X X 17 70000h-77FFFh E0000h – EFFFFh 64/32 1 1 1 0 X X X 16 68000h-6FFFFh D0000h – DFFFFh 64/32 1 1 0 1 X X X 15 60000h-67FFFh C0000h – CFFFFh 64/32 1 1 0 0 X X X 14 58000h-5FFFFh B0000h - BFFFFh 64/32 1 0 1 1 X X X 13 50000h-57FFFh A0000h - AFFFFh 64/32 1 0 1 0 X X X 12 48000h-4FFFFh 90000h – 9FFFFh 64/32 1 0 0 1 X X X 1140000h-47FFFh80000h – 8FFFFh64/321XXX10 38000h-3FFFFh 70000h –7FFFFh 64/32 0 1 1 1 X X X 9 30000h-37FFFh 60000h – 6FFFFh 64/32 0 1 1 0 X X X 8 28000h-2FFFFh 50000h – 5FFFFh 64/32 0 1 0 1 X X X 7 20000h-27FFFh 40000h – 4FFFFh 64/32 0 1 0 0 X X X 6 18000h-1FFFFh 30000h – 3FFFFh 64/32 0 0 1 1 X X X 5 10000h-17FFFh 20000h – 2FFFFh 64/32 0 0 1 0 X X X 4 08000h-0FFFFh 10000h – 1FFFFh 64/32 0 0 0 1 X X X 304000h-07FFFh08000h – 0FFFFh32/161XX2 03000h-03FFFh 06000h – 07FFFh 8/4 0 0 0 0 0 1 1 1 02000h-02FFFh 04000h – 05FFFh 8/4 0 0 0 0 0 1 0 000000h-01FFFh00000h – 03FFFh16/8XPRODUCT SELECTOR GUIDEProduct Number EN29LV800BRegulated Voltage Range: Vcc=3.0 – 3.6 V -55RSpeed OptionFull Voltage Range: Vcc=2.7 – 3.6 V-70 -90 Max Access Time, ns (t acc ) 55 70 90 Max CE# Access, ns (t ce ) 55 70 90 Max OE# Access, ns (t oe ) 30 30 35BLOCK DIAGRAMWE#CE# OE#State ControlCommand RegisterErase Voltage GeneratorInput/Output BuffersProgram Voltage GeneratorChip Enable Output EnableLogicData LatchY-Decoder X-Decoder Y-GatingCell MatrixTimerVcc DetectorA0-A18Vcc VssDQ0-DQ15 (A-1)Address LatchBlock Protect SwitchesSTBSTBRY/BY#TABLE 3. OPERATING MODES8M FLASH USER MODE TABLEDQ8-DQ15Operation CE# OE# WE# Reset# A0-A18 DQ0-DQ7 Byte# = V IH Byte#= V IL Read L L H H A IN D OUT D OUT High-Z Write L H L H A IN D IN D IN High-Z CMOS Standby V cc ± 0.3V X X V cc ± 0.3V X High-Z High-Z High-Z TTL Standby H X X H X High-Z High-Z High-Z Output Disable L H H H X High-Z High-Z High-Z Hardware Reset X X X L X High-Z High-Z High-Z Temporary SectorUnprotect X X X V ID A IN D IN D IN XNotes:L=logic low= V IL , H=Logic High= V IH , V ID =11 ± 0.5V, X=Don’t Care (either L or H, but not floating!), D IN =Data In, D OUT =Data Out, A IN =Address InTABLE 4. DEVICE IDENTIFICTION (Autoselect Codes)8M FLASH MANUFACTURER/DEVICE ID TABLENote:1. If a manufacturing ID is read with A8=L, the chip will output a configuration code 7Fh. A further Manufacturing ID must be read with A8=H.2. A9 = VID is for HV A9 Autoselect mode only. A9 must be ≤ Vcc (CMOS logic level) for Command Autoselect Mode.DescriptionModeCE #OE #W E#A18 to A12A11 to A10A92A8A7A6A5 to A2A1 A0 DQ8to DQ15 DQ7 to DQ0 Manufacturer ID:EonL L H X X V IDH1X L X L L X 1Ch Word L L H22h DAh Device ID (top bootblock) Byte L L H X X V ID X X L X L H X DAh Word L L H22h5Bh Device ID(bottom bootblock)Byte L L HX X V IDXXLXLHX 5Bh X01h(Protected)Sector ProtectionVerification L L H SA X V IDX X L X H LX00h(Unprotected)USER MODE DEFINITIONSWord / Byte ConfigurationThe signal set on the BYTE# Pin controls whether the device data I/O pins DQ15-DQ0 operate in the byte or word configuration. When the Byte# Pin is set at logic ‘1’, then the device is in word configuration, DQ15-DQ0 are active and are controlled by CE# and OE#.On the other hand, if the Byte# Pin is set at logic ‘0’, then the device is in byte configuration, and only data I/O pins DQ0-DQ7 are active and controlled by CE# and OE#. The data I/O pins DQ8-DQ14 are tri-stated, and the DQ15 pin is used as an input for the LSB (A-1) address function.Standby ModeThe EN29LV800B has a CMOS-compatible standby mode, which reduces the current to < 1µA (typical). It is placed in CMOS-compatible standby when the CE# pin is at V CC± 0.5. RESET# and BYTE# pin must also be at CMOS input levels. The device also has a TTL-compatible standby mode, which reduces the maximum V CC current to < 1mA. It is placed in TTL-compatible standby when the CE# pin is at V IH. When in standby modes, the outputs are in a high-impedance state independent of the OE# input.Read ModeThe device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is also ready to read array data after completing an Embedded Program or Embedded Erase algorithm.After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode. The system can read array data using the standard read timings, except that if it reads at an address within erase-suspended sectors, the device outputs status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See “Erase Suspend/Erase Resume Commands” for more additional information.The system must issue the reset command to re-enable the device for reading array data if DQ5 goes high, or while in the autoselect mode. See the “Reset Command” additional details.Output Disable ModeWhen the OE# pin is at a logic high level (V IH), the output from the EN29LV800B is disabled. The output pins are placed in a high impedance state.Auto Select Identification ModeThe autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on DQ15–DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed in-system through the command register.When using programming equipment, the autoselect mode requires V ID (10.5 V to 11.5 V) on address pin A9. Address pins A8, A6, A1, and A0 must be as shown in Autoselect Codes table. In addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits. Refer to the corresponding Sector Address Tables. The Command Definitions table shows the remaining address bits that are don’t-care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ15–DQ0.To access the autoselect codes in-system; the host system can issue the autoselect command via the command register, as shown in the Command Definitions table. This method does not require V ID. See “Command Definitions” for details on using the autoselect mode.Write ModeWrite operations, including programming data and erasing sectors of memory, require the host system to write a command or command sequence to the device. Write cycles are initiated by placing the byte or word address on the device’s address inputs while the data to be written is input on DQ[7:0] in Byte Mode (BYTE# = L) or on DQ[15:0] in Word Mode (BYTE# = H). The host system must drive the CE# and WE# pins Low and the OE# pin High for a valid write operation to take place. All addresses are latched on the falling edge of WE# and CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first. The system is not required to provide further controls or timings. The device automatically provides internally generated program / erase pulses and verifies the programmed /erased cells’ margin. The host system can detect completion of a program or erase operation by observing the RY/BY# pin, or by reading the DQ[7] (Data# Polling) and DQ[6] (Toggle) status bits.The ‘Command Definitions’ section of this document provides details on the specific device commands implemented in the EN29LV800B.Sector Protection/UnprotectionThe hardware sector protection feature disables both program and erase operations in any sector. The hardware sector unprotection feature re-enables both program and erase operations in previously protected sectors.There are two methods to enabling this hardware protection circuitry. The first one requires onlythat the RESET# pin be at V ID and then standard microprocessor timings can be used to enable or disable this feature. See Flowchart 7a and 7b for the algorithm and Figure 12 for the timings.When doing Sector Unprotect, all the other sectors should be protected first.The second method is meant for programming equipment. This method requires V ID be applied to both OE# and A9 pin and non-standard microprocessor timings are used. This method is described in a separate document called EN29LV800B Supplement, which can be obtained by contacting a representative of Eon Silicon Solution, Inc.Temporary Sector UnprotectThis feature allows temporary unprotection of previously protected sector groups to change data while in-system. The Sector Unprotect mode is activated by setting the RESET# pin to V ID. During this mode, formerly protected sectors can be programmed or erased by simply selecting the sector addresses. Once is removed from the RESET# pin, all the previously protected sectors are protected again. See accompanying figure and timing diagrams for more details.StartReset#=V ID(note 1) Perform Erase or ProgramOperationsReset#=V IHTemporary Sector Unprotect Completed (note 2)Notes:1. All protected sectors unprotected.2. Previously protected sectors protected again.Automatic Sleep ModeThe automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when addresses remain stable for t acc + 30ns. The automatic sleep mode is independent of the CE#, WE# and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output is latched and always available to the system. ICC4 in the DC Characteristics table represents the automatic sleep more current specification.Hardware Data ProtectionThe command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes as seen in the Command Definitions table. Additionally, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by false system level signals during Vcc power up and power down transitions, or from system noise.Low V CC Write InhibitWhen Vcc is less than V LKO, the device does not accept any write cycles. This protects data during Vcc power up and power down. The command register and all internal program/erase circuits are disabled, and the device resets. Subsequent writes are ignored until Vcc is greater than V LKO. The system must provide the proper signals to the control pins to prevent unintentional writes when Vcc is greater than V LKO.Write Pulse “Glitch” protectionNoise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.Logical InhibitWrite cycles are inhibited by holding any one of OE# = V IL, CE# = V IH, or WE# = V IH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a logical one. If CE#, WE#, and OE# are all logical zero (not recommended usage), it will be considered a read.Power-up Write InhibitDuring power-up, the device automatically resets to READ mode and locks out write cycles. Even with CE# = V IL, WE# = V IL and OE# = V IH, the device will not accept commands on the rising edge of WE#.COMMAND DEFINITIONSThe operations of EN29LV800B are selected by one or more commands written into the command register to perform Read/Reset Memory, Read ID, Read Sector Protection, Program, Sector Erase, Chip Erase, Erase Suspend and Erase Resume. Commands are made up of data sequenceswritten at specific addresses via the command register. The sequences for the specified operation are defined in the Command Definitions table (Table 5). Incorrect addresses, incorrect data values or improper sequences will reset the device to Read Mode.Table 5. EN29LV800B Command DefinitionsBus Cycles1stCycle 2ndCycle 3rdCycle 4thCycle5thCycle 6thCycle Command SequenceC y c l e sAddr DataAddr DataAddr DataAddr DataAddr DataAddr DataRead 1 RA RD Reset 1 xxx F0Word555 2AA555000/1007F/1CManufacturerID Byte 4AAA AA55555AAA90000/2007F/1CWord 555 2AA555 X0122DADevice ID Top Boot Byte 4 AAA AA55555 AAA 90X02DA Word 555 2AA555 X01225BDevice ID Bottom Boot Byte 4AAA AA55555AAA 90X025BXX00Word5552AA555(SA)X02XX0100A u t o s e l e c tSector Protect Verify Byte 4AAA AA55555AAA90(SA)X0401Word 555 2AA555Program Byte 4 AAA AA55555 AAAA0 PA PDWord 555 2AA555 5552AA 555Chip Erase Byte 6 AAA AA55555 AAA 80 AAA AA 555 55 AAA 10Word 555 2AA555 5552AASector Erase Byte6 AAA AA55555 AAA 80 AAA AA 555 55 SA 30Erase Suspend 1 xxx B0Erase Resume1 xxx 30Address and Data values indicated in hexRA = Read Address: address of the memory location to be read. This is a read cycle. RD = Read Data: data read from location RA during Read operation. This is a read cycle. PA = Program Address: address of the memory location to be programmed. X = Don’t-Care PD = Program Data: data to be programmed at location PASA = Sector Address: address of the Sector to be erased or verified. Address bits A18-A12 uniquely select any Sector.Reading Array DataThe device is automatically set to reading array data after power up. No commands are required to retrieve data. The device is also ready to read array data after completing an Embedded Program or Embedded Erase algorithm.Following an Erase Suspend command, Erase Suspend mode is entered. The system can read array data using the standard read timings, with the only difference in that if it reads at an address within erase suspended sectors, the device outputs status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception.The Reset command must be issued to re-enable the device for reading array data if DQ5 goes high, or while in the autoselect mode. See next section for details on Reset.Reset CommandWriting the reset command to the device resets the device to reading array data. Address bits are don’t-care for this command.The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the device to reading array data. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to reading array data (also applies to programming in Erase Suspend mode). Once programming begins, however, the device ignores reset commands until the operation is complete.The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to reading array data (also applies to autoselect during Erase Suspend).If DQ5 goes high during a program or erase operation, writing the reset command returns the device to reading array data (also applies during Erase Suspend).Autoselect Command SequenceThe autoselect command sequence allows the host system to access the manufacturer and devices codes, and determine whether or not a sector is protected. The Command Definitions table shows the address and data requirements. This is an alternative to the method that requires V ID on address bit A9 and is intended for PROM programmers.Two unlock cycles followed by the autoselect command initiate the autoselect command sequence. Autoselect mode is then entered and the system may read at addresses shown in Table 4 any number of times, without needing another command sequence.The system must write the reset command to exit the autoselect mode and return to reading array data.Word / Byte Programming CommandThe device may be programmed by byte or by word, depending on the state of the Byte# Pin. Programming the EN29LV800B is performed by using a four bus-cycle operation (two unlock write cycles followed by the Program Setup command and Program Data Write cycle). When the program command is executed, no additional CPU controls or timings are necessary. An internal timer terminates the program operation automatically. Address is latched on the falling edge of CE# or WE#, whichever is last; data is latched on the rising edge of CE# or WE#, whichever is first. Programming status may be checked by sampling data on DQ7 (DATA# polling) or on DQ6 (toggle bit). When the program operation is successfully completed, the device returns to read mode and the user can read the data programmed to the device at that address. Note that data can not be programmed from a 0 to a 1. Only an erase operation can change a data from 0 to 1. When programming time limit is exceeded, DQ5 will produce a logical “1” and a Reset command can return the device to Read mode.Chip Erase CommandChip erase is a six-bus-cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. The Command Definitions table shows the address and data requirements for the chip erase command sequence.Any commands written to the chip during the Embedded Chip Erase algorithm are ignored.The system can determine the status of the erase operation by using DQ7, DQ6, or DQ2. See “Write Operation Status” for information on these status bits. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched.Flowchart 4 illustrates the algorithm for the erase operation. See the Erase/Program Operations tables in “AC Characteristics” for parameters, and to the Chip/Sector Erase Operation Timings for timing waveforms.Sector Erase Command SequenceSector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two un-lock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the address of the sector to be erased, and the sector erase command. The Command Definitions table shows the address and data requirements for the sector erase command sequence.Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored.When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, or DQ2. Refer to “Write Operation Status” for information on these status bits. Flowchart 4 illustrates the algorithm for the erase operation. Refer to the Erase/Program Operations tables in the “AC Characteristics” section for parameters, and to the Sector Erase Operations Timing diagram for timing waveforms.Erase Suspend / Resume CommandThe Erase Suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. This command is valid only during the sector erase operation. The Erase Suspend command is ignored if written during the chip erase operation or Embedded Program algorithm. Addresses are don’t-cares when writing the Erase Suspend command.When the Erase Suspend command is written during a sector erase operation, the device requires a maximum of 20 µs to suspend the erase operation.After the erase operation has been suspended, the system can read array data from or program data to any sector not selected for erasure. (The device “erase suspends” all sectors selected for erasure.) Normal read and write timings and command definitions apply. Reading at any address within erase-suspended sectors produces status data on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. See “Write Operation Status” for information on these status bits.After an erase-suspended program operation is complete, the system can once again read array data within non-suspended sectors. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation. See “Write Operation Status” for more information. The Autoselect command is not supported during Erase Suspend Mode.The system must write the Erase Resume command (address bits are don’t-care) to exit the erase suspend mode and continue the sector erase operation. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the device has resumed erasing.WRITE OPERATION STATUSDQ7: DATA# PollingThe EN29LV800B provides DATA# polling on DQ7 to indicate the status of the embedded operations. The DATA# Polling feature is active during the embedded Programming, Sector Erase, Chip Erase, and Erase Suspend. (See Table 6)When the embedded Programming is in progress, an attempt to read the device will produce the complement of the data last written to DQ7. Upon the completion of the embedded Programming, an attempt to read the device will produce the true data written to DQ7. For the embedded Programming, DATA# polling is valid after the rising edge of the fourth WE# or CE# pulse in the four-cycle sequence.When the embedded Erase is in progress, an attempt to read the device will produce a “0” at the DQ7 output. Upon the completion of the embedded Erase, the device will produce the “1” at the DQ7 output during the read cycles. For Chip Erase, the DATA# polling is valid after the rising edge of the sixth WE# or CE# pulse in the six-cycle sequence. DATA# polling is valid after the last rising edge of the WE# or CE# pulse for chip erase or sector erase.DATA# Polling must be performed at any address within a sector that is being programmed or erased and not a protected sector. Otherwise, DATA# polling may give an inaccurate result if the address used is in a protected sector.Just prior to the completion of the embedded operations, DQ7 may change asynchronously when the output enable (OE#) is low. This means that the device is driving status information on DQ7 at one instant of time and valid data at the next instant of time. Depending on when the system samples the DQ7 output, it may read the status of valid data. Even if the device has completed the embedded operations and DQ7 has a valid data, the data output on DQ0-DQ6 may be still invalid. The valid data on DQ0-DQ7 will be read on the subsequent read attempts.The flowchart for DATA# Polling (DQ7) is shown on Flowchart 5. The DATA# Polling (DQ7) timing diagram is shown in Figure 8.RY/BY#: Ready/BusyThe RY/BY# is a dedicated, open-drain output pin that indicates whether an Embedded Algorithm is in progress or completed. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied together in parallel with a pull-up resistor to Vcc.In the output-low period, signifying Busy, the device is actively erasing or programming. This includes programming in the Erase Suspend mode. If the output is high, signifying the Ready, the device is ready to read array data (including during the Erase Suspend mode), or is in the standby mode.。

VISHAY钽电容规格书293D系列

This is expressed in X0 = ± 20% This is expressed in volts. picofarads. The To complete the threeX9 = ± 10% digit block, zeros precede first two digits are X5 = ± 5% the significant the voltage rating. A figures. The third is (Special Order) decimal point is indicated the number of zeros by an "R" to follow. (6R3 = 6.3 volts). Note: Preferred Tolerance and reel sizes are in bold.
DIMENSIONS in inches [millimeters]
L
H TH Min.
W
TW
P
CASE CODE A B C D E P
EIA SIZE 3216 3528 6032 7343 7343H 2012
L 0.126 ± 0.008 [3.2 ± 0.20] 0.138 ± 0.008 [3.5 ± 0.20] 0.236 ± 0.012 [6.0 ± 0.30] 0.287 ± 0.012 [7.3 ± 0.30] 0.287 ± 0.012 [7.3 ± 0.30] 0.079 ± 0.20 [2.0 ± 0.008]
H 0.063 ± 0.008 [1.6 ± 0.20] 0.075 ± 0.008 [1.9 ± 0.20] 0.098 ± 0.012 [2.5 ± 0.30] 0.110 ± 0.012 [2.8 ± 0.30] 0.158 ± 0.012 [4.0 ± 0.30] 0.047 Max. [1.2 Max.]

海尔电视机说明书29F5D-T.29F7A-T

3.时间设置...........................10 4.关机时间...........................10 5.开机时间...........................10 6.喜爱节目...........................11 7.转台时间1..........................11 8.台号1..............................11 9.记事时间...........................11 六.月历设置...........................11
4.波段选择在半自动搜索时,您想搜索的信号不在当前波段上，可以改变波段以提高搜索速度。（1）连续按菜单键，使屏幕出现如图所示菜单；（2）按P PV键,使“ ”指向波段；（3）按键，调节到您所需要的信号波段。
选台及存储
节目号
008
跳越
关
波段
UHF
微调
搜索
自动搜索节目号
节目交换跳越---
步骤八:观看电视节目
按遥控器上的数字直选键，选择自己喜爱的电视频道，开始观看电视节目。
注意：要想了解更详细的操作，请根据目录提示仔细阅读本说明书中相应章节。
注意事项
电视机的保养
擦拭时，请先将电视机电源插头拔下，切勿使用苯、汽油或其它化学品擦拭机壳和屏幕。
为了提高电视机寿命，请置于通风良好处。
为了防止燃烧或触电，请勿让电视机淋雨或受潮。
注意事项
电源线不要贴近热源、受挤压，插拔电源线时请捏住插头本体。
由于过载会造成电器烧毁或电击危害，
220V
380V
所以使用墙上的插座和引出线时不要超

S07J中文资料

V OHHigh-level output voltage VSN54LS07SN54LS07, SN74LS07, SN74LS17HEX BUFFERS/DRIVERS WITHOPEN-COLLECTOR HIGH-VOLTAGE OUTPUTS元器件交易网I OH V OLV CC = MIN,V IL = 0.8 VV CC = MIN,V IH = 2 V VmA SN54LS07PARAMETERTEST CONDITIONS MIN TYP MAX UNIT AYR L = 110 Ω,C L = 15 pFnsSN54LS07, SN74LS07, SN74LS17HEX BUFFERS/DRIVERS WITHOPEN-COLLECTOR HIGH-VOLTAGE OUTPUTS元器件交易网元器件交易网IMPORTANT NOTICETexas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinueany product or service without notice, and advise customers to obtain the latest version of relevant informationto verify, before placing orders, that information being relied on is current and complete. All products are soldsubject to the terms and conditions of sale supplied at the time of order acknowledgement, including thosepertaining to warranty, patent infringement, and limitation of liability.TI warrants performance of its semiconductor products to the specifications applicable at the time of sale inaccordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extentTI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarilyperformed, except those mandated by government requirements.CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OFDEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICALAPPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, ORWARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHERCRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TOBE FULLY AT THE CUSTOMER’S RISK.In order to minimize risks associated with the customer’s applications, adequate design and operatingsafeguards must be provided by the customer to minimize inherent or procedural hazards.TI assumes no liability for applications assistance or customer product design. TI does not warrant or representthat any license, either express or implied, is granted under any patent right, copyright, mask work right, or otherintellectual property right of TI covering or relating to any combination, machine, or process in which suchsemiconductor products or services might be or are used. TI’s publication of information regarding any thirdparty’s products or services does not constitute TI’s approval, warranty or endorsement thereof.Copyright © 1998, Texas Instruments Incorporated。

SY91001B芯片手册

SY91001B芯片手册
1.弄清楚芯片外部引线的功能，只有熟悉每一条引线，在将来工程应用中才有可能将芯片连接到系统总线上。

2.了解芯片的工作方式或者特点，以便将来遇到具体的工程问题时，能够知道该利用芯片的哪种工作方式或者那种工作特性可以解决问题。

3.理解芯片内部的控制字、命令字、状态字，以便在具体应用时能够选择控制字、命令字、状态字，并利用状态字对芯片编程。

4.了解芯片所占用的接口地址，以利于对芯片的具体连接。

5.在上述基础上，实现对芯片的初始化以具体应用。

BLW29中文资料

Fig.5 IE = Ie = 0; f = 1 MHz; Tj = 25 °C.
handbook, full pagewidth
1500
MGP418
fT (MHz)
1000 typ
500
0 0 2 4 6 8 −IE (A) 10
Fig.6 VCB = 13,5 V; f = 100 MHz; Tj = 25 °C.
BLW29
QUICK REFERENCE DATA R.F. performance up to Th = 25 °C MODE OF OPERATION c.w. class-B c.w. class-B VCE V 13,5 12,5 f MHz 175 175 PL W 15 15 Gp dB > 10 typ. 10, 5 η % > 60 typ. 67 zi Ω 1,3 + j0,68 − YL mS 180 − j54 −
BLW29
36 V 18 V 4 V 5 mA 4 mJ 4 mJ 40 10 to 80 1,5 V 900 MHz 825 MHz 43 pF 27 pF 2 pF
August 1986
4
Philips Semiconductors
Product speciﬁcation
VHF power transistor
August 1986
3
Philips Semiconductors
Product speciﬁcation
VHF power transistor
CHARACTERISTICS Tj = 25 °C Collector-emitter breakdown voltage VBE = 0; IC = 15 mA Collector-emitter breakdown voltage open base; IC = 100 mA Emitter-base breakdown voltage open collector; IE = 5 mA Collector cut-off current VBE = 0; VCE = 18 V Second breakdown energy; L = 25 mH; f = 50 Hz open base RBE = 10 Ω D.C. current gain(1) hFE typ. IC = 1,75 A; VCE = 5 V Collector-emitter saturation voltage(1) IC = 5 A; IB = 1 A Transition frequency at f = 100 MHz(1) −IE = 1,75 A; VCB = 13,5 V −IE = 5 A; VCB = 13,5 V Collector capacitance at f = 1 MHz IE = Ie = 0; VCB = 13,5 V Feedback capacitance at f = 1 MHz IC = 100 mA; VCE = 13,5 V Collector-stud capacitance Note 1. Measured under pulse conditions: tp ≤ 200 µs; δ ≤ 0,02. Cre Ccs typ. typ. Cc typ. fT fT typ. typ. VCEsat typ. ESBO ESBR > > ICES < V(BR)EBO > V(BR)CEO > V(BR) CES >

Victaulic唯特利管道产品安装、维护和测试手册说明书

Auto Drain 自S动lee排v水e 套管
Ball Drip 球形滴Plu阀n柱ge塞r
供W水at主er管Su控p制pl阀y Main Control
Valve
系统主管排水阀
System Main Drain Valve
注Ch水ar管g路e 球阀 Line Ball
Valve
报A警la测rm试T球es阀t Ball Valve
步骤 2a：如果已安装 746-LPA 系列干式加速器，请确认隔离球阀已关闭。步骤 2b：如果已安装 746-LPA 系列干式加速器，请打开 1/4 转排气球阀。第 3 步：确认报警测试球阀已关闭。第 4 步：开启压缩机或打开空气维护配管组件（AMTA）上的快充球阀，向系统中充气。至少将系统充气至 13 psi/90 kPa/0.9 Bar。第 5 步：当系统压力达到约 10 psi/69 kPa/0.7 Bar 且自动排气阀不再释放任何水气时，向上拉起 776 系列低压执行机构的自动排气套管。说明：自动排气螺钉应密封并保持在设置（“向上”）位置。第 6 步：系统空气压力建立后，关闭空气维护配件组件（AMTA）上的快充球阀。第 7 步：打开空气维护配件组件（AMTA）上的慢充球阀。说明：慢充球阀未打开可能会因系统压力下降，导致因系统泄露而引起的阀门误工作。第 8 步：打开注水管路球阀。让水流过自动排水管。第 9 步：向上拉起自动排水套管，直到螺钉处于设置（“向上”）位置为止。核实注水管路压力表确实有压力。步骤 9a：如果安装的是 746-LPA 系列干式加速器，请关闭 1/4 转排气球阀。步骤 9b：如果已安装 746-LPA 系列干式加速器，请打开隔离球阀。这样便可设定加速器。第 10 步：打开供水主管排水阀。第 11 步：缓慢打开供水主管控制阀，直到水流稳定地从打开的供水主管排水阀流出为止。第 12 步：水流稳定后，关闭供水主管排水阀。第 13 步：将供水主管控制阀完全打开。第 14 步：确认所有阀门都处于正常工作位置（请参阅下表）。

myslot

/cast 冰冷血脉
#showtooltip 寒冰箭
/cancelaura 寒冰屏障
/cast 寒冰箭
@ Myslot 导出数据 ( V11)
@ 时间：06/23/12 11:16:43
@ 人物：Tamuura
@ 职业：法师
@ 天赋：奥术:2 火焰:8 冰霜:31
@ 等级：85
@
@ 问题/建议请联系 farmer1992@
公会宗旨：
以义为先，以情为首，以实力证明，团结友爱齐心打造最特色的第一大混子公会！！！
公会成员必须遵守的准则：
1、禁止在YY上和Q群上乱发东西和吵架、骂人等等。
2、个人在游戏上和其他混子发生矛盾必须找流氓处理。
3、公会的混子不能骗自己公会的混子，欺骗公会混子的点卡或金钱等等。
4、公会的混子必须要听从流氓的命令。
任何公会任何家族和个体加盟我们《混子大队》公会，只要您有能力您有时间完全可以成为我们公会内阁混子参与公会发展大小事物的讨论.我们期待您的加盟加入共同发展我们公会
#showtooltip 冰枪术
/cancelaura 寒冰屏障
/ 冰枪术
#showtooltip 法术反制
/cancelaura 寒冰屏障
/stopcasting
/clearfocus [target=focus,dead]
/clearfocus [target=focus,noexists]
/Cast [target=focus,exists] 法术反制;法术反制
#showtooltip 冰冷血脉
/cast 生命之血
/use 灾变角斗士的统御徽章
@ --------------------

EN29GL064B-70BIP中文资料(Eon Silicon)中文数据手册「EasyDatasheet - 矽搜」

图 4.逻辑图
A0 – A21
复位＃
CE# OE# WE# Byte#
EN29GL064 RY/BY#
DQ0 – DQ15 (A-1)
芯片中文手册,看全文,戳
表 2.产品选择指南
产品编号
速度选项
全电压范围：VCC = 2.7 - 3.6 V V =1.65 – 3.6 V
功能
A21–A0 数据输入/输出. DQ15（数据输入/输出,文字模式）, A-1（LSB地址输入,字节模式）
芯片使能
输出使能
硬件复位引脚
就绪/忙输出
写使能
电源电压（2.7〜3.6V）
地面
V I / O输入. 字节/字模式选择写防护护/加速引脚留作将来使用.
没有连接到任何东西
初稿
EN29GL064
芯片中文手册,看全文,戳
初稿
EN29GL064
64兆位（8192K×8位/ 4096K×16位）闪存页模式闪存,CMOS 3.0电压只有
EN29GL064
特征
单电源工作
- 全电压范围：2.7至3.6伏读
写操作
高性能
- 存取时间快70纳秒
VIO 输入/输出1.65〜3.6伏特 - 所有输入电平（地址,控制和DQ输入
A10
A11
DQ7 DQ14 DQ13
DQ6
A5
B5
C5
D5
E5
F5
G5
H5
WE# RESET# A21
A19
DQ5 DQ12
VCC
DQ4
A4
B4
C4
D4
E4
F4
G4
H4

MX51_D901_WinCE_User_Manual

未经作者同意，任何单位和个人不得将本手册部分或全部，以任何形式用于商业目的。

在非商业场合使用本手册是被允许的。

更新记录更新时间更新原因更新内容更新人2009-11-9 文档创建(v1.0) 矽太恒科目录版权声明 (1)目录 (2)1.环境要求 (1)1.1.主机系统必备条件 (1)1.2.目标系统必备条件 (1)2.提供文件 (2)3.BOOTLOADER的第一次烧写 (3)3.1.XLDR.NB0简述 (3)3.2.B OOTLOADER烧入N ANDFLASH (3)3.3.B OOTLOADER烧入SD M EMORY (7)4.在主机上安装D501开发板的BSP包 (10)5.EBOOT的使用 (24)5.1.通过SD更新WINCE操作系统 (24)5.2.通过SD更新EBOOT (25)6.NAND FLASH驱动(FMD) (27)6.1.NAND FMD驱动简介 (27)6.2.系统需求 (27)6.3.驱动测试 (27)E (28)E驱动简介 (28)7.2.系统需求 (28)7.2.1.硬件要求 (28)7.2.2.系统要求 (28)7.3.驱动测试 (29)7.3.1.手工测试 (29)7.3.2.CETK测试 (29)8.FEC驱动 (30)8.1.FEC驱动介绍 (30)8.2.硬件要求 (30)8.3.驱动测试 (31)B驱动 (32)B HS H OST 2(H2)驱动 (32)B F ULL S PEED H OST(H1)驱动 (32)13.2.2.驱动简介 (32)13.2.2.系统需求 (33)13.2.2.驱动测试 (33)B OTG驱动(H IGH S PEED) (33)10.DISPLAY (34)10.1.D ISPLAY驱动简介 (34)10.2.系统需求 (35)13.2.2.硬件要求 (35)13.2.2.系统要求 (35)10.3.驱动测试 (35)13.2.2.手动测试 (35)13.2.2.CETK测试 (36)11.SDHC (37)11.1.SDHC驱动简介 (37)11.2.系统需求 (37)13.2.2.硬件要求 (37)13.2.2.系统要求 (37)13.2.2.注册表 (38)11.3.驱动测试 (38)13.2.2.手工测试 (38)13.2.2.CETK测试 (38)12.CAMERA (40)12.1.C AMERA驱动简介 (40)12.2.系统需求 (40)13.2.2.硬件要求 (40)13.2.2.系统要求 (41)13.2.2.软件要求 (41)13.2.2.注册表 (41)12.3.驱动测试 (42)13.2.2.测试程序的编译 (42)13.2.2.运行测试 (42)13.VPU (43)13.1VPU驱动简介 (43)13.2.系统需求 (43)13.2.1.硬件要求 (43)13.2.2.软件要求 (43)13.3.1.测试程序的编译 (44)13.2.3.Decoding Test (44)13.2.3.Encoding Test (44)14.UART (45)14.1.UART驱动简介 (45)14.2.系统需求 (45)14.2.1.硬件要求 (45)14.2.2.系统要求 (45)14.2.3.软件要求 (46)14.2.4.注册表 (46)15.KEYPAD (47)15.1.K EYPAD驱动简介 (47)15.2.系统需求 (47)15.2.1.硬件要求 (47)15.2.2.系统要求 (47)15.3.驱动测试 (48)15.3.1.驱动参数设置 (48)15.3.2.运行测试 (48)16.AUDIO (49)16.1A UDIO驱动简介 (49)16.2系统需求 (50)16.2.1硬件要求 (50)16.2.2系统要求 (50)16.3驱动测试 (50)17.TOUCH PANEL (51)17.1.T OUCH P ANEL驱动简介 (51)17.2.系统需求 (51)17.2.1.硬件要求 (51)17.2.2.系统要求 (51)17.3.驱动测试 (52)18.ATA (53)18.1.ATA驱动简介 (53)18.2.系统需求 (54)18.2.1.硬件要求 (54)18.2.2.系统要求 (54)19.MULTIMEDIA (55)19.1.M ULTIMEDIA驱动简介 (55)19.1.1.驱动信息 (55)19.1.2.BSP目录树结构 (55)19.1.3.BSP驱动加载信息确认 (55)19.2.系统需求 (56)19.2.1.硬件要求 (56)19.2.2.系统要求 (56)19.3.驱动测试 (56)19.3.1.音频解码测试（Audio Decoder Test） (56)19.3.2.视频解码测试（Video Decoder Test） (56)19.3.3.图像解码测试（Image Decoder Test） (56)19.3.4.MP3编码测试（MP3 Encoder Test） (57)19.3.5.WMA8编码测试（WMA8 Encoder Test） (57)19.3.6.PEQ音频后处理试验（PEQ Audio Post-processing Test） (58)19.3.7.VPU编码测试（VPU Encoder Test） (59)19.3.8.数字音频录音测试（Digital Audio Recorder Test） (59)19.3.9.AVI数字A/V记录测试（Digital A/V Recorder for AVI Test） (60)19.3.10.硬件视频交错启用/禁用（Hardware Video De-interlace Enable/Disable） (61)19.3.11.G.711编/解码测试（G.711 Encoder/Decoder Test） (61)19.3.12.G.723.1编/解码测试（G.723.1 Encoder/Decoder Test） (62)19.3.13.G.726编/解码测试（G.726 Encoder/Decoder Test） (62)19.3.14.G.729AB编/解码测试（G.729AB Encoder/Decoder Test） (63)19.3.15.NB_AMR编/解码测试（NB_AMR Encoder/Decoder Test） (64)19.3.16.WB_AMR 编/解码测试（WB_AMR Encoder/Decoder Test） (64)20.常见问题及解决方法 (66)1.环境要求1.1. 主机系统必备条件z安装Microsoft Visual Studio 2005，Platform Builder for CE 6.0 z网卡1.2. 目标系统必备条件z MX51 D901开发板z网线、串口线(直连线)2.提供文件z BSP & OSDesigns文件夹： MX51D901开发板的BSP、 CSP源代码，WINCE6示例工程，包含MX51D901开发板的开发平台的各种源代码、执行脚本等。

长虹机芯表

长虹机芯表机芯型号适应机型NC-329寸型号：C2919P，C2919PK，C2919N，C2919PS，C2919PV，C2919PT，C2920，C2920PN，C2939AE，C2939T，C2939KE，C2939KS，C2939KV。

34寸型号：C3418PN，C3418PS，C3418PB，C3418PK，C3418N，C3419PD，C3419D，C3418KV，C3419PN，C3419PBCN-5机芯21寸：N2118B，N2119B，R2116N，R2118N，F N，F N。

25寸：N2516，N2516B，C2588D，C2588E，R2516N/FN，R2518N/FN，R2519N，2516FN，F N，F N，N16，N18，N19，N19E A。

29寸：N2918，N2918A，N2918B，N2919。

NC-629寸：G2966，G2966A，G2967，G2967A，G2967B，PF29G88，R2916G，R2917G，R2918G，R2919G。

3434寸：寸：PF34G8PF34G8。

38寸：G3898，G3898A，G3899，G3899A，R3816G，R3817G，R3818G，R3819G。

CN-7机芯29寸：T2981，T2982，T2981A，T2982A，T81，T81A，S T81，T82，29T82A，S T82，R2916T，R2917T，R2918T，R2919T。

34寸：T88，S T18，T8，T19，R3415T，C3419T，R3416T，C3419PT，R3417T，T3418A，R3418T，T3418。

CN-9机芯G1430，R2112T，R2113T，R2115T，R2117T，B26，B27，B28，B32，2126FB，F B，F B，F B，F B，G2128，PF21B8。

2525寸：寸：G2521G2521，，B1525B15，，B1625B16，，G2529G2529，，G2530G2530，，G2523G2523，，G2538G2538，，G2510BG2510B，，G2526G2526，，G2532，G2539，PF25B8。

长虹各型遥控器型号对照表

长虹各型遥控器型号对照表长虹各型遥控器型号对照表（仅供参考长虹各型遥控器型号对照表（仅供参考）遥控器对应型号备注 TV K11B 34D18 25D18A 2939FD 2936FD 2931FD 2938FD 29SD81 29SD82 34SD81 29D82M 2526FD 29D85 R2518AE/D 2528FD 29ST82 29SD82 D2982M 29SD81 29D81 TV K11F G2573 G3478 G2988 G2978 G2585 PF29D18 G2985 TV K11G G3488 G3480 PF29D9 G29D9 G2989 G2983（A）G25D19 PF25D19 TV K12F H1498K TV K12I PF2198KB、H2199KB、 TV K16E PF2983、SF2983、SF2583 TV K16H PF2139、SF2139 TV K16P PF2983、SF2983、SF2583K16G:SF2539（A）、PF2539 TV K18B SF1498E TV K1A C1462 C1742 C1942 C2145 TV K1B C1742-41/21/22 C1861 C1862 C1863 C1941 C2143 C2163 TV K1D C2165 系列 C2167 C2168A C2169A TV K4A C2188 C2588A/B/K/V/Z C2589/V/Z C2988 TV K4C C2588P/PZ C2988PC3418PK TV K4N C3419PD/D C2919PD 2920PD/PN C2939D G2958 C3419PN/BT TV K4PC2588PK /PV/PI TV K5C C1851 C1951 C2151C/Z C2152 TV K6E A2118/ME TV K6K 29A18 TV K7B T2981/A/ME/MA T2982A R3418T 34T18 34ST18 C3419T R3415T R3416T R3417T R3418MA C2919PT C2939T R2916T R2917T机芯TV TV TV TV TV TV TV TV TV TV TV TV TV TV TV TVTV TV TV TVR2918T C3419PT T3418/A/C 29ST13 R2918T K8C R2116N R2118/N 2116N 2118FN K9A D2965BT K9B C2995A K10A 学习机⽤ K10B R2112T R2113T R2115T R2117T 2126FB 2131FB 21B26 25B15 29B38 2938FB 2131FB 21B27 21B26 2127FB 21B28 2128FB T2115B T2116B T2117B 2126FB T2118B G2130 2108PF2118FB K10C K10F G2923/B G2936/B G2925B G2929/BG2521 G2935/B G2938 G2939/B G2526/B G2538 G2528B G2928 G2933 G2529 G2129 PF25B8 G2532 G2539 G1430 G2130 PF21B8 G2536 G2510/B H21K60(B) H21K65(B) H21K59(B) H21K68(B) K10G PF25E8 G29E6 G29E8 PF29E8 PF29E18 K10L H25K60(B) G2989(B) K11B R2938D/D2989 K11F K11G G2983、 K11N H25S86(D)、H29S86（D）、PF2519D、H2519D、PF2919D、H2919D、PF2999D、PF2589D、H2589D、PF2989D、PF3489D、 G3898(A)、G25D19A K12A21K18/21K31/21K32 K12A-C1 K12D G2110 G2112 G2516 25K18 G2510A G2101 G2911 G2908 G2913 G2919 G2113 G2109G2915 G2508 G2918 G2916 G2509 G2112 G2512 G2510 G2103 G2111 G2102/A G2101/A G2902/A G2105 G2210 G2501/AG2132/K 21K18 21K21 21K23 21K31 21K32 H2183K、H2135W、H2123K、H2199KB（A）、H2119KB（A） K12F H1498KK12F1 H1418K K12G GH2151K、H2135W、H2535K、H2199KB（A）、H2599KB（A）、H2123K K12I PF2198KB、H2199KBTV TV TV TV TV TV TV TV TV TV TVTV TV TV TV TV TV TV TV TV TV TV TVK12P PF2599K K12R PF2188K/ H2599KB /H2999KB /H2111K K12S H2511K/PF2583K K15A K16C SF2599、SF2515（A）、H29S86 PF2998 SF2598 PF2986 PF3415 SF3415 SF2951F PF2915 H25S86 SF3498F SF2915 SF2998 PF2515 SF2551PF2598 K16D PF2198、SF2198、SF2199、 PF2115、SF2115、SF2186、SF2119 SF2151 K16E PF2983、SF2983、SF2583 K16F SF2183/⼩屏幕新版 OSD、NEC 码 PF3498 SF2983 SF2183 SF2583 K16G SF2539（A） SF2939 PF2539 K16H PF2139 SF2139 K16J PF2598\A、SF2598\A、SF3498、PF2998\A、SF2998、PF2515、SF2515、PF2986\A、SF2515（A）、PF2915、SF2915、 PF3415、 SF3415、SF2551、SF2951F K16K PF2539、SF2911、SF2539、SF2539（A）、PF2939、SF2939（A）、SF2511、SF3488、SF3498、SF2588 SF3411F PF2588 K16N PF2155、PF21118、PF21156、PF2155、SF2198 、SF2198G （CH-16A、新版 OSD、NEC 码） K16P PF2983、SF2983、SF2583 （NEC 码） K16Q PF2139、SF2139（新版OSD、NEC 码）、PF2195、SF2111 K16T PF3495、PF2995、PF2595、SF2911/F、SF3411/F、PF2992 K16Z PF29008 K18B SF1498E SF2170E K18D PF2591E PF2991E PF2918E PF3418E SF1498E SF2591E SF3418E PF2593E PF2191E K18ESF2118E PF2118E SF2191E K18G SF2166K K18I HD29988 HD34988 PF2993E PF2193E K18J SF2566E SF2966E PF2955E TV TV TV TV TV TV TV TV TV TV TV TV TV TV TV TV TV TV TV TVTV TV TV TVK1A C1462/C1742/C1942/C2415/C1402/CK44A/CJK53B2/CJKJ56B2/CTV130 K1B C1742-01/C1742-21/1742-22/C1861/C1862/C1862/C1941/C2143/C2163 K1C C1742-01/C1742-21/1742-22/C2162/C2163 K1DC2165/C2165A/C2165AY/C2165C/C2165E/C2167/C2168A/C2169A K1E C1462-21 K1F C1462-01 K1G C2164 K1H C2165PK1I C2165PI K1J C1462-02 K1L C1742A/C2165F/C2166/C2166A/C2166C/C2166K/C2166KV/C2167F/C2168F/C2169F K1MC2170 K1P C1942A/C2145A K1Q C2165K/C2165KV/C2167K/C2167KF/C2167KV/C2167T/C2169K/C2169KV/P2116/P2119K22A CHD32200 K2A M11 K2B C2141/C2142 TDA K3B C2192A/C2192AV/C2192M TDA K3C TDA K3DC2191/C2191C/C2191D/C2191E/C2191M/C2193A/C2193AV/C2193M/D2111/C2595/D2521/D2991/D2522/D2523/D2526/D2592 /D2598/C2991/C2991E/C2992/C2993/C2993A/C2995/D2963/D2965/D2965MA/D211A/D2115/D2115/D2116/D2117/D2118/C2592AE/C2592AV/C2593/C2591AV TDA K3E D2961A/D2962A/D2963A/D2965A/D2966A/D2960/D2961/D2961/D29966 TDA K3H D2115A/D2116A/D2117A/D2118A/C2192/D2598A/C2193/D2521A/D2522A/D2523A/D2526A NC-2 K4AC2188/C2588A/C2588I/C2588K/C2588K/C2588V/C2588Z/C2589/C2589V/C2589Z/C2988 NC-2 K4A-AU C2588AUM11 TA M11 TA TA TA TA TA TA TA TA TA TA TATV TV TV TV TV TV TV TV TV TV TV TV TV TV TV TV TV TV TV TV TV TVNC-2 K4B C2518 NC-2 K4C C2588P/C2588PZ/C2988P/C3418PK NC-3 K4DC2918PN/C2918PS/C2919P/C2919PS/C2919PN/C2919PI/C2919I/C2939A、AE、KE、KS、KV/G2958/C3418KV/C2919PV/C29199K /C3418BT/C3418PS/C3418PN/G2958A/G2958AE NC-3 K4J NC-3 K4L C2919PN NC-3 K4N C3419PD/C3419D/C2919PD/C2920PD/C2920PN/C2939D/G2958A/C3419PN/C3419BT NC-3 K4N-1 C3419ME NC-2K4P C2588PK/C2588PV/C2588PI A3 K5B C2151/C2151A A3 K5C C1851/C1951/C2151C/C2151Z/C2152 A3 K5DB1818/B1819/B2111/B2112/C1951/B2113/B2115/B2116/B2117/C1851K/C1853/C1951K/C2151KC1918/C2151KV/C2152K/C2152KV/C2153/C2155 A6 K6C A2113/A2116/A2117AV/C2191AV/P2119AV A6 K6C-1 P2119A/A2117/C2191A/P2119MA A6K6C-3 A2528B/ P2119B A6 K6D A2528/A2528B A6 K6D-1 A2528AV A6 K6D-2 A2528ME A6 K6E A2118/A2118ME A6 K6FA2116B A2117B A2120B A2119BC/BD R2111A R2112A/AE R2113A/AE R2117A/AE R2118A/AE/AM 2117FA 2118FA 2112FA R2120AE 2120FA 2122FA 2131FA 2112FA A6 K6G A2112B A2113B A2115B A2118B/BD A2121B A2122B R2115A/AER2116A/AE/MA 2116FA R2121A R2122/A 21A21 R2123A R2113A R2119A/AE 2115FA 21A12 A6 K6I R2518A/AE R2918A/AE A2528A/B R2517MA R2916A/AE A6 K6K 29A18TV TV TV TV TV TV TV TV TV TV TV TV TV TV TV TV TV TV TV TV TV TV TV TV TVNC-6 K7A G2966/A/B/C PF29G88A G2967/A/C/B R2916G R2917G R2918G R2919G G3898/A/C PF29G88 G3898MA G3899A R3816G R3817G R3818G R3819G NC-6 K7A-1PF29G88EA CN-7 K7B T2981/T2981A/T2982/T2982A/R3418T/34T18/34ST18/T3418 CN-5 K8A N2918 N2516 R2519NR2519MA N2918AM CN-5 K8B C2588D C2588E R2516N/FN R2518N/FN/MA 2516FN 2518FN N2918A 2916FN 2918FNR2916N/FN CN-5 K8C R2116N/2116FN/25N16/25N18/25N19 CN-5 K8D 25N16 R2118/N 2116FN 2118FN K9A D2965BT K9B K9C D2521B D2522B D2523B D2526B D2598A/B R2512D R2513D R2515D R2516D R2517D K9D D2961B D2962B D2963BD2965B D2966B R2912D R2913D R2916D R2917D R2918D R3418D K9F DP2998 DP3498 KDT1 PF1517DV KDT5ACHD2988、CHD3488、CHD2983、CHD2992A KDT5B CHD2918 、CHD3418 KDT6D CHD29181、CHD3418、CHD2990、CHD2990(A)、CHD34181、CHD3490、CHD3490(A)、 KDT6E CHD29166、CHD34166、CHD3495、CHD2995 KDT6KCHD29166（F20） KDT6H CHD29168 CHD29158 CHD29100C CHD34166(F20) KPT6E CHD2590 KT5A DP3498M、DP2998M、DP3415 KTD1 C1401DV、PF1517DV、PF2117DV、PF2981DV、PF2581DV、PF2117DV KTD4A CHD2917DV KTK3 CHD29100C、CHD34100C Y1TV Y3 TV C1742 TV CK44A,C1742 TV CHD34200 背投 K9E 29DT18 PF29DT18 51PDT18 43PDT18 DP2998 DP3488 背投东⽅影都 K8G 43PT18/43PT28/43PT28A/51PT18/51PT28/51PT28A 背投 K9E43PDT18/51PDT18/65PDT18/DP2998/29DT18/PF29DT18 背投 K9FDP4388/DP4388（01）/DP4388A/DP4389/DP4888/DP5188/DP5188（01）/DP5188A/DP5189/DP6188/ 背投 KDT6ACHD3490(A) CHD2990 CHD2990(A) 背投 KPT3A CHD3891/CHD4388 旧/CHD4390/CHD4391/CHD5188旧/CHD5190/HP3891A/HP4368/HP4388/HP4388A/HP4390/HP4390A/HP4391A/HP4888A/HP4888B/HP5168/HP5188/HP5188A/HP5189/HP5190/HP5190A/HP6188/HP7088/CHD4011W/CHD4311W 背投 KPT3B HPW6588 背投 KPT3C KP4395/KP5195 背投 KPT6A JP5185/JP5186/JP5195/JP5625/JP6125/JP7025 背投 KPT71 CHD55B5W 背投 KPT7A CHD3851/CHD38A1/CHD38C1/CHD4351/CHD4375/CHD4388新/CHD4395/CHD4890/CHD5175/CHD5188 新/HP38A1/HP38C1 /HP4375/HP4890/HP5175 背投 KPT7BCHD4011W/CHD4311W/CHD5115W 背投 KPT7C DLP5131/DLP6531W/JP5131/DLP5132/DLP5132W 背投 KPT-7C DLP5132背投 KPT7D CHD5116W 背投 KPT7E CHD5195 背投 KPT8A CHD4390/CHD5190 背投 KT5A 背投 KT8B 背投待定 CHD3852背投待定 CHD3891S 背投待定 CHD38C1S 背投待定 CHD4011FW 背投待定 CHD4352 背投待定 CHD4365 背投待定CHD4391S 背投 KPT7I CHD43B5 CHD51B5 背投待定 CHD43D5S 背投待定 CHD43E5F 背投待定 CHD43F5 背投待定CHD5117FW 背投待定 CHD51D5S 背投待定 CHD51E5F 背投待定 CHD51F5 背投待定 CHD6125 背投待定 CHD6525W 背投待定 CHD7025 背投待定 DLP5131W 背投待定 JP5615 背投待定 LCD5131W 空调 KK2 KFR-40GW/BMP KFR-36GW/BMP 空调KK4 KFR-28GW/BMP 空调 KK7B KFR-25GW/Q/EQ KFR-28GW/Q/EQ KFR-35GW/Q/EQ 空调 KK8B KFR-7LW/WDAS（L7121B）空调 KK1 KRF-33GWH KRF-28GW/WS KFR-33GW/WS KFR-30GW/WDS KFR-36GW/WDS KFR-35GW/WS KFR-34GW/WDS（C3422D） KCD-23G/WS（C3331B）KCD-23G/WS（2331A） KR-33DW/J KFR-51GW/WS KFR-33GW/S KCD-23/WS（C2331A） KR-35/WS空调空调空调空调空调空调空调 KF-25GW/W/WCS 空调空调空调空调空调空调空调空调空调空调空调空调空调空调空调空调平板平板KK1 KK10A KK10A-C3 KK10B KK11A KK2 KK3 KK4 KK5 KK5A KK5B KK5C KK5D KK5E KK5F KK6A KK7A KK7B KK7CKK8A KK8B KK8H KK9B KLC03B KLC1BKF-25GW/WS KF-34GW/WS KF-25GW/WCS KF-33DW/J KF-23GW/WS KF-34GW/WCS（G3413D）KF-51GW/WS KC-25/WS KC-35/WSKFR-51LW/D/WDS/WDES KFR-71LW/D/WDS/WDES KFR-120LW /WDS KFR-75LW /WDS KF-51LW/KF-51LW /WDS KF-71LW /WDS KF-120LW /WDS KFR-60LW /WDS/WDES KF-60LW /WS KF-75LW/W3S KFR-45LW /BMP KFR-50LW /BMP/WBQ KFR-28GW/BQ KFR-35GW/BQ KFR-40GW/BQ KFR-（4+25）0GW/BQ/ KFR-22,30,35GW/BQ KFR-22,35,40GW/Q KF-25GW/Q/EQ KF-35GW/Q/EQ / KF-40GW KFR-50LW/WDCS（L5021B）CHD-W320C6L CHD-TM201B3、CHD-TM150A1平板 KLC1B/JUL2.018.161 CHD-TM181B3/CHD-TM201B3/CHD-W170B3/M150A1T/CHD-TM181B3/CHD-TM201B3C 平板KLC1B/JUL2.018.258 CHD-TM201E3 平板 KLC3A T201E3U 平板 KLC3A-C2 W300E6U 平板 KLC3B CHD-T150E3、CHD-TM150E3、CHD-TM201E3、CHD-W300C6、CHD-W300E6N、CHD-W300E6N(A)、CHD-W320C6、CHD-W320C6L、PT4206、CHD-TM150E3/CHD-W320C6L/CHD-W300C6 /CHD-W300D6/CHD-W300E6/CHD-W320C6 平板 KLC3C PT4206、PT4206(H)/PT4206(V2 屏)PT4208(L)LG 屏/PT4208(松下屏) 平板 KLC3D-C2 CHD-W300E 平板 KLC58-9 PT5058 平板 KLC5B CHD-TM150F7、CHD-W170F7 、CHD-TD270F8、CHD-W270F8、CHD-W320F8、CHD-TD320F8、CHD-TD370F8、 CHD-W370F8/CHD-TD201F7/CHD-W260F8/CHD-TM201F7/CHD-W170F7 平板 KLC5C CHD-W320F8P 平板 PT4216 平板 PT5016平板 PT4206 视听 DK2 DVD6000 视听 VK4A VD9000 视听 DK10BDVD263/PDVD589/DVD587/DVD587A/DVD588/DVD588A/PDVD586/PDVD586A/PDVD589A 视听 DK11C DRW910A 视听DK11F HDVD600/HDVD610 视听 DK12A DVD590/DVD591 视听 DK2 DVD6000 视听 DK3 DVD5600 视听 DK4DVD6100/DVD7100 视听 DK5A DVD569E 视听 DK5B DVD568E/DVD568/DVD569视听视听视听视听视听视听视听视听视听视听视听视听视听视听视听视听视听视听视听视听视听视听视听视听视听视听DK5C DVD510 DK5F PDVD586 DK5G DVD585 DK5L DVD300/DVD310 DK5M DVD261/DVD262 DK5NDVD286/DVD262/DVD289/DVD261 DK6A DAV620 DK6A DAV620 DK9A DVD800 DK9A DVD800 DK9B DVD-P582/DVD-P652/DVD-P652A/DVD-P701B/DVD-P652B/DVD-P701A DK9C DVD-P703T/DVD-P653T DK9D DVD-P703M/DVD-P653M DVD595YKQ-CHR102 DVD595 DVD596YKQ-CHR100 DVD596 DVD598YKQ-CHR200 DVD598 DVD599YKQ-CHR301 DVD599 JDK1(JUL2.018.206) TV104G5 JUL2.018.230 DVD588 RM658 DAV658P RM659PA DAV625/DAV659PSVCD810YKQ-CHR101 SVCD810 SVCD830YKQ-CHR101 SVCD830 TK1 VD1000 VK1 VD3000 VK1A VD6000视听视听视听视听视听视听VK2 VK4 VK4A VK4B-2 VK4D VK4G LK5VD8000 VD9000 VD938 S100 S3000 S3310/S338<, BR>UK1A。

长虹LS29机芯彩电维修手册

晶振电路 VIF_CTL：伴音制式控制
HPLUG：HDMI的热插拔控制，Q6
LED_CTL：指示灯亮和熄灭的控制，Q14
CON12插座接口电路
STANDBY开机控制信号
低功耗待机控制电路
上屏电压控制电路
工厂模式进入方法 • 1、在TV模式下通过遥控器，按如下顺序输入：静音-菜单-数字键7-数字键2-数字键1-数字键7即可进入工厂模式菜单。 • 2、工厂菜单显示样式如下图： • Ver：LSC29-MXX-V0.10-WP（软件版本） • Nov 02 2009 • 09:56:22 （软件生成日期）
配备了一组PC (RGB) 信号输入终端, 能连接个人电脑，并且作为大画面的显示设备。15针的RGB终端能够十分方便的连接于电脑上。注意：此机器只有1路 HMDI接口
5
产品基本接口配置
功能和接口配置：
基本功能包含RF、1路AV输入、1路SVIDEO输入、1路YPBPR输入、1路VGA 输入、、1路HDMI输入和1Байду номын сангаасAV输出。
VGA信号流程(音频）
伴音信号流程分析
伴音信号流程分析-2
伴音电路实物图片
控制电路
ON_PANEL：Q19和Q20 组成上屏电压的控制，正常工作时Q20的基级是低电平，U18的2脚是低电平，7、8脚是5V PW_CTL：Q21和Q22组成+12V的供电控制，正常工作时Q22的基级是低电平，U18的4脚是低电平，5、6脚是12V
LS29机芯所覆盖的机型
系列 720系列 610系列整机型号 LT24720F/LT24720FX LT19610(L15) LT22610(L15) LT26610(L15) 710系列 629系列 LT32710(L15) LT37710(L15) LT19629(L15) LT22629(L15) LT26629(L15) LT32629(L15) 630系列 LT24630/LT24630X 正在首批生产完成首批正在批量生产备注说明已批量