5962-0050601Q2A中文资料
5962-9760807QYA资料
1Features•7.4SPECint95,6.1SPECfp95at 300MHz (estimated)•Superscalar (3instructions per clock peak)•Dual 16KB Caches •Selectable Bus Clock•32-bit Compatibility PowerPC Implementation •On-chip Debug Support•P D typical =3.5Watts (266MHz),Full Operating Conditions •Nap,Doze and Sleep Modes for Power Savings •Branch Folding•64-bit Data Bus (32-bit Data Bus Option)•4-Gbytes Direct Addressing Range•Pipelined Single/Double Precision Float Unit •IEEE 754Compatible FPU•IEEE P 1149-1Test Mode (JTAG/C0P)•f INT max =300MHz •f BUS max =75MHz•Compatible CMOS Input/TTL OutputScreening/Quality/PackagingThis product is manufactured in full compliance with:•CI-CGA 255:MIL-STD-883class Q or According to A TMEL-Grenoble standards •CBGA 255:Upscreenings based upon A TMEL-Grenoble standards •Full Military Temperature Range (T c =-55°C,T c =+125°C)IndustriaL Temperature Range (T c =-40°C,T c =+110°C)•Internal/IO Power Supply =2.5±5%//3.3V ±5%•255-lead CBGA Package and 255-lead CBGA with SCI (CI-CGA)PackageDescriptionThe PID7t-603e implementation of PowerPC 603e (after named 603r)is a low-power implementation of reduced instruction set computer (RISC)microprocessors Pow-erPC äfamily.The 603r implements 32-bit effective addresses,integer data types of 8,16and 32bits,and floating-point data types of 32and 64bits.The 603r is a low-power 2.5/3.3-volt design and provides four software controllable power-saving modes.The 603r is a superscalar processor capable of issuing and retiring as many as three instructions per clock.Instructions can execute out of order for increased perfor-mance;however,the 603r makes completion appear sequential.The 603r integrates five execution units and is able to execute five instructions in parallel.The 603r provides independent on-chip,16-Kbyte,four-way set-associative,physically addressed caches for instructions and data and on-chip instruction and data Memory Management Units (MMUs).The MMUs contain 64-entry,two-way set-associative,data and instruction translation look aside buffers that provide support for demand-paged virtual memory address translation and variable-sized block translation.The 603r has a selectable 32-or 64-bit data bus and a 32-bit address bus.The 603r interface protocol allows multiple masters to complete for system resources through a central external arbiter.The 603r supports single-beat and burst data transfers for memory accesses,and supports memory-mapped I/O.2TSPC603R2125A–HIREL–04/02The 603r uses an advanced,2.5/3.3V CMOS process technology and maintains full interface compatibility with TTL devices.The 603r integrates in-system testability and debugging features through JTAG boundary-scan capability.General DescriptionFigure 1.BlockDiagram3TSPC603R2125A –HIREL –04/02IntroductionThe 603r is a low-power implementation of the PowerPC microprocessor family of reduced instruction set computer (RISC)microprocessors.The 603r implements the 32-bit portion of the PowerPC architecture,which provides 32-bit effective addresses,integer data types of 8,16and 32bits,and floating-point data types of 32and 64bits.For 64-bit PowerPC microprocessors,the PowerPC architecture provides 64-bit integer data types,64-bit addressing,and other features required to complete the 64-bit architecture.The 603r provides four software controllable power-saving modes.Three of the modes (the nap,doze,and sleep modes)are static in nature,and progressively reduce the amount of power dissipated by the processor.The fourth is a dynamic power manage-ment mode that causes the functional units in the 603r to automatically enter a low-power mode when the functional units are idle without affecting operational perfor-mance,software execution,or any external hardware.The 603r is a superscalar processor capable of issuing and retiring as many as three instructions per clock.Instructions can execute out of order for increased performance;however,the 603r makes completion appear sequential.The 603e integrates five execution units —an integer unit (IU),a floating-point unit (FPU),a branch processing unit (BPU),a load/store unit (LSU)and a system register unit (SRU).The ability to execute five instructions in parallel and the use of simple instructions with rapid execution times yield high efficiency and throughput for 603r-based systems.Most integer instructions execute in one clock cycle.The FPU is pipelined so a single-precision multiply-add instruction can be issued every clock cycle.The 603r provides independent on-chip,16-Kbyte,four-way set-associative,physically addressed caches for instructions and data and on-chip instruction and data memory management units (MMUs).The MMUs contain 64-entry,two-way set-associative,data and instruction translation look aside buffers (DTLB and ITLB)that provide support for demand-paged virtual memory address translation and variable-sized block translation.The TLBs and caches use a least recently used (LRU)replacement algorithm.The 603r also supports block address translation through the use of two independent instruction and data block address translation (IBAT and DBAT)arrays of four entries each.Effec-tive addresses are compared simultaneously with all four entries in the BAT array during block translation.In accordance with the PowerPC architecture,if an effective address hits in both the TLB and BAT array,the BAT translation takes priority.The 603r has a selectable 32-or 64-bit data bus and a 32-bit address bus.The 603r interface protocol allows multiple masters to compete for system resources through a central external arbiter.The 603r provides a three-state coherency protocol that sup-ports the exclusive,modified,and invalid cache states.This protocol as a compatible subset of the MESI (modified/exclusive/shared/invalid)four-state protocol and operates coherently in systems that contain four-state caches.The 603r supports single-beat and burst data transfers for memory accesses,and supports memory-mapped I/O.The 603r uses an advanced,0.29µm 5metal layer CMOS process technology and maintains full interface compatibility with TTL devices.4TSPC603R2125A –HIREL –04/02Pin AssignmentsCBGA 255and CI-CGA 255PackagesFigure 2(pin matrix)shows the pinout as viewed from the top of the CBGA and CI-CGA packages.The direction of the top surface view is shown by the side profile of the packages.Figure 2.CBGA 255and CI –CGA 255Top View5TSPC603R2125A –HIREL –04/02Pinout ListingDDDD Table 1.Power and Ground Pins6TSPC603R2125A –HIREL –04/02DD 2.NC (no-connect)in the 603e BGA package;internally tied to GND in the 603r BGA package to indicate to the power supplythat a low-voltage processor is present.Signal DescriptionFigure 3,Table 3and Table 4describe the signals on the TSPC603r and indicate signal functions.The test signals,TRST,TMS,TCK,TDI and TDO,comply with subset P-1149.1of the IEEE testability bus standard.The 3signals LSSD_MODE,LI_TSTCLK and L2_TSTCLK are test signals for factory use only and must be pulled up to V DD for normal machine operations.Table 2.Signal Pinout Listing7TSPC603R2125A –HIREL –04/02Figure 3.Functional Signal GroupsTable 3.Address and Data Bus Signal Index8TSPC603R2125A –HIREL –04/02Table 4.Signal Index9TSPC603R2125A –HIREL –04/02Table 4.Signal Index (Continued)10TSPC603R2125A –HIREL –04/02DetailedSpecificationsScopeThis drawing describes the specific requirements for the microprocessor TSPC603r,in compliance with MIL-STD-883class B or ATMEL-Grenoble standard screening.Applicable Documents -STD-883:T est methods and procedures for -PRF-38535:General specifications for microcircuits.Requirements GeneralThe microcircuits are in accordance with the applicable documents and as specified herein.Design and Construction•Terminal connectionsThe terminal connections shall be as shown in Figure 15and Figure 3.•Lead material and finishLead material and finish shall be as specified in MIL-STD-1835.Absolute Maximum RatingsAbsolute maximum ratings are stress rating only and functional operation at the maxi-mum is not guaranteed.Stresses beyond those listed may affect device reliability or cause permanent damage to the device.Notes:1.Functional operating conditions are given in AC and DC electrical specifications.Stresses beyond the absolute maximumslisted may affect device reliability or cause permanent damage to the device.2.Caution :Input voltage must not be greater than OV DD by more than 2.5V at any times,including during power-on reset.3.Caution :OV DD voltage must not be greater than V DD /AV DD by more than 1.2V at any times,including during power-on reset.4.Caution :V DD /AV DD voltage must not be greater than OV DD by more than 0.4V at any times,including during power-on reset.(1)(2)(3)(4)TSPC603RRecommended Operating Conditions These are the recommended and tested operating conditions.Proper device operation outside of these conditions is not guaranteed.Thermal Characteristics The data found in this section concerns603r’s packaged in the255-lead21mmmulti-layer ceramic(MLC),ceramic BGA package.Data is shown for the case of usingthe Thermalloy#2328B heat sink.The internal thermal resistance for this package is negligible due to the exposed diedesign.A thermal interface material is recommended at the package lid-to-heat sinkinterface to minimize the thermal contact resistance.Additionally,the CBGA package offers an excellent thermal connection to the card andpower planes.Heat generated at the chip is dissipated through the package,the heatsink(when used)and the card.The parallel heat flow paths result in the lowest overallthermal resistance as well as offer significantly better power dissipation capability if aheat sink is not used.The thermal characteristics for the flip-chip CBGA and CI-CGA packages are as follows:Thermal resistance(junction-to-case)=R jc orθjc=0.095°C/Watt for the2packages.Thermal resistance(junction-to-ball)=R jb orθjb=3.5°C/Watt for the CBGA package.Thermal resistance(junction-to-bottom SCI)=R js orθjs=3.7°C/Watt for the CI-CGA package.The junction temperature can be calculated from the junction to ambient thermal resis-tance,as follow:Junction temperature:T j=T a+(R jc+R cs+R sa)*PWhere:T a is the ambient temperature in the vicinityof the deviceR jc is the die junction-to-case thermalresistance of the deviceR cs is the case-to-heat sink thermalresistance of the interface materialR sa is the heat sink-to-ambientthermal resistanceP is the power dissipated by the deviceDuring operation,the die-junction temperatures(T j)should be maintained less than thevalue specified in Table6.The thermal resistance of the thermal interface material(R cs)is typically about1°C/Watt.Assuming a T a of85°C and a consumption(P)of3.6Watts,the junction temperature ofthe device would be as follow:T j=85°C+(0.095°C/Watt+1°C/Watt+R sa)*3.5Watts.For the Thermalloy heat sink#2328B,the heat sink-to-ambient thermal resistance(R sa)versus airflow velocity is shown in Figure4.Figure4.CBGA Thermal Management ExampleAssuming an air velocity of1.0m/sec,the associated overall thermal resistance andjunction temperature,found in Table7will result.Table7.Thermal Resistance and Junction TemperatureVendors such as Aavid Engineering Inc.,Thermalloy,and Wakefield Engineering cansupply heat sinks with a wide range of thermal performance.Power Consideration The PowerPC603r is a microprocessor specifically designed for low-power operation.As the603e microprocessor version,the603r provides both automatic and pro-gram-controllable power reduction modes for progressive reduction of powerconsumption.This chapter describes the hardware support provided by the603r forpower management.Dynamic Power Management Dynamic power management automatically powers up and down the individual execu-tion units of the603r,based upon the contents of the instruction stream.For example,ifno floating-point instructions are being executed,the floating-point unit is automaticallypowered down.Power is not actually removed from the execution unit;instead,eachexecution unit has an independent clock input,which is automatically controlled on aclock-by-clock basis.Since CMOS circuits consume negligible power when they are notswitching,stopping the clock to an execution unit effectively eliminates its power con-sumption.The operation of DPM is completely transparent to software or any externalhardware.Dynamic power management is enabled by setting bit11in HID0onpower-up,of following HRESET.TSPC603R Programmable Power Modes The603r provides four programmable power states—full power,doze,nap and sleep.Software selects these modes by setting one(and only one)of the three power savingmode bits.Hardware can enable a power management state through external asynchro-nous interrupts The hardware interrupt causes the transfer of program flow to interrupthandler code.The appropriate mode is then set by the software.The603r provides aseparate interrupt and interrupt vector for power management—the system manage-ment interrupt(SMI).The603r also contains a decrement timer which allows it to enterthe nap or doze mode for a predetermined amount of time and then return to full poweroperation through the decrementer interrupt(DI).Note that the603r cannot switch fromon power management mode to another without first returning to full on mode.The napand sleep modes disable bus snooping;therefore,a hardware handshake is provided toensure coherency before the603r enters these power management modes.Table8summarizes the four power states.Table8.Power PC603r Microprocessor Programmable Power ModesPower Management Modes The following sections describe the characteristics of the603r’s power managementmodes,the requirements for entering and exiting the various modes,and the systemcapabilities provided by the603r while the power management modes are active.FULL-Power Mode with DPM Disabled:Full-power mode with DPM disabled powermode is selected when the DPM enable bit(bit11)in HID0is cleared.•Default state following power-up and HRESET.•All functional units are operating at full processor speed at all times.FULL-Power Mode with DPM Enabled:Full-power mode with DPM enabled(HID0[11]=1)provides on-chip power management without affecting the functionality or perfor-mance of the603r.•Required functional units are operating at full processor speed.•Functional units are clocked only when needed.•No software or hardware intervention required after mode is set.•Software/hardware and performance transparent.Doze Mode:Doze mode disables most functional units but maintains cache coherencyby enabling the bus interface unit and snooping.A snoop hit will cause the603r toenable the data cache,copy the data back to memory,disable the cache,and fullyreturn to the doze state.•Most functional units disabled.•Bus snooping and time base/decrementer still enabled.•Dose mode sequence:-Set doze bit(HID0[8)=1).-603r enters doze mode after several processor clocks.•Several methods of returning to full-power mode:-Assert INT,SMI,MCP or decrementer interrupts.-Assert hard reset or soft reset.•T ransition to full-power state takes no more than a few processor cycles.•PLL running and locked to SYSCLK.Nap Mode:The nap mode disables the603r but still maintains the phase locked loop (PLL)and the time base/decrementer.The time base can be used to restore the603r to full-on state after a programmed amount of time.Because bus snooping is disabled for nap and sleep mode,a hardware handshake using the quiesce request and quiesce acknowledge signals are requires to maintain data coherency.The 603r will assert the signal to indicate that it is ready to disable bus snooping. When the system has ensured that snooping is no longer necessary,it will assertand the603r will enter the sleep or nap mode.•Time base/decrementer still enabled.•Most functional units disabled(including bus snooping).•All nonessential input receivers disables.•Nap mode sequence:-Set nap bit(HID0[9]=1)-603r asserts quiesce request signal-System asserts quiesce acknowledge signal-603r enters sleep mode after several processor clocks•Several methods of returning to full-power mode:-Assert INT,SPI,MCP or decrementer interrupts-Assert hard reset or soft reset•T ransition to full-power takes no more than a few processor cycles.•PLL running and locked to SYSCLK.Sleep Mode:Sleep mode consumes the least amount of power of the four modes since all functional units are disabled.To conserve the maximum amount of power,the PLL may be disabled and the SYSCLK may be removed.Due to the fully static design of the 603r,internal processor state is preserved when no internal clock is present.Because the time base and decrementer are disabled while the603r is in sleep mode,the603r’s time base contents will have to be updated from an external time base following sleep mode if accurate time-of-day maintenance is required.Before the603r enters the sleep mode,the603r will assert the QREQ signal to indicate that it is ready to disable bus snooping.When the system has ensured that snooping is no longer necessary,it will assert QACK and the603r will enter the sleep mode.•All functional units disabled(including bus snooping and time base).•All nonessential input receivers disabled:-Internal clock regenerators disabled-PLL still running(see below)•Sleep mode sequence:-Set sleep bit(HID0[10]=1)-603r asserts quiesce request-System asserts quiesce acknowledge-603r enters sleep mode after several processor clocksTSPC603R•Several methods of returning to full-power mode:-Assert INT ,SMI,or MCP interrupts -Assert hard reset or soft reset•PLL may be disabled and SYSCLK may be removed while in sleep mode.•Return to full-power mode after PLL and SYSCLK disabled in sleep mode:-Enable SYSCLK-Reconfigure PLL into desired processor clock mode-System logic waits for PLL startup and relock time (100µsec)-System logic asserts one of the sleep recovery signals (for example,INT or SMI)Power Management Software ConsiderationsSince the 603r is a dual issue processor with out-of-order execution capability,care must be taken in how the power management mode is entered.Furthermore,nap and sleep modes require all outstanding bus operations to be completed before the power management mode is entered.Normally during system configuration time,one of the power management modes would be selected by setting the appropriate HID0mode ter on,the power management mode is invoked by setting the MSR[POW]bit.To pro-vide a clean transition into and out of the power management mode,the stmsr [POW]should be preceded by a sync instruction and followed by an isync instruction.Power DissipationDD power (AV DD ).OV DD power is system dependent but is typically ≤10%of V DD .Worst-case AV DD =15mW.2.Typical power is an average value measured at V DD =AV DD =2.5V ,OV V =3.3V ,in a system executing typical applicationsand benchmark sequences.3.Maximum power is measured at V DD =2.625V using a worst-case instruction mix.4.To calculate the power consumption at low temperature (-55°C),use a factor of 1.25.Table 9.Power Dissipation (1)(2)(3)(4)V DD /A V DD =2.5±5%V,O V DD =3.3±5%V,GND =0V,0°C ≤T C ≤125°C CPU Clock FrequencyMarking Each microcircuit is legible and permanently marked with the following information asminimum:•A TMEL logo•Manufacturer’s part number•Class B identification if applicable•Date-code of inspection lot•ESD identifier if available•Country of manufacturingElectrical CharacteristicsGeneral Requirements All static and dynamic electrical characteristics specified for inspection purposes and therelevant measurement conditions are given below:•Table10:Static electrical characteristics for the electrical variants•Table11:Dynamic electrical characteristics for the603rThese specifications are for166MHz to300MHz processor core frequencies.The pro-cessor core frequency is determined by the bus(SYSCLK)frequency and the settings ofthe PLL_CFG0to PLL_CFG3signals.All timings are respectively specified to the risingedge of SYSCLK.Static CharacteristicsTable10.Electrical CharacteristicsV=A V=2.5V±5%;O V=3.3±5%V,GND=0V,-55°C≤TC≤125°C2.Capacitance is periodically sampled rather than100%tested.3.Leakage currents are measured for nominal OV DD and V DD or both OV DD and V DD.Same variation(for example,both V DDand OV DD vary by either+5%or-5%).TSPC603RDynamic Characteristics•Clock AC SpecificationsTable 11provides the clock AC timing specifications as defined in Figure 5.2.Cycle-to-cycle jitter is guaranteed by design.3.Timing is guaranteed by design and characterization,and is not tested.4.PLL relock time is the maximumamount of time required for PLL lock after a stable V DD ,OV DD ,AV DD and SYSCLK are reached during the power-on reset sequence.This specification also applies when the PLL has been disabled and subse-quently re-enabled during sleep mode.Also note that must be held asserted for a minimum of 255bus clocks after the PLL relock time (100µs)during the power-on reset sequence.5.Caution :The SYSCLK frequency and PLL_CFG[0-3]settings must be chosen such that the resulting SYSCLK (bus)fre-quency ,CPU (core)frequency,and PLL (VCO)frequency do not exceed their respective maximum or minimum operating frequencies.Refer to the PLL_CFG[0-3]signal description for valid PLL_CFG[0-3]settings.Figure 5.SYSCLK Input Timing DiagramTable 11.Clock AC Timing Specifications (1)(2)(3)(4)V V V•Input AC specificationsTable 12provides the input AC timing specifications for the 603r as defined in Figure 6and Figure 7.of the input SYSCLK.Both input and output timings are measured at the pin.See Figure 7.2.Address/data/transfer attribute input signals are composed of thefollowing:A[0-31],AP[0-3],TT[0-4],TC[0-1],TBST,TSIZ[0-2],DH[0-31],DL[0-31],DP[9-7].3.All other input signals are composed of the following:TS,ABB,DBB,ARTRY ,BG,AACK,DBG,DBWO,TA,DRTRY ,TEA,,TBEN,4.The setup and hold time is with respect to the rising edge of HRESET.See Figure 7.5.t sysclk is the period of the external clock (SYSCLK)in nanoseconds (ns).The numbers given in the table must be multipliedby the period of SYSCLK to compute the actual time duration (in nanoseconds)of the parameter in question.6.These values are guaranteed by design,and are not tested.7.This specification is for configuration mode only.Also note that HRESET must be held asserted for a minimum of 255busclocks after the PLL relock time (100µs)during the power-on reset sequence.Figure 6.Input Timing DiagramTable 12.Input AC Timing Specifications (1)V V VTSPC603R Figure7.Mode Select Input Timing Diagram•Output AC SpecificationsTable13provides the output AC timing specifications for the603r(shown in Figure8). Table13.Output AC Timing Specifications(1)(2)V=A V=2.5V±5%;O V=3.3±5%V,GND=0V,C=50pF,-55°C≤Tnal in question.Both input and output timings are measured at the pin.See Figure8.2.All maximum timing specifications assume C L=50pF.3.This minimum parameter assumes C L=0pF.4.SYSCLK to output valid(5.5V to0.8V)includes the extra delay associated with discharging the external voltage from5.5V to0.8V instead of from V DD to0.8V(5V CMOS levels instead of3.3V CMOS levels).5.t sysclk is the period of the external bus clock(SYSCLK)in nanoseconds(ns).The numbers given in the table must be multi-plied by the period of SYSCLK to compute the actual time duration(ns)of the parameter in question.6.Output signal transitions from GND to2.0V or V DD to0.8V.7.Nominal precharge width for ABB and DBB is0.5*t sysclk.8.Nominal precharge width for is1.0*t sysclk.Figure8.Output Timing DiagramJTAG AC TimingSpecificationsTable14.JTAG AC Timing Specifications(independent of SYSCLK)V=A V=2.5V±5%;O V=3.3±5%V,GND=0V,C=50pF,-55°C≤T21TSPC603R2125A –HIREL –04/022.Non-test signal input timing with respect to TCK.3.Non-test signal output timing with respect to TCK.Figure 9.Clock Input Timing DiagramFigure 10.TRST Timing DiagramTable 14.JTAG AC Timing Specifications (independent of SYSCLK)V =A V =2.5V ±5%;O V =3.3±5%V,GND =0V,C =50pF,-55°C ≤T22TSPC603R2125A –HIREL –04/02Figure 11.Boundary-scan Timing DiagramFigure 12.Test Access Port Timing DiagramFunctional DescriptionPowerPC Registers andProgramming Model The PowerPC architecture defines register-to-register operations for most computa-tional instructions.Source operands for these instructions are accessed from theregisters or are provided as immediate values embedded in the instruction opcode.Thethree-register instruction format allows specification of a target register distinct from thetwo source operands.Load and store instructions transfer data between registers andmemory.PowerPC processors have two levels of privilege -supervisor mode of operation (typi-cally used by the operating system)and user mode of operation (used by the applicationsoftware).The programming models incorporate 32GPRs,32FPRs,special-purposeregisters (SPRs)and several miscellaneous registers.Each PowerPC microprocessoralso has its own unique set of hardware implementation (HID)registers.23TSPC603R2125A –HIREL –04/02Having access to privilege instructions,registers,and other resources allows the operat-ing system to control the application environment (providing virtual memory andprotecting operating-system and critical machine resources).Instructions that controlthe state of the processor,the address translation mechanism,and supervisor registerscan be executed only when the processor is operating in supervisor mode.The following sections summarize the PowerPC registers that are implemented in the603r.General-Purpose Registers(GPRs)The PowerPC architecture defines 32user-level,general-purpose registers (GPRs).These registers are either 32bits wide in 32-bit PowerPC microprocessors and 64bitswide in 64-bit PowerPC microprocessors.The GPRs serve as the data source or desti-nation for all integer instructions.Floating-Point Registers(FPRs)The PowerPC architecture also defines 32user-level,64-bit floating-point registers (FPRs).The FPRs serve as the data source or destination for floating-point instructions.These registers can contain data objects of either single-or double-precision float-ing-point formats.Condition Register (CR)The CR is a 32-bit user-level register that consists of eight four-bit fields that reflect theresults of certain operations,such as move,integer and floating-point compare,arith-metic,and logical instructions,and provide a mechanism for testing and branching.Floating-Point Status andControl Register (FPSCR)The floating-point status and control register (FPSCR)is a user-level register that con-tains all exception signal bits,exception summary bits,exception enable bits,androunding control bits needed for compliance with the IEEE 754standard.Machine State Register (MSR)The machine state register (MSR)is a supervisor-level register that defines the state ofthe processor.The contents of this register are saved when an exception is taken andrestored when the exception handling completes.The 603r implements the MSR as a32-bit register,64-bit PowerPC processors implement a 64-bit MSR.Segment Registers (SRs)For memory management,32-bit PowerPC microprocessors implement sixteen 32-bitsegment registers (SRs).To speed access,the 603r implements the segment registersas two arrays;a main array (for data memory accesses)and a shadow array (for instruc-tion memory accesses).Loading a segment entry with the Move to Segment Register(STSR)instruction loads both arrays.。
5962-9650501QXA资料
LM2991Negative Low Dropout Adjustable RegulatorGeneral DescriptionThe LM2991is a low dropout adjustable negative regulator with a output voltage range between −3V to −24V.The LM2991provides up to 1A of load current and features a On /Off pin for remote shutdown capability.The LM2991uses new circuit design techniques to provide a low dropout voltage,low quiescent current and low tempera-ture coefficient precision reference.The dropout voltage at 1A load current is typically 0.6V and a guaranteed worst-case maximum of 1V over the entire operating tem-perature range.The quiescent current is typically 1mA with a 1A load current and an input-output voltage differential greater than 3V.A unique circuit design of the internal bias supply limits the quiescent current to only 9mA (typical)when the regulator is in the dropout mode (V OUT −V IN ≤3V).The LM2991is short-circuit proof,and thermal shutdown in-cludes hysteresis to enhance the reliability of the device when inadvertently overloaded for extended periods.The LM2991is available in 5-lead TO-220and TO-263packages and is rated for operation over the automotive temperature range of −40˚C to +125˚-Aero versions are also avail-able.Featuresn Output voltage adjustable from −3V to −24V,typically −2V to −25Vn Output current in excess of 1An Dropout voltage typically 0.6V at 1A load n Low quiescent currentn Internal short circuit current limitn Internal thermal shutdown with hysteresis n TTL,CMOS compatible ON/OFF switchn Functional complement to the LM2941seriesApplicationsn Post switcher regulator n Local,on-card,regulation n Battery operated equipmentTypical ApplicationDS011260-1V OUT =V REF (1+R2/R1)*Required if the regulator is located further than 6inches from the power supply filter capacitors.A 1µF solid tantalum or a 10µF aluminum electrolytic capacitor is recommended.**Required for stability.Must be at least a 10µF aluminum electrolytic or a 1µF solid tantalum to maintain stability.May be increased without bound to maintain regulation during transients.Locate the capacitor as close as possible to the regulator.The equivalent series resistance (ESR)is critical,and should be less than 10Ωover the same operating temperature range as the regulator.May 1999LM2991Negative Low Dropout Adjustable Regulator©1999National Semiconductor Corporation Connection Diagrams and Ordering Information5-Lead TO-220Straight LeadsDS011260-9Front ViewOrder Number LM2991T See NS Package Number T05A5-Lead TO-220Bent,Staggered LeadsDS011260-2Front ViewOrder Number LM2991T Flow LB03See NS Package Number T05DTO2635-Lead Surface-Mount PackageDS011260-11Top ViewDS011260-12Side ViewOrder Number LM2991S See NS Package Number TS5B16-Lead Ceramic Dual-in-Line PackageDS011260-29Top ViewOrder Number LM2991J-QMLV5962-9650501VEAOrder Number LM2991J-QML5962-9650501QEASee NS Package Number J16A16-Lead Ceramic Surface-Mount PackageDS011260-30Top ViewOrder Number LM2991WG-QML5962-9650501QXASee NS Package Number WG16A 2Absolute Maximum Ratings(Note1)If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.Input Voltage−26V to+0.3V ESD Susceptibility(Note2)2kV Power Dissipation(Note3)Internally limited Junction Temperature(T Jmax)125˚C Storage Temperature Range−65˚C to+150˚C Lead Temperature(Soldering,10sec.)230˚COperating Ratings(Note1)Junction Temperature Range(T J)−40˚C to+125˚C Maximum Input Voltage(Operational)−26VElectrical CharacteristicsV IN=−10V,V O=−3V,I O=1A,C O=47µF,R1=2.7k,T J=25˚C,unless otherwise specified.Boldface limits apply overthe entire operating junction temperature range.Parameter Conditions Typical Min Max Units(Note4)Reference Voltage5mA≤I O≤1A−1.210−1.234−1.186V5mA≤I O≤1A,−1.27−1.15VV O−1V≥V IN≥−26VOutput Voltage−2−3V Range V IN=−26V−25−24V Line Regulation I O=5mA,V O−1V≥V IN≥−26V0.0040.04%/V Load Regulation50mA≤I O≤1A0.040.4% Dropout Voltage I O=0.1A,∆V O≤100mV0.10.2V0.3I O=1A,∆V O≤100mV0.60.8V1Quiescent Current I O≤1A0.75mA Dropout Quiescent V IN=V O,I O≤1A1650mA CurrentRipple Rejection V ripple=1Vrms,f ripple=1kHz,6050dBI O=5mAOutput Noise10Hz−100kHz,I O=5mA200450µVON/OFF Input(V OUT:ON) 1.20.8V Voltage(V OUT:OFF) 1.3 2.4ON/OFF Input V ON/OFF=0.8V(V OUT:ON)0.110µA Current V ON/OFF=2.4V(V OUT:OFF)40100Output Leakage V IN=−26V,V ON/OFF=2.4V60250µA Current V OUT=0VCurrent Limit V OUT=0V2 1.5ANote1:Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.Operating Ratings indicate conditions for which the deivce is in-tended to be functional,but do not guarantee specific performance limits.For guaranteed specifications and test conditions,see the Electrical Characteristics.Note2:Human body model,100pF discharged through a1.5kΩresistor.Note3:The maximum power dissipation is a function of T Jmax,θJA and T A.The maximum allowable power dissipation at any ambient temperature is P D=(T Jmax−T A)/θJA.If this dissipation is exceeded,the die temperature will rise above125˚C and the LM2991will go into thermal shutdown.For the LM2991,the junction-to-ambient thermal resistance is53˚C/W for the TO-220,73˚C/W for the TO-263,and junction-to-case thermal resistance is3˚C.If the TO-263package is used,the thermal resistance can be reduced by increasing the PC board copper area thermally connected to the ing0.5square inches of copper area,θJA is50˚C/W;with1square inch of copper area,θJA is37˚C/W;and with1.6or more square inches of copper area,θJA is32˚C/W.Note4:Typicals are at T J=25˚C and represent the most likely parametric norm.3Typical Performance CharacteristicsDropout VoltageDS011260-13Normalized Output VoltageDS011260-14Output VoltageDS011260-15Output Noise Voltage DS011260-16Quiescent Current DS011260-17Maximum Output CurrentDS011260-18Line Transient Response DS011260-19Load Transient Response DS011260-20Maximum Output CurrentDS011260-21Ripple Rejection DS011260-22Output Impedance DS011260-23ON /OFF Control VoltageDS011260-24 4Typical Performance Characteristics(Continued)Application HintsEXTERNAL CAPACITORSThe LM2991regulator requires an output capacitor to main-tain stability.The capacitor must be at least 10µF aluminum electrolytic or 1µF solid tantalum.The output capacitor’s ESR must be less than 10Ω,or the zero added to the regu-lator frequency response by the ESR could reduce the phase margin,creating oscillations.The shaded area in the Output Capacitor ESR graph indicates the recommended ESR range.An input capacitor,of at least 1µF solid tantalum or 10µF aluminum electrolytic,is also needed if the regulator is situated more than 6inches from the input power supply filter.MINIMUM LOADA minimum load current of 500µA is required for proper op-eration.The external resistor divider can provide the mini-mum load,with the resistor from the adjust pin to ground set to 2.4k Ω.SETTING THE OUTPUT VOLTAGEThe output voltage of the LM2991is set externally by a resis-tor divider using the following equation:V OUT =V REF x (1+R 2/R 1)−(I ADJ x R 2)where V REF =−1.21V.The output voltage can be pro-grammed within the range of −3V to −24V,typically an evenAdjust Pin CurrentDS011260-25Low Voltage BehaviorDS011260-26Maximum Power Dissipation (TO-220)DS011260-27Maximum Power Dissipation (TO-263)(See Note 3)DS011260-28Output Capacitor ESR RangeDS011260-55Application Hints(Continued)greater range of −2V to −25V.The adjust pin current is about 60nA,causing a slight error in the output voltage.However,using resistors lower than 100k Ωmakes the adjust pin cur-rent negligible.For example,neglecting the adjust pin cur-rent,and setting R2to 100k Ωand V OUT to −5V,results in an output voltage error of only 0.16%.ON/OFF PINThe LM2991regulator can be turned off by applying a TTL or CMOS level high signal to the ON/OFF pin (see Adjustable Current Sink Application).FORCING THE OUTPUT POSITIVEDue to an internal clamp circuit,the LM2991can withstand positive voltages on its output.If the voltage source pulling the output positive is DC,the current must be limited to 1.5A.A current over 1.5A fed back into the LM2991could damage the device.The LM2991output can also withstand fast posi-tive voltage transients up to 26V,without any current limiting of the source.However,if the transients have a duration of over 1ms,the output should be clamped with a Schottky di-ode to ground.Typical ApplicationsFully Isolated Post-Switcher RegulatorDS011260-6Adjustable Current SinkDS011260-10 6Equivalent SchematicD S 011260-87Physical Dimensions inches(millimeters)unless otherwise noted5-Lead T0-220,Straight Leads(T)Order Number LM2991TNS Package Number T05A5-Lead T0-220,Bent,Staggered Leads(T)Order Number LM2991T Flow LBO3NS Package Number T05D8Physical Dimensions inches(millimeters)unless otherwise noted(Continued)TO-2635-Lead Plastic Surface Mount PackageOrdering Number LM2991SNS Package Number TS5B9Physical Dimensions inches(millimeters)unless otherwise noted(Continued)16-Lead Ceramic Dual-in-Line PackageOrder Number LM2991J-QMLV5962-9650501VEAOrder Number LM2991J-QML5962-9650501QEANS Package Number J16A10Physical Dimensionsinches (millimeters)unless otherwise noted (Continued)LIFE SUPPORT POLICYNATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION.As used herein:1.Life support devices or systems are devices or systems which,(a)are intended for surgical implant into the body,or (b)support or sustain life,and whose failure to perform when properly used in accordance with instructions for use provided in the labeling,can be reasonably expected to result in a significant injury to the user.2.A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system,or to affect its safety or effectiveness.National Semiconductor Corporation AmericasTel:1-800-272-9959Fax:1-800-737-7018Email:support@National Semiconductor EuropeFax:+49(0)180-5308586Email:europe.support@Deutsch Tel:+49(0)180-5308585English Tel:+49(0)180-5327832Français Tel:+49(0)180-5329358Italiano Tel:+49(0)180-5341680National Semiconductor Asia Pacific Customer Response Group Tel:65-2544466Fax:65-2504466Email:sea.support@National Semiconductor Japan Ltd.Tel:81-3-5639-7560Fax:81-3-5639-750716-Lead Ceramic Surface-Mount PackageOrder Number LM2991WG-QML5962-9650501QXANS Package Number WG16ALM2991Negative Low Dropout Adjustable RegulatorNational does not assume any responsibility for use of any circuitry described,no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.元器件交易网。
API-526-2009(中文版)-上
API-526-2009(中文版)-上钢制法兰连接泄压阀——标准API 5262009年4月，第6版钢制法兰连接泄压阀1 范围此标准是钢制法兰连接泄压阀的采购规范。
弹簧直接荷载式和先导操作泄压阀的基本要素如下：——流道命名及面积——阀门进、出口规格及压力等级——材料——压力温度额定值——进、出口中心到法兰面的尺寸2 引用标准下列引用的文件对本文件的应用是不可缺少的。
对于标明日期的引用文件，仅该版适用。
未标明日期的引用文件，其最新版（包括任何修改）适用。
推荐规程API 520（所有部分），规格，选型及泄压设备现安装标准API 527，泄压阀阀座密封ASME B16.5，管法兰和法兰组件ASME 锅炉和压力容器规范（BPVC），第Ⅷ卷：压力容器，第1、2篇ASME BPVC，第Ⅱ部分：材料：ASME SA-216，可熔焊高温碳钢铸件ASME SA-217，高温承压马氏体及合金钢铸件ASME SA-351，承压奥氏体，奥氏体-铁素体（双相）钢铸件ASME SA-494，镍及镍合金铸件3 术语和定义API 520第Ⅰ部分定义了泄压阀术语。
4 责任4.1 买方为下列内容负首要责任：a）选择泄压阀的型号及所需的压力温度等级；b）指定材料能够抗工艺流体和环境腐蚀；c）基于排泄条件选择最小的流道面积。
排泄条件来自对泄压系统全面认识及适用规范和法规的要求；d）提供规格和选型数据。
4.2 制造方为下列内容负首要责任：a）设计制造的泄压阀满足本标准和采购规范的要求；b）发布基于认证测试数据的排泄能力；K 1.838L 2.853M 3.60N 4.34P 6.38Q 11.05R 16.00T 26.007 设计7.1 一般要求本标准讨论的泄压阀的设计制造应符合ASME BPVC第Ⅷ卷泄压设备的应用要求。
7.2 流道面积的确定最小有效流道面积应根据API 520第1部分确定。
7.3 阀门选型本标准中描述的阀门，进出口法兰规格和压力温度等级应按照表3到表16（弹簧荷载式泄压阀）和表17到表30（先导操作泄压阀）中的数据。
5962-8874701YA中文资料
3.3HERMETIC TO-3 FIXED VOLTAGE NEGATIVEREGULATORS APPROVED TO DESC DRAWINGSFEATURES•Output Voltages: -5V, -12V, -15V•Output Voltages Set Internally to ±1%•Built-In Thermal Overload Protection•Short Circuit Current Limiting•Similar To Industry Standards 7905, 7912, 7915•Hi-Rel Screening AvailableDESCRIPTIONThese three terminal negative regulators are supplied in a hermetically sealed TO-3metal package . All protective features are designed into the circuit, including thermal shutdown, current limiting and safe-area control. With heat sinking, they can deliver over 1.5 amps of output current. These units feature internally trimmed output voltages to ±1% of nominal voltage. Standard voltages are -5V, -12V, -15V. These units are ideally suited for Military applications where a hermetically sealed package is required.PART NUMBER DESIGNATORStandard Military Drawing Number Omnirel Part Number5962-8874601 YX OM1905NKM5962-8874701 YX OM1912NKM5962-8874801 YX OM1915NKMOM1915NKM OM1905NKM OM1912NKMOM1905NKM - OM1915NKM3.3ELECTRICAL CHARACTERISTICS -5 Volt VIN= -10V, I o= 500mA, -55°C T A 125°C (unless otherwise specified) Parameter Symbol Test Conditions Min.Max.UnitOutput Voltage V OUT T A= 25°C-4.95-5.05VV IN= -7.5V to -20V•-4.85-5.15VI O = 5mA to 1.0 A, P<20WLine Regulation V RLINE V IN= -7.5V to -20V12mV (Note 1)•25mV(Note 4)V IN= -8.0V to -12V5mV•12mV Load Regulation V RLOAD I O = 5mA to 1.5 Amp20mV (Note 1)•25mVI O = 250mA to 750 mA15mV•30mV Standby Current Drain I SCD 2.5mA• 3.0mA Standby Current Drain D I SCD V IN= -7.0V to -20V•0.4mA Change With Line(Line)Standby Current Drain D I SCD I O= 5mA to 1000mA•0.4mA Change With Load(Load)Dropout Voltage V DO D V OUT= 100mV, I O=1.0A• 2.5V Peak Output Current I O (pk) T A= 25°C 1.5 3.3A Short Circuit Current I DS V IN= -35V 1.2A (Note 2)• 2.8A Ripple Rejection D V IN f =120 Hz, D V IN= -10V63dBD V OUT(Note 3)•60dBOutput Noise Voltage N O T A= 25°C, f =10 Hz to 100KHz40µV/V (Note 3)RMS Long Term Stability D V OUT T A= 25°C, t = 1000 hrs.75mV (Note 3)D tNotes:1.Load and Line Regulation are specified at a constant junction temperature. Pulse testing with low duty cycle is used.Changes in output voltage due to heating effects must be taken into account separately.2.Short Circuit protection is only assured up to V IN= -35V.3.If not tested, shall be guaranteed to the specified limits.The • denotes the specifications which apply over the full operating temperature range.ABSOLUTE MAXIMUM RATINGS @ 25°CInput Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -35 V Operating Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . .- 55°C to + 150°C Storage Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65°C to + 150°C Typical Power/Thermal Charateristics:Rated Power @ 25°C T C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20WT A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6W Thermal Resistance q JC . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2°C/W aa q JA.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42°C/WOM1905NKM - OM1915NKM3.3PLANE2 PLCS.Pin Connection Pin 1: Ground Pin 2: Output Case: InputOM1905NKM - OM1915NKM3.3。
5962-88769022A资料
Hermetically Sealed,Wide Supply Voltage OptocouplersReliability Data SheetDescriptionThe reliability data shown includes Agilent reliability test data from the past three years on this product family. All of these products use the same LEDs, the same logic gate ICs, the same DSCC approved packaging materials, processes, stress conditions and testing.The data in Tables 1 and 2 reflect actual test data on dual channel devices. The single channel HCPL-5201 data in Table 3 is inferred from the demonstrated life test data using the factor (1.5) found in the “Photodiode Detector Isolator” section of MIL-HDBK-217, combined with any single channel data obtained. This dataDefinition of FailureInability to switch, i.e., “functional failure”, is the definition of failure in this data sheet. Specifically,failure occurs when the device fails to switch ON with 2 times the minimum recommended drive current (but not exceeding the max. rating) or fails to switch OFF when there is no input current.Failure Rate ProjectionsThe demonstrated point mean time to failure (MTTF) is measured at the absolutemaximum stress condition. The failure rate projections in Tables 2and 3 use the Arrheniusacceleration relationship, where a 0.43 eV activation energy is used as in the hybrid section of MIL-HDBK-217.Applications InformationThe data of Tables 1, 2, and 3 were obtained on MIL-PRF-38534screened devices with high temperature operating life duration up to 5000 hours. An exponential (random) failuredistribution is assumed, expressed in units of FIT (failures per billionis taken from testing on Agilent Technologies’ devices using internal Agilent processes,material specifications, design standards, and statistical process controls. THEY ARE NOT TRANSFERABLE TO OTHER MANUFACTURERS’ SIMILAR PART TYPES.device hours) are only defined in the random failure portion of the reliability curve.For valid system reliability calculations, it is necessary to adjust for the time when the system is not in operation.Note that if you are using MIL-HDBK-217 for predictingcomponent reliability, the results may not be comparable to those given in Tables 2 and 3 due to the different conditions and factorsOperating Life TestTable 1. Demonstrated Operating Life Test Performance, HCPL-5231Demonstrated Demonstrated Stress Test Total Devices Total Device Number of MTTF (hr)@FITs @Condition Tested Hours Failed Units T A = +125°C T A = +125°C I f = 8 mA 4301,747,00011,747,000572I out = -15 mA V CC = 20 V T A = +125°C T j = +155°CAgilent5962-8876901PX, 5962-8876904KPX HCPL-5231, HCPL-523K5962-8876801PX, 5962-8876802KPX HCPL-5201, HCPL-520K5962-88769022A, 5962-8876905K2A HCPL-6231, HCPL-623K5962-8876903FC, 5962-8876906KFC HCPL-6251, HCPL-625K Data subject to change.Copyright © 2000 Agilent Technologies, Inc.Obsoletes 5967-6008E 5968-9397E (2/00)Environmental TestingAll high reliability hermeticoptocouplers listed meet the 100%screening and qualityconformance inspection testing of MIL-PRF-38534, class H or class K as applicable.Table 4. ESDS Classification per Method 3015, MIL-STD-883that have been accounted for in MIL-HDBK-217. For example, it is unlikely that your application will exercise all available channels at full rated power with the LED(s)always ON as Agilent testing does.Thus, your application total power and duty cycle must be carefullyconsidered when comparing Tables 2 and 3 to predictions using MIL-HDBK-217.Electrostatic Discharge SensitivityPart NumberESD Class 5962-8876904KPX, HCPL-523K 35962-8876901PX, HCPL-523135962-8876802KPX, HCPL-520K 15962-8876801PX, HCPL-520115962-8876905K2A, HCPL-623K 15962-88769022A, HCPL-623115962-8876906KFC, HCPL-625K 35962-8876903FC, HCPL-62513Table 3. Reliability Projections for Single Channel Devices Listed in Title Typical (60% Confidence)90% Confidence AmbientJunctionMTTF FITs MTTF FITs Temperature (°C)Temperature (°C)(hr/fail)(fail/109hr)(hr/fail)(fail/109hr))1251451,297,000771674,0001,4841201401,498,000668778,0001,2851101302,018,0004961,051,0009521001202,759,0003621,440,000695901103,836,0002612,006,000499801005,429,0001842,844,00035270907,830,0001284,111,000243608011,531,000876,069,000165507017,369,000589,164,000109406026,814,0003714,186,00070305042,522,0002422,560,00044254554,133,0001828,763,00035Table 2. Reliability Projections for Dual Channel Devices Listed in Title Typical (60% Confidence)90% Confidence AmbientJunctionMTTF FITs MTTF FITs Temperature (°C)Temperature (°C)(hr/fail)(fail/109hr)(hr/fail)(fail/109hr))125155865,0001,157449,0002,227120150992,0001,009515,0001,9411101401,317,000759686,0001,4581001301,774,000564925,0001,081901202,427,0004121,268,000789801103,374,0002961,767,000566701004,774,0002092,505,00039960906,886,0001453,622,000276508010,141,000995,346,000187407015,274,000658,073,000124306023,580,0004212,496,00080255529,589,0003415,703,00064。
API598中文
最小试验压力
试验项目
磅／平方英寸(表压) 巴
阀门(蝶阀和止回阀除外)
高压密封和上密封
低压密封和上密封
60-100
4-7
蝶阀
高压密封
低压密封
60-100
4-7
止回阀
高压密封
125 磅级(铸铁)
NPS 2～12
200 14
NPS14～48
150 11
250 磅级(铸铁)
NPS 2～12
500 35
NPS 14～24
0
C
D
24
C
D
40
C
D
56
c
D
· 对于液体试验，1毫升(cm3)相当于16滴。 ：在规定的最短试验持续时间内(见表4)无泄漏．对于液体试验，“o”滴表示在每 个规定的最短试验持续即闭 内无可见泄漏．对于气体试验，“o”气泡表示在每个规定的最短试验持续时间内泄 漏量小于1个气泡。 ‘最大允许泄漏率应是公称通径每英寸每分钟o．18立方英寸(3cm)。 ‘最大允许泄漏率应是公称通径每英寸每小时1．5标准立方英尺(o．04Zm')。 ·对于规格大于NPS 24的止回阀，允许的泄漏率应由买方与制造厂商定。 3．9．3 使用非金属(如，陶瓷)密封材料的阀门，其密封试验的允许泄漏率应与表5规 定的同类型和规格的金属密封阀门相同。 第4章 压力试验方法 4．1 概述 4．1．1 对于具有允许应急的或补充的向密封面或填料部位注入密封脂这种结构的阀 门，在试验时，注入系统应是空的和不起作用的，油封式旋塞阀除外。 4．1．2 当液体作为试验介质进行试验时，阀门内应基本上没有空气。 4．1．3 要求的保护涂层，如油漆，可能掩盖表面缺陷。在检查和压力试验前，任何 表面不应有这类涂层(磷化处理或类似的化学处理用于保护阀门表面是允许的，甚至可 在试验前进行，只要这类处理不掩盖气孔等缺陷)。 4．1．4 当进行闸阀、旋塞阀和球阀密封试验时，阀门制造厂应采用这样的试验方法， 在阀座和阀盖间的阀体腔内注满介质并加压。这样能确保不至由于在试验中逐渐向上述 部位充注介质和加压而使密封面的泄漏未被察觉。 4．1．5 当进行阀门密封试验时，阀门制造厂的试验方法应能确保不使用过大的力来 关闭阀门．所 施加的关闭力可在MSSSP--91的适当数值中确定，但在任何情况下这个力不能超过阀门 制造广 公布的值。 4．2 壳体试验
5082-A901-MO000资料
Features• Low Power Consumption • Industry Standard Size• Industry Standard Pinout • Choice of Character Size7.6 mm (0.30 in), 10 mm (0.40 in), 10.9 mm (0.43 in), 14.2 mm (0.56 in), 20 mm (0.80 in)• Choice of ColorsAlGaAs Red, High Efficiency Red (HER), Yellow, Green• Excellent Appearance Evenly Lighted Segments±50° Viewing Angle• Design FlexibilityCommon Anode or Common CathodeSingle and Dual DigitLeft and Right Hand Decimal Points±1. Overflow Character• Categorized for Luminous IntensityYellow and Green Categorized for ColorUse of Like Categories Yields a Uniform Display• Excellent for Long Digit String Multiplexing DescriptionThese low current seven segment displays are designed for applica-tions requiring low power consumption. They are tested and selected for their excellent low current characteristics to ensure that the segments are matched at low currents. Drive currents as low as 1 mA per segment are available.Pin for pin equivalent displays are also available in a standard current or high light ambient design. The standard current displays are available in all colors and are ideal for most applica-tions. The high light ambient displays are ideal for sunlight ambients or long string lengths. For additional information see the 7.6 mm Micro Bright Seven Segment Displays, 10 mm Seven Segment Displays, 7.6 mm/10.9 mm Seven Segment Displays, 14.2 mm Seven Segment Displays, 20 mm Seven Segment Displays, or High Light Ambient Seven Segment Displays data sheets.Low Current Seven SegmentDisplays Technical Data HDSP-335x SeriesHDSP-555x SeriesHDSP-751x SeriesHDSP-A10x Series HDSP-A80x Series HDSP-A90x Series HDSP-E10x Series HDSP-F10x Series HDSP-G10x Series HDSP-H10x Series HDSP-K12x, K70x Series HDSP-N10x SeriesHDSP-N40x SeriesDevicesAlGaAs HER Yellow Green Package HDSP-HDSP-HDSP-HDSP-Description Drawing A1017511A801A9017.6 mm Common Anode Right Hand Decimal A A1037513A803A9037.6 mm Common Cathode Right Hand Decimal B A1077517A807A9077.6 mm Common Anode ±1. Overflow C A1087518A808A9087.6 mm Common Cathode ±1. Overflow D F10110 mm Common Anode Right Hand Decimal E F10310 mm Common Cathode Right Hand Decimal F F10710 mm Common Anode ±1. Overflow G F10810 mm Common Cathode ±1. Overflow H G10110 mm Two Digit Common Anode Right Hand Decimal X G10310 mm Two Digit Common Cathode Right Hand Decimal Y E100335010.9 mm Common Anode Left Hand Decimal I E101335110.9 mm Common Anode Right Hand Decimal J E103335310.9 mm Common Cathode Right Hand Decimal K E106335610.9 mm Universal ±1. Overflow[1]L H101555114.2 mm Common Anode Right Hand Decimal M H103555314.2 mm Common Cathode Right Hand Decimal N H107555714.2 mm Common Anode ±1. Overflow O H108555814.2 mm Common Cathode ±1. Overflow P K121K70114.2 mm Two Digit Common Anode Right Hand Decimal R K123K70314.2 mm Two Digit Common Cathode Right Hand Decimal S N10020 mm Common Anode Left Hand Decimal Q N101N40120 mm Common Anode Right Hand Decimal T N103N40320 mm Common Cathode Right Hand Decimal U N10520 mm Common Cathode Left Hand Decimal V N106N40620 mm Universal ±1. Overflow[1]W Note:1. Universal pinout brings the anode and cathode of each segment’s LED out to separate pins. See internal diagrams L or W.Part Numbering System5082-x xx x-x x x xxHDSP-x xx x-x x x xxMechanical Options[1]00: No mechanical optionColor Bin Options[1,2]0: No color bin limitationMaximum Intensity Bin[1,2]0: No maximum intensity bin limitationMinimum Intensity Bin[1,2]0: No minimum intensity bin limitationDevice Configuration/Color[1]G: GreenDevice Specific Configuration[1]Refer to respective datasheetPackage[1]Refer to Respective datasheetNotes:1. For codes not listed in the figure above, please refer to the respective datasheet or contact your nearest Agilent representative fordetails.2. Bin options refer to shippable bins for a part-number. Color and Intensity Bins are typically restricted to 1 bin per tube (excep-tions may apply). Please refer to respective datasheet for specific bin limit information.Package DimensionsPackage Dimensions (cont.)Package Dimensions (cont.)*The Side View of package indicates Country of Origin.Package Dimensions (cont.)Package Dimensions (cont.)Package Dimensions (cont.)Internal Circuit DiagramInternal Circuit Diagram (cont.)Absolute Maximum RatingsAlGaAs Red - HDSP-HERA10X/E10X/H10X HDSP-751X/Yellow GreenK12X/N10X/N40X335X/555X/HDSP-A80X HDSP-A90X Description F10X, G10X Series K70X Series Series Series Units Average Power per Segment or DP375264mW Peak Forward Current per 45mA Segment or DPDC Forward Current per15[1]15[2]mA Segment or DPOperating Temperature Range-20 to +100-40 to +100°C Storage Temperature Range -55 to +100°C Reverse Voltage per Segment 3.0V or DPWave Soldering Temperature for 3Seconds (1.60 mm [0.063 in.] below 250°C seating body)Notes:1. Derate above 91°C at 0.53 mA/°C.2. Derate HER/Yellow above 80°C at 0.38 mA/°C and Green above 71°C at 0.31 mA/°C.Electrical/Optical Characteristics at T A = 25°CAlGaAs RedDeviceSeriesHDSP-Parameter Symbol Min.Typ.Max.Units Test Conditions315600I F = 1 mA A10x3600I F = 5 mA330650I F = 1 mAF10x, G10x3900I F = 5 mA390650I F = 1 mA E10x Luminous Intensity/Segment[1,2]I Vµcd(Digit Average)3900I F = 5 mA400700I F = 1 mAH10x, K12x4200I F = 5 mA270590I F = 1 mAN10x, N40x3500I F = 5 mA1.6I F = 1 mAForward Voltage/Segment or DP V F 1.7V I F = 5 mA1.82.2I F = 20 mA PkAll Devices Peak WavelengthλPEAK645nmDominant Wavelength[3]λd637nmReverse Voltage/Segment or DP[4]V R 3.015V I R = 100 µATemperature Coefficient of∆V F/°C-2 mV mV/°CV F/Segment or DPA10x255F10x, G10x320E10x340Thermal Resistance LED RθJ-PIN°C/W/SegH10x, K12x Junction-to-Pin400N10x, N40x430High Efficiency RedDeviceSeriesHDSP-Parameter Symbol Min.Typ.Max.Units Test Conditions160270I F = 2 mA 751x1050I F = 5 mA200300I F = 2 mA Luminous Intensity/Segment[1,2]I V mcd(Digit Average)1200I F = 5 mA335x, 555x,K70x270370I F = 2 mA1480I F = 5 mA1.6I F = 2 mAForward Voltage/Segment or DP V F 1.7V I F = 5 mA2.1 2.5I F = 20 mA Pk All Devices Peak WavelengthλPEAK635nmDominant Wavelength[3]λd626nmReverse Voltage/Segment or DP[4]V R 3.030V I R = 100 µATemperature Coefficient of∆V F/°C-2mV/°CV F/Segment or DP751x200335x Thermal Resistance LED RθJ-PIN280°C/WJunction-to-Pin555x, K70x345YellowDeviceSeriesHDSP-Parameter Symbol Min.Typ.Max.Units Test Conditions Luminous Intensity/Segment[1,2]250420I F = 4 mA(Digit Average)I V mcd1300I F = 10 mA1.7I F = 4 mAForward Voltage/Segment or DP V F 1.8V I F = 5 mA A80x2.1 2.5I F = 20 mA PkPeak WavelengthλPEAK583nmDominant Wavelength[3,5]λd581.5585592.5nmReverse Voltage/Segment or DP[4]V R 3.030V I R = 100 µATemperature Coefficient of∆V F/°C-2mV/°CV F/Segment or DPThermal Resistance LED RθJ-PIN200°C/WJunction-to-PinGreenDeviceSeriesHDSP-Parameter Symbol Min.Typ.Max.Units Test Conditions Luminous Intensity/Segment[1,2]250475I F = 4 mA(Digit Average)I V mcd1500I F = 10 mA1.9I F = 4 mAForward Voltage/Segment or DP V F 2.0V I F = 10 mA A90x2.1 2.5I F = 20 mA PkPeak WavelengthλPEAK566nmDominant Wavelength[3,5]λd571577nmReverse Voltage/Segment or DP[4]V R 3.030V I R = 100 µATemperature Coefficient of∆V F/°C-2mV/°CV F/Segment or DPThermal Resistance LED RθJ-PIN200°C/WJunction-to-PinNotes:1. Device case temperature is 25°C prior to the intensity measurement.2. The digits are categorized for luminous intensity. The intensity category is designated by a letter on the side of the package.3. The dominant wavelength, λd, is derived from the CIE chromaticity diagram and is the single wavelength which defines the color of thedevice.4. Typical specification for reference only. Do not exceed absolute maximum ratings.5. The yellow (HDSP-A800) and Green (HDSP-A900) displays are categorized for dominant wavelength. The category is designated by anumber adjacent to the luminous intensity category letter.AlGaAs RedIntensity Bin Limits (mcd)AlGaAs RedHDSP-A10xIV Bin Category Min.Max.E0.3150.520F0.4280.759G0.621 1.16H0.945 1.71I 1.40 2.56J 2.10 3.84K 3.14 5.75L 4.708.55HDSP-E10x/F10x/G10xIV Bin Category Min.Max.D0.3910.650E0.5320.923F0.755 1.39G 1.13 2.08H 1.70 3.14HDSP-H10x/K12xIV Bin Category Min.Max.C0.4150.690D0.5650.990E0.810 1.50F 1.20 2.20G 1.80 3.30H 2.73 5.00I 4.097.50HDSP-N10xIV Bin Category Min.Max.A0.2700.400B0.3250.500C0.4150.690D0.5650.990E0.810 1.50F 1.20 2.20G 1.80 3.30H 2.73 5.00I 4.097.50Intensity Bin Limits (mcd), continued HERHDSP-751xIV Bin Category Min.Max.B0.1600.240C0.2000.300D0.2500.385E0.3150.520F0.4280.759G0.621 1.16HDSP-751xIV Bin Category Min.Max.B0.2400.366C0.3000.477D0.3910.650E0.5320.923F0.755 1.39G 1.13 2.08H 1.70 3.14HDSP-555x/K70xIV Bin Category Min.Max.A0.2700.400B0.3250.500C0.4150.690D0.5650.990E0.810 1.50F 1.20 2.20G 1.80 3.30H 2.73 5.00I 4.097.50Intensity Bin Limits (mcd), continued YellowHDSP-A80xIV Bin Category Min.Max.D0.2500.385E0.3150.520F0.4250.760G0.625 1.14H0.940 1.70I 1.40 2.56J 2.10 3.84K 3.14 5.76L 4.718.64M7.0713.00N10.6019.40O15.9029.20P23.9043.80Q35.8065.60GreenHDSP-A90xIV Bin Category Min.Max.E0.3150.520F0.4250.760G0.625 1.14H0.940 1.70I 1.40 2.56J 2.10 3.84K 3.14 5.76L 4.718.64M7.0713.00N10.6019.40O15.9029.20P23.9043.80Q35.8065.60Electrical/OpticalFor more information on electrical/optical characteristics, please see Application Note 1005.Contrast Enhancement For information on contrast enhancement, please see Application Note 1015.Soldering/Cleaning Cleaning agents from the ketone family (acetone, methyl ethyl ketone, etc.) and from the chorinated hydrocarbon family (methylene chloride, trichloro-ethylene, carbon tetrachloride, etc.) are not recommended for cleaning LED parts. All of these various solvents attack or dissolve the encapsulating epoxies used to form the package of plastic LED parts.For information on soldering LEDs, please refer to Application Note 1027.Note:All categories are established for classification of products. Productsmay not be available in all categories. Please contact your localAgilent representatives for further clarification/information.Color Categories/semiconductorsFor product information and a complete list ofdistributors, please go to our web site.For technical assistance call:Americas/Canada: +1 (800) 235-0312 or(916) 788 6763Europe: +49 (0) 6441 92460China: 10800 650 0017Hong Kong: (+65) 6271 2451India, Australia, New Zealand: (+65) 6271 2394Japan: (+81 3) 3335-8152(Domestic/International), or0120-61-1280(Domestic Only)Korea: (+65) 6271 2194Malaysia, Singapore: (+65) 6271 2054Taiwan: (+65) 6271 2654Data subject to change.Copyright © 2005 Agilent Technologies, Inc.Obsoletes 5988-8412ENJanuary 19, 20055989-0080EN。
5962-8776601SA中文资料
PACKAGING INFORMATIONOrderable Device Status(1)PackageType PackageDrawingPins PackageQtyEco Plan(2)Lead/Ball Finish MSL Peak Temp(3)5962-87766012A ACTIVE LCCC FK201TBD Call TI Level-NC-NC-NC 5962-8776601RA ACTIVE CDIP J201TBD Call TI Level-NC-NC-NC 5962-8776601SA ACTIVE CFP W201TBD Call TI Level-NC-NC-NC 5962-88693012A ACTIVE LCCC FK201TBD Call TI Level-NC-NC-NC 5962-8869301RA ACTIVE CDIP J201TBD Call TI Level-NC-NC-NC SN54ALS804AJ ACTIVE CDIP J201TBD Call TI Level-NC-NC-NC SN54AS804BJ ACTIVE CDIP J201TBD Call TI Level-NC-NC-NC SN74ALS804ADW ACTIVE SOIC DW2025Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN74ALS804ADWE4ACTIVE SOIC DW2025Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN74ALS804ADWR ACTIVE SOIC DW202000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN74ALS804ADWRE4ACTIVE SOIC DW202000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN74ALS804AN ACTIVE PDIP N2020Pb-Free(RoHS)CU NIPDAU Level-NC-NC-NCSN74ALS804ANE4ACTIVE PDIP N2020Pb-Free(RoHS)CU NIPDAU Level-NC-NC-NCSN74AS804BDW ACTIVE SOIC DW2025Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN74AS804BDWE4ACTIVE SOIC DW2025Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN74AS804BDWR ACTIVE SOIC DW202000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN74AS804BDWRE4ACTIVE SOIC DW202000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN74AS804BN ACTIVE PDIP N2020Pb-Free(RoHS)CU NIPDAU Level-NC-NC-NCSN74AS804BNE4ACTIVE PDIP N2020Pb-Free(RoHS)CU NIPDAU Level-NC-NC-NC SNJ54ALS804AFK ACTIVE LCCC FK201TBD Call TI Level-NC-NC-NC SNJ54ALS804AJ ACTIVE CDIP J201TBD Call TI Level-NC-NC-NC SNJ54AS804BFK ACTIVE LCCC FK201TBD Call TI Level-NC-NC-NC SNJ54AS804BJ ACTIVE CDIP J201TBD Call TI Level-NC-NC-NC SNJ54AS804BW ACTIVE CFP W201TBD Call TI Level-NC-NC-NC (1)The marketing status values are defined as follows:ACTIVE:Product device recommended for new designs.LIFEBUY:TI has announced that the device will be discontinued,and a lifetime-buy period is in effect.NRND:Not recommended for new designs.Device is in production to support existing customers,but TI does not recommend using this part in a new design.PREVIEW:Device has been announced but is not in production.Samples may or may not be available.OBSOLETE:TI has discontinued the production of the device.(2)Eco Plan-The planned eco-friendly classification:Pb-Free(RoHS)or Green(RoHS&no Sb/Br)-please check /productcontent for the latest availability information and additional product content details.TBD:The Pb-Free/Green conversion plan has not been defined.Pb-Free(RoHS):TI's terms"Lead-Free"or"Pb-Free"mean semiconductor products that are compatible with the current RoHS requirementsfor all6substances,including the requirement that lead not exceed0.1%by weight in homogeneous materials.Where designed to be soldered at high temperatures,TI Pb-Free products are suitable for use in specified lead-free processes.Green(RoHS&no Sb/Br):TI defines"Green"to mean Pb-Free(RoHS compatible),and free of Bromine(Br)and Antimony(Sb)based flame retardants(Br or Sb do not exceed0.1%by weight in homogeneous material)(3)MSL,Peak Temp.--The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications,and peak solder temperature.Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.TI bases its knowledge and belief on information provided by third parties,and makes no representation or warranty as to the accuracy of such information.Efforts are underway to better integrate information from third parties.TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary,and thus CAS numbers and other limited information may not be available for release.In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s)at issue in this document sold by TI to Customer on an annual basis.IMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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5962-9452602MGA中文资料
Original Creation Date: 05/18/95Last Update Date: 06/14/04Last Major Revision Date: 09/02/97MNLM193A-X REV 1B3MICROCIRCUIT DATA SHEETLOW POWER LOW OFFSET VOLTAGE DUAL COMPARATORSGeneral DescriptionThe LM193A consists of two independent precision voltage comparators with an offset voltage specification as low as 2.0mV max for two comparators which were designed specifically to operate from a single power supply over a wide range of voltages.Operation from split power supplies is also possible and the low power supply currentdrain is independent of the magniture of the power supply voltage. These comparators also have a unique characteristic in that the input common-mode voltage range includes ground,even though operated from a single power supply voltage.Application areas include limit comparators, simple analog to digital converters; pulse,squarewave and time delay generators; wide range VCO; MOS clock timers; multivibrators and high voltage digital logic gates. The LM193A was designed to directly interface with TTL and CMOS. When operated from both plus and minus power supplies, the LM193A will directly interface with MOS logic where their low power drain is a distinct advantage over standard comparators.NS Part NumbersLM193AH-QMLV LM193AH/883LM193AJ-QMLV LM193AJ/883Industry Part NumberLM193APrime DieLM193AControlling DocumentSee Features PageProcessingMIL-STD-883, Method 5004Quality Conformance InspectionMIL-STD-883, Method 5005Subgrp Description Temp ( C)o 1Static tests at +252Static tests at +1253Static tests at -554Dynamic tests at +255Dynamic tests at +1256Dynamic tests at -557Functional tests at +258A Functional tests at +1258B Functional tests at -559Switching tests at +2510Switching tests at +12511Switching tests at-55MICROCIRCUIT DATA SHEET MNLM193A-X REV 1B3Features- Wide supply- Voltage range 2.0Vdc to 36Vdc- Single or dual supplies +1.0Vdc to +18Vdc- Very low supply current drain (0.4mA)independent of supply voltage- Low input biasing current 25nA Typ- Low input offset current +3nA Typ- Input common-mode voltage rangeincludes ground- Differential input voltage rangeequal to the power supply voltage- Low output saturation voltage 250mV at 4mA Typ- Output voltage compatible with TTL,DTL, ECL, MOS and CMOS logic systemsCONTROLLING DOCUMENTS:LM193AH/883 5962-9452602MGALM193AH-QMLV 5962-9452602VGALM193AJ-QMLV 5962-9452602VPALM193AJ/883 5962-9452602MPAMICROCIRCUIT DATA SHEET MNLM193A-X REV 1B3(Absolute Maximum Ratings)(Note 1)Supply Voltage, V+36Vdc or +18VdcDifferential Input Voltage(Note 6)36VdcInput Voltage-0.3Vdc to +36VdcInput Current (Vin < -0.3 Vdc)(Note 5)50mAMaximum Junction Temperature150 CPower Dissipation(Note 2, 3)METAL CAN660mWCERDIP780mWOutput Short-Circuit to Gnd(Note 4)ContinuousOperating Temperature Range-55 C to +125 CThermal ResistanceThetaJAMETAL CAN (Still Air)174 C/W(500LF/Min Air flow)99 C/WCERDIP (Still Air)146 C/W(500LF/Min Air flow)85 C/WThetaJCMETAL CAN44 C/WCERDIP33 C/WLead Temperature(Soldering, 10 seconds)+260 CESD Tolerance(Note 7)500VNote 1:Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.Operating Ratings indicate conditions for which the device is functional, but do notguarantee specific performance limits. For guaranteed specifications and testconditions, see the Electrical Characteristics. The guaranteed specifications applyonly for the test conditions listed. Some performance characteristics may degradewhen the device is not operated under the listed test conditions.Note 2:The maximum power dissipation must be derated at elevated temperatures and isdictated by Tjmax (maximum junction temperature ), ThetaJA (package junction toambient thermal resistance), and TA (ambient temperature). The maximum allowablepower dissipation at any temperature is Pdmax = (Tjmax - TA)/ThetaJA or the numbergiven in the Absolute Maximum Ratings, whichever is lower.Note 3:The LM193A must be derated based on a 150 C maximum junction temperature. The low bias dissipation and the ON-OFF characteristic of the outputs keeps the chipdissipation very small (PD<100mV), provided the output transistors are allowed tosaturate.Note 4:Short circuits from the output to V+ can cause excessive heating and eventualdestruction. When considering short circuits to ground, the maximum output current isapproximately 20mA independent of the magnitude of V+.MNLM193A-X REV 1B3MICROCIRCUIT DATA SHEET(Continued)Note 5:This input current will only exist when the voltage at any of the input leads is driven negative. It is due to the collector-base junction of the input PNPtransistors becoming forward biased and thereby acting as input diode clamps. Inaddition to this diode action, there is also lateral NPN parasitic transistor actionon the IC chip. This transistor action can cause the output voltages of thecomparators to go to the V+ voltage level (or to ground for a large overdrive) forthe time duration that an input is driven negative. This is not destructive andnormal output states will re-establish when the input voltage, which was negative,again returns to a value greater than -0.3Vdc.Note 6:Positive excursions of input voltage may exceed the power supply level. As long as the other voltage remains within the common-mode range, the comparator will provide aproper output state. The low input voltage state must not be less than -0.3Vdc (or0.3Vdc below the magnitude of the negative power supply, if used).Note 7:Human body model, 1.5K Ohms in series with 100pF.MNLM193A-X REV 1B3MICROCIRCUIT DATA SHEETElectrical CharacteristicsDC PARAMETERS(The following conditions apply to all the following parameters, unless otherwise specified.)DC:V+ = 5V, Vcm = 0SYMBOL PARAMETER CONDITIONS NOTES PIN-NAME MIN MAX UNITSUB-GROUPSIcc Supply Current Rl = Infinity 1.0mA1, 2,3V+ = 36V, Rl = Infinity 2.5mA1, 2,3Icex Output LeakageCurrent V+ = 30V, Vin+ = 1V, Vo = 30, Vin- = 0-0.650.65uA1-1.0 1.0uA2, 3Isink Output SinkCurrent Vo = 1.5V, Vin- = 1V, Vin+ = 0 6.0mA14.0mA2, 3Vsat Output SaturationVoltage Isink = 4mA, Vin- = 1V, Vin+ = 00.4V10.7V2, 3Vio Input OffsetVoltage-2.0 2.0mV1-4.0 4.0mV2, 3 V+ = 30V, Vcm = 0-2.0 2.0mV1-4.0 4.0mV2, 3 V+ = 30V, Vcm = 28.5V-2.0 2.0mV1V+ = 30V, Vcm = 28.0V-4.0 4.0mV2, 3Iib+Input BiasCurrent Vout = 1.5V-100-1nA1-300-1nA2, 3Iib-Input BiasCurrent Vout = 1.5V-100-1nA1-300-1nA2, 3Iio Input offsetCurrent Rs = 50 Ohms, Vout = 1.5V-2525nA1-100100nA2, 3Vcm Common ModeVoltage V+ = 30V128.5V1128V2, 3PSRR Power SupplyRejection RatioV+ = 5V to 30V, Rs = 50 Ohms60dB1CMRR Common ModeRejection Ratio V+ = 30V, Vcm = 0V to 28.5V,Rs = 50 Ohms60dB1Vdiff DifferentialInput Voltage V+ = 30V, +Vin = 36V, -Vin = 0V4500nA1, 2,3V+ = 30V, +Vin = 0V, -Vin = +36V4500nA1, 2,3Avs Voltage Gain V+ = 15V, 1V <= Vout <= 11V,RPULLUP = 15K 250V/mV4 225V/mV5, 6MNLM193A-X REV 1B3MICROCIRCUIT DATA SHEETElectrical CharacteristicsAC PARAMETERS(The following conditions apply to all the following parameters, unless otherwise specified.)AC:Vcc = 5V, Vcm = 0SYMBOL PARAMETER CONDITIONS NOTES PIN-NAME MIN MAX UNITSUB-GROUPStRLH Response Time V+ = 5V, Vod = 5mV3 5.0uS9V+ = 5V, Vod = 50mV30.8uS9 tRHL Response Time V+ = 5V, Vod = 5mV3 2.5uS9V+ = 5V, Vod = 50mV30.8uS9DC PARAMETERS: DRIFT VALUES(The following conditions apply to all the following parameters, unless otherwise specified.)DC:V+ = 5V, Vcm = 0. "Delta calculations performed on Jan S and QMLV devices at Group B, Subgroup 5 ONLY."Vio Input OffsetVoltageV+ = 30V, Vcm = 0-11mV1Iib+Input BiasCurrent-1515nA1Iib-Input BiasCurrent-1515nA1Note 1:Parameter guaranteed by the Vio testsNote 2:Datalog reading in K = V/mV.Note 3:Bench TestedNote 4:The value for Vdiff is not data logged during Read and Record.MICROCIRCUIT DATA SHEET MNLM193A-X REV 1B3Graphics and DiagramsGRAPHICS#DESCRIPTION06048HRA2CERDIP (J), 8 LEAD (B/I CKT)09319HRA2METAL CAN (H), TO-99, 8 LD, .200 DIA P.C.(B/I CKT)H08CRF METAL CAN (H), TO-99, 8LD .200 DIA P.C. (P/P DWG)J08ARL CERDIP (J), 8 LEAD (P/P DWG)P000171A METAL CAN (H), TO-99, 8LD, .200 DIA P.C. (PINOUT)P000172B CERDIP (J), 8 LEAD (PINOUT)See attached graphics following this page.N MIL/AEROSPACE OPERATIONS 2900 SEMICONDUCTOR DRIVE SANTA CLARA, CA 95050123456 78 IN- AIN+ AOUTPUT AGND IN+ BIN- B OUTPUT BV+LM193AH, LM193HCONNECTION DIAGRAM TOP VIEWP000171A8 - PIN METAL CANN MIL/AEROSPACE OPERATIONS2900 SEMICONDUCTOR DRIVESANTA CLARA, CA 95050LM193J, LM193AJCONNECTION DIAGRAMTOP VIEWP000172B8 - LEAD DIP1 8234 5 7 6 OUTPUT AIN- AIN+ AV-IN + BIN- B OUTPUT B V+MICROCIRCUIT DATA SHEET MNLM193A-X REV 1B3Revision HistoryRev ECN #Rel Date Originator Changes1A2M000281701/16/03Rose Malone Update MDS: MNLM193A-X, Rev. 1A1 to MNLM193A-X, Rev.1A2. Main Table Adding reference to LM193AJ/883 andSMD number, B/I CKTS and Pin Out for J pkg.1A3M000408706/14/04Rose Malone Updated MDS: MNLM193A-X, Rev. 1A2 to MNLM193A-X, Rev.1A3. Updated Burn-In Ckt from 05363HRA2 to 09319HRA2in Graphics Section.1B3M000439106/14/04Rose Malone Update MDS: MNLM193A-X, Rev. 1A3 to 1B3. Added Note 4to Vdiff parameter and to note section.8。
5962-9452801QXA中文资料
Original Creation Date: 07/12/96Last Update Date: 08/14/03Last Major Revision Date: 07/30/03MN54ACTQ16374-X REV 2A0MICROCIRCUIT DATA SHEET16-Bit D Flip-Flop with TRI-STATE OutputsGeneral DescriptionThe ACTQ16374 contains sixteen non-inverting D flip-flops with TRI-STATE outputs and is intended for bus oriented applications. The device is byte controlled. A buffered clock (CP) and Output Enable (OE) are common to each byte and can be shorted together for full 16-bit operation.The ACTQ16374 utilizes NSC Quiet Series technology to guarantee quiet output switching and improved dynamic threshold performance. FACT Quiet Series TM features GTO TM output control for superior performance.NS Part Numbers54ACTQ16374FMQBIndustry Part Number54ACTQ16374Prime DieD16374ProcessingMIL-STD-883, Method 5004Quality Conformance InspectionMIL-STD-883 5005Subgrp Description Temp ( C)o 1Static tests at +25 C 2Static tests at +125 C 3Static tests at -55 C 4Dynamic tests at +25 C 5Dynamic tests at +125 C 6Dynamic tests at -55 C 7Functional tests at +25 C 8A Functional tests at +125 C 8B Functional tests at -55 C 9Switching tests at +25 C 10Switching tests at +125 C 11Switching tests at-55 CMICROCIRCUIT DATA SHEET MN54ACTQ16374-X REV 2A0Features- Utilizes NSC FACT Quiet Series technology- Guaranteed simultaneous switching noise level and dynamic threshold performance- Guaranteed pin-to-pin output skew- Buffered Positive edge-triggered clock- Separate control logic for each byte- 16-bit version of the ACTQ374- Outputs source/sink 24 mA- Additional spec for Multiple Output Switching- Output Loadings specs for both 50 pF and 250 pF loadsMICROCIRCUIT DATA SHEET MN54ACTQ16374-X REV 2A0(Absolute Maximum Ratings)(Note 1)Supply Voltage (Vcc)-0.5V to +7.0VDC Input Diode Current (Iik)Vin = -0.5V-20 mAVin = Vcc +0.5V+20 mADC Output Diode Current (Iok)Vo = -0.5V-20 mAVo = Vcc +0.5V+20 mADC Output Voltage (Vo)-0.5V to Vcc +0.5VDC Vcc or Ground Current Per Output Pin+50 mAThermal ResistanceJunction-To-Case (Theta JC)10 C/WattJunction-To-Ambient (Theta JA)80 C/Watt(1 Watt at no airflow)Storage Temperature-65 C to +150 CLead Temperature(Soldering, 10 seconds)+300 CESD ClassificationClass 2Maximum Power Dissipation750 mWDC Output Source/Sink Current (Io)+50 mAJunction Temperature (Tj)CERAMIC FLATPACK+175 CNote 1:Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure thatthe system design is reliable over its power supply, temperature, and output/inputloading variables. National does not recommend operation of FACT TM circuits outsidedatabook specifications.Recommended Operating ConditionsSupply Voltage (Vcc)4.5V to5.5VInput Voltage (Vi)0V to VccOutput Voltage (Vo)0V to VccOperating Temperature (Ta)-55 C to +125 CMinimum Input Edge Rate (Delta V/Delta t)ACTQ DevicesVin from 0.8V to 2.0VVcc @ 4.5V, 5.5V125 mV/nsMaximum Output Current-24 mAHigh Level (IOH)Low Level (IOL)24 mAMN54ACTQ16374-X REV 2A0MICROCIRCUIT DATA SHEETElectrical CharacteristicsDC PARAMETERS(The following conditions apply to all the following parameters, unless otherwise specified.)DC:VCC 4.5V to 5.5V, Temp. Range: -55C to 125C. NOTE: -55C TEMPERATURE, SUBGROUP 3 IS GUARANTEED BUT NOT TESTED.SYMBOL PARAMETER CONDITIONS NOTES PIN-NAME MIN MAX UNITSUB-GROUPSIIH High Level inputCurrent VCC=5.5V, VIH=5.5V1, 2INPUT0.1uA11, 2INPUT 1.0uA2, 3IIL Low Level inputCurrent VCC=5.5V, VIL=0.0V1, 2INPUT-0.1uA11, 2INPUT-1.0uA2, 3VOL Low level outputvoltage VCC=4.5V, VIL=0.8V, IOL=24.0mA,VIH=2.0V1, 2OUTPUT.36V11, 2OUTPUT.50V2, 3 VCC=4.5V, VIL=0.8V, IOL=50.0uA,VIH=2.0V1, 2OUTPUT.10V1, 2,3 VCC=5.5V, VIL=0.8V, IOL=24.0mA,VIH=2.0V1, 2OUTPUT.36V11, 2OUTPUT.50V2, 3 VCC=5.5V, VIL=0.8V, IOL=50.0uA,VIH=2.0V1, 2OUTPUT.10V1, 2,3VIOL Dynamic OutputCurrent LOW VCC=5.5V, VIH=5.5V, VIL=0.0V,IOL=50.0mA1,2, 5OUTPUT 1.65V1, 2,3VOH High Level OutputVoltage VCC=4.5V, VIL=0.8V, IOL=-24.0mA,VIH=2.0V1, 2OUTPUT 3.86V11, 2OUTPUT 3.70V2, 3 VCC=4.5V, VIL=0.8V, IOL=-50.0uA,VIH=2.0V1, 2OUTPUT 4.4V1, 2,3 VCC=5.5V, VIL=0.8V, IOL=-24.0mA,VIH=2.0V1, 2OUTPUT 4.86V11, 2OUTPUT 4.7V2, 3 VCC=5.5V, VIL=0.8V, IOL=-50.0uA,VIH=2.0V1, 2OUTPUT 5.4V1, 2,3VIOH Dynamic OutputCurrent HIGH VCC=5.5V, VIH=5.5V, VIL=0.0V,IOL=-50.0mA1,2, 5OUTPUT 3.85V1, 2,3ICC Supply Current VCC=5.5V, VIN=5.5V or Gnd1, 2VCC8.0uA11, 2VCC160uA2, 3 ICCT Supply Current VCC=5.5V, VINH=3.4V1, 2VCC 1.0mA11, 2VCC 1.6mA2, 3IOZH Maximum TRI-STATELeakage Current VCC=4.5V, VOUT=4.5V, VIL=0.0V,VIH(OE)=2.0V1, 2OUTPUT0.5uA11, 2OUTPUT10uA2, 3 VCC=5.5V, VOUT=5.5V, VIL=0.0V,VIH(OE)=2.0V1, 2OUTPUT0.5uA11, 2OUTPUT10uA2, 3MN54ACTQ16374-X REV 2A0MICROCIRCUIT DATA SHEETElectrical CharacteristicsDC PARAMETERS(Continued)(The following conditions apply to all the following parameters, unless otherwise specified.)DC:VCC 4.5V to 5.5V, Temp. Range: -55C to 125C. NOTE: -55C TEMPERATURE, SUBGROUP 3 IS GUARANTEED BUT NOT TESTED.SYMBOL PARAMETER CONDITIONS NOTES PIN-NAME MIN MAX UNITSUB-GROUPSIOZL Maximum TRI-STATELeakage Current VCC=4.5V, VOUT=4.5V, VIL=4.5V,VIH(OE)=2.0V1, 2OUTPUT-0.5uA11, 2OUTPUT-10uA2, 3 VCC=5.5V, VOUT=5.5V, VIL=5.5V,VIH(OE)=2.0V1, 2OUTPUT-0.5uA11, 2OUTPUT-10uA2, 3VIKL VCC=4.5V, IKL=-18mA1, 2INPUT-1.2V1, 2,3 VIKH VCC=4.5V, IKH=18mA1, 2INPUT 5.7V1, 2,3CIN INPUT PINCAPACITANCE6INPUT10pF4COUT OUTPUT PINCAPACITANCE6OUTPUT15pF4CPD POWER DISSIPATIONCAPACITANCE6100pF4VILD Maximum LowDynamic InputVoltage LevelVCC=5.0V, LOAD 50pF / 500 OHMS6, 9INPUT0.8V4VIHD Minimum HighDynamic InputVoltage LevelVCC=5.0V, LOAD 50pF / 500 OHMS6, 9INPUT 2.0V4VOLP Quiet OutputMaximum DynamicVol VCC=5.0V, LOAD 50pF / 500 OHMS MaximumHigh Output Noise6, 8OUTPUT1100mV4VOLV Quiet OutputMinmum DynamicVol VCC=5.0V, LOAD 50pF / 500 OHMS MaximumLow Output Noise6, 8OUTPUT-1300mV4VOHP Maximum Overshoot VCC=5.0V, LOAD 50pF / 500 OHMS MaximumOvershoot 6, 8OUTPUT VOH+1200mV4VOHV Minimum Vcc Droop VCC=5.0V, LOAD 50pF / 500 OHMS MinimumVcc Droop 6, 8OUTPUT VOH-1400mV4MN54ACTQ16374-X REV 2A0MICROCIRCUIT DATA SHEETElectrical CharacteristicsAC PARAMETERS(The following conditions apply to all the following parameters, unless otherwise specified.)AC:CL=50pf, RL=500 OHMS, TR/TFALL=3.0ns, Temp range: -55C to +125C. NOTE: -55C TEMPERATURE, SUBGROUP 11 IS GUARANTEED BUT NOT TESTED.SYMBOL PARAMETER CONDITIONS NOTES PIN-NAME MIN MAX UNITSUB-GROUPStpLH Propagation Delay Vcc = 4.5V3,4, 7CP toOn3.09.0ns93, 4, 7CP toOn3.010.5ns10, 11tpHL Propagation Delay Vcc = 4.5V3,4, 7CP toOn3.09.0ns93, 4, 7CP toOn1.010.5sn10, 11tpLZ Output DisableTime Vcc = 4.5V3,4, 7OE toOn2.08.0ns93,4, 7OE toOn2.09.0ns10, 11tpHZ Output DisableTime Vcc = 4.5V3,4, 7OE toOn2.08.0ns93,4, 7OE toOn2.09.0ns10, 11tpZL Output EnableTime Vcc = 4.5V3,4, 7OE toOn3.010.0ns93,4, 7OE toOn3.011.5ns10, 11tpZH Output EnableTime Vcc = 4.5V3,4, 7OE toOn3.09.0ns93,4, 7OE toOn3.010.5ns10, 11Fmax Maximum ClockFrequency Vcc = 4.5V6CP75Mhz96CP65Mhz10, 11tset (H/L)Set-up Time Vcc = 4.5V6In toCP 3.0ns9, 10,11Thold (H/L)Hold Time Vcc = 4.5V6In toCP1.0ns9, 10,11Twidth (H/L)Pulse Width Vcc = 4.5V6CPPulse5.0ns9, 10,11TOSHL Pin to Pin SkewHL Data to Output Vcc = 4.5V6Pin toPinSkew1.3ns9, 10,11TOSLH Pin to Pin SkewLH Data to Output Vcc = 4.5V6Pin toPinSkew2.1ns9, 10,11TOST Pin to Pin SkewLH/HL Data toOutput Vcc = 4.5V6Pin toPinSkew4.0ns9, 10,11MN54ACTQ16374-X REV 2A0MICROCIRCUIT DATA SHEETNote 1:SCREEN TESTED 100% ON EACH DEVICE AT +25C & +125C TEMPERATURE, SUBGROUPS 1, 2, 7, &8.Note 2:SAMPLE TESTED (METHOD 5005, TABLE 1) ON EACH MFG. LOT AT +25C & +125C TEMPERATURE, SUBGROUPS A1, 2, 7, & 8.Note 3:SCREEN TESTED 100% ON EACH DEVICE AT +25C TEMPERATURE ONLY SUBGROUP A9.Note 4:SAMPLE TESTED (METHOD 5005, TABLE 1) ON EACH MFG. LOT AT +25C & +125C TEMPERATURE, SUBGROUPS A9 & 10.Note 5:TRANSMISSION LINE DRIVING TEST, GUARDBANDED LIMITS SET FOR +25C, 2 MSEC DURATION MAX.Note 6:GUARANTEED BUT NOT TESTED. (DESIGN CHARACTERIZATION DATA)Note 7:+25C & +125C MIN LIMITS GUARANTEED FOR 5.5V BY GUARDBANDING 4.5V MIN. LIMITS.Note 8:MAX NUMBER OF OUTPUTS DEFINED AS (N). DATA INPUTS ARE DRIVEN 0V TO 3V. ONE OUTPUT @ VOL.Note 9:MAX NUMBER OF DATA INPUTS (N) SWITCHING. (N-1) INPUTS SWITCHING 0V TO 3V.INPUT-UNDER-TEST SWITCHING 3V TO THRESHOLD (VILD), 0V TO THRESHOLD (VIHD), FREQ= 1MHZ.MICROCIRCUIT DATA SHEET MN54ACTQ16374-X REV 2A0Revision HistoryRev ECN #Rel Date Originator Changes2A0M000407908/14/03Rose Malone Updated MDS: MN54ACTQ16374-X, Rev. 1A0 toMN54ACTQ16374-X, Rev. 2A0. Changed limits for thefollowing parameters: VOLP from 0.8V to 1100mV, VOLVfrom -0.8V to -1300mV, VOHP from VOH +1.0V to VOH+1200mV and VOHV from VOH -1.0V to VOH -1400mV.。
5962-8757702RA中文资料
82C87HCMOS Octal Inverting Bus TransceiverFile Number2978.1March 1997Features•Full Eight Bit Bi-Directional Bus Interface •Industry Standard 8287 Compatible Pinout•High Drive Capability- B Side I OL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20mA - A Side I OL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12mA •Three-State Inverting Outputs•Propagation Delay . . . . . . . . . . . . . . . . . . . . .35ns Max.•Gated Inputs-Reduce Operating Power-Eliminate the Need for Pull-Up Resistors •Single 5V Power Supply•Low Power Operation . . . . . . . . . . . . . . .ICCSB = 10µA •Operating Temperature Range-C82C87H . . . . . . . . . . . . . . . . . . . . . . . . .0o C to +70o C -I82C87H. . . . . . . . . . . . . . . . . . . . . . . .-40o C to +85o C -M82C87H. . . . . . . . . . . . . . . . . . . . . .-55o C to +125o CDescriptionThe Intersil 82C87H is a high performance CMOS Octal T ransceiver manufactured using a self-aligned silicon gate CMOS process (Scaled SAJI IV). The 82C87H provides a full eight-bit bi-directional bus interface in a 20 pin package. The T ransmit (T) control determines the data direction. The active low output enable (OE) permits simple interface to the 80C86, 80C88 and other microprocessors. The 82C87H has gated inputs, eliminating the need for pull-up/pull-down resis-tors and reducing overall system operating power dissipation.The 82C87H provides inverted data at the outputs.Ordering InformationPART NUMBERS PACK-AGETEMP.RANGE PKG.NO.5MHz 8MHzCP82C87H-5CP82C87H 20 LdPDIP0o C to +70o CE20.3IP82C87H-5IP82C87H-40o C to +85o C E20.3CS82C87H-5CS82C87H 20 LdPLCC0o C to +70o CN20.35IS82C87H-5IS82C87H-40o C to +85o C N20.35CD82C87H-5CD82C87H 20 LdCERDIP 0o C to +70o CF20.3ID82C87H-5ID82C87H-40o C to +85o C F20.3MD82C87H-5/B --55o C to +125o CF20.35962-8757702RA -SMD #F20.3MR82C87H-5/B -20 Pad CLCC -55o C to +125o CJ20.A 5962-87577022A-SMD #J20.ACAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.Pinouts82C87H (PDIP, CERDIP)TOP VIEW82C87H (PLCC, CLCC)TOP VIEW1112131415161718201910987654321A0A1A2A3A4A5A7A6OE GND V CC B1B2B3B0B4B5B6B7T1932201151617181491011121345678A4A5A6A7A3O EG N DTB 7B 6B2B3B4B5B1A 2A 1A 0V C CB 0TRUTH TABLET OE A B X H Hi-Z Hi-Z H L I O LLOIH = Logic One L = Logic Zero I = Input Mode O = Output Mode X = Don’t CareHi-Z = High ImpedancePIN NAMESPIN DESCRIPTION A 0-A 7Local Bus Data I/O Pins B 0-B 7System Bus Data I/O Pins T Transmit Control Input OEActive Low Output EnableFunctional DiagramGated InputsDuring normal system operation of a latch, signals on the bus at the device inputs will become high impedance or make transitions unrelated to the operation of the latch.These unrelated input transitions switch the input circuitry and typically cause an increase in power dissipation in CMOS devices by creating a low resistance path between V CC and GND when the signal is at or near the input switch-ing threshold. Additionally, if the driving signal becomes high impedance (“float” condition), it could create an indetermi-nate logic state at the inputs and cause a disruption in device operation.The Intersil 82C8X series of bus drivers eliminates these conditions by turning off data inputs when data is latched (STB = logic zero for the 82C82/83H) and when the device is disabled (OE = logic one for the 82C87H/87H). These gated inputs disconnect the input circuitry from the V CC and ground power supply pins by turning off the upper P-Chan-nel and lower N-Channel (See Figures 1 and 2). No current flow from V CC to GND occurs during input transitions and invalid logic states from floating inputs are not transmitted.The next stage is held to a valid logic level internal to the device.D.C. input voltage levels can also cause an increase in ICC if these input levels approach the minimum V IH or maximum V IL conditions. This is due to the operation of the input cir-cuitry in its linear operating region (partially conducting state). The 82C8X series gated inputs mean that this condi-tion will occur only during the time the device is in the trans-parent mode (STB = logic one). ICC remains below the maximum ICC standby specification of 10µA during the time inputs are disabled, thereby greatly reducing the average power dissipation of the 82C8X series devices.Decoupling CapacitorsThe transient current required to charge and discharge the 300pF load capacitance specified in the 82C86H/87H data sheet is determined by:Assuming that all outputs change state at the same time and that dv/dt is constant;where tR = 20ns, V CC = 5.0V , C L = 300pF on each eight out-puts.This current spike may cause a large negative voltage spike on V CC which could cause improper operation of the device. T o fil-ter out this noise, it is recommended that a 0.1µF ceramic disc capacitor be placed between V CC and GND at each device,with placement being as near to the device as possible.TB7B6B5B4B3B2B1B0A0A1A2A3A4A5A6A7OEI C L dv dt ⁄()=(EQ. 4)I C L V CC 80%×()tR tF⁄------------------------------------=(EQ. 5)I 803001012–××() 5.0V 0.8×()20109–×()⁄×=480mA=(EQ. 6)STB DATA INV CC PNV CCINTERNAL DATAPPN NFIGURE 3.82C82/83HDATA ININTERNAL DATAV CCV CC NNPPPNOE FIGURE 4.82C86H/87H GATED INPUTSAbsolute Maximum Ratings Thermal InformationSupply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+8.0V Input, Output or I/O Voltage . . . . . . . . . . . .GND -0.5V to V CC+0.5V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Class 1 Operating ConditionsOperating Voltage Range. . . . . . . . . . . . . . . . . . . . .+4.5V to +5.5V Operating Temperature RangeC82C87H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0o C to +70o C I82C87H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40o C to +85o C M82C87H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55o C to +125o C Thermal Resistance (T ypical)θJA (o C/W)θJC (o C/W) CERDIP Package . . . . . . . . . . . . . . . .7016 CLCC Package . . . . . . . . . . . . . . . . . .8020 PDIP Package. . . . . . . . . . . . . . . . . . .75N/A PLCC Package . . . . . . . . . . . . . . . . . .75N/A Storage Temperature Range. . . . . . . . . . . . . . . . . .-65o C to +150o C Maximum Junction T emperature Hermetic Package. . . . . . .+175o C Maximum Junction T emperature Plastic Package. . . . . . . . .+150o C Maximum Lead T emperature (Soldering 10s). . . . . . . . . . . .+300o C (PLCC - Lead Tips Only)Die CharacteristicsGate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .265 GatesCAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.DC Electrical Specifications V CC = 5.0V±10%; T A = 0o C to +70o C (C82C87H);T A = -40o C to +85o C (I82C87H);T A = -55o C to +125o C (M82C87H)SYMBOL PARAMETER MIN MAX UNITS TEST CONDITIONS V IH Logical One 2.0-V C82C87H, I82C87HInput Voltage 2.2-V M82C87H (Note 1)V IL Logical Zero Input Voltage-0.8VV OH Logical One Output VoltageB Outputs 3.0-V I OH = -8mAA Outputs 3.0-V I OH = -4mAA orB Outputs V CC -0.4-V I OH = -100µAV OL Logical Zero Output VoltageB Outputs-0.45V I OL = 20mAA Outputs-0.45V I OL = 12mAI I Input Leakage Current-10.010.0µA V IN = GND or V CC DIP Pins 9, 11IO Output Leakage Current-10.010.0µA VO = GND or V CC,OE ≥V CC -0.5VDIP Pins 1 - 8, 12 - 19 ICCSB Standby Power SupplyCurrent-10µA V IN = V CC or GND, V CC = 5.5V, Outputs OpenICCOP Operating Power SupplyCurrent-1mA/MHz T A = +25o C, Typical (See Note 2)NOTES:1.V IH is measured by applying a pulse of magnitude = V IH(MIN) to one data input at a time and checking the corresponding device output fora valid logical “1” during valid input high time. Control pins (T,OE) are tested separately with all device data input pins at V CC -0.4.2.Typical ICCOP = 1mA/MHz of read/ cycle time. (Example: 1.0µs read/write cycle time = 1mA).Capacitance T A = +25o CSYMBOL PARAMETER TYPICAL UNITS TEST CONDITIONS CIN Input CapacitanceB Inputs18pF Freq = 1MHz, all measurements arereferenced to device GNDA Inputs14pFTiming WaveformAC Electrical SpecificationsV CC = 5.0V ±10%; T A = 0o C to +70o C (C82C87H);Freq = 1MHzT A = -40o C to +85o C (I82C87H);T A = -55o C to +125o C (M82C87H)SYMBOL PARAMETERMIN NOTE 4UNITS TEST CONDITIONS 82C87H MAX82C87H-5MAX(1)TIVOVInput to Output Delay Notes 1, 2Inverting 53035ns Non-Inverting53235ns (2)TEHTV Transmit/Receive Hold Time 5--ns Notes 1, 2(3)TTVEL Transmit/Receive Setup Time 10--ns Notes 1, 2(4)TEHOZ Output Disable Time 53035ns Notes 1, 2(5)TELOV Output Enable Time 105065ns Notes 1, 2(6)TR, TF Input Rise/Fall Times-2020nsNotes 1, 2(7)TEHELMinimum Output Enable High Time Note 382C87H 30--ns 82C87H-535--nsNOTES:1.All AC parameters tested as per test circuits and definitions in timing waveforms and test load circuits. Input rise and fall times are driven at 1ns/V .2.Input test signals must switch between V IL - 0.4V and V IH +0.4V.3.A system limitation only when changing direction. Not a measured parameter.4.82C87H is available in commercial and industrial temperature ranges only. 82C87H-5 is available in commercial, industrial and military temperature ranges.INPUTSTR, TF (6)2.0V 0.8VV OH -0.1V TELOV (5)V OL +0.1V TTVEL (3)3.0V 0.45VOUTPUTSTTEHEL (7)TIVOV(1)TEHOZ(4)TEHTV (2)OETest Load CircuitsA SIDE OUTPUTSTIVOV LOAD CIRCUITTELOV OUTPUT HIGH ENABLE LOAD CIRCUITTELOV OUTPUT LOW ENABLE LOAD CIRCUITTEHOZ OUTPUT LOW/HIGH DISABLE LOAD CIRCUITB SIDE OUTPUTSTIVOV LOAD CIRCUITTELOV OUTPUT HIGH ENABLE LOAD CIRCUITTELOV OUTPUT LOW ENABLE LOAD CIRCUITTEHOZ OUTPUT LOW/HIGH DISABLE LOAD CIRCUITNOTE:Includes jig and stray capacitance.Burn-In CircuitsMD82C87H CERDIPOUTPUT TEST POINT2.36V100pF 160Ω(SEE NOTE)OUTPUT TEST POINT1.5V100pF 375Ω(SEE NOTE)OUTPUT TEST POINT1.5V100pF 91Ω(SEE NOTE)OUTPUT TEST POINT2.36V50pF160Ω(SEE NOTE)OUTPUT TEST POINT2.27V300pF 91Ω(SEE NOTE)OUTPUT TEST POINT1.5V300pF 180Ω(SEE NOTE)OUTPUT TEST POINT1.5V300pF 51Ω(SEE NOTE)OUTPUT TEST POINT2.27V50pF91Ω(SEE NOTE)1098765432111121314151617181920V CCF2R1F2F2F2F2F2F2F2AA A A A A A A R1V CC C1R2V CCAR1R1R1R1R1R1R1R1R3MR82C87H CLCCNOTES:1.V CC = 5.5V ±0.5V , GND = 0V2.V IH = 4.5V ± 10%3.V IL = -0.2V to 0.4V4.R1 = 47k Ω± 5%5.R2 = 2.4k Ω± 5%6.R3 = 1.5k Ω± 5%7.R4 = 1k Ω± 5%8.R5 = 5k Ω± 5%9.C1 = 0.01µF minimum 10.F0 = 100kHz ± 10%11.F1 = F0/2, F2 = F1/2, F3 = F2/2Burn-In Circuits(Continued)456789101112131514181716V CCC1F2F2R5F2R5R5F3R5F1F0F3F2F2F2F2F2R5R5R5R5R5F3F3F3F3F3R5R5R5R5R5R4R4R5R5F33212019All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.For information regarding Intersil Corporation and its products, see web site Die CharacteristicsDIE DIMENSIONS:138.6 x 155.5 x 19± 1mils METALLIZATION:T ype: Si - AlThickness: 11k ű1k ÅGLASSIVATION:Type: SiO 2Thickness: 8k ű 1k ÅWORST CASE CURRENT DENSITY:1.47 x 105 A/cm 2Metallization Mask Layout82C87HA2A1A0V CCB0B1B2B3B4B5B6B7T GND OE A7A6A5A4A3。
5962-9950701QKA中文资料
54LVX338410-Bit Low Power Bus SwitchGeneral DescriptionThe 54LVX3384provides 10bits of high-speed CMOS TTL-compatible bus switches.The low on resistance of the switch allows inputs to be connected to outputs without add-ing propagation delay or generating additional ground bounce noise.The device is organized as two 5-bit switches with separate bus enable (OE )signals.When OE is low,the switch is on and port A is connected to port B.When OE is high,the switch is open and a high-impedance state exists between the two ports.Featuresn 4Ωswitch connection between two portsn Minimal propagation delay through the switch n Ultra low power with <0.1µA typical I CC n Zero ground bounce in flow-through mode n Control inputs compatible with TTL levels n Available in CDIP and Cerpack PackagingnStandard Microcircuit Drawing (SMD)5962-9950701Ordering CodeOrder Number Package NumberPackage Description54LVX3384J-QML J24F 24-Lead Ceramic Dual-in-line54LVX3384W-QMLW24C24-Lead CerpackLogic Diagram Pin DescriptionsPin Names DescriptionOEA,OEB Bus Switch EnableA 0–A 9Bus AB 0–B 9Bus BConnection DiagramTruth TableOEA OEB B 0–B 4B 5–B 9Function L L A 0–A 4A 5–A 9Connect L H A 0–A 4HIGH-Z State Connect H L HIGH-Z State A 5–A 9Connect HHHIGH-Z StateHIGH-Z StateDisconnectDS101061-1Pin Assignment for CDIP and CerpackApril 199954LVX338410-Bit Low Power Bus Switch©1999National Semiconductor Corporation Absolute Maximum Ratings(Note1)If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.Supply Voltage(V CC)-0.5V to+7.0V DC Switch Voltage(V S)−0.5V to+7.0V DC Input Voltage(V IN)(Note2)−0.5V to+7.0V DC Input Diode Current(I IK)V IN<0V−20mA DC Output(I OUT)Sink Current100mA Storage Temperature Range(T STG)−65˚C to+150˚C Power Dissapation500mW Junction Temperature(T J)175˚C Recommended Operating Conditions(Note3)Power Supply Operating(V CC) 4.5V to5.5V Input Voltage(V IN)0V to5.5V Input Rise and Fall Time(t r,t f)Switch Control Input0nS/V to5nS/V Switch I/O0nS/V to DC Free Air Operating Temperature(T A)−55˚C to+125˚C Note1:The“Absolute Maximum Ratings”are those values beyond which the safety of the device cannot be guaranteed.The device should not be op-erated at these limits.The parametric values defined in the“Electrical Char-acteristics”table are not guaranteed at the absolute maximum ratings.The “Recommended Operating Conditions”table will define the conditions for ac-tual device operation.Note2:The input and output negative voltage ratings may be exceeded if the input and output diode current ratings are observed.Note3:Unused control inputs must be held HIGH or LOW.They may not float.DC Electrical CharacteristicsSymbol Parameter V CC(V)T A=−55˚C to+125˚C Units Condition Min MaxV IC Clamp Diode Voltage 4.5−1.2V I IN=−18mAV IH High Level Input Voltage 4.5-5.5 2.0VV IL Low Level Input Voltage 4.5-5.50.8VI I Input Leakage Current 5.5±1.0µA0≤V IN≤5.5V I OZ TRI-STATE Leakage Current 5.5±10.0µA0≤A,B≤V CCR ON Switch On Resistance(Note4)4.510ΩV IN=0V,I IN=30mA 4.520ΩV IN=0V,I IN=15mAI CC Quiescent Supply Current 5.510µA V IN=V CC or GND,I OUT=0∆I CC Increase in I cc per Input 5.5 2.5mA One input at3.4VOther inputs at V CC or GNDI OFF Power Off Leakage Current0.010µA V IN=5.5V or0.0VI OS Short Circuit Output Current(Note5)4.580mA V IN=4.5V,V OUT=0.0VNote4:Measured by voltage drop between A and B pin at indicated current through the switch.On resistance is determined by the lower of the voltages on the two(A or B)pins.Note5:Not more than one output tested at a time.2AC Electrical CharacteristicsSymbol Parameter T A=−55˚C to+125˚CC L=50pF,RU=RD=500ΩUnits Conditions Figure No.V CC=4.5−5.5VMin Maxt PHL,t PLHProp Delay Bus to Bus(Note6)0.25ns V I=open Figures1,2t PZH,t PZLOutput Enable Time 1.0 6.0ns V I=7V for t PZL Figures1,2OE A,OE B to An,Bn V I=open for t PZHt PHZ,t PLZOutput Disable Time 1.0 6.0ns I I=7V for t PLZ Figures1,2OE A,OE B to An,Bn V I=open for t PHZNote6:This parameter is guaranteed by design but not tested.The bus switch contributes no propagation delay other than the RC delay of the typical On resistanceof the switch and the50pF load capacitance,when driven by an ideal voltage the source(zero output impedance).Capacitance(Note7)Symbol Parameter Max Units ConditionsC IN Control Input Capacitance10pF V CC=OpenC I/O(OFF)Input/Output Capacitance12pF V CC,OE=5.0VNote7:Capacitance is characterized but not tested.3AC Loading and WaveformsDS101061-4Note:Input driven by50Ohms source terminated in50OhmsNote:C L includes load and stray capacitanceNote:Input PRR=1.0MHz,t W=500nSFIGURE1.AC Test CircuitDS101061-5FIGURE2.AC Waveforms54LVX3384V IN vs R ON(Typ)DS101061-34Physical Dimensions inches(millimeters)unless otherwise noted24-Lead Ceramic Dual-in-linePackage Number J24F24-Lead CerpackPackage Number W24C5NotesLIFE SUPPORT POLICYNATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION.As used herein:1.Life support devices or systems are devices or systems which,(a)are intended for surgical implant into the body,or (b)support or sustain life,and whose failure to perform when properly used in accordance with instructions for use provided in the labeling,can be reasonably expected to result in a significant injury to the user.2.A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system,or to affect its safety or effectiveness.National Semiconductor Corporation AmericasTel:1-800-272-9959Fax:1-800-737-7018Email:support@National Semiconductor EuropeFax:+49(0)180-5308586Email:europe.support@Deutsch Tel:+49(0)180-5308585English Tel:+49(0)180-5327832Français Tel:+49(0)180-5329358Italiano Tel:+49(0)180-5341680National Semiconductor Asia Pacific Customer Response Group Tel:65-2544466Fax:65-2504466Email:sea.support@National Semiconductor Japan Ltd.Tel:81-3-5639-7560Fax:81-3-5639-750754L V X 338410-B i t L o w P o w e r B u s S w i t c hNational does not assume any responsibility for use of any circuitry described,no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.。
AEC-Q200 中文(单一元件)
耐溶解力
机械冲击
振动
耐焊接热
ESD
MIL-STD12 202 Method 215 MIL-STD13 202 Method 213 MIL-STD14 202 Method 204 MIL-STD15 202 Method 210 AEC-Q200002 or 17 ISO/DIS 10605
Байду номын сангаас
水系化学清洗。OKEM清洗或等同。
可焊性 电性能描述 线路板弯曲 引线强度 （SMD)
引脚产品和SMD都适用。不用电性能测试。50倍放大，条件： 引脚产品Method A@235℃,category 3. 18 J-STD-002 SMD 产品：a)Method B,4小时@155℃干热@235 ℃ b)Method B @215℃ category3 c)Method D category3 @260℃ 19 User Spec 每批和规定数量的样品进行参数测试。室温下和工作温度下最小，最大平均，标准值。 AEC-Q200最少保留60秒 21 005 AEC-Q20022 006
注：受压前电性能测试也作电性能参数。1000小时测试时250小时和 500小时作间隙测试。
见213方法图1，C条 5g的力20分钟，用8*5*0.031英寸的PCB在3个方向各做12各循环。在8英寸边上有7个支撑点，在对面的角 上两个支撑点。器件安装在任意一个支撑点的2英寸范围内。测试从10HZ-2000HZ. 未预热的样品Condition B. 备注：单波焊接-Porcedure 1 引脚产品焊料少于1.5mm,除了230℃外其他 Procedure 1，SMD产品浸到覆盖SMD引脚。
aecq200标准中谐振器相关部份主要在5455两页见如下译文aecq200d版本2010年6月1日汽车电子委员会元件技术会表12参考方法陶瓷谐振器受测项目序号参考标准附加条件前期与后期电性能测试1用户标准测试除了可适用测试标准和表12中的额外要求中列出的项目
5962-8670405VPA中文资料
UC1842A/3A/4A/5A UC2842A/3A/4A/5A UC3842A/3A/4A/5A•Optimized for Off-line and DC to DC Converters•Low Start Up Current (<0.5mA)•Trimmed Oscillator Discharge Current •Automatic Feed Forward Compensation •Pulse-by-Pulse Current Limiting•Enhanced Load Response Characteristics •Under-Voltage Lockout With Hysteresis •Double Pulse Suppression •High Current Totem Pole Output •Internally Trimmed Bandgap Reference •500kHz Operation •Low R O Error AmpCurrent Mode PWM ControllerThe UC1842A/3A/4A/5A family of control ICs is a pin for pin compati-ble improved version of the UC3842/3/4/5family.Providing the nec-essary features to control current mode switched mode power supplies,this family has the following improved features.Start up cur-rent is guaranteed to be less than 0.5mA.Oscillator discharge is trimmed to 8.3mA.During under voltage lockout,the output stage can sink at least 10mA at less than 1.2V for V CC over 5V .The difference between members of this family are shown in the table below.FEATURESDESCRIPTIONPart #UVLO On UVLO Off Maximum DutyCycleUC1842A 16.0V 10.0V <100%UC1843A 8.5V 7.9V <100%UC1844A 16.0V 10.0V <50%UC1845A8.5V7.9V<50%UC1842A/3A/4A/5A UC2842A/3A/4A/5AUC3842A/3A/4A/5ACONNECTION DIAGRAMSABSOLUTE MAXIMUM RATINGS (Note 1)Note 1.All voltages are with respect to Ground, Pin 5.Currents are positive into, negative out of the specified terminal.Consult Packaging Section of Databook for thermal limitations and con-siderations of packages.Pin numbers refer to DIL package only.Supply Voltage (Low Impedance Source). . . . . . . . . . . . . .30V Supply Voltage (I CC mA). . . . . . . . . . . . . . . . . . . .Self Limiting Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±1A Output Energy (Capacitive Load). . . . . . . . . . . . . . . . . . . . .5µJ Analog Inputs (Pins 2, 3). . . . . . . . . . . . . . . . . . .-0.3V to +6.3V Error Amp Output Sink Current . . . . . . . . . . . . . . . . . . . .10mA Power Dissipation at T A ≤25°C (DIL-8). . . . . . . . . . . . . . . .1W Storage Temperature Range. . . . . . . . . . . . . .-65°C to +150°C Lead Temperature (Soldering, 10 Seconds). . . . . . . . . .300°C N/C VREF VCC OUTPUT VCC GND 12345678161514131211N/C N/C N/CRT/CT N/C COMP VFB ISENSE PWRGND N/C109SOIC-WIDE16(TOP VIEW)DW PackagePARAMETERTEST CONDITIONSUC184xA\UC284xA UC384xAUNITSMIN.TYP.MAX.MIN.TYP.MAX.Reference Section Output Voltage T J = 25°C, I O = 1mA 4.955.00 5.05 4.905.00 5.10V Line Regulation 12≤V IN 25V 620620mV Load Regulation 1≤I O ≤20mA 625625mV Temp. Stability(Note 2, Note 7)0.20.40.20.4mV/°C Total Output Variation Line, Load, Temp. 4.95.14.825.18V Output Noise Voltage 10Hz ≤f ≤10kHz T J = 25°C (Note 2)5050µV Long Term Stability T A = 125°C, 1000Hrs. (Note 2)525525mV Output Short Circuit -30-100-180-30-100-180mA Oscillator Section Initial Accuracy T J = 25°C (Note 6)475257475257kHz Voltage Stability 12≤V CC ≤25V0.210.21%Temp. Stability T MIN ≤T A ≤T MAX (Note 2)55%AmplitudeV PIN 4peak to peak (Note 2) 1.7 1.7V Discharge Current T J = 25°C,V PIN 4= 2V (Note 8)7.88.38.87.88.38.8mA V PIN 4= 2V (Note 8)7.58.87.68.8mA Error Amp Section Input VoltageV PIN 1= 2.5V2.45 2.50 2.55 2.42 2.50 2.58V Input Bias Current -0.3-1-0.3-2µA A VOL2≤V O ≤4V65906590dB Unity Gain Bandwidth T J = 25°C (Note 2)0.710.71MHz PSRR12≤V CC ≤25V60706070dB Output Sink Current V PIN 2= 2.7V,V PIN 1= 1.1V 2626mA Output Source Current V PIN 2= 2.3V,V PIN 1= 5V-0.5-0.8-0.5-0.8mA V OUT High V PIN 2= 2.3V,R L = 15k to ground 5656V V OUT LowV PIN 2= 2.7V,R L = 15k to Pin 80.7 1.10.7 1.1V Current Sense Section Gain(Note 3, Note 4) 2.853 3.15 2.853 3.15V/V Maximum Input Signal V PIN 1= 5V (Note 3)0.91 1.10.91 1.1V PSRR12≤V CC ≤25V (Note 3)7070dB Input Bias Current -2-10-2-10µA Delay to Output V PIN 3= 0 to 2V (Note 2)150300150300ns Output Section Output Low Level I SINK = 20mA 0.10.40.10.4V I SINK = 200mA 15 2.215 2.2V Output High Level I SOURCE = 20mA 1313.51313.5V I SOURCE = 200mA1213.51213.5V Rise Time T J = 25°C, C L = 1nF (Note 2)5015050150ns Fall TimeT J = 25°C, C L = 1nF (Note 2)5015050150ns UVLO SaturationV CC = 5V,I SINK = 10mA0.71.20.71.2VELECTRICAL CHARACTERISTICS Unless otherwise stated,these specifications apply for –55°C ≤T A ≤125°C for theUC184xA;–40°C ≤T A ≤125°C for the UC284xAQ;–40°C ≤T A ≤85°C for the UC284xA;0≤T A ≤70°C for the UC384xA;V CC =15V (Note 5);R T =10k;C T =3.3nF;T A =T J ;Pin numbers refer to DIL-8.PARAMETERTEST CONDITIONSUC184xA\UC284xA UC384xAUNITSMIN.TYP.MAX.MIN.TYP.MAX.Under-Voltage Lockout Section Start Threshold x842A/4A 15161714.51617.5V x843A/5A 7.88.49.07.88.49.0V Min. Operation Voltage After x842A/4A 910118.51011.5V Turn On x843A/5A 7.07.68.27.07.68.2V PWM SectionMaximum Duty Cycle x842A/3A 94961009496100%x844A/5A474850474850%Minimum Duty Cycle 00%Total Standby Current Start-Up Current0.30.50.30.5mA Operating Supply Current V PIN 2=V PIN 3= 0V 11171117mA V CC Zener VoltageI CC = 25mA30343034VNote 2:Ensured by design, but not 100% production tested.Note 3:Parameter measured at trip point of latch with V PIN2= 0.Note 4:Gain defined as:A VPIN VPIN =∆∆13;0V PIN 30.8V .Note 5:Adjust V CC above the start threshold before setting at 15V .Note 6:Output frequency equals oscillator frequency for the UC1842A and UC1843A.Output frequency is one half oscillator fre-quency for the UC1844A and UC1845A.Note 7:“Temperature stability, sometimes referred to as average temperature coefficient, is described by the equation:Temp Stability VREF max VREF min TJ max TJ min =−−()()()().V REF (max) and V REF (min) are the maximum & minimum reference volt-age measured over the appropriate temperature range.Note that the extremes in voltage do not necessarily occur at the extremes in temperature.”Note 8:This parameter is measured with R T = 10k to V REF .This contributes approximately 300 A of current to the measurement.The total current flowing into the R T /C pin will be approximately 300 A higher than the measured value.ELECTRICAL CHARACTERISTICS Unless otherwise stated,these specifications apply for –55°C ≤T A ≤125°C for theUC184xA;–40°C ≤T A ≤125°C for the UC284xAQ;–40°C ≤T A ≤85°C for the UC284xA;0≤T A ≤70°C for the UC384xA;V CC =15V (Note 5);R T =10k;C T =3.3nF;T A =T J ;Pin numbers refer to DIL-8.Error Amplifier Open-Loop Frequency ResponseOutput Saturation CharacteristicsUC2842A/3A/4A/5AAPPLICATIONS DATA (cont.)UC2842A/3A/4A/5AUC3842A/3A/4A/5AAPPLICATIONS DATA (cont.)PACKAGING INFORMATIONOrderable Device Status(1)PackageType PackageDrawingPins PackageQtyEco Plan(2)Lead/Ball Finish MSL Peak Temp(3)5962-8670405PA ACTIVE CDIP JG81None A42SNPB Level-NC-NC-NC 5962-8670405VPA ACTIVE CDIP JG81None Call TI Level-NC-NC-NC 5962-8670405VXA ACTIVE LCCC FK201None Call TI Level-NC-NC-NC 5962-8670405XA ACTIVE LCCC FK201None POST-PLATE Level-NC-NC-NC 5962-8670406PA ACTIVE CDIP JG81None A42SNPB Level-NC-NC-NC 5962-8670406VPA ACTIVE CDIP JG81None Call TI Level-NC-NC-NC 5962-8670406VXA ACTIVE LCCC FK201None Call TI Level-NC-NC-NC 5962-8670406XA ACTIVE LCCC FK201None POST-PLATE Level-NC-NC-NC 5962-8670407PA ACTIVE CDIP JG81None A42SNPB Level-NC-NC-NC 5962-8670407VPA ACTIVE CDIP JG81None Call TI Level-NC-NC-NC 5962-8670407VXA ACTIVE LCCC FK201None Call TI Level-NC-NC-NC 5962-8670407XA ACTIVE LCCC FK201None POST-PLATE Level-NC-NC-NC 5962-8670408PA ACTIVE CDIP JG81None A42SNPB Level-NC-NC-NC 5962-8670408VPA ACTIVE CDIP JG81None Call TI Level-NC-NC-NC 5962-8670408VXA ACTIVE LCCC FK201None Call TI Level-NC-NC-NC 5962-8670408XA ACTIVE LCCC FK201None POST-PLATE Level-NC-NC-NC UC1842AJ ACTIVE CDIP JG81None A42SNPB Level-NC-NC-NCUC1842AJ883B ACTIVE CDIP JG81None A42SNPB Level-NC-NC-NCUC1842AJQMLV ACTIVE CDIP JG8None Call TI Call TIUC1842AL883B ACTIVE LCCC FK201None POST-PLATE Level-NC-NC-NCUC1842ALQMLV ACTIVE LCCC FK20None Call TI Call TI UC1843AJ ACTIVE CDIP JG81None A42SNPB Level-NC-NC-NCUC1843AJ883B ACTIVE CDIP JG81None A42SNPB Level-NC-NC-NCUC1843AJQMLV ACTIVE CDIP JG8None Call TI Call TIUC1843AL883B ACTIVE LCCC FK201None POST-PLATE Level-NC-NC-NCUC1843ALQMLV ACTIVE LCCC FK20None Call TI Call TI UC1844AJ ACTIVE CDIP JG81None A42SNPB Level-NC-NC-NCUC1844AJ883B ACTIVE CDIP JG81None A42SNPB Level-NC-NC-NCUC1844AJQMLV ACTIVE CDIP JG8None Call TI Call TIUC1844AL883B ACTIVE LCCC FK201None POST-PLATE Level-NC-NC-NCUC1844ALQMLV ACTIVE LCCC FK20None Call TI Call TI UC1845AJ ACTIVE CDIP JG81None A42SNPB Level-NC-NC-NCUC1845AJ883B ACTIVE CDIP JG81None A42SNPB Level-NC-NC-NCUC1845AJQMLV ACTIVE CDIP JG8None Call TI Call TIUC1845AL883B ACTIVE LCCC FK201None POST-PLATE Level-NC-NC-NCUC1845ALQMLV ACTIVE LCCC FK20None Call TI Call TI UC2842AD ACTIVE SOIC D1450None CU NIPDAU Level-1-220C-UNLIM UC2842AD8ACTIVE SOIC D875None CU NIPDAU Level-1-220C-UNLIM UC2842AD8TR ACTIVE SOIC D82500None CU NIPDAU Level-1-220C-UNLIM UC2842AD8TRG4ACTIVE SOIC D82500None Call TI Call TIUC2842ADTR ACTIVE SOIC D142500None CU NIPDAU Level-1-220C-UNLIM UC2842ADW ACTIVE SOIC DW1640None CU NIPDAU Level-2-220C-1YEAROrderable Device Status(1)PackageType PackageDrawingPins PackageQtyEco Plan(2)Lead/Ball Finish MSL Peak Temp(3)UC2842ADWTR ACTIVE SOIC DW162000None CU NIPDAU Level-2-220C-1YEAR UC2842AJ OBSOLETE CDIP JG8None Call TI Call TIUC2842AN ACTIVE PDIP P850Pb-Free(RoHS)CU SNPB Level-NC-NC-NC UC2843AD ACTIVE SOIC D1450None CU NIPDAU Level-1-220C-UNLIM UC2843AD8ACTIVE SOIC D875None CU NIPDAU Level-1-220C-UNLIM UC2843AD8TR ACTIVE SOIC D82500None CU NIPDAU Level-1-220C-UNLIM UC2843ADTR ACTIVE SOIC D142500None CU NIPDAU Level-1-220C-UNLIM UC2843ADW ACTIVE SOIC DW1640None CU NIPDAU Level-2-220C-1YEAR UC2843ADWTR ACTIVE SOIC DW162000None CU NIPDAU Level-2-220C-1YEAR UC2843AJ OBSOLETE CDIP JG8None Call TI Call TIUC2843AN ACTIVE PDIP P850Pb-Free(RoHS)CU SNPB Level-NC-NC-NC UC2843AQ ACTIVE PLCC FN2046None CU SNPB Level-2-220C-1YEAR UC2844AD ACTIVE SOIC D1450None CU NIPDAU Level-1-220C-UNLIM UC2844AD8ACTIVE SOIC D875None CU NIPDAU Level-1-220C-UNLIM UC2844AD8TR ACTIVE SOIC D82500None CU NIPDAU Level-1-220C-UNLIM UC2844AD8TRG4PREVIEW SOIC D82500None Call TI Call TIUC2844ADTR ACTIVE SOIC D142500None CU NIPDAU Level-1-220C-UNLIM UC2844ADW ACTIVE SOIC DW1640None CU NIPDAU Level-2-220C-1YEAR UC2844ADWTR ACTIVE SOIC DW162000None CU NIPDAU Level-2-220C-1YEAR UC2844AJ ACTIVE CDIP JG81None A42SNPB Level-NC-NC-NC UC2844AN ACTIVE PDIP P850Pb-Free(RoHS)CU SNPB Level-NC-NC-NC UC2844AQD ACTIVE SOIC D1450None Call TI Level-1-220C-UNLIM UC2844AQD8ACTIVE SOIC D875None Call TI Level-1-220C-UNLIM UC2844AQD8R ACTIVE SOIC D82500None Call TI Level-1-220C-UNLIM UC2844AQDR ACTIVE SOIC D142500None Call TI Level-1-220C-UNLIM UC2845AD ACTIVE SOIC D1450None CU NIPDAU Level-1-220C-UNLIM UC2845AD8ACTIVE SOIC D875None CU NIPDAU Level-1-220C-UNLIM UC2845AD8TR ACTIVE SOIC D82500None CU NIPDAU Level-1-220C-UNLIM UC2845AD8TRG4PREVIEW SOIC D82500None Call TI Call TIUC2845ADTR ACTIVE SOIC D142500None CU NIPDAU Level-1-220C-UNLIM UC2845ADW ACTIVE SOIC DW1640None CU NIPDAU Level-2-220C-1YEAR UC2845AN ACTIVE PDIP P850Pb-Free(RoHS)CU SNPB Level-NC-NC-NC UC3842AD ACTIVE SOIC D1450None CU NIPDAU Level-1-220C-UNLIM UC3842AD8ACTIVE SOIC D875None CU NIPDAU Level-1-220C-UNLIM UC3842AD8TR ACTIVE SOIC D82500None CU NIPDAU Level-1-220C-UNLIM UC3842ADTR ACTIVE SOIC D142500None CU NIPDAU Level-1-220C-UNLIM UC3842ADW ACTIVE SOIC DW1640None CU NIPDAU Level-2-220C-1YEAR UC3842ADWTR ACTIVE SOIC DW162000None CU NIPDAU Level-2-220C-1YEAR UC3842AJ ACTIVE CDIP JG81None A42SNPB Level-NC-NC-NC UC3842AN ACTIVE PDIP P850Pb-Free(RoHS)CU SNPB Level-NC-NC-NCOrderable Device Status(1)PackageType PackageDrawingPins PackageQtyEco Plan(2)Lead/Ball Finish MSL Peak Temp(3)UC3842ANG4ACTIVE PDIP P850Green(RoHS&no Sb/Br)CU NIPDAU Level-NA-NA-NAUC3843AD ACTIVE SOIC D1450None CU NIPDAU Level-1-220C-UNLIM UC3843AD8ACTIVE SOIC D875None CU NIPDAU Level-1-220C-UNLIM UC3843AD8G4ACTIVE SOIC D875None Call TI Call TIUC3843AD8TR ACTIVE SOIC D82500None CU NIPDAU Level-1-220C-UNLIM UC3843AD8TRG4ACTIVE SOIC D82500Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMUC3843ADG4ACTIVE SOIC D1450Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIM UC3843ADTR ACTIVE SOIC D142500None CU NIPDAU Level-1-220C-UNLIM UC3843AJ ACTIVE CDIP JG81None A42SNPB Level-NC-NC-NCUC3843AN ACTIVE PDIP P850Pb-Free(RoHS)CU SNPB Level-NC-NC-NCUC3843ANG4ACTIVE PDIP P850Green(RoHS&no Sb/Br)CU NIPDAU Level-NA-NA-NA UC3844AD ACTIVE SOIC D1450None CU NIPDAU Level-1-220C-UNLIM UC3844AD8ACTIVE SOIC D875None CU NIPDAU Level-1-220C-UNLIM UC3844AD8TR ACTIVE SOIC D82500None CU NIPDAU Level-1-220C-UNLIM UC3844AD8TRG4ACTIVE SOIC D82500Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIM UC3844ADTR ACTIVE SOIC D142500None CU NIPDAU Level-1-220C-UNLIM UC3844ADW ACTIVE SOIC DW1640None CU NIPDAU Level-2-220C-1YEAR UC3844ADWTR ACTIVE SOIC DW162000None CU NIPDAU Level-2-220C-1YEAR UC3844AN ACTIVE PDIP P850Pb-Free(RoHS)CU SNPB Level-NC-NC-NC UC3845AD ACTIVE SOIC D1450None CU NIPDAU Level-1-220C-UNLIM UC3845AD8ACTIVE SOIC D875None CU NIPDAU Level-1-220C-UNLIM UC3845AD8TR ACTIVE SOIC D82500None CU NIPDAU Level-1-220C-UNLIM UC3845ADTR ACTIVE SOIC D142500None CU NIPDAU Level-1-220C-UNLIM UC3845ADW ACTIVE SOIC DW1640None CU NIPDAU Level-2-220C-1YEAR UC3845ADWTR ACTIVE SOIC DW162000None CU NIPDAU Level-2-220C-1YEAR UC3845AJ ACTIVE CDIP JG81None A42SNPB Level-NC-NC-NCUC3845AN ACTIVE PDIP P850Pb-Free(RoHS)CU SNPB Level-NC-NC-NCUC3845ANG4ACTIVE PDIP P850Green(RoHS&no Sb/Br)CU NIPDAU Level-NA-NA-NA(1)The marketing status values are defined as follows:ACTIVE:Product device recommended for new designs.LIFEBUY:TI has announced that the device will be discontinued,and a lifetime-buy period is in effect.NRND:Not recommended for new designs.Device is in production to support existing customers,but TI does not recommend using this part in a new design.PREVIEW:Device has been announced but is not in production.Samples may or may not be available.OBSOLETE:TI has discontinued the production of the device.(2)Eco Plan-May not be currently available-please check /productcontent for the latest availability information and additional product content details.None:Not yet available Lead(Pb-Free).Pb-Free(RoHS):TI's terms"Lead-Free"or"Pb-Free"mean semiconductor products that are compatible with the current RoHS requirementsfor all 6substances,including the requirement that lead not exceed 0.1%by weight in homogeneous materials.Where designed to be soldered at high temperatures,TI Pb-Free products are suitable for use in specified lead-free processes.Green (RoHS &no Sb/Br):TI defines "Green"to mean "Pb-Free"and in addition,uses package materials that do not contain halogens,including bromine (Br)or antimony (Sb)above 0.1%of total product weight.(3)MSL,Peak Temp.--The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications,and peak solder temperature.Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.TI bases its knowledge and belief on information provided by third parties,and makes no representation or warranty as to the accuracy of such information.Efforts are underway to better integrate information from third parties.TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary,and thus CAS numbers and other limited information may not be available for release.In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s)at issue in this document sold by TI to Customer on an annualbasis.PACKAGE OPTION ADDENDUM 10-Mar-2005Addendum-Page 4元器件交易网。
5962-9088108QPA中文资料
D D D D D D
Supply Current . . . 300 µA Max High Unity-Gain Bandwidth . . . 2 MHz Typ High Slew Rate . . . 0.45 V/µs Min Supply-Current Change Over Military Temp Range . . . 10 µA Typ at VCC ± = ± 15 V Specified for Both 5-V Single-Supply and ±15-V Operation Phase-Reversal Protection
D D D D D
High Open-Loop Gain . . . 6.5 V/µV (136 dB) Typ Low Offset Voltage . . . 100 µV Max Offset Voltage Drift With Time 0.005 µV/mo Typ Low Input Bias Current . . . 50 nA Max Low Noise Voltage . . . 19 nV/√Hz Typ
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
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—
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† The D packages are available taped and reeled. To order a taped and reeled part, add the suffix R (e.g., TLE2021CDR). ‡ The DB and PW packages are only available left-end taped and reeled. § Chip forms are tested at 25°C only. TLE2022 AVAILABLE OPTIONS PACKAGED DEVICES TA VIOmax AT 25°C 150 µV 300 µV 500 µV 150 µV 300 µV 500 µV 150 µV 300 µV 500 µV SMALL OUTLINE† (D) TLE2022BCD TLE2022ACD TLE2022CD TLE2022BID TLE2022AID TLE2022ID — TLE2022AMD TLE2022MD SSOP‡ (DB) — — TLE2022CDBLE — — — CHIP CARRIER (FK) CERAMIC DIP (JG) PLASTIC DIP (P) — TLE2022ACP TLE2022CP — TLE2022AIP TLE2022IP — TLE2022AMP TLE2022MP TSSOP‡ (PW) — — TLE2022CPWLE — CHIP FORM§ (Y) — — TLE2022Y —
5962-9550404QCA中文资料
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Advanced LinCMOS is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. On products compliant to MILĆPRFĆ38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
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CERAMIC FLATPACK (U) — — — — — TLV2262AMU TLV2262MU
† The D packages are available taped and reeled. Add R suffix to device type (e.g., TLV2262CDR). ‡ The PW package is available only left-end taped and reeled. § Chips are tested at 25°C. TLV2264 AVAILABLE OPTIONS PACKAGED DEVICES TA −40°C to 125°C −40°C to 125°C −55°C to 125°C VIOmax AT 25°C 950 µV 2.5 mV 950 µV 2.5 mV 950 µV 2.5 mV SMALL OUTLINE (D) TLV2264AID TLV2264ID TLV2264AQD TLV2264QD — — CHIP CARRIER (FK) — — — — TLV2264AMFK TLV2264MFK CERAMIC DIP (J) — — — — TLV2264AMJ TLV2264MJ PLASTIC DIP (N) TLV2264AIN TLV2264IN — — — — TSSOP (PW) TLV2264AIPWLE — — — — — CERAMIC FLATPACK (W) — — — — TLV2264AMW TLV2264MW
5962-9583401QXC中文资料
FEATURES q >155.5 Mbps (77.7 MHz) switching rates q +340mV differential signaling q 5 V power supplyq TTL compatible outputsq Ultra low power CMOS technology q 8.0ns maximum propagation delay q 3.0ns maximum differential skewqRadiation-hardened design; total dose irradiation testing to MIL-STD-883 Method 1019- Total-dose: 300 krad(Si) and 1Mrad(Si)- Latchup immune (LET > 111 M eV-cm 2/mg)q Packaging options:- 16-lead flatpack (dual in-line)q Standard Microcircuit Drawing 5962-95834- QML Q and V compliant partq Compatible with IEEE 1596.3SCI LVDSqCompatible with ANSI/TIA/EIA 644-1996 LVDS StandardINTRODUCTIONThe UT54LVDS032 Quad Receiver is a quad CMOSdifferential line receiver designed for applications requiring ultra low power dissipation and high data rates. The device is designed to support data rates in excess of 155.5 Mbps (77.7 MHz) utilizing Low Voltage Differential Signaling (LVDS) technology.The UT54LVDS032 accepts low voltage (340mV) differential input signals and translates them to 5V TTL output levels. The receiver supports a three-state function that may be used to multiplex outputs. The receiver also supports OPEN, shorted and terminated (100 Ω) input fail-safe. Receiver output will be HIGH for all fail-safe conditions.The UT54LVDS032 and companion quad line driver UT54LVDS031 provides new alternatives to high power pseudo-ECL devices for high speed point-to-point interface applications.Standard Products UT54LVDS032 Quad ReceiverData SheetMay 22, 2003TRUTH TABLEPIN DESCRIPTION APPLICATIONS INFORMATIONThe UT54LVDS032 receiver’s intended use is primarily in an uncomplicated point-to-point configuration as is shown in Figure 3. This configuration provides a clean signalingenvironment for quick edge rates of the drivers. The receiver is connected to the driver through a balanced media which may be a standard twisted pair cable, a parallel pair cable, or simply PCB traces. Typically, the characteristic impedance of the media is in the range of 100Ω. A termination resistor of 100Ω should be selected to match the media and is located as close to the receiver input pins as possible. The termination resistor converts the current sourced by the driver into voltages that are detected by the receiver. Other configurations are possible such as a multi-receiver configuration, but the effects of a mid-stream connector(s), cable stub(s), and other impedance discontinuities, as well as ground shifting, noise margin limits, and total termination loading must be taken into account.The UT54LVDS032 differential line receiver is capable of detecting signals as low as 100mV, over a + 1V common-mode range centered around +1.2V. This is related to the driver offset voltage which is typically +1.2V. The driven signal is centered around this voltage and may shift +1V around this center point. The +1V shifting may be the result of a ground potential difference between the driver’s ground reference and the receiver’s ground reference, the common-mode effects of coupled noise or a combination of the two. Both receiver input pins should honor their specified operating input voltage range of 0V to +2.4V (measured from each pin to ground).Enables Input Output EN EN R IN+ - R IN -R OUT LHX Z All other combinations of ENABLE inputsV ID > 0.1V H V ID < -0.1V L Full Fail-safe OPEN/SHORT or TerminatedHPin Description2, 6, 10, 14R IN+Non-inverting receiver input pin 1, 7, 9, 15R IN-Inverting receiver input pin3, 5, 11, 13R OUT Receiver output pin 4EN Active high enable pin, OR-edwith EN 12EN Active low enable pin, OR-edwith EN 16V DD Power supply pin, +5V + 10%8V SSGround pinFigure 2. UT54LVDS032 PinoutUT54LVDS032Receiver161514131211109V DD R IN4-R IN4+R OUT4EN R OUT3R IN3+R IN3-1R IN1-2R IN1+3R OUT14EN 5R OUT26R IN2+7R IN2-8V SSENABLEDATA INPUT1/4 UT54LVDS0311/4 UT54LVDS032+-DATA OUTPUTFigure 3. Point-to-Point ApplicationRT 100ΩReceiver Fail-SafeThe UT54LVDS032 receiver is a high gain, high speed device that amplifies a small differential signal (20mV) to TTL logic levels. Due to the high gain and tight threshold of the receiver, care should be taken to prevent noise from appearing as a valid signal.The receiver’s internal fail-safe circuitry is designed to source/ sink a small amount of current, providing fail-safe protection (a stable known state of HIGH output voltage) for floating, terminated or shorted receiver inputs.1. Open Input Pins. The UT54LVDS032 is a quadreceiver device, and if an application requires only 1, 2or 3 receivers, the unused channel(s) inputs should beleft OPEN. Do not tie unused receiver inputs to groundor any other voltages. The input is biased by internal highvalue pull up and pull down resistors to set the output toa HIGH state. This internal circuitry will guarantee aHIGH, stable output state for open inputs.2. Terminated Input. If the driver is disconnected (cable unplugged), or if the driver is in a three-state condition, the receiver output will again be in a HIGH state, even with the end of cable 100Ω termination resistor across the input pins. The unplugged cable can become a floating antenna which can pick up noise. If the cable picks up more than 10mV of differential noise, the receiver may see the noise as a valid signal and switch. To insure that any noise is seen as common-mode and not differential, a balanced interconnect should be used. Twisted pair cable offers better balance than flat ribbon cable.3. Shorted Inputs. If a fault condition occurs that shorts the receiver inputs together, thus resulting in a 0V differential input voltage, the receiver output remains in a HIGH state. Shorted input fail-safe is not supported across the common-mode range of the device (V SS to 2.4V). It is only supported with inputs shorted and no external common-mode voltage applied.ABSOLUTE MAXIMUM RATINGS 1(Referenced to V SS )Notes:1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability and performance.2. Maximum junction temperature may be increased to +175°C during burn-in and steady-static life.3. Test per MIL-STD-883, Method 1012.RECOMMENDED OPERATING CONDITIONSSYMBOL PARAMETERLIMITS V DD DC supply voltage -0.3 to 6.0V V I/O Voltage on any pin -0.3 to (V DD + 0.3V)T STG Storage temperature -65 to +150°C P D Maximum power dissipation 1.25 W T J Maximum junction temperature 2+150°C ΘJC Thermal resistance, junction-to-case 310°C/WI IDC input current±10mASYMBOL PARAMETERLIMITS V DD Positive supply voltage 4.5 to 5.5V T C Case temperature range -55 to +125°C V INDC input voltage, receiver inputs DC input voltage, logic inputs2.4V0 to V DD for EN, ENDC ELECTRICAL CHARACTERISTICS 1(V DD = 5.0V +10%; -55°C < T C < +125°C)Notes:1. Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground.2. Output short circuit current (I OS ) is specified as magnitude only, minus sign indicates direction only. Only one output should be shorted at a time, do not excee d maximum junction temperature specification.3. Guaranteed by characterization.4. Device tested at V CC =5.5V only.SYMBOL PARAMETERCONDITIONMIN MAXUNIT V IH High-level input voltage (TTL) 2.0V V IL Low-level input voltage (TTL)0.8V V OL Low-level output voltage I OL = 2mA, V DD = 4.5V 0.3V V OH High-level output voltage I OH = -0.4mA, V DD = 4.5V 4.0V I INLogic input leakage currentInputs, V IN = 0 and 2.4V, V CC = 5.5Enables = EN/EN= 0 and 5.5V, V CC = 5.5-10-10+10+10µAV TH 3Differential Input High Threshold V CM = +1.2V +100mV V TL 3Differential Input Low Threshold V CM = +1.2V -100mV I I Receiver input Current V IN = 2.4V-10+10µΑI OZ 4Output Three-State Current Disabled, V OUT = 0 V or V DD -10+10µΑV CL Input clamp voltage I CL = +/-18mA -1.5 1.5V I OS 3Output Short Circuit Current Enabled, V OUT = 0 V 2-15-130mA I CC 4Loaded supply current receivers enabledEN, EN = V DD or V SS Inputs Open 11mAI CCZ 4Loaded supply current receivers disabledEN = V SS , EN = V DD Inputs Open11mAAC SWITCHING CHARACTERISTICS 1, 2, 3, 4(V DD = +5.0V + 10%, T A = -55 °C to +125 °C)Notes:1. Channel-to-Channel Skew is defined as the difference between the propagation delay of the channel and the other channels in the same chip with an event on the inputs.2. Generator waveform for all tests unless otherwise specified: f = 1 MHz, Z 0 = 50Ω, t r and t f (0% - 100%) < 1ns for R IN and t r and t f < 6ns for EN or EN.3. C L includes probe and jig capacitance.4. Guaranteed by characterization.5. Chip to Chip Skew is defined as the difference between the minimum and maximum specified differential propagation delays.SYMBOL PARAMETERMIN MAX UNIT t PHLD Differential Propagation Delay High to Low CL = 20pf (figures 4 and 5)1.08.0ns t PLHD Differential Propagation Delay Low to High CL = 20pf (figures 4 and 5)1.08.0ns t SKD Differential Skew (t PHLD - t PLHD ) (figures 4 and 5)0 3.0ns t SK14Channel-to-Channel Skew 1 (figures 4 and 5)03.0ns t SK24Chip-to-Chip Skew 5 (figures 4 and 5)7.0ns t TLH 4Rise Time (figures 4 and 5) 2.0ns t THL 4Fall Time (figures 4 and 5)2.0ns t PHZ 4Disable Time High to Z (figures 6 and 7)20ns t PLZ 4Disable Time Low to Z (figures 6 and 7)20ns t PZH 4Enable Time Z to High (figures 6 and 7)20ns t PZL 4Enable Time Z to Low (figures 6 and 7)20nsRR IN+R OUTReceiver EnabledGenerator50ΩFigure 4. Receiver Propagation Delay and Transition Time Test Circuit or Equivalent CircuitR IN-50ΩC LR IN-R IN+RV OLFigure 5. Receiver Propagation Delay and Transition Time WaveformsFigure 6. Receiver Three-State Delay Test Circuit or Equivalent CircuitR IN+R IN-ENV DD2K2K20pfEN when EN = V DDEN when EN = V SSOutput when V ID = -100mV Output when V ID = +100mVV OHV SS V DD Figure 7. Receiver Three-State Delay WaveformV OLPACKAGINGNotes:1. All exposed metalized areas are gold plated over electroplated nickel per MIL-PRF-38535.2. The lid is electrically connected to VSS.3. Lead finishes are in accordance to MIL-PRF-38535.4. Package dimensions and symbols are similar to MIL-STD-1835 variation F-5A.5. Lead position and coplanarity are not measured.6. ID mark symbol is vendor option.7. With solder, increase maximum by 0.003.Figure 8. 16-pin Ceramic FlatpackORDERING INFORMATION UT54LVDS032 QUAD RECEIVER:UT 54LVDS032- * * * * *Device Type:UT54LVDS032 LVDS ReceiverAccess Time:Not applicablePackage Type:(U) = 16-lead Flatpack (dual-in-line)Screening:(C) = Military Temperature Range flow (P) = Prototype flowLead Finish:(A) = Hot solder dipped (C) = Gold(X) = Factory option (gold or solder)Notes:1.Lead finish (A,C, or X) must be specified.2.If an “X” is specified when ordering, then the part marking will match the lead finish and will be either “A” (solder) or “C” (gold).3.Prototype flow per UTMC Manufacturing Flows Document. Tested at 25°C only. Lead finish is GOLD ONLY. Radiation neither tested nor guaranteed.itary Temperature Range flow per UTMC Manufacturing Flows Document. Devices are tested at -55°C, room temp, and 125°C. Radiation neither tested nor guaranteed.11UT54LVDS032 QUAD RECEIVER: SMD 5962 - ***Federal Stock Class Designator: No OptionsTotal Dose(R) = 1E5 rad(Si)(F) = 3E5 rad(Si)(G) = 5E5 rad(Si)(H) = 1E6 rad(Si)Drawing Number: 95834Device Type02 = LVDS ReceiverClass Designator:(Q) = QML Class Q(V) = QML Class VCase Outline:(X) = 16 lead Flatpack (dual-in-line)Lead Finish:(A) = Hot solder dipped(C) = Gold(X) = Factory Option (gold or solder)**95834Notes:1.Lead finish (A,C, or X) must be specified.2.If an “X” is specified when ordering, part marking will match the lead finish and will be either “A” (solder) or “C” (gold).3.Total dose radiation must be specified when ordering. QML Q and QML V not available without radiation hardening.元器件交易网。
5962-9755901Q2A中文资料
PACKAGING INFORMATIONOrderable Device Status(1)PackageType PackageDrawingPins PackageQtyEco Plan(2)Lead/Ball Finish MSL Peak Temp(3)5962-86839012A ACTIVE LCCC FK201None Call TI Level-NC-NC-NC 5962-8683901RA ACTIVE CDIP J201None Call TI Level-NC-NC-NC 5962-8683901SA ACTIVE CFP W201None Call TI Level-NC-NC-NC 5962-9755901Q2A ACTIVE LCCC FK201None Call TI Level-NC-NC-NC 5962-9755901QRA ACTIVE CDIP J201None Call TI Level-NC-NC-NC 5962-9755901QSA ACTIVE CFP W201None Call TI Level-NC-NC-NC JM38510/38303B2A ACTIVE LCCC FK201None Call TI Level-NC-NC-NC JM38510/38303BRA ACTIVE CDIP J201None Call TI Level-NC-NC-NC SN54ALS244CJ ACTIVE CDIP J201None Call TI Level-NC-NC-NC SN54AS244AJ ACTIVE CDIP J201None Call TI Level-NC-NC-NCSN74ALS244C-1DW ACTIVE SOIC DW2025Pb-Free(RoHS)CU NIPDAU Level-2-250C-1YEAR/Level-1-235C-UNLIMSN74ALS244C-1DWR ACTIVE SOIC DW202000Pb-Free(RoHS)CU NIPDAU Level-2-250C-1YEAR/Level-1-235C-UNLIMSN74ALS244C-1N ACTIVE PDIP N2020Pb-Free(RoHS)CU NIPDAU Level-NC-NC-NCSN74ALS244C-1NSR ACTIVE SO NS202000Pb-Free(RoHS)CU NIPDAU Level-2-260C-1YEAR/Level-1-235C-UNLIMSN74ALS244CDBLE OBSOLETE SSOP DB20None Call TI Call TISN74ALS244CDBR ACTIVE SSOP DB202000Pb-Free(RoHS)CU NIPDAU Level-2-260C-1YEAR/Level-1-235C-UNLIMSN74ALS244CDW ACTIVE SOIC DW2025Pb-Free(RoHS)CU NIPDAU Level-2-250C-1YEAR/Level-1-235C-UNLIMSN74ALS244CDWR ACTIVE SOIC DW202000Pb-Free(RoHS)CU NIPDAU Level-2-250C-1YEAR/Level-1-235C-UNLIMSN74ALS244CN ACTIVE PDIP N2020Pb-Free(RoHS)CU NIPDAU Level-NC-NC-NCSN74ALS244CNSR ACTIVE SO NS202000Pb-Free(RoHS)CU NIPDAU Level-2-260C-1YEAR/Level-1-235C-UNLIMSN74AS244ADW ACTIVE SOIC DW2025Pb-Free(RoHS)CU NIPDAU Level-2-250C-1YEAR/Level-1-235C-UNLIMSN74AS244ADWR ACTIVE SOIC DW202000Pb-Free(RoHS)CU NIPDAU Level-2-250C-1YEAR/Level-1-235C-UNLIMSN74AS244AN ACTIVE PDIP N2020Pb-Free(RoHS)CU NIPDAU Level-NC-NC-NCSN74AS244ANSR ACTIVE SO NS202000Pb-Free(RoHS)CU NIPDAU Level-2-260C-1YEAR/Level-1-235C-UNLIMSNJ54ALS244CFK ACTIVE LCCC FK201None Call TI Level-NC-NC-NC SNJ54ALS244CJ ACTIVE CDIP J201None Call TI Level-NC-NC-NC SNJ54ALS244CW ACTIVE CFP W201None Call TI Level-NC-NC-NC SNJ54AS244AFK ACTIVE LCCC FK201None Call TI Level-NC-NC-NC SNJ54AS244AJ ACTIVE CDIP J201None Call TI Level-NC-NC-NC SNJ54AS244AW ACTIVE CFP W201None Call TI Level-NC-NC-NC(1)The marketing status values are defined as follows:ACTIVE:Product device recommended for new designs.LIFEBUY:TI has announced that the device will be discontinued,and a lifetime-buy period is in effect.NRND:Not recommended for new designs.Device is in production to support existing customers,but TI does not recommend using this part in a new design.PREVIEW:Device has been announced but is not in production.Samples may or may not be available.OBSOLETE:TI has discontinued the production of the device.(2)Eco Plan-May not be currently available-please check /productcontent for the latest availability information and additional product content details.None:Not yet available Lead(Pb-Free).Pb-Free(RoHS):TI's terms"Lead-Free"or"Pb-Free"mean semiconductor products that are compatible with the current RoHS requirements for all6substances,including the requirement that lead not exceed0.1%by weight in homogeneous materials.Where designed to be soldered at high temperatures,TI Pb-Free products are suitable for use in specified lead-free processes.Green(RoHS&no Sb/Br):TI defines"Green"to mean"Pb-Free"and in addition,uses package materials that do not contain halogens, including bromine(Br)or antimony(Sb)above0.1%of total product weight.(3)MSL,Peak Temp.--The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications,and peak solder temperature.Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.TI bases its knowledge and belief on information provided by third parties,and makes no representation or warranty as to the accuracy of such information.Efforts are underway to better integrate information from third parties.TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary,and thus CAS numbers and other limited information may not be available for release.In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s)at issue in this document sold by TI to Customer on an annual basis.IMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. T esting and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed.TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. T o minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards.TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI.Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation.Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions:Products ApplicationsAmplifiers Audio /audioData Converters Automotive /automotiveDSP Broadband /broadbandInterface Digital Control /digitalcontrolLogic Military /militaryPower Mgmt Optical Networking /opticalnetwork Microcontrollers Security /securityTelephony /telephonyVideo & Imaging /videoWireless /wirelessMailing Address:Texas InstrumentsPost Office Box 655303 Dallas, Texas 75265Copyright 2005, Texas Instruments Incorporated。
5962-9961001HXA中文资料
fIN = 41 MHz
fIN = 71 MHz
fIN = 121 MHz
Full
VI
Full
VI
Full
I
Full
IV
Full
I
Full
Full
IV
25°C
V
25°C
V
Full
IV
Full
IV
25°C
V
25°C
V
Full
IV
Full
IV
Full
IV
Full
IV
Full
IV
25°C
V
4, 5, 6 12 12
12 12 12 12
12 12 12 12 12
105
10
45
50
55
1.0
0.25
3.0
5.3
4.5
5.5
8.0
3.5
3.3
The AD10200 operates with 5.0 V supply for the analog-todigital conversion. Each channel is completely independent allowing operation with independent encode and analog inputs. The AD10200 is packaged in a 68-lead ceramic chip carrier package. Manufacturing is done on Analog Devices, Inc. MIL38534 Qualified Manufacturers Line (QML) and components are available up to Class-H (–55°C to +125°C).
5962-9954401HXC中文资料
MOR SERIES 120 WATTDC/DC C ONVERTERS 28 V OLT I NPUT+_F EATURES•–55°C to +125°C operation •16 to 40 VDC input •Fully isolated•Magnetic feedback•Fixed frequency 550 kHz typ.••Will withstand transients of up to 50 V for up to 120 msec.•Output trim 60% to 110%•Input and output side inhibit •Remote sense •Synchronization•Parallel up to 5 units•Output short circuit protection•Up to 80 W/in 3, 87% efficiency DESCRIPTIONWith up to 120 watts of output power, the MOR Series™of DC/DC converters operates from a standard 28 volt bus and offers a wide input range of 16 to 40 VDC. Full operation over the military temper-ature range, –55°C to +125°C, makes the MOR Series an ideal choice for military, aerospace, space, and other high reliability appli-cations. In compliance with MIL-STD-704D, the converters will with-stand transients of up to 50 volts for up to 120 milliseconds. Use Interpoint’s FME 28-461 E MI filter to pass MIL-STD-461C, CE 03requirements.The MOR Series converters incorporate a single-ended forward topology which uses a constant frequency Pulse Width Modulator(PWM) current mode control design and switches at 550 kHz,nominal. The converters also provide short circuit protection by restricting the current to 125% of the full load output current. All models offer two inhibits, one referenced to input common and one referenced to output common. A remote sense function is available on single output models.Using the trim function, the MOR Series can provide any output from 2 to 33 VDC. For example, trimming the two 15 volt outputs of the 15 dual (MOR2815D) to 14 volts, and then stacking the outputs will provide a 28 volt output. See Figure 11.元器件交易网TYPICAL CHARACTERISTICSSYNC AND INHIBIT (INH1,INH2)PINS NOT IN USERECOMMENDED OPERATING CONDITIONSABSOLUTE MAXIMUM RATINGSInput Voltage Range•16 to 40 VDC continuous •50 V for 120 msec transient Case Operating Temperature (Tc)•–55°C to +125°C full power •–55°C to +135°C absolute Derating Output Power/Current•Linearly from 100% at 125°C to 0% at 135°C2MOR SERIES 120 WATTDC/DC CONVERTERSInput Voltage •16 to 40 VDCPower Dissipation (Pd)•30 WOutput Power•66 to 120 watts depending on modelLead Soldering Temperature (10 sec per lead)•300°CStorage Temperature Range (Case)•–65°C to +150°COutput Voltage Temperature Coefficient •100 ppm/°C typicalInput to Output Capacitance •150 pF typicalUndervoltage Lockout •15.5 V input typical Current Limit•125% of full load typical Isolation•100 megohm minimum at 500 V Audio Rejection •40 dB typicalConversion Frequency•Free run mode 550 kHz typical460 kHz. min, 570 kHz max • External sync range 525 to 625 kHz Inhibit Pin Voltage (unit enabled)• INH1 = 13 V typ, INH2 = 8 V typNotes: See notes 1, 2, 3, and 4 on the following page.SINGLE OUTPUT MODELS MOR283R3S MOR2805S MOR286R3S MOR289R5S PARAMETER CONDITION MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS OUTPUT VOLTAGE 3.25 3.30 3.35 4.95 5.00 5.05 6.24 6.30 6.369.409.509.60VDC OUTPUT CURRENT V IN = 16 to 40 VDC 0—200—200—160—11A OUTPUT POWER V IN = 16 to 40 VDC 0—660—1000—1000—105WOUTPUT RIPPLE 10 kHz - 20 MHz VOLTAGETc = –55°C to +125°C —3080—3080—75100—75120mV p-p10 kHz - 2 MHz Tc = –55°C to +125°C —2050—2050—5060—5080LINE REGULATION V IN = 16 to 40 VDC —020—020—020—020mV LOAD REGULATION NO LOAD TO FULL —020—020—020—020mV INPUT VOLTAGE CONTINUOUS 162840162840162840162840VDC TRANSIENT 120 ms——50——50——50——50V INPUT CURRENTNO LOAD —70130—70130—70130—70130mA FULL LOAD —— 3.2—— 4.67—— 4.45—— 4.63A INHIBITED - INH1——10——10——10——10mAINHIBITED - INH2——70——70——70——70INPUT RIPPLE 10 kHz - 20 MHz CURRENT Tc = –55°C to +125°C —4090—50130—50100—50130mA pp EFFICIENCY 7478—7881—8183—8184—%LOAD FAULT 1POWER DISSIPATIONOVERLOAD ——27——30——30——30W SHORT CIRCUIT 2——22——27——24——24RECOVERY ——10——10——10——10msOUTPUT CURRENTTRIP POINT ——25——25——20——14ASHORT CIRCUIT 2——24——24——19——13STEP LOAD RESP .50% – 100% – 50%TRANSIENT ——250——250——500——500mV pk RECOVERY 3——200——200——300——300µs STEP LINE RESP .16 – 40 – 16 VDC TRANSIENT 4——400——400——500——500mV pk RECOVERY 3——300——300——300——300µs START-UPDELAY ——10——10——10——10ms OVERSHOOT —025—050—050—050mV pk INHIBIT PIN CURRENTUNIT INHIBITED—0.11.0—0.11.0—0.11.0—0.11.0mASync In (525 to 625 kHz)•Logic low 0.8 V max, duty cycle 15% to 50%•Logic high 4.5 V min, 9 V max •Referenced to input commonSync Out - Referenced to input common Inhibit (INH1,INH2) :TTL Open Collector •Logic low (output disabled), V = 0.2 V max.•INH1 referenced to input common •INH2 referenced to output common•Logic high (output enabled) open collectorTrim CaseInhibit (INH1,INH2) Sync Out Sync In ShareSense LinesNo connectionUsers discrimination No connection No connectionConnect to input common No connectionMust be connected to appropriate outputsElectrical Characteristics:25°C Tc,28 VDC Vin,100% load,free run,unless otherwise specified.元器件交易网3MOR SERIES 120 WATTDC/DC CONVERTERSSINGLE AND DUAL OUTPUT MODELSMOR2812S MOR2815S MOR283R3D MOR2805D PARAMETER CONDITIONSMIN TYP MAX MIN TYP MAX MIN TYP MAX MINTYP MAXUNITS OUTPUT VOLTAGE 5+V OUT 11.8812.0012.1214.8515.0015.153.25 3.30 3.354.955.00 5.05VDC –V OUT—————— 3.22 3.30 3.38 4.92 5.00 5.08OUTPUT CURRENT V IN = 16 to 40 VDC 0—9.20—8—±10206—±10206A OUTPUT POWER V IN = 16 to 40 VDC ——110——120——666——1006WOUTPUT RIPPLE 10 kHz -20 MHz VOLTAGETc = –55°C to +125°C — 75120—75150—5080—5080mV p-p+V OUT , ±V OUT 10 kHz -2 MHz Tc = –55°C to +125°C—50100—50120—3550—3550LINE REGULATION +V OUT—020—020—2550—2550mV V IN = 16 to 40 VDC –V OUT ———————50100—50100LOAD REGULATION +V OUT —020—020—2550—2550mV –V OUT ———————50150—50150CROSS REGULATION 7NEGATIVE V OUT ———————610—58%INPUT VOLTAGE CONTINUOUS 162840162840162840162840VDC TRANSIENT 120 msec——50——50——50——50V INPUT CURRENTNO LOAD —70130—70130—70140—70140mA FULL LOAD —— 4.72—— 5.10—— 3.2—— 4.67A INHIBITED - INH1——10——10——10——10mAINHIBITED - INH2——70——70——70——70INPUT RIPPLE 10 kHz - 20 MHz CURRENT Tc = –55°C to +125°C —50130—50130—60130—60130mA p-p EFFICIENCY 8486—8487—7677—7881—%LOAD FAULT 1POWER DISSIPATIONOVERLOAD ——30——30——27——30W SHORT CIRCUIT 2——22——22——22——27RECOVERY ——10——10——10——10msOUTPUT CURRENTTRIP POINT ——12——10——25——25ASHORT CIRCUIT 2——11——9——24——24STEP LOAD RESP .50% – 100% — 50%+V OUT , ±V OUT TRANSIENT ——600——600——250——250mV pk RECOVERY 3——300——300——200——200µs STEP LINE RESP .16 – 40 – 16 VDC +V OUT , ±V OUT TRANSIENT 4——600——600——400——400mV pk RECOVERY 3——300——300——300——300µs START-UPDELAY ——10——10——10——10ms OVERSHOOT ——50——50——25——50mV pk INHIBIT PIN CURRENTUNIT INHIBITED—0.11.0—0.11.0—0.11.0—0.11.0mANotes:1.Load fault conditions are measured with a resistive load.2.Short circuit is measured with a 10 m W (±10%) load.3.Time to settle to within 1% of Vout.4.Transition time > 10 µs5.Output voltage for dual output models is measured at half load.6.The maximum specification is the total output current/power. Up to 70% of that total is available from either output provided the other output maintains a minimum of 15% the total power used.7.Cross regulation percentages are for the following conditions:+Po = 30% and –Po = 70%+Po = 10% and –Po = 50%+Po = 70% and –Po = 30%+Po = 50% and –Po = 10%Electrical Characteristics:25°C Tc,28 VDC Vin,100% load,free run,unless otherwise specified.元器件交易网4MOR SERIES 120 WATTDC/DC CONVERTERSDUAL OUTPUT MODELSMOR286R3DMOR289R5D MOR2812D MOR2815D PARAMETER CONDITIONSMIN TYP MAX MIN TYP MAX MINTYP MAXMINTYP MAXUNITS OUTPUT VOLTAGE 5+V OUT 6.24 6.30 6.369.409.509.6011.8812.0012.1214.8515.0015.15VDC –V OUT6.20 6.30 6.409.359.509.6511.8012.0012.2014.7615.0015.24OUTPUT CURRENT 6V IN = 16 to 40 VDC —±816—±5.5311.05—±4.589.16—±4.008.00A 6OUTPUT POWER V IN = 16 to 40 VDC ——100——105——110——120WOUTPUT RIPPLE 10 kHz -20 MHz VOLTAGETc = –55°C to +125°C — 50100—75120—75120—75150mV p-p+V OUT / –V OUT 10 kHz -2 MHz Tc = –55°C to +125°C—3060—5080—50100—50120LINE REGULATION +V OUT —2550—2550—2550—2550mV V IN = 16 to 40 VDC –V OUT —50160—50100—50100—50100LOAD REGULATION +V OUT —2550—2550—2550—2550mV –V OUT—50200—50200—50200—50200CROSS REGULATION 7NEGATIVE V OUT —58—47—35—24%INPUT VOLTAGE CONTINUOUS 162840162840162840162840VDC TRANSIENT 120 msec ——50——50——50——50V INPUT CURRENTNO LOAD —70140—70140—70140—70140mA FULL LOAD —— 4.45—— 4.63—— 4.72—— 5.10A INHIBITED - INH1——10——10——10——10mAINHIBITED - INH2——70——70——70——70INPUT RIPPLE 10 kHz - 20 MHz CURRENT Tc = –55°C to +125°C ——130——130——130——130mA p-p EFFICIENCY 8183—8284—8486—8587—%LOAD FAULT 1POWER DISSIPATIONOVERLOAD ——30——30——30——30W SHORT CIRCUIT 2——24——24——22——20RECOVERY ——10——10——10——10msOUTPUT CURRENTTRIP POINT ——20——14——11——10ASHORT CIRCUIT 2——19——13——10——9STEP LOAD RESP .50% – 100% — 50%±V OUTTRANSIENT ——500——500——600——600mV pk RECOVERY 3——300——300——300——300µs STEP LINE RESP .16 – 40 – 16 VDC ±V OUT TRANSIENT 4——500——600——600——750mV pk RECOVERY 3——300——300——300——300µs START-UPTIME ——10——10——10——10ms OVERSHOOT ——50——50——50——50mV pk INHIBIT PIN CURRENTUNIT INHIBITED—0.11.0—0.11.0—0.11.0—0.11.0mAElectrical Characteristics:Tc = 25°C,full load,Vin = 28 VDC,free run,unless otherwise specified.Notes:1.Load fault conditions are measured with a resistive load.2.Short circuit is measured with a 10 m W (±10%) load.3.Time to settle to within 1% of Vout.4.Transition time > 10 µs5.Output voltage for dual output models is measured at half load.6.The maximum specification is the total output current/power. Up to 70% of that total is available from either output provided the other output maintains a minimum of 15% the total power used.7.Cross regulation percentages are for the following conditions:+Po = 30% and –Po = 70%+Po = 10% and –Po = 50%+Po = 70% and –Po = 30%+Po = 50% and –Po = 10%元器件交易网PIN DESCRIPTIONS AND FUNCTIONSP IN O UTP OSITIVE I NPUT AND I NPUT C OMMONSteady state voltage range is 16 to 40 VDC. Transient range is 40 to 50 V for a maximum of 120 msec. Low voltage lockout prevents the units from operating below approximately 15.5 VDC input voltage to keep system current levels smooth, especially during initialization or re-start operations. All models include a soft-start function to prevent large current draw and minimize overshoot.C ASE ANDE XTERNAL I NPUTF ILTERSInternal 500 V capacitors are connected between the case and input common and between the case and output common. See Figure 1.Interpoint’s FME filters are recommended to meet CE03 require-ments for reflected input line current. When using an external input filter it is important that the case of the filter and the case of the converter be connected through as low as an impedance as possible. Direct connection of the baseplates to chassis ground is the best connection. If connected by a single trace, the trace should be as wide as it is long. T RIMBoth single and dual outputmodels include a trim function.Output voltage can be trimmedfrom 60% up to 110% of nominalV out . When trimming up, do notexceed the maximum outputpower. When trimming down, donot exceed the maximum outputcurrent.On dual models the positiveoutput is regulated and thenegative output is transformercoupled (cross-regulated) to thepositive output. When trimmingthe duals, both output voltageswill be adjusted equally.I NHIBIT1 AND2Two inhibit terminals disable switching, resulting in no output and very low quiescent input current. The two inhibit pins allow access to an inhibit function on either side of the isolation barrier to help maintain isolation.An open collector isrequired for inter-facing with both ofthe inhibit pins.Applying an open-collector TTL logiclow to either inhibitpin will inhibit theconverter. Applyingan open collectorTTL logic high orleaving the pinsopen will enable the converter. Inhibit 1 is referenced to Input Common, while Inhibit 2 is referenced to Sense Return on the output side.The open circuitvoltage for Inhibit 1 is13 V and for Inhibit 2 itis 8 V. Float the inhibitpin(s) if not used. Therequired logic lowvoltage level is 0.2 Vmaximum.5MOR SERIES120 WATTDC/DC CONVERTERS元器件交易网6MOR SERIES 120 WATTDC/DC CONVERTERSS YNC I N AND S YNC O UTThe MOR converters can be synchronized to the system clock by applying a TTL compat-ible sync signal to the Sync In pin. Sync Out can be used to synchro-nize other components to the MOR converter ’s switching frequency.The frequency range for external synchronization is 525 to 625 kHz.The requirements for an external signal are 15% to 50% duty cycle,0 ≤L ≤0.8 V and 4.5 ≤H ≤9 V.Both Sync In and Sync Out are referenced to input common. Sync In should be grounded to input common if not used.P OSITIVE S ENSE ,S ENSE R ETURNA special remote sensing feature maintains the desired output voltage at the load. When this feature is not used, connect the sense lines to their respective output terminals. Remote sensing is available on single output models only. See Figure 12. Do not exceed 110% of Vout and maximum output power.S HARE (P ARALLELING )By using the Share pin, up to five single or dual converters may be paralleled for a total output power of over 500 watts (90% Pout /converter, max.). The converters will share within 10% of each other at 25 to 90% rated power. MOR converters feature true n+1redundancy for reliability in critical applications. See Figure 9 for the proper connections.All Positive Outputs and Positive Senses should be connected to a common point. All Negative Outputs and Sense Returns should be connected to a common point. The Share pin is referenced to Sense Return. Leave the share pin floating (unconnected) if not used.P OSITIVE O UTPUT ,N EGATIVE O UTPUT AND O UTPUT C OMMONOutput current is limited to 125% of maximum specified current under short circuit or load fault conditions.Single output models operate from no load to full load. Dual output models with balanced loads operate from no load to full load. For dual models with unbalanced loads, at least 10% of the total output power must be drawn from the positive outputat all times, however, the negative output does not require a minimum load.See note 7, cross regula-tion, under the E lectrical Characteristics Tables.Dual outputs may be“stacked ” to double the output voltage.T YPICAL C ONNECTIONS元器件交易网7MOR SERIES 120 WATTDC/DC C ONVERTERS元器件交易网8MOR SERIES 120 WATTDC/DC CONVERTERSIGUREF IGURE 29FIGURE 30F IGURE 31MOR2812D Sync Out200V /d i v500 ns/divMOR2805S Output Ripple (Vout)20 m V /d i vMOR2805S Input Ripple Current (Iin)20 m A /d i v1 µs/div25 µs/divRepresentative of all models80% LoadTypical Performance Curves:25°C Tc ,28 VDC Vin,100% load,20 MHz BW,free run,unless otherwise specified.元器件交易网9MOR SERIES 120 WATTDC/DC CONVERTERSF IGURE 38F IGURE 39F IGURE 40F IGURE 41F IGURE 42F IGURE43MOR2815S Step Load Response100 -50%Step Load200 m V /d i v100 µs/div50 - 100%Step LoadMOR2815S Step Line Response50 µs/divVoutVinVoutVinV i n 10 V /d i vV o u t 50 m V /d i vMOR2815S Turn On Response2.5 ms/divVinVout20 V /d i v5 V /d i vMOR2805D Output Ripple (±Vout)20 m V /d i v1 µs/div+Vout–VoutMOR2805D Input Ripple (Iin)20 m A /d i v1 µs/div 25 µs/divMOR2805D Step Load Response100 - 50%Step Load50 m V /d i v50 µs/div50% Load +Vout–Vout18 to 40 V, 40 to 18 V, 50% loadAll combinations of line and load80% load each output80% load each outputTypical Performance Curves:25°C Tc ,28 VDC Vin,100% load,20 MHz BW,free run,unless otherwise specified.F IGURE 35F IGURE 36F IGURE 37F IGURE 32F IGURE 33F IGURE 34MOR2805S Step Load Response100 -50%Step Load100 m V /d i v100 µs/divMOR2805S Step Line ResponseMOR2805S Turn On ResponseVoutVinVinVoutMOR2805S Inhibit Release Inrush Current 5 ms/div50 - 100%Step LoadVoutVinV i n 10 V /d i vV o u t 50 m V /d i v10 V /d i v2 V /d i vIinVout2 A /d i v2 V /d i vMOR2815S Output Ripple (Vout)20 m V /d i v1 µs/divMOR2815S Input Ripple (Iin)20 m A /d i v18 to 40 V, 40 to 18 VAll combinations of line and loadWith and without 470 µF cap. load元器件交易网10MOR SERIES 120 WATTDC/DC C ONVERTERSF IGURE 50F IGURE 51F IGURE 52F IGURE 53F IGURE 54MOR2812D Step Load Response100 - 50%Step Load100 m V /d i v100 µs/div50% Load+Vout –VoutMOR2812D Step Load Response50 - 100%Step Load100 m V /d i v50% Load+Vout–VoutMOR2812D Step Line Response100 µs/div+VoutVin+VoutVinV i n 10 V /d i vV o u t 100 m V /d i vMOR2812D Turn On Response2.5 ms/divVin+Vout20 V /d i v5 V /d i v–VoutMOR2812D Inhibit Release Inrush CurrentIinVout2 A /d i v 5 V /d i v18 to 40 V, 40 to 18 VTypical Performance Curves:25°C Tc ,28 VDC Vin,100% load,20 MHz BW,free run,unless otherwise specified.VinF IGURE 44F IGURE 45F IGURE 46F IGURE 47F IGURE 48F IGURE 49MOR2805D Step Load Response50 - 100%Load50 m V /d i v50 µs/div50% Load+Vout–VoutMOR2805D Step Line Response25 µs/div–VoutVin+VoutMOR2805D Step Line Response–Vout+Vout MOR2805D Turn On Response2.5 ms/divVin+Vout20 V /d i v2 V /d i v–VoutMOR2812D Output Ripple (±Vout)20 m V /d i v+Vout–VoutMOR2812D Input Ripple (Iin)20 m A /d i v1 µs/div 25 µs/div V i n 20 V /d i vV o u t 100 m V /d i vV in 20 V /d i vV o u t 100 m V /d i v 80% load each output18 to 40 V, 80% load each output40 to 18 V, 80% load each output元器件交易网1112120 WATT1314120 WATT1516120 WATTTEST125°C 125°C STANDARD/ES /883 (Class H)*PRE-CAP INSPECTION 25°C Method 2017,2032yesyesyesTEMPERATURE CYCLE (10 times)Method 1010, Cond. C, -65°C to 150°C no no yes Method 1010, Cond. B, -55°C to 125°C no yes noCONSTANT ACCELERATION 25°C Method 2001, 3000 g no no yes Method 2001, 500 gno yes noBURN-INMethod 1015, 160 hours at 125°C no no yes 96 hours at 125°C case (typical)no yes noFINAL ELECTRICAL TEST MIL-PRF-38534, Group A Subgroups 1 through 6: -55°C, +25°C, +125°C no no yes Subgroups 1 and 4: +25°C case yes yes noHERMETICITY TESTING 25°C Fine Leak, Method 1014, Cond. A no yes yes Gross Leak, Method 1014, Cond. C no yes yes Gross Leak, Dip (1 x 10-3)yes no noFINAL VISUAL INSPECTION 25°C Method 2009yes yes yesTest methods are referenced to MIL-STD-883 as determined by MIL-PRF-38534.E NVIRONMENTAL S CREENING20420-001-DTS RevD. This revision supercedes all previous releases.All technical information is believed to be accurate, but no responsibility is assumed for errors or omissions. Interpoint reserves the right to make changes in products or specifications without notice. MOR Series is a trademark of Interpoint. Copyright ©1999-2003 Interpoint. All rights reserved.Contact Information:Interpoint Headquarters USA Phone:1-800-822-8782+425-882-3100Email:power@ Interpoint UKPhone:+44-1252-872266Email:poweruk@Interpoint FrancePhone:+33-134285455Email:powerfr@。
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θJA
Package thermal impedance
Tstg
Storage temperature range
Ptot
Power dissipation(6)(7)
VI < 0 VO < 0
D package(4) DB package(4) NS package(4) PW package(4) RGY package(5)
TA –40°C to 85°C
–40°C to 125°C
–55°C to 125°C
ORDERING INFORMATION
PACKAGE (1)
ORDERABLE PART NUMBER
QFN – RGY
Reel of 1000
SN74LVC157ARGYR
Tube of 40
SN74LVC157AD
< 0.8 V at VCC = 3.3 V, TA = 25°C • Typical VOHV (Output VOH Undershoot)
> 2 V at VCC = 3.3 V, TA = 25°C
• Latch-Up Performance Exceeds 250 mA Per JESD 17
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
FEATURES
• Operate From 1.65 V to 3.6 V
• Specified From –40°C to 85°C, –40°C to 125°C, and –55°C to 125°C
• Inputs Accept Voltages to 5.5 V
• Max tpd of 5.2 ns at 3.3 V • Typical VOLP (Output Ground Bounce)
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
12 4Y
Pin numbers shown are for the D, DB, J, NS, PW, RGY, and W packages.
2
元器件交易网
SN54LVC157A, SN74LVC157A QUADRUPLE 2-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS
SCAS292P – JANUARY 1993 – REVISED JULY 2005
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
VCC
Supply voltage range
SN74LVC157A . . . RGY PACKAGE (TOP VIEW)
SN54LVC157A . . . FK PACKAGE (TOP VIEW)
Hale Waihona Puke VCCGNC
A/B
1A
VCC
A/B
A /B 1 1A 2 1B 3 1Y 4 2A 5 2B 6 2Y 7 GND 8
16 VCC 15 G 14 4A 13 4B 12 4Y 11 3A 10 3B 9 3Y
3Y
GND
NC - No internal connection
DESCRIPTION/ORDERING INFORMATION
These quadruple 2-line to 1-line data selectors/multiplexers are designed for 1.65-V to 3.6-V VCC operation. The 'LVC157A devices feature a common strobe (G) input. When G is high, all outputs are low. When G is low, a 4-bit word is selected from one of two sources and is routed to the four outputs. The devices provide true data.
元器件交易网
SN54LVC157A, SN74LVC157A QUADRUPLE 2-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS
SCAS292P – JANUARY 1993 – REVISED JULY 2005
• ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101)
BRK
BRK
SN54LVC157A . . . J OR W PACKAGE SN74LVC157A . . . D, DB, NS, OR PW PACKAGE (TOP VIEW)
VI
Input voltage range(2)
VO
Output voltage range(2)(3)
IIK
Input clamp current
IOK
Output clamp current
IO
Continuous output current
Continuous current through VCC or GND
1 1A 2 1B 3 1Y 4 2A 5 2B 6 2Y 7
8
16 15 G 14 4A 13 4B 12 4Y 11 3A 10 3B
9
3 2 1 20 19
1B 4
18 4A
1Y 5
17 4B
NC 6
16 NC
2A 7
15 4Y
2B 8
14 3A
9 10 11 12 13
3B
3Y
NC
GND
2Y
(2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. (3) The value of VCC is provided in the recommended operating conditions table. (4) The package thermal impedance is calculated in accordance with JESD 51-7. (5) The package thermal impedance is calculated in accordance with JESD 51-5. (6) For the D package, above 70°C the value of Ptot derates linearly with 8 mW/K. (7) For the DB, NS, and PW packages, above 60°C the value of Ptot derates linearly with 5.5 mW/K.
Reel of 2000
SN74LVC157APWR
Reel of 250
SN74LVC157APWT
CDIP – J
Tube of 25
SNJ54LVC157AJ
CFP – W
Tube of 150
SNJ54LVC157AW
LCCC – FK
Tube of 55
SNJ54LVC157AFK
TOP-SIDE MARKING LC157A
LVC157A
LVC157A LC157A
LC157A
SNJ54LVC157AJ SNJ54LVC157AW SNJ54LVC157AFK
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at /sc/package.
Copyright © 1993–2005, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
TA = –40°C to 125°C
MIN