8位串行模数转换器TLC548_TLC549的应用

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芯片TLC549介绍(中文的)

8位串行模数转换器TLC548、TLC549的应用1. 概述TLC548，TLC549是美国德州仪器公司生产的8位串行A/D转换器芯片，可与通用微处理器、控制器通过CLK、CS、DATA OUT三条口线进行串行接口。

具有4MHz片内系统时钟和软、硬件控制电路，转换时间最长17μs，TLC548允许的最高转换速率为45 500次/s，TLC549为40 000次/s。

总失调误差最大为±0.5LSB，典型功耗值为6mW。

采用差分参考电压高阻输入，抗干扰，可按比例量程校准转换范围，V REF-接地，V REF+－V REF-≥1V，可用于较小信号的采样。

2. 芯片简介2.1 TLC548、TLC549的内部框图和管脚名称TLC548、TLC549的内部框图和引脚名称如图1所示。

2.2 极限参数TLC548/549的极限参数如下：●电源电压：6.5V；●输入电压范围：0.3V～V CC＋0.3V；●输出电压范围：0.3V～V CC＋0.3V；●峰值输入电流(任一输入端)：±10mA；●总峰值输入电流(所有输入端)：±30mA；●工作温度：TLC548C、TLC549C：0℃～70℃TLC548I、TLC549I：－40℃～85℃TLC548M、TLC549M：－55℃～125℃3. 工作原理TLC548、TLC549均有片内系统时钟，该时钟与I/O CLOCK是独立工作的，无须特殊的速度或相位匹配。

其工作时序如图2所示。

当CS为高时，数据输出(DATA OUT)端处于高阻状态，此时I/O CLOCK 不起作用。

这种CS控制作用允许在同时使用多片TLC548、TLC549时，共用I/O CLOCK，以减少多路(片)A/D并用时的I/O控制端口。

一组通常的控制时序为：(1)将CS置低。

内部电路在测得CS下降沿后，再等待两个内部时钟上升沿和一个下降沿后，然后确认这一变化，最后自动将前一次转换结果的最高位(D7)位输出到DATA OUT端上。

目前常用的AD芯片（TI公司）

⽬前常⽤的AD芯⽚（TI公司）⽬前AD/DA的常⽤芯⽚介绍：TI公司AD/DA器件：1)TLC548/549TLC548和TLC549是以8位开关电容逐次逼近A/D转换器为基础⽽构造的CMOSA/D转换器。

它们设计成能通过3态数据输出与微处理器或外围设备串⾏接⼝。

TLC548和TLC549仅⽤输⼊/输出时钟和芯⽚选择输⼊作数据控制。

TLC548的最⾼I/OCLOCK 输⼊频率为2.048MHz,⽽TLC549的I/OCLOCK输⼊频率最⾼可达1.1MHz。

TLC548和TLC549的使⽤与较复杂的TLC540和TLC541⾮常相似；不过，TLC548和TLC549提供了⽚内系统时钟，它通常⼯作在4MHz且不需要外部元件。

⽚内系统时钟使内部器件的操作独⽴于串⾏输⼊/输出端的时序并允许TLC548和TLC549象许多软件和硬件所要求的那样⼯作。

I/OCLOCK和内部系统时钟⼀起可以实现⾼速数据传送，对于TLC548为每秒45,500次转换，对于TLC549为每秒40,000次的转换速度。

TLC548和TLC549的其他特点包括通⽤控制逻辑，可⾃动⼯作或在微处理器控制下⼯作的⽚内采样-保持电路，具有差分⾼阻抗基准电压输⼊端，易于实现⽐率转换(ratiometricconversion).定标(scaling)以及与逻辑和电源噪声隔离的电路。

整个开关电容逐次逼近转换器电路的设计允许在⼩于17µs的时间内以最⼤总误差为±0.5最低有效位(LSB)的精度实现转换。

2)TLV5616TLV5616是⼀个12位电压输出数模转换器(DAC),带有灵活的4线串⾏接⼝，可以⽆缝连接TMS320.SPI.QSPI和Microwire串⾏⼝。

数字电源和模拟电源分别供电，电压范围2.7～5.5V。

输出缓冲是2倍增益rail-to-rail输出放⼤器，输出放⼤器是AB类以提⾼稳定性和减少建⽴时间。

rail-to-rail输出和关电⽅式⾮常适宜单电源。

串行AD转换器TLC549的应用设计

串行AD转换器TLC549的应用设计
一、TLC549的简介
TLC549是一种高精度的8位左对齐的模拟-数字转换器，它由Texas Instruments公司公司开发。

使用了低功耗CMOS和 Flash-Plus（快速结构）技术，它具有较高的性能，抗干扰性和功耗低的特点。

它的电源电压
为3 V - 5 V，并具有外部时钟，转换速度可达6个MHz，带宽为200 KHz，转换精度高达8位。

根据TLC549的特性，它可以实现高精度，高带宽，高速率，低功耗，低失真和低噪声等功能，因此，它在很多领域中得到了广泛的应用。

（1）量测系统
应用TLC549可以设计一种低功耗的量测系统，因为TLC549可以将模
拟量（如温度、湿度、压力等）转换成数字量，并将数字量输出至数字接口，从而实现模拟信号检测以及声音检测的功能。

TLC549采用单片机的
接口结构，它的带宽高达200KHz，转换精度高达8位，可以满足多种精度，带宽的需求。

（2）无线传感器系统
TLC549可以用于设计无线传感器系统，它可以将模拟信号转换成数
字信号，然后将数字信号传输至接收端，进而实现无线传感器的功能。

TLC549能够将模拟信号转换为8位高精度的数字信号，并将数据以比特
的形式传输出去，降低了传输成本，实现了真正的无线传感器系统。

芯片TLC549,TLC548介绍_中文的_

具有4MHz片内系统时钟和软、硬件控制电路，转换时间最长17μs，TLC548允许的最高转换速率为45 500次/s，TLC549为40 000次/s。

总失调误差最大为±0.5LSB，典型功耗值为6mW。

采用差分参考电压高阻输入，抗干扰，可按比例量程校准转换范围，V REF-接地，V REF+－V REF-≥1V，可用于较小信号的采样。

2. 芯片简介2.1 TLC548、TLC549的内部框图和管脚名称TLC548、TLC549的内部框图和引脚名称如图1所示。

其工作时序如图2所示。

当CS为高时，数据输出(DATA OUT)端处于高阻状态，此时I/O CLOCK 不起作用。

这种CS控制作用允许在同时使用多片TLC548、TLC549时，共用I/O CLOCK，以减少多路(片)A/D并用时的I/O控制端口。

一组通常的控制时序为：(1)将CS置低。

TLC548,TLC549 8位串行AD转换器芯片介绍

TLC548，TLC549 8位串行A/D转换器芯片介绍TLC548，TLC549是美国德州仪器公司生产的8位串行A/D转换器芯片，可与通用微处理器、控制器通过I/O CLOCK、CS、DATA OUT三条口线进行串行接口。

具有4MHz片内系统时钟和软、硬件控制电路，转换时间最长17μs，TLC548允许的最高转换速率为45 500次/s，TLC549为40 000次/s。

总失调误差最大为±0.5LSB，典型功耗值为6mW。

采用差分参考电压高阻输入，抗干扰，可按比例量程校准转换范围，VREF-接地，VREF+－VREF-≥1V，可用于较小信号的采样。

2. 芯片简介2.1 TLC548、TLC549的内部框图和管脚名称TLC548、TLC549的内部框图和引脚名称如图1所示。

2.2 极限参数TLC548/549的极限参数如下：●电源电压：6.5V；●输入电压范围：0.3V～VCC＋0.3V；●输出电压范围：0.3V～VCC＋0.3V；●峰值输入电流(任一输入端)：±10mA；●总峰值输入电流(所有输入端)：±30mA；●工作温度：TLC548C、TLC549C：0℃～70℃TLC548I、TLC549I：－40℃～85℃TLC548M、TLC549M：－55℃～125℃3. 工作原理TLC548、TLC549均有片内系统时钟，该时钟与I/O CLOCK是独立工作的，无须特殊的速度或相位匹配。

其工作时序如图2所示。

当CS为高时，数据输出(DATA OUT)端处于高阻状态，此时I/O CLOCK不起作用。

这种CS控制作用允许在同时使用多片TLC548、TLC549时，共用I/O CLOCK，以减少多路(片)A/D并用时的I/O 控制端口。

一组通常的控制时序为：(1)将CS置低。

tlc549时序图

CS = 0; 出最高位 _nop_(); _nop_();
//CS 置低，片选有效，同时 DO 输 //适当延迟时间1.4us Setup Time
for(i = 0; i < 8; i++) //串行数据移位输入 {
tmp <<= 1; tmp |= DO;
CLK = 1; _nop_(); CLK = 0;
void Data_Conversion(void) { unsigned char AD_Data; AD_Data = TLC549_ADC(); Volt = 5.0 / 256 * AD_Data * 1000; }
/*-------------------------------------------------------------*/
//防止头文件被重复调用 #ifndef __TLC549_ADC_H__ #define __TLC549_ADC_H__
/*-------------------------------------------------------------*/ //包含头文件
#include<intrins.h>
//0.4us //CLK transition time Max 0.1us
//0.4us
}
CS = 1;
//CS 置高，片选无效
for(i = 17; i != 0; i--) _nop_(); //Next Coversion 需要延迟时间17us
return (tmp);
}
/*-------------------------------------------------------------*/ //电压换算并扩大1000倍

TLC549IP;TLC549CP;TLC549CD;TLC548CP;TLC549ID;中文规格书,Datasheet资料

TLC548C, TLC548I, TLC549C, TLC549I 8-BIT ANALOG-TO-DIGITAL CONVERTERSWITH SERIAL CONTROLSLAS067C – NOVEMBER 1983 – REVISED SEPTEMBER 19961POST OFFICE BOX 655303 •DALLAS, TEXAS 75265D Microprocessor Peripheral or Standalone OperationD 8-Bit Resolution A/D ConverterD Differential Reference Input Voltages D Conversion Time ...17 µs MaxDTotal Access and Conversion Cycles Per Second– TLC548...up to 45500– TLC549...up to 40000D On-Chip Software-Controllable Sample-and-Hold FunctionD Total Unadjusted Error ...±0.5 LSB Max D 4-MHz Typical Internal System Clock D Wide Supply Range ...3V to 6VD Low Power Consumption ...15mW Max D Ideal for Cost-Effective, High-Performance Applications including Battery-Operated Portable InstrumentationDPinout and Control Signals Compatible With the TLC540 and TLC545 8-Bit A/D Converters and with the TLC1540 10-Bit A/D ConverterDCMOS TechnologydescriptionThe TLC548 and TLC549 are CMOS analog-to-digital converter (ADC) integrated circuits built around an 8-bit switched-capacitor successive-approximation ADC. These devices are designed for serial interface with a microprocessor or peripheral through a 3-state data output and an analog input. The TLC548 and TLC549 use only the input/output clock (I/O CLOCK) input along with the chip select (CS) input for data control. The maximum I/O CLOCK input frequency of the TLC548 is 2.048 MHz, and the I/O CLOCK input frequency of the TLC549 is specified up to 1.1 MHz.AVAILABLE OPTIONSPACKAGET A SMALL OUTLINE(D)PLASTIC DIP(P)0°C to 70°C TLC548CD TLC549CD TLC548CP TLC549CP –40°C to 85°CTLC548ID TLC549IDTLC548IP TLC549IPCopyright © 1996, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date.Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.12348765REF+ANALOG INREF–GNDV CCI/O CLOCK DATA OUT CSD OR P PACKAGE(TOP VIEW)TLC548C, TLC548I, TLC549C, TLC549I 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROLSLAS067C – NOVEMBER 1983 – REVISED SEPTEMBER 19962POST OFFICE BOX 655303 •DALLAS, TEXAS 75265description (continued)Operation of the TLC548 and the TLC549 is very similar to that of the more complex TLC540 and TLC541devices; however, the TLC548 and TLC549 provide an on-chip system clock that operates typically at 4 MHz and requires no external components. The on-chip system clock allows internal device operation to proceed independently of serial input/output data timing and permits manipulation of the TLC548 and TLC549 as desired for a wide range of software and hardware requirements. The I/O CLOCK together with the internal system clock allow high-speed data transfer and conversion rates of 45500 conversions per second for the TLC548, and 40000 conversions per second for the TLC549.Additional TLC548 and TLC549 features include versatile control logic, an on-chip sample-and-hold circuit that can operate automatically or under microprocessor control, and a high-speed converter with differential high-impedance reference voltage inputs that ease ratiometric conversion, scaling, and circuit isolation from logic and supply noises. Design of the totally switched-capacitor successive-approximation converter circuit allows conversion with a maximum total error of ±0.5 least significant bit (LSB) in less than 17 µs.The TLC548C and TLC549C are characterized for operation from 0°C to 70°C. The TLC548I and TLC549I are characterized for operation from –40°C to 85°C.functional block diagramREF –6488DATAOUT8-Bit Analog-to Digital Converter (Switched-Capacitors)8-to-1 Data Selector and DriverOutput Data RegiserInternal System ClockSample and Hold75231ANALOG INREF +CSI/O CLOCKControl Logic and Output Countertypical equivalent inputsINPUT CIRCUIT IMPEDANCE DURING SAMPLING MODEINPUT CIRCUIT IMPEDANCE DURING HOLD MODE1 k Ω TYPC i = 60 pF TYP (equivalent input capacitance)5 M Ω TYPANALOG INANALOG INTLC548C, TLC548I, TLC549C, TLC549I 8-BIT ANALOG-TO-DIGITAL CONVERTERSWITH SERIAL CONTROLSLAS067C – NOVEMBER 1983 – REVISED SEPTEMBER 19963POST OFFICE BOX 655303 •DALLAS, TEXAS 75265operating sequencet ent ent su(CS)B7B0B1B2B3B4B5B6B7Conversion Data BMSB MSB LSBHi-Z StateMSBLSB (see Note B)MSB Previous Conversion Data AA7A7A6A5A4A3A2A1A0Hi-Z StateDon’t11(see Note A)t conv t su(CS)Access Cycle B88765432765432CLOCK I/O CSOUTDATA CareSample Cycle BAccess Cycle CSample Cycle Ct wH(CS)NOTES: A.The conversion cycle, which requires 36 internal system clock periods (17 µs maximum), is initiated with the eighth I/O clock pulsetrailing edge after CS goes low for the channel whose address exists in memory at the time.B.The most significant bit (A7) is automatically placed on the DATA OUT bus after CS is brought low. The remaining seven bits (A6–A0)are clocked out on the first seven I/O clock falling edges. B7–B0 follows in the same manner.absolute maximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage, V CC (see Note 1) 6.5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input voltage range at any input –0.3 V to V CC + 0.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output voltage range –0.3 V to V CC + 0.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Peak input current range (any input) ±10 mA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Peak total input current range (all inputs) ±30 mA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating free-air temperature range, T A (see Note 2): TLC548C, TLC549C 0°C to 70°C. . . . . . . . . . . . . TLC548I, TLC549I –40°C to 85°C. . . . . . . . . . . . Storage temperature range, T stg –65°C to 150°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NOTES: 1.All voltage values are with respect to the network ground terminal with the REF– and GND terminals connected together, unlessotherwise noted.2.The D package is not recommended below –40°C.TLC548C, TLC548I, TLC549C, TLC549I 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROLSLAS067C – NOVEMBER 1983 – REVISED SEPTEMBER 19964POST OFFICE BOX 655303 •DALLAS, TEXAS 75265recommended operating conditionsTLC548TLC549MINNOMMAXMIN NOMMAXUNIT Supply voltage, V CC356356V Positive reference voltage, V ref+ (see Note 3) 2.5V CC V CC +0.12.5V CC V CC +0.1V Negative reference voltage, V ref – (see Note 3)–0.10 2.5–0.10 2.5V Differential reference voltage, V ref+, V ref – (see Note 3)1V CC V CC +0.21V CC V CC +0.2V Analog input voltage (see Note 3)0V CC0V CCV High-level control input voltage, V IH (for V CC = 4.75 V to 5.5 V)22V Low-level control input voltage, V IL (for V CC = 4.75 V to 5.5 V)0.80.8V Input/output clock frequency, f clock(I/O) (for V CC = 4.75 V to 5.5 V)0 2.0480 1.1MHz Input/output clock high, t wH(I/O) (for V CC = 4.75 V to 5.5 V)200404ns Input/output clock low, t wL(I/O) (for V CC = 4.75 V to 5.5 V)200404ns Input/output clock transition time, t t(I/O)(for V CC = 4.75 V to 5.5 V) (see Note 4 and Operating Sequence)100100ns Duration of CS input high state during conversion, t wH(CS)(for V CC = 4.75 V to 5.5 V) (see Operating Sequence)1717µs Setup time, CS low before first I/O CLOCK, t su(CS) (for V CC = 4.75 V to 5.5 V) (see Note 5) 1.4 1.4µs TLC548C, TLC549C 070070CTLC548I, TLC549I–4085–4085°NOTES: 3.Analog input voltages greater than that applied to REF+ convert to all ones (11111111), while input voltages less than that appliedto REF– convert to all zeros (00000000). For proper operation, the positive reference voltage V ref+, must be at least 1 V greater than the negative reference voltage, V ref–. In addition, unadjusted errors may increase as the differential reference voltage, V ref+ – V ref–,falls below 4.75 V.4.This is the time required for the I/O CLOCK input signal to fall from V IH min to V IL max or to rise from V IL max to V IH min. In the vicinityof normal room temperature, the devices function with input clock transition time as slow as 2 µs for remote data acquisition applications in which the sensor and the ADC are placed several feet away from the controlling microprocessor.5.To minimize errors caused by noise at the CS input, the internal circuitry waits for two rising edges and one falling edge of internalsystem clock after CS ↓ before responding to control input signals. This CS setup time is given by the t en and t su(CS) specifications.TLC548C, TLC548I, TLC549C, TLC549I 8-BIT ANALOG-TO-DIGITAL CONVERTERSWITH SERIAL CONTROLSLAS067C – NOVEMBER 1983 – REVISED SEPTEMBER 19965POST OFFICE BOX 655303 •DALLAS, TEXAS 75265electrical characteristics over recommended operating free-air temperature range,V CC = V ref+ = 4.75 V to 5.5 V, f clock(I/O) = 2.048 MHz for TLC548 or 1.1 MHz for TLC549 (unless otherwise noted)PARAMETERTEST CONDITIONS MIN TYP †MAXUNIT V OH High-level output voltage V CC = 4.75 V,I OH = –360 µA 2.4V V OL Low-level output voltageV CC = 4.75 V,I OL = 3.2 mA 0.4V I OZ High impedance off state output current V O = V CC ,CS at V CC 10High-impedance off-state output current V O = 0,CS at V CC–10µA I IH High-level input current, control inputs V I = V CC 0.005 2.5µA I IL Low-level input current, control inputsV I = 0–0.005–2.5µA I I()Analog channel on-state input current during sample Analog input at V CC 0.41I(on)g g cycleAnalog input at 0 V –0.4–1µA I CCOperating supply current CS at 0 V 1.8 2.5mA I CC + I ref Supply and reference current V ref+ = V CC1.93mA Input capacitance Analog inputs 755C iInput capacitanceControl inputs515pFoperating characteristics over recommended operating free-air temperature range, V CC = V ref+ = 4.75 V to 5.5 V, f clock(I/O) = 2.048 MHz for TLC548 or 1.1 MHz for TLC549 (unless otherwise noted)TEST CONDITIONS TLC548TLC549PARAMETERTEST CONDITIONS MINTYP †MAX MIN TYP †MAX UNIT E L Linearity error See Note 6±0.5±0.5LSB E ZS Zero-scale error See Note 7±0.5±0.5LSB E FS Full-scale error See Note 7±0.5±0.5LSB Total unadjusted error See Note 8±0.5±0.5LSB t convConversion timeSee Operating Sequence 8171217µs Total access and conversion timeSee Operating Sequence 12221925µs t a Channel acquisition time (sample cycle)See Operating Sequence44I/O clock cycles t v Time output data remains valid after I/O CLOCK ↓1010nst d Delay time to data output valid I/O CLOCK ↓200400ns t en Output enable time 1.4 1.4µs t dis Output disable time 150150ns t r(bus)Data bus rise timeSee Figure 1300300nst f(bus)Data bus fall time 300300ns †All typicals are at V CC = 5 V, T A = 25°C.NOTES: 6.Linearity error is the deviation from the best straight line through the A/D transfer characteristics.7.Zero-scale error is the difference between 00000000 and the converted output for zero input voltage; full-scale error is the differencebetween 11111111 and the converted output for full-scale input voltage.8.Total unadjusted error is the sum of linearity, zero-scale, and full-scale errors.TLC548C, TLC548I, TLC549C, TLC549I 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROLSLAS067C – NOVEMBER 1983 – REVISED SEPTEMBER 19966POST OFFICE BOX 655303 •DALLAS, TEXAS 75265PARAMETER MEASUREMENT INFORMATIONSee Note B0.4 V2.4 V t f(bus)Outputt r(bus)0.8 V2.4 V 0.8 Vt dDATA OUTVOLTAGE WAVEFORMS FOR RISE AND FALL TIMESVOLTAGE WAVEFORMS FOR DELAY TIMEV CC3 k Ω3 k ΩV CCSee Note B 50%50%0 V0 Vt PLZI/O CLOCKVOLTAGE WAVEFORMS FOR ENABLE AND DISABLE TIMESOutput Waveform 1(see Note C)t PHZV OH 90%10%t PZL0 VV CC 50%CSLOAD CIRCUIT FOR t PZL AND t PLZLOAD CIRCUIT FOR t PZH AND t PHZLOAD CIRCUIT FORt d , t r , AND t fSee Note BOutput Under Test Test Point3 k Ω1.4 VOutput Waveform 2(see Note C)C L(see Note A)Output Under Test Test Point C L(see Note A)Output Under Test Test PointC L(see Note A)t PZH50%NOTES: A.C L = 50 pF for TLC548 and 100 pF for TLC549; C L includes jig capacitance.B.t en = t PZH or t PZL , t dis = t PHZ or t PLZ .C.Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.Figure 1. Load Circuits and Voltage WaveformsTLC548C, TLC548I, TLC549C, TLC549I 8-BIT ANALOG-TO-DIGITAL CONVERTERSWITH SERIAL CONTROLSLAS067C – NOVEMBER 1983 – REVISED SEPTEMBER 19967POST OFFICE BOX 655303 •DALLAS, TEXAS 75265APPLICATIONS INFORMATIONsimplified analog input analysisUsing the equivalent circuit in Figure 2, the time required to charge the analog input capacitance from 0 to V S within 1/2 LSB can be derived as follows:The capacitance charging voltage is given byV C = V S 1–e–t c /R t C i ( )(1)whereR t = R s + r iThe final voltage to 1/2 LSB is given by(2)V C (1/2 LSB) = V S – (V S /512)Equating equation 1 to equation 2 and solving for time t c givesV S –(V S /512) = V S 1–e(3)–t c /R t C i( )andt c (1/2 LSB) = R t × C i × ln(512)(4)Therefore, with the values given the time for the analog input signal to settle ist c (1/2 LSB) = (R s + 1 k Ω) × 60 pF × ln(512)(5)This time must be less than the converter sample time shown in the timing diagrams.R sr i V SV C 1 k Ω MAXDriving Source †TLC548/9V IV I = Input Voltage at ANALOG IN V S = External Driving Source Voltage R s = Source Resistance r i = Input Resistance C i = Input Capacitance†Driving source requirements:•Noise and distortion for the source must be equivalent to the resolution of the converter.•R s must be real at the input frequency.C i55 pF MAX Figure 2. Equivalent Input Circuit Including the Driving SourceTLC548C, TLC548I, TLC549C, TLC549I 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROLSLAS067C – NOVEMBER 1983 – REVISED SEPTEMBER 19968POST OFFICE BOX 655303 •DALLAS, TEXAS 75265PRINCIPLES OF OPERATIONThe TLC548 and TLC549 are each complete data acquisition systems on a single chip. Each contains an internal system clock, sample-and-hold function, 8-bit A/D converter, data register, and control logic circuitry. For flexibility and access speed, there are two control inputs: I/O CLOCK and chip select (CS). These control inputs and a TTL-compatible 3-state output facilitate serial communications with a microprocessor or minicomputer. A conversion can be completed in 17 µs or less, while complete input-conversion-output cycles can be repeated in 22 µs for the TLC548 and in 25 µs for the TLC549.The internal system clock and I/O CLOCK are used independently and do not require any special speed or phase relationships between them. This independence simplifies the hardware and software control tasks for the device.Due to this independence and the internal generation of the system clock, the control hardware and software need only be concerned with reading the previous conversion result and starting the conversion by using the I/O clock. In this manner, the internal system clock drives the “conversion crunching” circuitry so that the control hardware and software need not be concerned with this task.When CS is high, DATA OUT is in a high-impedance condition and I/O CLOCK is disabled. This CS control function allows I/O CLOCK to share the same control logic point with its counterpart terminal when additional TLC548 and TLC549 devices are used. This also serves to minimize the required control logic terminals when using multiple TLC548 and TLC549 devices.The control sequence has been designed to minimize the time and effort required to initiate conversion and obtain the conversion result. A normal control sequence is:1.CS is brought low. To minimize errors caused by noise at CS, the internal circuitry waits for two rising edgesand then a falling edge of the internal system clock after a CS ↓ before the transition is recognized. However,upon a CS rising edge, DATA OUT goes to a high-impedance state within the specified t dis even though the rest of the integrated circuitry does not recognize the transition until the specified t su(CS) has elapsed. This technique protects the device against noise when used in a noisy environment. The most significant bit (MSB)of the previous conversion result initially appears on DATA OUT when CS goes low.2.The falling edges of the first four I/O CLOCK cycles shift out the second, third, fourth, and fifth most significantbits of the previous conversion result. The on-chip sample-and-hold function begins sampling the analog input after the fourth high-to-low transition of I/O CLOCK. The sampling operation basically involves the charging of internal capacitors to the level of the analog input voltage.3.Three more I/O CLOCK cycles are then applied to the I/O CLOCK terminal and the sixth, seventh, and eighthconversion bits are shifted out on the falling edges of these clock cycles.4.The final (the eighth) clock cycle is applied to I/O CLOCK. The on-chip sample-and-hold function begins thehold operation upon the high-to-low transition of this clock cycle. The hold function continues for the next four internal system clock cycles, after which the holding function terminates and the conversion is performed during the next 32 system clock cycles, giving a total of 36 cycles. After the eighth I/O CLOCK cycle, CS must go high or the I/O clock must remain low for at least 36 internal system clock cycles to allow for the completion of the hold and conversion functions. CS can be kept low during periods of multiple conversion. When keeping CS low during periods of multiple conversion, special care must be exercised to prevent noise glitches on the I/O CLOCK line. If glitches occur on I/O CLOCK, the I/O sequence between the microprocessor/controller and the device loses synchronization. When CS is taken high, it must remain high until the end of conversion. Otherwise, a valid high-to-low transition of CS causes a reset condition, which aborts the conversion in progress.A new conversion may be started and the ongoing conversion simultaneously aborted by performing steps 1 through 4 before the 36 internal system clock cycles occur. Such action yields the conversion result of the previous conversion and not the ongoing conversion.TLC548C, TLC548I, TLC549C, TLC549I 8-BIT ANALOG-TO-DIGITAL CONVERTERSWITH SERIAL CONTROLSLAS067C – NOVEMBER 1983 – REVISED SEPTEMBER 19969POST OFFICE BOX 655303 •DALLAS, TEXAS 75265PRINCIPLES OF OPERATIONFor certain applications, such as strobing applications, it is necessary to start conversion at a specific point in time.This device accommodates these applications. Although the on-chip sample-and-hold function begins sampling upon the high-to-low transition of the fourth I/O CLOCK cycle, the hold function does not begin until the high-to-low transition of the eighth I/O CLOCK cycle, which should occur at the moment when the analog signal must be converted. The TLC548 and TLC549 continue sampling the analog input until the high-to-low transition of the eighth I/O CLOCK pulse. The control circuitry or software then immediately lowers I/O CLOCK and starts the holding function to hold the analog signal at the desired point in time and starts the conversion.PACKAGING INFORMATIONOrderableDeviceStatus (1)Package Type Package DrawingPins Package Qty Eco Plan (2)Lead/Ball Finish MSL Peak Temp (3)TLC548CD ACTIVE SOIC D 875Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM TLC548CDG4ACTIVE SOIC D 875Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM TLC548CDR ACTIVE SOIC D 82500Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM TLC548CDRG4ACTIVE SOIC D 82500Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM TLC548CP ACTIVE PDIP P 850Pb-Free (RoHS)CU NIPDAU N /A for Pkg Type TLC548CPE4ACTIVE PDIP P 850Pb-Free (RoHS)CU NIPDAU N /A for Pkg Type TLC548ID ACTIVE SOIC D 875Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM TLC548IDG4ACTIVE SOIC D 875Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM TLC548IDR ACTIVE SOIC D 82500Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM TLC548IDRG4ACTIVE SOIC D 82500Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM TLC548IP ACTIVE PDIP P 850Pb-Free (RoHS)CU NIPDAU N /A for Pkg Type TLC548IPE4ACTIVE PDIP P 850Pb-Free (RoHS)CU NIPDAU N /A for Pkg Type TLC549CD ACTIVE SOIC D 875Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM TLC549CDG4ACTIVE SOIC D 875Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM TLC549CDR ACTIVE SOIC D 82500Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM TLC549CDRG4ACTIVE SOIC D 82500Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM TLC549CP ACTIVE PDIP P 850Pb-Free (RoHS)CU NIPDAU N /A for Pkg Type TLC549CPE4ACTIVE PDIP P 850Pb-Free (RoHS)CU NIPDAU N /A for Pkg Type TLC549ID ACTIVE SOIC D 875Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM TLC549IDG4ACTIVE SOIC D 875Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM TLC549IDR ACTIVE SOIC D 82500Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM TLC549IDRG4ACTIVE SOIC D 82500Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM TLC549IP ACTIVE PDIP P 850Pb-Free (RoHS)CU NIPDAU N /A for Pkg Type TLC549IPE4ACTIVE PDIP P 850Pb-Free (RoHS)CU NIPDAU N /A for Pkg Type TLC549IPSACTIVESOPS880Green (RoHS &no Sb/Br)CU NIPDAULevel-1-260C-UNLIMPACKAGE OPTION ADDENDUM6-Nov-2006Addendum-Page 1分销商库存信息:TITLC549IP TLC549CP TLC549CD TLC548CP TLC549ID TLC548IP TLC548ID TLC548CD TLC549CDR TLC549CDRG4TLC549IDR TLC549IDRG4 TLC548CDR TLC548CDRG4TLC549IPSR TLC549IPSRG4TLC548IDR TLC548IDRG4 TLC549CPE4TLC549IPE4TLC549CDG4 TLC548CPE4TLC549IDG4TLC548IPE4 TLC549IPS TLC549IPSG4TLC548CDG4 TLC548IDG4。

串行A_D转换器TLC548_549及其应用

收稿日期:2001-02作者简介:李国厚(1968-),男,讲师,主要从事工业自动控制的应用研究和教学工作。

串行A/D 转换器TLC548/549及其应用李国厚(河南职业技术师范学院机电系,河南新乡453003)摘要:介绍TI 公司的串行A/D 转换器TLC548/549的结构、特性和工作原理,讨论了芯片与MCU 连接的软件和硬件接口设计。

关键词:串行ADC;单片机;接口TLC 548/549Serial A/D Converter and Its ApplicationLI Guo-he(Henan Vocational-technical T eachers College,Xinxiang 453003,China)Abstract:The structure,features and principle of serial A/D converter TLC548/549are introduced in this paper,the software and hardware desi gns of its interface with MCU are also discussed in detail.Key words:serial ADC;monolithic microcomputer;interface1 TLC548/549的特点TLC548/549是以8位开关电容逐次逼近A/D 转换器为基础而构造的C MOS A/D 转换器,设计成能通过三态输出与微处理器或外围设备串行接口。

TLC548/549用输入/输出时钟(I/O CLOCK)和芯片选择(CS)输入作数据控制,其最高I/O CLOCK 频率分别为2 048MHz 和1 1MHz 。

TLC548/549片内系统时钟工作在4MHz(不需要外部时钟)。

片内系统时钟使内部器件的操作独立于串行输入/输出时序并允许TLC548/549像许多软件和硬件所要求的那样工作。

芯片TLC549介绍(中文的)

具有4MHz片内系统时钟和软、硬件控制电路，转换时间最长17μs，TLC548允许的最高转换速率为45 500次/s，TLC549为40 000次/s。

总失调误差最大为±0.5LSB，典型功耗值为6mW。

采用差分参考电压高阻输入，抗干扰，可按比例量程校准转换范围，V REF-接地，V REF+－V REF-≥1V，可用于较小信号的采样。

2. 芯片简介2.1 TLC548、TLC549的内部框图和管脚名称TLC548、TLC549的内部框图和引脚名称如图1所示。

其工作时序如图2所示。

当CS为高时，数据输出(DATA OUT)端处于高阻状态，此时I/O CLOCK 不起作用。

这种CS控制作用允许在同时使用多片TLC548、TLC549时，共用I/O CLOCK，以减少多路(片)A/D并用时的I/O控制端口。

一组通常的控制时序为：(1)将CS置低。

TLC549串行A

TLC549串行A/D 转换实验一、实验目的1、掌握单片机和TLC549硬件联接及软件编程二、实验说明TLC549是一种采用8位逐次逼近式工作的A/D 转换器。

内部包含系统时钟、采样和保持、8位A/D 转换器、数据寄存器以及控制逻辑电路。

TLC549每25uS 重复一次“输入—转换—输出”。

器件有两个控制输入：I/O CLOCK 和片选（CS ）。

内部系统时钟和I/O CLOCK 可独立使用。

应用电路的设计只需利用I/O 时钟启动转换或读出转换结果。

当CS 为高电平时，DATA OUT 处于高阻态且I/O 时钟被禁止。

当CS 变为低电平时，前次转换结果的最高有效位（MSB ）开始出现在DATA OUT 端。

在接下来的7个I/O CLOCK 周期的下降沿输出前次转换结果的后7位，至此8位数据已经输出。

然后再将第8个时钟周期加至I/O CLOCK ，此时钟周期的下跳沿变使芯片进行下一轮的AD 转换。

在第8个I/O CLOCK 周期之后，CS 必须变为高电平，并且保持高电平直至转换结束为止（>17uS ），否则CS 的有效高电平至低电平的转换将引起复位（其它详细资料看芯片说明）。

三、实验内容及步骤本实验用到单片机最小系统（F1区）、7279键盘（B3区）、八位动态数码显示（I2区）、电位器（A2区）和串行A/D 转换（H6区）。

1、7279阵列式键盘的CS 、CLK 、DATA 分别接单片机最小系统的P2.7、P1.6、P1.7口，用8P 排线将JD3B 和八位动态数码显示的JD1I 相连,7279键盘的JD4B 和八位动态数码显示的JD0I 相连。

单片机最小系统的P1.0、P1.1、P1.2接串行A/D 转换DATA 、CLK 、 CS-549，AIN 接电位器（A2区）0～5V 可调输出端。

打开单片机最小系统的电源开关，串行A/D 转换的JT1H 电源短路帽打在VCC 处。

2、用串行数据通信线连接计算机与仿真器，把仿真器插到模块的锁紧插座中，请注意仿真器的方向：缺口朝上。

tlc549与单片机连接图

tlc549与单片机连接图
TLC549 是采用IinCMOSTM 技术并以开关电容逐次逼近原理工作的8 位串行A / D7 芯片，可与通用微处理器、控制器通过I/0 CLOCK、CS、DATA OUT.三条口线进行串行接口。

TLC549 具有4MHZ 的片内系统时钟和软、硬件控制电路，转换时间最长为17u s，允许的最高转换速率为40000次/S.总失调误差最大为土0.5LSB，典型功耗值为6 mW。

TLC549 采用差分参考电压高阻输入，抗千扰，可按比例量程校准转换范围，由于其VREF-接地时，（VREF+）-（VREF-）21V，故可用于较小信号的采样，此外，该芯片还单电源3~6v 的供电范围。

总之，TLC549 具有控制口线少，时序简单，转换速度快，功耗低，价格便宜等特
TLC549的极限参数如下：
电源电压：6.5 V；
输入电压范围：0.3V~VCC：+o.3V；。

TLC549中文介绍

TLC549中文介绍
TLC549是一款模拟到数字转换器(ADC)，由德州仪器公司(Texas Instruments)开发和生产。

这款芯片是一种单通道、低功耗、高精度的
12位ADC。

它被广泛应用于工业自动化、仪器仪表、通信设备和消费类电
子产品等领域。

TLC549还具有自动电源关闭(PS)功能，其中在转换完成后，芯片会
自动从待机模式切换到关闭模式，从而降低功耗并延长电池寿命。

此外，
它还具有多通道选择功能，使用户能够选择要转换的输入通道。

这些功能
可通过串行外设控制简化系统设计，降低成本和复杂度。

在实际应用中，TLC549可以用于测量和监测温度、压力、湿度、流
量等环境参数。

它还可以用于采集音频和视频信号，用于语音和图像处理。

由于其高精度和低功耗特性，TLC549也可以用于精密仪器和仪表，如电
压表和多用途测试仪。

总的来说，TLC549是一款功能强大的模拟到数字转换器，适用于多
种应用场景。

它具有高精度、低功耗、可编程的参考电压和内部时钟发生
器等特点，使其成为众多电子产品中不可或缺的一部分。

串行AD转换器TLC549的应用设计

课程设计任务书题目串行AD转换器TLC549的应用设计系(部) 信息科学与电气工程学院专业电子信息工程班级电信091班学生姓名王凤娟学号09081924512 月26 日至12 月30 日共 1 周指导教师(签字)系主任(签字)2011年12 月30 日摘要本次课程设计的主要目的，就是通过应用8位串行模数转换器TLC549采集电压信号，并进行AD转换，转换成数字信号传送给51单片机，在单片机内部通过编写程序进行数据处理，最后通过单片机的I/O口控制芯片74LS164显示出所采集的电压大小，另外利用键盘控制电压大小的上下限，也即量程，如果超出上下限，则指示灯发光。

关键字：TLC549 AD转换74LS164 量程AbstractIn this class, the design of the main purpose, is through the application of eight serial adc voltage signal collection of eight bits, and AD transform, converted into digital signals to 51 single-chip microcomputer, the microcontroller internal by writing program data processing, the last through the single-chip microcomputer of I/O mouth control chip 74 LS164 shows which collection of voltage size, in addition to use the keyboard control voltage size the upper and lower limits that range, if exceeded the upper and lower limits of the indicator light to shine.Key words：TLC549eight bits AD transform 74 LS164 range目录摘要............................................................................................................... 错误！未定义书签。

基于TLC549的串行AD转换实例

基于TLC549的串行A/D转换实例本文为《51基础与应用实例》的部分内容，浅显易懂，《51基础与应用实例》为三恒星科技公司公司编写，新华书店公开发行，未经许可不得转载实例说明单片机已经广泛应用于智能仪表和数据采集领域，促进了测量仪表和测量系统的自动化、智能化。

在A/D转换系统设计中，实现了将模拟量转换为单片机能识别的数字量的过程。

设计者的主要任务是根据用户对A/D转换通道的技术要求，合理地选择通道的结构并按一定的技术准则等因素恰当地选择所需的各种集成电路。

本例主要介绍8位A/D转换芯片TLC549在51单片机系统中的应用，在分析TLC549的结构、特点和工作原理的基础上，提供一个硬件连接和软件编程。

硬件电路设计单片机和A/D转换器之间的接口设计是硬件电路设计的关键。

TLC549芯片可方便地与具有串行外围接口(SPI)的单片机或微处理器配合使用，也可与51系列通用单片机连接使用。

串行A/D转换电路单片机部分原理图如图7-9所示。

图7-9 串行A/D转换原理图由硬件电路设计可以看出在本例中驱动TLC549芯片实现A/D 转换时，单片机AT89C52采用异步串行接口。

单片机AT89C52采用的时钟晶振大小为12MHz，其引脚P1.0与TLC549芯片的输入/输出时钟I/O CLOCK 相连，引脚P1.1与TLC549芯片的数据输出脚DATA OUT相连，P1.2与TLC549芯片的片选脚/CS相连，从TLC549芯片转换的数据经数据输出脚DATA OUT 送入单片机AT89C52中。

单片机AT89C52的P1.0、P1.1具有双重功能：标准I/O口或模拟比较器。

在用作模拟比较器时，它们作为内部模拟比较器的输入端AIN1和AIN2，是集电极开路电路，因此在用作标准I/O使用时，应外接上拉电阻。

电路中正基准电压REF+接+5V，负基准电压REF-接地，因此测量范围是0V~5V，对应输出数字量是0~255。

微机原理与接口实验—TLC549 8位串行AD

数字地与模拟地
正确的接地 AGND DGND
小电流 Z
大电流 Z
数字地对模拟地产生干扰
AGND DGND
小电流
大电流
Z
Z
工作时序
先读出前一次转换结果后，再进行本次转换
控制时序
1动. 将将本C次S置转低换。结内果部的电最路高在位测(D得7)C位S输下出降到沿D后A，TA等O待UteTn端后上自。 2. 前四个IO_CLOCK 周期的下降沿依次移出第2、3、4 和第5 个位(D6、D5、D4、D3)，片上采样保持电路在第4 个IO_CLOCK 下降沿开始采样模拟输入。 3. 接下来的3个IO_CLOCK 周期的下降沿移出第6、7、 8(D2、D1、D0)个转换位。 4. 最后，片上采样保持电路在第8个I/O CLOCK 周期的下降沿后，开始A/D转换。第8个IO_CLOCK后，CS 必须为高等待，保或持IO和_C转LO换C工K作保的持完低成电。平，这种状态需要维持tconv以
实验箱原理图
PAD_AD_CLK1 PAD_AD_REF 3 2
I/O CLK REF+ REFANLG IN
VCC DO
8 6
4 GND
CS 5
TLC549CP
VCC
J16 C17 104
GND R49 1K
PAD_AD_DO1 PAD_AD_~CS1
实验目的
学习使用串行模数转换芯片TLC549进行电压采集和数据处理。
实验内容
1. REF+连基准源的+5V（通过可调电阻调整），CLK、 DAT和-CS分别连P10、P11和P12。D2区电位器的输出连ANIN。通过单片机P1口控制串行AD转换芯片TLC549 实现模拟电压信号的采集，并存入内部数据存储器。记录 10组不同的电压转换值，并分析误差。

TLC549中文介绍与参考程序

TLC549中文介绍与参考程序TLC549使用单电源供电，工作电压范围为2.7V至5.5V。

它采用内部运算放大器和参考电压，具有高共模抑制比和低失调电压，提供准确的测量结果。

通过SPI接口，可以轻松地将数据传输到微控制器或其他数字设备。

以下是TLC549的主要特性：1.高精度：TLC549是一款12位的ADC，可以实现精确的模拟信号转换。

2.内部参考电压：TLC549已集成内部参考电压和运算放大器，可消除外部参考电压的需求，并提供更好的测量精度。

3.低功耗：TLC549在工作模式下的功耗非常低，适合各种低功率应用。

4.SPI接口：TLC549采用串行外围接口（SPI）进行数据传输，与微控制器和其他数字设备兼容。

5.可编程的采样率：TLC549的采样率可以通过控制输入引脚进行编程，以满足不同应用的要求。

下面是一个使用TLC549的参考程序，该程序可以读取模拟信号并将其转换为数字值：```#include <SPI.h>const int chipSelectPin = 10; // SPI芯片选择引脚int val = 0; // 储存读取到的模拟值void setuSerial.begin(9600);SPI.begin(;pinMode(chipSelectPin, OUTPUT);digitalWrite(chipSelectPin, HIGH); // 初始化SPI芯片选择引脚void loodigitalWrite(chipSelectPin, LOW); // 选中TLC549芯片delayMicroseconds(10);SPI.transfer(0x00); // 发送开始转换命令delayMicroseconds(10);val = SPI.transfer(0x00); // 读取转换结果的高8位val = (val << 8) + SPI.transfer(0x00); // 读取转换结果的低4位digitalWrite(chipSelectPin, HIGH); // 取消选中TLC549芯片Serial.println(val); // 打印转换结果delay(1000);```上述程序使用了SPI库，首先在`setup(`函数中初始化SPI通信，并设置芯片选择引脚为输出模式。

8位串行模数转换器TLC548、TLC549的应用

© 1995-2005 Tsinghua Tongfang Optical Disc Co., Ltd. All rights reserved.
2. 芯片简介
2. 1 TL C548 、TL C549 的内部框图和管脚名称 TL C548 、TL C549 的内部框图和引脚名称如图
1 所示。 2. 2 极限参数
图 1 TL C548 、TL C549 内部框图
TL C548/ 549 的极限参数如下 : ●电源电压 :6. 5V ; ●输入电压范围 :0. 3V～VCC + 0. 3V ; ●输出电压范围 :0. 3V～VCC + 0. 3V ; ●峰值输入电流 (任一输入端) : ±10mA ; ●总峰值输入电流 (所有输入端) : ±30mA ; ●工作温度 : TL C548C 、TL C549C :0 ℃～70 ℃
换结果。
若要
在特定的
图 4 程序流程图
时刻采样模拟信号 ,
应使第 8 个 I/ O CL OC K 时钟的下降沿与该时刻对应 , 因为芯片虽在第 4 个 I/ O CL OC K 时钟下降沿开始采样 ,却在第 8 个 I/ O CL OC K 的下降沿开始保存。
4. 应用接口及采样程序
围接
TL C548 I 、TL C549 I : - 40 ℃～85 ℃ TL C548M 、TL C549M : - 55 ℃～125 ℃
3. 工作原理
TL C548 、TL C549 均有片内系统时钟 , 该时钟与 I/ O CL OC K 是独立工作的 , 无须特殊的速度或相位匹配。其工作时序如图 2 所示。
MOV R0 , # 00H ;移位计数为零。

TLC549实验报告

六
本实验流程图
MCU
液晶 TLC549 模拟量
七
本实验程序代码
/************************************ *文件名：tlc549驱动程序 *功能：tlc549采集模拟电压并于液晶上显示大小 *作者：刘烈报 *单位：湖南理工物电系创新基地 * All rights reseverd *开始时间：2009.08.6 *结束时间：2009.08.6 *版本信息： * *注备： **************************************/ #include <intrins.h> #include <reg52.h> #define uchar unsigned char #define uint unsigned int #define ulong unsigned long uchar getdata,PSB; uchar code table0[]="TLC549"; uchar code table[]="输入电压:"; /************************* TLC549配制 **************************/ sbit tlc_clk = P3^6; sbit tlc_data = P3^5; sbit tlc_cs = P3^4; /*********************************************** 液晶的配置 ************************************************/ #define DATABUS P0 sbit RS_LCD = P2^0; sbit RW_LCD = P2^1; sbit E_LCD = P2^2; /***********************************************

tlc549操作时序图电路图

实验电路图如下图 TLC549 操作时序图及工作原理：实验电路图如下图。P1.0 接 TLC549 的时钟引脚 CLK ，作为单片机的时钟输出；P1.1 接 TLC549 的数据引脚 DAT ，读取数据；P1.2 接 TLC549 的片选引脚，低电平有效。实验电路图实验时，P1.2 联接 CS ，输出低电平，使片选使能。P1.0 联接 CLK
引脚，输出时钟。时钟为高电平时读取 ANIN 电压，由 DAT 输出给单片机 P1.1。每个高电平时钟读取 1 个 bit ，8 个时钟可以读取 1 个 byte 的转换结果，数据高位先读取。程序中用八次循环，可以读出一个字节的转换结果。时序图如下图。 TLC549 操作时序图
实验结果用 P0 口接 8 位发光二极管表示电压变化。从 00000000 到 11111111 为电压从最小到最大的变化显示。
tlc549 操作时序图电路图
TLC549 是 TI 公司生产的一种低价位、高性能的 8 位 A/D 转换器。采用了 CMOS 工艺，它以 8 位开关电容逐次逼近的方法实现转换速度小于 17us，最大转换速率为 A/D 转换。其
40000HZ，4MHZ 典型方便地采用三线串行接口方式与各种微处理器连接，构成各种廉价的测控应用系统。 tlc549 波形图 tlc549 电路图 tlc549 实验案例