PCI内核源代码说明

PCI从设备代码说明：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity pcislave is port( //PCI接口说明//CLK：33M PCI 时钟；//RST ： PCI 复位，低有效；// IDSEL ： PCI 配置空间选择，高有效；// FRAME ：PCI 祯周期开始，低有效；// IRDY ： PCI主设备准备好，低有效；clk,rst,idsel,frame,irdy : in std_logic;// TRDY ： PCI目标设备准备好，低有效；// DEVSEL ：PCI目标设备选择，低有效；// STOP ： PCI目标设备停止，低有效；trdy,devsel,stop : inout std_logic;// PCI 效验输出使能，高有效；paren1 : out std_logic;// DATA RD OUT ：局部总线读输出信号，高有效；// DATA WR ：局部总线写输出信号，高有效；// DMASEL ：DMA允许，高有效；data_rd_out,data_wr,dmasel : out std_logic;// IOSEL : IO空间选择输出，高有效；// MEMSEL ：内存空间选择输出，高有效；iosel,memsel : buffer std_logic;// EXT ADD ：局部总线地址译码输出，IO空间只用（7 到0）ext_add : out std_logic_vector(21 downto 0);// CBE ：PCI命令及字节输入cbe : in std_logic_vector(3 downto 0);// AD ： PCI地址及数据复用信号ad : inout std_logic_vector(31 downto 0));end pcislave;architecture beha of pcislave is// 目标读状态机type slaverdst is (idle1,dev_st1,rdst1,rdst2,rdst3,rdst4,rdstopst,ctst1);//目标写状态机type slavewrst is (idle2,dev_st2,wrst1,wrst2,wrst3,wrst4,wrstopst,ctst2);signal pre_state1,nxt_state1 : slaverdst;signal pre_state2,nxt_state2 : slavewrst;// PCI配置空间定义：// PCI ID号定义constant id : std_logic_vector(31 downto 0) :="01000010010110000001000100000000"; // PCI 设备类型定义constant clss : std_logic_vector(31 downto 0) :="00000100000000000000000000000000";//PCI 编程接口类型定义：constant ht : std_logic_vector(31 downto 0) :="00000000000000000010000000000000";//PCI 保留空间定义，全‘0’constant res : std_logic_vector(31 downto 0) :="00000000000000000000000000000000";//PCI 保留地址译码，全‘0’constant base : std_logic_vector(31 downto 0) :="00000000000000000000000000000000"; signal add,basereg1,basereg0,wrreg,intreg,stc,dqreg : std_logic_vector(31 downto 0);signal cmd : std_logic_vector(3 downto 0);signal st_clr,st_clr1,io_sel,iordsel,iowrsel,memrdsel,memwrsel,membase0_sel : std_logic; signal iobase0_sel,ioen,memen,io_rd_sel,io_wr_sel,mem_rd_sel,mem_wr_sel,cfg_sel : std_logic; signal rdsel,wrsel,dev_sel,cfg_rd_sel,cfg_wr_sel,devid,statecmd,classcd,hdtp : std_logic;signal base0,base1,base2,base3,base4,base5,res1,res2,res3,res4,res5,int_sel : std_logic;signal cfgwr,cfgwr1,data_out,data_out1,spar_en : std_logic;begincon_st : process(clk,rst)begin //PCI目标命令及地址锁存if rst='0' then add<=(others=>'0');cmd<=(others=>'0');elsif rising_edge(clk) thenif (frame='0' and irdy='1' and trdy='1' and devsel='1' and stop='1')then cmd<=cbe;add<=ad;end if;end if;// PCI IO及内存空间访问锁存if (rst='0' or st_clr='1') then io_sel<='0';elsif rising_edge(clk) thenif (frame='0' and irdy='1' and trdy='1' and devsel='1' and stop='1')then io_sel<='1';else io_sel<='0';end if;end if;// PCI IO命令译码if cmd="0010" then iordsel<='1';else iordsel<='0';end if;if cmd="0011" then iowrsel<='1';else iowrsel<='0';end if;//PCI内存命令译码if cmd="0110" then memrdsel<='1';else memrdsel<='0';end if;if cmd="0111" then memwrsel<='1';else memwrsel<='0';end if;//PCI内存空间访问地址选中if (add(31 downto 22)=basereg1(31 downto 22)) then membase0_sel<='1';else membase0_sel<='0';end if;//PCI IO空间访问地址选中if add(15 downto 8)=basereg0(15 downto 8) then iobase0_sel<='1';else iobase0_sel<='0';end if;// PCI IO访问及内存访问地址选中if io_sel='1' and iordsel='1' and iobase0_sel='1' and ioen='1' then io_rd_sel<='1';else io_rd_sel<='0';end if;if io_sel='1' and iowrsel='1' and iobase0_sel='1' and ioen='1' then io_wr_sel<='1';else io_wr_sel<='0';end if;if io_sel='1' and memrdsel='1' and membase0_sel='1' and memen='1' then mem_rd_sel<='1';else mem_rd_sel<='0';end if;if io_sel='1' and memwrsel='1' and membase0_sel='1' and memen='1' then mem_wr_sel<='1';else mem_wr_sel<='0';end if;//PCI配置空间访问选中if (rst='0' or st_clr='1') then cfg_sel<='0';elsif rising_edge(clk) thenif (idsel='1' and frame='0' and irdy='1' and trdy='1' and devsel='1' and stop='1') then cfg_sel<='1';else cfg_sel<='0';end if;end if;//PCI配置访问译码输出if cmd="1010" then rdsel<='1';else rdsel<='0';end if;if cmd="1011" then wrsel<='1';else wrsel<='0';end if;//PCI配置空间访问译码if (add(10 downto 6)="00000" and add(1 downto 0)="00") then dev_sel<='1';else dev_sel<='0';end if;if cfg_sel='1' and dev_sel='1' and rdsel='1' then cfg_rd_sel<='1';else cfg_rd_sel<='0';end if;if cfg_sel='1' and dev_sel='1' and wrsel='1' then cfg_wr_sel<='1';else cfg_wr_sel<='0';end if;//PCI空间访问地址译码if rising_edge(clk) thenif add(5 downto 2)="0000" then devid<='1';else devid<='0';end if;if add(5 downto 2)="0001" then statecmd<='1';else statecmd<='0';end if; if add(5 downto 2)="0010" then classcd<='1';else classcd<='0';end if;if add(5 downto 2)="0011" then hdtp<='1';else hdtp<='0';end if;if add(5 downto 2)="0100" then base0<='1';else base0<='0';end if;if add(5 downto 2)="010 1" then base1<='1';else base1<='0';end if;if add(5 downto 2)="0110" then base2<='1';else base2<='0';end if;if add(5 downto 2)="0111" then base3<='1';else base3<='0';end if;if add(5 downto 2)="1000" then base4<='1';else base4<='0';end if;if add(5 downto 2)="1001" then base5<='1';else base5<='0';end if;if add(5 downto 2)="1010" then res1<='1';else res1<='0';end if;if add(5 downto 2)="1011" then res2<='1';else res2<='0';end if;if add(5 downto 2)="1100" then res3<='1';else res3<='0';end if;if add(5 downto 2)="1101" then res4<='1';else res4<='0';end if;if add(5 downto 2)="1110" then res5<='1';else res5<='0';end if;if add(5 downto 2)="1111" then int_sel<='1';else int_sel<='0';end if;end if;//PCI从读状态机case pre_state1 iswhen idle1 => if (cfg_rd_sel='1' or io_rd_sel='1' or mem_rd_sel='1')then nxt_state1<=dev_st1;else nxt_state1<=idle1;end if;when dev_st1 => if irdy='0' then nxt_state1<=rdst1;else nxt_state1<=dev_st1;end if;when rdst1 => if irdy='0' then nxt_state1<=rdst2;else nxt_state1<=rdst1;end if;when rdst2 => if irdy='0' then nxt_state1<=rdst3;else nxt_state1<=rdst2;end if;when rdst3 => if irdy='0' then nxt_state1<=rdst4;else nxt_state1<=rdst3;end if;when rdst4 => if frame='0' then nxt_state1<=rdstopst;else nxt_state1<=ctst1;end if;when rdstopst => if frame='0' or irdy='0' then nxt_state1<=rdstopst;else nxt_state1<=ctst1;end if;when ctst1 => nxt_state1<=idle1;when others=> nxt_state1<=idle1;end case;//PCI从写状态机case pre_state2 iswhen idle2=> if (cfg_wr_sel='1' or io_wr_sel='1' or mem_wr_sel='1')then nxt_state2<=dev_st2;else nxt_state2<=idle2;end if;when dev_st2=> if irdy='0' then nxt_state2<=wrst1;else nxt_state2<=dev_st2;end if;when wrst1=> if irdy='0' then nxt_state2<=wrst2;else nxt_state2<=wrst1;end if;when wrst2=> if irdy='0' then nxt_state2<=wrst3;else nxt_state2<=wrst2;end if;when wrst3=> if irdy='0' then nxt_state2<=wrst4;else nxt_state2<=wrst3;end if;when wrst4=> if frame='0' then nxt_state2<=wrstopst;else nxt_state2<=ctst2;end if;when wrstopst => if frame='0' or irdy='0' then nxt_state2<=wrstopst;else nxt_state2<=ctst2;end if;when ctst2 => nxt_state2<=idle2;when others=> nxt_state2<=idle2;end case;if rst='0' then wrreg<=(others=>'0');elsif rising_edge(clk) then wrreg<=ad;end if;//配置空间0地址寄存器if rst='0' then basereg0<="11111111111111111111111100000001";elsif rising_edge(clk) thenif (cfgwr='1' and base0='1' and wrsel='1') thenbasereg0(31 downto 8)<=wrreg(31 downto 8);basereg0(7 downto 0)<="00000001";end if;end if;//配置空间1地址寄存器if rst='0' then basereg1<="11111111110000000000000000000000";elsif rising_edge(clk) thenif (cfgwr='1' and base1='1' and wrsel='1') thenbasereg1(31 downto 22)<=wrreg(31 downto 22);basereg1(21 downto 0)<="0000000000000000000000";end if;end if;//配置空间中断寄存器if rst='0' then intreg<="00000000000000000000000111111111";elsif rising_edge(clk) thenif (cfgwr='1' and int_sel='1' and wrsel='1') thenintreg(31 downto 8)<="000000000000000000000001";intreg(7 downto 0)<=wrreg(7 downto 0);end if;end if;//配置空间状态及命令寄存器if rst='0' then stc<="00000100000000000000000000000000";elsif rising_edge(clk) thenif (cfgwr='1' and statecmd='1' and wrsel='1') thenstc(31 downto 3)<="00000100000000000000000000000";stc(2 downto 0)<=wrreg(2 downto 0);end if;end if;ioen<=stc(0);memen<=stc(1);dmasel<=stc(2);PCI读效验产生if rst='0' then paren1<='0';cfgwr<='0';st_clr<='0';data_out<='0';elsif rising_edge(clk) thenparen1<=spar_en;cfgwr<=cfgwr1;st_clr<=st_clr1;data_out<=data_out1;end if;if rising_edge(clk) thenif devid='1' then dqreg<=id;elsif statecmd='1' then dqreg<=stc;elsif classcd='1' then dqreg<=clss;elsif hdtp='1' then dqreg<=ht;elsif res1='1' or res2='1' or res3='1' or res4='1' or res5='1'or base2='1' or base3='1' or base4='1' or base5='1' then dqreg<=base; elsif base0='1' then dqreg<=basereg0;elsif base1='1' then dqreg<=basereg1;elsif int_sel='1' then dqreg<=intreg;else dqreg<=(others=>'0');end if;end if;end process;//PCI数据输出ad<=dqreg when data_out='1' and rdsel='1'else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";state1_pro : process(clk,rst)begin if rst='0' then pre_state1<=idle1;elsif rising_edge(clk) then pre_state1<=nxt_state1;end if;end process;state2_pro : process(clk,rst)begin if rst='0' then pre_state2<=idle2;elsif rising_edge(clk) then pre_state2<=nxt_state2;end if;end process;//PCI效验信号产生spar_en<='1' when pre_state1=rdst4else '0';//局部总线写信号产生cfgwr1<='1' when pre_state2=wrst2 or pre_state2=wrst3 else '0';st_clr1<='1' when pre_state1=dev_st1 or pre_state2=dev_st2 else '0';//局部总线读信号产生data_out1<='1' when pre_state1=rdst1 or pre_state1=rdst2or pre_state1=rdst3 or pre_state1=rdst4else '0';//PCI目标选择信号输出devsel<='0' when pre_state1=dev_st1 or pre_state1=rdst1 or pre_state1=rdst2or pre_state1=rdst3 or pre_state1=rdst4 or pre_state1=rdstopstor pre_state2=dev_st2 or pre_state2=wrst1 or pre_state2=wrst2or pre_state2=wrst3 or pre_state2=wrst4 or pre_state2=wrstopst else '1' when pre_state1=ctst1 or pre_state2=ctst2else 'Z';//PCI目标准备好信号输出trdy<='0' when pre_state1=rdst4 or pre_state2=wrst4else '1' when pre_state1=dev_st1 or pre_state1=rdst1 or pre_state1=rdst2or pre_state1=rdst3 or pre_state1=rdstopstor pre_state2=dev_st2 or pre_state2=wrst1 or pre_state2=wrst2or pre_state2=wrst3 or pre_state2=wrstopstor pre_state1=ctst1 or pre_state2=ctst2else 'Z';//PCI目标停止信号输出stop<='0' when pre_state1=rdstopst or pre_state2=wrstopstelse '1' when pre_state1=dev_st1 or pre_state1=rdst1 or pre_state1=rdst2or pre_state1=rdst3 or pre_state1=rdst4or pre_state2=dev_st2 or pre_state2=wrst1 or pre_state2=wrst2or pre_state2=wrst3 or pre_state2=wrst4or pre_state1=ctst1 or pre_state2=ctst2else 'Z';// 局部总线读信号输出data_rd_out<=data_out and ((iordsel and iobase0_sel)or (memrdsel and membase0_sel));//局部总线io译码输出iosel<=(iordsel or iowrsel) and iobase0_sel;//局部总线内存译码输出memsel<=(memrdsel or memwrsel) and membase0_sel;//局部总线写信号输出data_wr<=cfgwr and ((iowrsel and iobase0_sel) or(memwrsel and membase0_sel));//局部总线地址输出ext_add<=add(21 downto 0);end beha;。