IC datasheet pdf-CD74AC540,pdf(Octal Buffer_Line Drivers, 3-State)

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IC datasheet pdf-OPA604,pdf(FET-Input, Low Distortion Operational Amplifier)

µVPP
fA/√Hz
V dB
Ω || pF Ω || pF
dB
MHz V/µs µs µs
%
V mA mA Ω
V V mA
°C °C °C/W
OPA604
3
SBOS019A

THD + N (%)
Current Noise (fA/ Hz)
TYPICAL CHARACTERISTICS

Copyright © 1992-2003, Texas Instruments Incorporated
ABSOLUTE MAXIMUM RATINGS
Power Supply Voltage ....................................................................... ±25V Input Voltage ............................................................... (V–)–1V to (V+)+1V Output Short Circuit to Ground ................................................ Continuous Operating Temperature .................................................. –40°C to +100°C Storage Temperature ...................................................... –40°C to +125°C Junction Temperature .................................................................... +150°C Lead Temperature (soldering, 10s) AP .......................................... +300°C Lead Temperature (soldering, 3s) AU ............................................ +260°C

IC datasheet pdf-REF1004,pdf(Micropower Voltage Reference)

REF1004 is a drop-in replacement for the LT1004 as well as an upgraded replacement of the LM185/385 series references. The REF1004C is characterized for operation from 0°C to 70°C and the REF1004I is characterized for operation from –40°C to +85°C.
The REF1004 is offered in an 8-lead Plastic SOIC package and shipped in anti-static rails or tape and reel.
Typical Operating Circuit
NC 1 NC 2 NC 3 Anode 4
IR = 100µA
10Hz ≤ IR ≤ 10kHz
60
120
µV
LONG TERM STABILITY
IR = 100µA
TA = 25°C ± 0.1°C
20
2 (1) This specification applies over the full operating temperature range of 0°C ≤ TA ≤ 70°C. (2) This specification applies over the full operating temperature range of 40°C ≤ TA ≤ +85°C. (3) Denotes the specifications which apply over the full operating temperature range.

IC datasheet pdf-CD74ACT10,pdf(QUADRUPLE 2-INPUT POSITIVE-NAND GATES)

TRIPLE 3-INPUT POSITIVE-NAND GATESTRIPLE 3-INPUT POSITIVE-NAND GATESIMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries(TI)reserve the right to make corrections,modifications,enhancements, improvements,and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty.Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty.Except where mandated by government requirements,testing of all parameters of each product is not necessarily performed.TI assumes no liability for applications assistance or customer product design.Customers are responsible for their products and applications using TI components.To minimize the risks associated with customer products and applications,customers should provide adequate design and operating safeguards.TI does not warrant or represent that any license,either express or implied,is granted under any TI patent right,copyright,mask work right,or other TI intellectual property right relating to any combination,machine,or process in which TI products or services are rmation published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement e of such information may require a license from a third party under the patents or other intellectual property of the third party,or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties,conditions,limitations,and notices.Reproduction of this information with alteration is an unfair and deceptive business practice.TI is not responsible or liable for such altered documentation.Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice.TI is not responsible or liable for any such statements.TI products are not authorized for use in safety-critical applications(such as life support)where a failure of the TI product would reasonably be expected to cause severe personal injury or death,unless officers of the parties have executed an agreement specifically governing such use.Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications,and acknowledge and agree that they are solely responsible for all legal,regulatory and safety-related requirements concerning their products and any use of TI products in such safety-critical applications,notwithstanding any applications-related information or support that may be provided by TI.Further,Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in such safety-critical applications.TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are specifically designated by TI as military-grade or"enhanced plastic."Only products designated by TI as military-grade meet military specifications.Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at the Buyer's risk,and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are designated by TI as compliant with ISO/TS16949requirements.Buyers acknowledge and agree that,if they use anynon-designated products in automotive applications,TI will not be responsible for any failure to meet such requirements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions:Products ApplicationsAmplifiers AudioData Converters AutomotiveDSP BroadbandInterface Digital ControlLogic MilitaryPower Mgmt Optical NetworkingMicrocontrollers SecurityLow Power TelephonyWirelessVideo&ImagingWirelessMailing Address:Texas Instruments,Post Office Box655303,Dallas,Texas75265Copyright©2007,Texas Instruments IncorporatedPACKAGING INFORMATION Orderable DeviceStatus (1)Package Type Package Drawing Pins Package Qty Eco Plan (2)Lead/Ball Finish MSL Peak Temp (3)CD74ACT10EACTIVE PDIP N 1425Pb-Free (RoHS)CU NIPDAU N /A for Pkg Type CD74ACT10EE4ACTIVE PDIP N 1425Pb-Free (RoHS)CU NIPDAU N /A for Pkg Type CD74ACT10MACTIVE SOIC D 1450Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM CD74ACT10M96ACTIVE SOIC D 142500Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM CD74ACT10M96E4ACTIVE SOIC D 142500Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM CD74ACT10M96G4ACTIVE SOIC D 142500Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM CD74ACT10ME4ACTIVE SOIC D 1450Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM CD74ACT10MG4ACTIVE SOIC D 1450Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM (1)The marketing status values are defined as follows:ACTIVE:Product device recommended for new designs.LIFEBUY:TI has announced that the device will be discontinued,and a lifetime-buy period is in effect.NRND:Not recommended for new designs.Device is in production to support existing customers,but TI does not recommend using this part in a new design.PREVIEW:Device has been announced but is not in production.Samples may or may not be available.OBSOLETE:TI has discontinued the production of the device.(2)Eco Plan -The planned eco-friendly classification:Pb-Free (RoHS),Pb-Free (RoHS Exempt),or Green (RoHS &no Sb/Br)-please check /productcontent for the latest availability information and additional product content details.TBD:The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS):TI's terms "Lead-Free"or "Pb-Free"mean semiconductor products that are compatible with the current RoHS requirements for all 6substances,including the requirement that lead not exceed 0.1%by weight in homogeneous materials.Where designed to be soldered at high temperatures,TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1)lead-based flip-chip solder bumps used between the die and package,or 2)lead-based die adhesive used between the die andleadframe.The component is otherwise considered Pb-Free (RoHS compatible)as defined above.Green (RoHS &no Sb/Br):TI defines "Green"to mean Pb-Free (RoHS compatible),and free of Bromine (Br)and Antimony (Sb)based flame retardants (Br or Sb do not exceed 0.1%by weight in homogeneous material)(3)MSL,Peak Temp.--The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications,and peak solder temperature.Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.TI bases its knowledge and belief on information provided by third parties,and makes no representation or warranty as to the accuracy of such information.Efforts are underway to better integrate information from third parties.TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary,and thus CAS numbers and other limited information may not be available for release.In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s)at issue in this document sold by TI to Customer on an annual basis.PACKAGE OPTION ADDENDUM 23-Apr-2007TAPE AND REEL INFORMATION*All dimensions are nominal Device Package Type Package DrawingPinsSPQ Reel Diameter (mm)Reel Width W1(mm)A0(mm)B0(mm)K0(mm)P1(mm)W (mm)Pin1Quadrant CD74ACT10M96SOIC D 142500330.016.4 6.59.0 2.18.016.0Q1*All dimensions are nominalDevice Package Type Package Drawing Pins SPQ Length(mm)Width(mm)Height(mm) CD74ACT10M96SOIC D142500346.0346.033.0。

CD74ACT541中文资料

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265Copyright © 1999, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date.Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.The CD54/74AC540, -541, and CD54/74ACT540, -541 octal buffer/line drivers use the RCA ADVANCED CMOS technology. The CD54/74AC/ACT540 are inverting 3-state buffers having two active-LOW output enables. The CD54/74AC/ACT541 are non-inverting 3-state buffers having two active-LOW output enables.The CD74AC540, -541, and CD74ACT540, -541 are supplied in 20-lead dual-in-line plastic packages (E suffix) and in 20-lead dual-in-line small-outline plastic packages (M suffix). Both package types are operable over the following temperature ranges: Industrial (–40 to +85°C) and Extended Industrial/Military (–55 to +125°C).The CD54AC540, -541, and CD54ACT540, -541, available in chip form (H suffix), are operable over the –55 to +125°C temperature range.L H ZData sheet acquired from Harris Semiconductor SCHS285A – Revised November 1999MAXIMUM RATINGS,Absolute-Maximum Values:. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .DC SUPPLY-VOLTAGE (V CC)–0.5 to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .DC INPUT DIODE CURRENT, I IK (for V I < –0.5 or V I > V CC + 0.5 V)±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .DC OUTPUT DIODE CURRENT, I OK (for V O < –0.5 or V O > V CC + 0.5 V)±50 mA DC OUTPUT SOURCE OR SINK CURRENT per Output Pin, I O (for V O > –0.5 or V O < V CC + 0.5 V)±50 mA. . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .DC V CC OR GROUND CURRENT (I CC or I GND)±100 mA*. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .PACKAGE THERMAL IMPEDANCE, θJA (see Note 1):E package69°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .M package58°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .STORAGE TEMPERATURE (T stg)–65 to +150°C LEAD TEMPERATURE (DURING SOLDERING):. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm) from case for 10 s maximum+265°C. . . . . . . . . . . . . . . . . . . . . . . .Unit inserted into PC board min. thickness 1/16 in. (1.59 mm) with solder contacting lead tips only+300°C * For up to 4 outputs per device: add ±25 mA for each additional output.NOTE 1:The package thermal impedance is calculated in accordance with JESD 51.2POST OFFICE BOX 655303 • DALLAS, TEXAS 752653 POST OFFICE BOX 655303 • DALLAS, TEXAS 752654POST OFFICE BOX 655303 • DALLAS, TEXAS 75265ns5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265POST OFFICE BOX 655303 • DALLAS, TEXAS 75265元器件交易网IMPORTANT NOTICETexas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinueany product or service without notice, and advise customers to obtain the latest version of relevant informationto verify, before placing orders, that information being relied on is current and complete. All products are soldsubject to the terms and conditions of sale supplied at the time of order acknowledgement, including thosepertaining to warranty, patent infringement, and limitation of liability.TI warrants performance of its semiconductor products to the specifications applicable at the time of sale inaccordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extentTI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarilyperformed, except those mandated by government requirements.CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OFDEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICALAPPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, ORWARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHERCRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TOBE FULLY AT THE CUSTOMER’S RISK.In order to minimize risks associated with the customer’s applications, adequate design and operatingsafeguards must be provided by the customer to minimize inherent or procedural hazards.TI assumes no liability for applications assistance or customer product design. TI does not warrant or representthat any license, either express or implied, is granted under any patent right, copyright, mask work right, or otherintellectual property right of TI covering or relating to any combination, machine, or process in which suchsemiconductor products or services might be or are used. TI’s publication of information regarding any thirdparty’s products or services does not constitute TI’s approval, warranty or endorsement thereof.Copyright © 1999, Texas Instruments Incorporated。

IC datasheet pdf-TL1431,pdf(Precision Programmable Reference)

(4) The package thermal impedance is calculated in accordance with JESD 51-7.
(5) Maximum power dissipation is a function of TJ(max), θJC, and TC. The maximum allowable power dissipation at any allowable case temperature is PD = (TJ(max) – TC)/θJC. Operating at the absolute maximum TJ of 150°C can affect reliability.
2
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

FEATURES
1
•2 0.4% Initial Voltage Tolerance • 0.2-Ω Typical Output Impedance • Fast Turnon…500 ns
D PACKAGE (TOP VIEW)
CATHODE 1 ANODE 2 ANODE 3 NC 4
II(ref)
Reference input current range
θJA

CD74ACT540中文资料

CD74HCT540资料

Data sheet acquired from Harris Semiconductor SCHS189Features•CD74HC540, CD74HCT540 . . . . . . . . . . . . . . .Inverting•CD74HC541, CD74HCT541 . . . . . . . . . . . . . .Non-Inverting •Buffered Inputs •Three-State Outputs •Bus Line Driving Capability•Typical Propagation Delay = 9ns at V CC = 5V ,C L = 15pF, T A = 25o C•Fanout (Over Temperature Range)-Standard Outputs. . . . . . . . . . . . . . .10 LSTTL Loads -Bus Driver Outputs . . . . . . . . . . . . .15 LSTTL Loads •Wide Operating Temperature Range . . .-55o C to 125o C •Balanced Propagation Delay and Transition Times •Signiﬁcant Power Reduction Compared to LSTTL Logic ICs •HC Types-2V to 6V Operation-High Noise Immunity: N IL = 30%, N IH = 30% of V CC at V CC = 5V •HCT Types- 4.5V to 5.5V Operation-Direct LSTTL Input Logic Compatibility,V IL = 0.8V (Max), V IH = 2V (Min)-CMOS Input Compatibility, I l ≤1µA at V OL , V OHDescriptionThe Harris CD74HC540and CD74HCT540are Inverting Octal Buffers and Line Drivers with Three-State Outputs and the capability to drive 15LSTTL loads.The Harris CD74HC541and CD74HCT541are Non-Inverting Octal Buff-ers and Line Drivers with Three-State Outputs that can drive 15LSTTL loads.The Output Enables (OE1)and (OE2)con-trol the Three-State Outputs.If either OE1or OE2is HIGH the outputs will be in the high impedance state.For data output OE1 and OE2 both must be LOW.Ordering InformationPART NUMBER TEMP.RANGE (o C)PACKAGE PKG.NO.CD74HC540E -55 to 12520 Ld PDIP E20.3CD74HCT540E -55 to 12520 Ld PDIP E20.3CD74HC541E -55 to 12520 Ld PDIP E20.3CD74HCT541E -55 to 12520 Ld PDIP E20.3CD74HC540M -55 to 12520 Ld SOIC M20.3CD74HCT540M -55 to 12520 Ld SOIC M20.3CD74HC541M -55 to 12520 Ld SOIC M20.3CD74HCT541M-55 to 12520 Ld SOICM20.3NOTES:1.When ordering,use the entire part number.Add the sufﬁx 96to obtain the variant in the tape and reel.2.Wafer and die for this part number is available which meets all electrical specifications.Please contact your local sales office or Harris customer service for ordering information.PinoutsCD74HC540, CD74HCT540(PDIP , SOIC)TOP VIEWCD74HC541, CD74HCT541(PDIP , SOIC)TOP VIEW1112131415161718201910987654321OE A0A1A2A3A4A6A5A7GND V CC Y0Y1Y2OE2Y3Y4Y5Y6Y71112131415161718201910987654321OE1A0A1A2A3A4A6A5A7GND V CC Y0Y1Y2OE2Y3Y4Y5Y6Y7January 1998CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.File Number1659.2CD74HC540, CD74HCT540,CD74HC541, CD74HCT541High Speed CMOS LogicOctal Buffer and Line Drivers, Three-State[ /Title (CD74HC540,CD74HCT540,CD74HC541,CD74HCT54Functional DiagramTRUTH TABLEINPUTSOUTPUTSOE1OE2An 540541L L H L H H X X Z Z X H X Z Z LLLHLNOTE:H = HIGH Voltage Level L = LOW Voltage Level X = Don’t CareZ = High ImpedanceD 0Y 0D 2D 4D 6Y 2Y 4Y 6D 1D 3D 5D 7Y 1Y 3Y 5Y 7OE AOE B540541Y 0Y 2Y 4Y 6Y 1Y 3Y 5Y 7Absolute Maximum Ratings Thermal InformationDC Supply Voltage, V CC. . . . . . . . . . . . . . . . . . . . . . . .-0.5V to 7V DC Input Diode Current, I IKFor V I < -0.5V or V I > V CC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, I OKFor V O < -0.5V or V O > V CC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Drain Current, per Output, I OFor -0.5V < V O < V CC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±35mA DC Output Source or Sink Current per Output Pin, I OFor V O > -0.5V or V O < V CC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA DC V CC or Ground Current, I CC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA Operating ConditionsTemperature Range, T A . . . . . . . . . . . . . . . . . . . . . .-55o C to 125o C Supply Voltage Range, V CCHC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, V I, V O . . . . . . . . . . . . . . . . .0V to V CC Input Rise and Fall Time2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .400ns (Max)Thermal Resistance (T ypical, Note 3)θJA (o C/W) PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .125 SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .120 Maximum Junction T emperature. . . . . . . . . . . . . . . . . . . . . . .150o C Maximum Storage Temperature Range . . . . . . . . . .-65o C to 150o C Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300o C (SOIC - Lead Tips Only)CAUTION:Stresses above those listed in“Absolute Maximum Ratings”may cause permanent damage to the device.This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.NOTE:3.θJA is measured with the component mounted on an evaluation PC board in free air.DC Electrical SpeciﬁcationsPARAMETER SYMBOLTESTCONDITIONS VCC(V)25o C-40o C TO 85o C-55o C TO125o CUNITS V I(V)I O(mA)MIN TYP MAX MIN MAX MIN MAXHC TYPESHigh Level Input Voltage V IH--2 1.5-- 1.5- 1.5-V4.5 3.15-- 3.15 - 3.15-V6 4.2-- 4.2- 4.2-VLow Level Input Voltage V IL--2--0.5-0.5-0.5V4.5-- 1.35- 1.35- 1.35V6-- 1.8- 1.8- 1.8VHigh Level Output VoltageCMOS Loads V OH V IH or V IL-0.022 1.9-- 1.9- 1.9-V -0.02 4.5 4.4-- 4.4 - 4.4-V-0.026 5.9-- 5.9- 5.9-VHigh Level Output VoltageTTL Loads---------V -6 4.5 3.98-- 3.84- 3.7-V -7.86 5.48-- 5.34- 5.2-VLow Level Output VoltageCMOS Loads V OL V IH or V IL0.022--0.1-0.1-0.1V0.02 4.5--0.1-0.1-0.1V0.026--0.1-0.1-0.1VLow Level Output VoltageTTL Loads---------V6 4.5--0.26-0.33-0.4V7.86--0.26-0.33-0.4VInput Leakage Current I I V CC orGND-6--±0.1-±1-±1µAQuiescent Device CurrentI CC V CC or GND 06--8-80-160µA Three-State Leakage Current I OZV IL or V IHV O =V CC or GND6--±0.5-±5.0-±10µAHCT TYPES High Level Input Voltage V IH -- 4.5 to 5.52--2-2-V Low Level Input VoltageV IL -- 4.5 to 5.5--0.8-0.8-0.8V High Level Output VoltageCMOS Loads V OHV IH or V IL-0.024.54.4-- 4.4- 4.4-VHigh Level Output Voltage TTL Loads -6 4.5 3.98-- 3.84- 3.7-VLow Level Output VoltageCMOS Loads V OLV IH or V IL0.02 4.5--0.1-0.1-0.1VLow Level Output Voltage TTL Loads 6 4.5--0.26-0.33-0.4VInput Leakage CurrentI I V CC and GND 0 5.5-±0.1-±1-±1µA Quiescent Device CurrentI CC V CC or GND 0 5.5--8-80-160µA Three-State Leakage CurrentI OZV IL or V IHV O =V CC or GND 5.5--±0.5-±5.0-±10µAAdditional Quiescent Device Current Per Input Pin: 1 Unit Load∆I CCV CC -2.1-4.5 to5.5-100360-450-490µANOTE:For dual-supply systems theoretical worst case (V I = 2.4V , V CC = 5.5V) speciﬁcation is 1.8mA.DC Electrical Speciﬁcations(Continued)PARAMETER SYMBOL TEST CONDITIONSV CC (V)25o C-40o C TO 85o C -55o C TO 125o C UNITS V I (V)I O (mA)MIN TYP MAX MIN MAX MIN MAX HCT Input Loading TableINPUT UNIT LOADSHCT540HCT541A0 - A710.4OE20.750.75OE11.151.15NOTE:Unit load is ∆I CC limit speciﬁc in DC Electrical Speciﬁcations Table, e.g., 360µA max. at 25o C.Switching Speciﬁcations C L = 50pF, Input t r, t f= 6nsPARAMETER SYMBOLTESTCONDITIONS V CC(V)25o C-40o C TO85o C-55o C TO125o CUNITSMIN TYP MAX MIN MAX MIN MAXHC TYPESPropagation Delay t PLH, t PHL C L = 50pFData to Outputs (540)2--110-140-165ns4.5--22-28-33nsC L = 15pF5-9-----nsC L = 50pF6--19-24-28nsData to Outputs (541)t PLZ,t PHZ C L = 50pF2--115-145-175ns4.5--23-29-35nsC L = 15pF5-9-----nsC L = 50pF6--20-25-30nsOutput Enable and Disable to Outputs (540)t PLZ,t PHZ C L = 50pF2--160-200-240ns4.5--32-40-48nsC L = 15pF5-13-----nsC L = 50pF6--27-34-41nsOutput Enable and Disable to Outputs (541)t PLZ,t PHZ C L = 50pF2--160-200-240ns4.5--32-40-48nsC L = 15pF5-14-----nsC L = 50pF6--23-29-35nsOutput Transition Time t THL, t TLH C L = 50pF2--60-75-90ns4.5--12-15-18ns6--10-13-15ns Input Capacitance C I C L = 50pF-10-10-10-10pF Three-State OutputCapacitanceC O--20-20-20-20pFPower Dissipation Capacitance(Notes 4, 5) (540)C PD C L = 15pF5-50-----pFPower Dissipation Capacitance(Notes 4, 5) (541)C PD C L = 15pF5-48-----pF HCT TYPESPropagation Delay t PHL,t PLHData to Outputs (540)C L = 50pF 4.5--24-30-36nsC L = 15pF5-9-----nsData to Outputs (541)t PHL,t PLH C L = 50pF 4.5--28-35-42nsC L = 15pF5-11-----nsOutput Enable and Disable to Outputs (540, 541)t PLZ,t PHZ C L = 50pF 4.5--35-44-53nsC L = 15pF5-14-----nsOutput Transition Time t TLH, t THL C L = 50pF 4.5--12-15-18ns Input Capacitance C I C L = 50pF-10-10-10-10pFThree-State Output CapacitanceC O --20-20-20-20pF Power Dissipation Capacitance (Notes 4, 5) (540, 541)C PDC L = 15pF5-55-----pFNOTES:4.C PD is used to determine the dynamic power consumption, per channel.5.P D = V CC 2 f i (C PD + C L ) where f i =Input Frequency, C L = Output Load Capacitance, V CC = Supply Voltage.Switching SpeciﬁcationsC L = 50pF, Input t r , t f = 6ns (Continued)PARAMETERSYMBOL TEST CONDITIONSV CC (V)25o C-40o C TO 85o C -55o C TO 125o C UNITS MIN TYP MAX MIN MAX MIN MAX Test Circuits and WaveformsFIGURE 1.HC TRANSITION TIMES AND PROPAGATIONDELAY TIMES, COMBINATION LOGICFIGURE 2.HCT TRANSITION TIMES AND PROPAGATIONDELAY TIMES, COMBINATION LOGICFIGURE 3.HC THREE-STATE PROPAGATION DELAYWAVEFORM FIGURE 4.HCT THREE-STATE PROPAGATION DELAYWAVEFORMt PHLt PLHt THLt TLH 90%50%10%50%10%INVERTING OUTPUTINPUTGNDV CCt r = 6nst f = 6ns90%t PHLt PLHt THLt TLH 2.7V 1.3V 0.3V1.3V 10%INVERTING OUTPUTINPUTGND3Vt r = 6nst f = 6ns90%50%10%90%GNDV CC 10%90%50%50%OUTPUT DISABLEOUTPUT LOWTO OFFOUTPUT HIGHTO OFFOUTPUTS ENABLEDOUTPUTS DISABLEDOUTPUTS ENABLED6ns 6nst PZH t PHZt PZLt PLZ0.32.7GND3V10%90%1.3V1.3VOUTPUT DISABLEOUTPUT LOWTO OFFOUTPUT HIGHTO OFFOUTPUTS ENABLEDOUTPUTS DISABLEDOUTPUTS ENABLEDt r6nst PZHt PHZt PZLt PLZ6nst f 1.3CD74HC540, CD74HCT540, CD74HC541, CD74HCT541NOTE:Open drain waveforms t PLZ and t PZL are the same as those for three-state shown on the left.The test circuit is Output R L =1k Ωto V CC , C L = 50pF .FIGURE 5.HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUITTest Circuits and Waveforms (Continued)IC WITH THREE-STATE OUTPUT OTHER INPUTS TIED HIGH OR LOW OUTPUT DISABLEV CC FOR t PLZ AND t PZL GND FOR t PHZ AND t PZHOUTPUTR L = 1k ΩC L 50pFIMPORTANT NOTICETexas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability.TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK.In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards.TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.Copyright © 1999, Texas Instruments Incorporated。

CD74AC540中文资料

74AC540中文资料

2
元器件交易网
74AC540
AC Electrical Characteristics
VCC Symbol tPLH tPHL tPZH tPZL tPHZ tPLZ Parameter Propagation Delay Data to Output Propagation Delay Data to Output Output Enable Time Output Enable Time Output Disable Time Output Disable Time (V) (Note 5) 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0
元器件交易网
74AC540 Octal Buffer/Line Driver with 3-STATE Outputs
November 1988 Revised November 1999
74AC540 Octal Buffer/Line Driver with 3-STATE Outputs
TA = −40°C to +85°C CL = 50 pF Min 1.0 1.0 1.0 1.0 2.5 2.0 2.0 1.5 1.5 1.0 2.0 1.5 Max 8.0 6.5 7.5 6.0 12.0 9.5 11.0 8.5 14.0 11.0 11.0 9.0 ns ns ns ns ns ns Units
Ds009966

元器件交易网
74AC540
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC) DC Input Diode Current (IIK) VI = −0.5V VI = VCC + 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = −0.5V VO = VCC + 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) Junction Temperature (TJ) PDIP 140°C ±50 mA −65°C to +150°C ±50 mA −20 mA +20 mA −0.5V to VCC + 0.5V −20 mA +20 mA −0.5V to VCC + 0.5V −0.5V to +7.0V

IC datasheet pdf-CAT4104 pdf,datasheet

CAT4104700 mA Quad ChannelConstant Current LED DriverDescriptionThe CAT4104 provides four matched low dropout current sinks to drive high −brightness LED strings up to 175 mA per channel. The LED channel current is set by an external resistor connected to the RSET pin. The LED pins are compatible with high voltage up to 25 V supporting applications with long strings of LEDs.The EN/PWM logic input supports the device enable and high frequency external Pulse Width Modulation (PWM) dimming control.Thermal shutdown protection is incorporated in the device to disable the LED outputs whenever the die temperature exceeds 150°C.The device is available in the 8−pad TDFN 2 mm x 3 mm package and the SOIC 8−Lead 150 mil wide package.Features•4 Matched LED Current Sinks up to 175 mA •Up to 25 V Operation on LED Pins•Low Dropout Current Source (0.4 V at 175 mA)•LED Current Set by External Resistor•High Frequency PWM Dimming via EN/PWM •“Zero” Current Shutdown Mode •Thermal Shutdown Protection•TDFN 8−pad 2 x 3 mm and SOIC 8−lead Packages•These Devices are Pb −Free, Halogen Free/BFR Free and are RoHS CompliantApplications•Automotive Lighting•General and Architectural Lighting •LCD BacklightFigure 1. Typical Application Circuit768 WONOFFSOIC −8V SUFFIX CASE 751BD PIN CONNECTIONSMARKING DIAGRAMSCAT4104V = CAT4104VHC = CAT4104VP2SOIC 8−lead (Top View)Device Package Shipping ORDERING INFORMATIONCAT4104V −GT3(Note 1)SOIC −8(Pb −Free)3,000/Tape & Reel 1.Lead Finish is NiPdAuCAT4104V TDFN −8VP SUFFIX CASE 511AKCAT4104VP2−GT3(Note 1)TDFN −8(Pb −Free)3,000/Tape & ReelGNDVIN RSET LED4LED3LED2LED11EN/PWM GNDVINRSET LED4LED3LED2LED1EN/PWM TDFN 8−pad (Top View)HC1Table 1. ABSOLUTE MAXIMUM RATINGSParameter Rating Unit VIN, RSET, EN/PWM Voltages−0.3 to 6V LED1, LED2, LED3, LED4 Voltages−0.3 to 25V Storage Temperature Range−65 to +160_C Junction Temperature Range−40 to +150_C Lead Temperature300_C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.Table 2. RECOMMENDED OPERATING CONDITIONSParameter Rating Unit VIN 3.0 to 5.5V Voltage applied to LED1 to LED4, outputs off up to 25V Voltage applied to LED1 to LED4, outputs on up to 6 (Note 2)V Ambient Temperature Range−40 to +85_CI LED per LED pin10 to 175mA2.Keeping LEDx pin voltage below 6 V in operation is recommended to minimize thermal dissipation in the package.NOTE:Typical application circuit with external components is shown on page 1.Table 3. ELECTRICAL OPERATING CHARACTERISTICS (Min and Max values are over the recommended operating conditions= 25°C.)unless specified otherwise. Typical values are at VIN = 5.0 V, TTable 4. RECOMMENDED EN/PWM TIMING (Min and Max values are over the recommended operating conditions unless specified otherwise. Typical values are at VIN = 5.0 V, T AMB = 25°C.)Symbol NameConditions MinTyp MaxUnits T PS Turn −On time, EN/PWM rising to I LED from shutdownI LED = 175 mA I LED = 80 mA 1.51.3m s T P1Turn −On time, EN/PWM rising to I LED I LED = 175 mA 600ns T P2Turn −Off time, EN/PWM falling to I LED I LED= 175 mA I LED = 80 mA 400300ns T R LED rise time I LED = 175 mA I LED = 80 mA 700440ns T F LED fall time I LED = 175 mA I LED = 80 mA360320ns T LO EN/PWM low time 1m s T HI EN/PWM high time5m s T PWRDWNEN/PWM low time to shutdown delay48msFigure 2. CAT4104 EN/PWM TimingEN/PWM OperationThe EN/PWM pin has two primary functions. One function enables and disables the device. The other function turns the LED channels on and off for PWM dimming control. The device has a very fast turn −on time (from EN/PWM rising to LED on) and allows “instant on” when dimming LED using a PWM signal.Accurate linear dimming is compatible with PWM frequencies from 100 Hz to 5 kHz for PWM duty cycle down to 1%. PWM frequencies up to 50 kHz can be supported for duty cycles greater than 10%.When performing a combination of low frequencies and small duty cycles, the device may enter shutdown mode.This has no effect on the dimming accuracy, because the turn −on time T PS is very short, in the range of 1 m s.To ensure that PWM pulses are recognized, pulse width low time T LO should be longer than 1 m s. The CAT4104enters a “zero current” shutdown mode after a 4 ms delay (typical) when EN/PWM is held low.Figure 3. Quiescent Current vs. Input Voltage(RSET Open)Figure 4. Quiescent Current vs. RSET CurrentINPUT VOLTAGE (V)RSET CURRENT (mA)5.55.04.54.03.53.00.40.60.81.01.22.01.51.00.5002468Figure 5. Quiescent Current vs. Input Voltage(Full Load)Figure 6. LED Dropout vs. LED Pin VoltageINPUT VOLTAGE (V)LED PIN VOLTAGE (V)5.55.04.54.03.53.05.05.56.06.57.0 1.00.80.60.40.2004080120160200Figure 7. LED Line RegulationFigure 8. LED Current Change vs.TemperatureVIN (V)TEMPERATURE (°C)5.55.04.54.03.53.00408012016020012080400−4004080120160200Q U I E S C E N T C U R R E N T (m A )Q U I E S C E N T C U R R E N T (m A )Q U I E S C E N T C U R R E N T (m A )L E D C U R R E N T (m A )L E D C U R R E N T (m A )L E D C U R R E N T (m A )No LoadFull LoadFigure 9. LED Current vs. RSET ResistorFigure 10. LED Current vs. LED Pin VoltageRSET (k W )LED PIN VOLTAGE (V)1010.1101001000654321004080120160200Figure 11. RSET Pin Voltage vs. Input VoltageFigure 12. RSET Pin Voltage vs. TemperatureINPUT VOLTAGE (V)TEMPERATURE (°C)5.55.04.54.03.53.01.101.151.201.251.3012080400−401.101.151.201.251.30Figure 13. LED Off Current vs. LED PinVoltageLED PIN VOLTAGE (V)0.20.40.60.81.0L E D C U R R E N T (m A )L E D C U R R E N T (m A )R S E T V O L T A G E (V )R S E T V O L T A G E (V )L E D O F F C U R R E N T (m A )Figure 14. EN/PWM Pull −down Current vs.V EN/PWMFigure 15. EN/PWM Threshold vs. VINENABLE VOLTAGE (V)INPUT VOLTAGE (V)54321005101520250.40.60.81.01.21.4Figure 16. Power Up from Shutdown Figure 17. Power DownFigure 18. PWM 200 Hz, 1% Duty CycleE N A B L E C U R R E N T (m A )E N A B L E T H R E S H O L D (V )Table 5. PIN DESCRIPTIONSNamePinSOIC 8−LeadPinTDFN 8−Lead FunctionLED111LED1 cathode terminalLED222LED2 cathode terminalLED333LED3 cathode terminalLED444LED4 cathode terminalGND5 5 and TAB Ground referenceEN/PWM66Device enable input and PWM control VIN77Device supply pinRSET88LED current set pin for the LED channels Pin FunctionVIN is the supply pin for the device. A small 0.1 m F ceramic bypass capacitor is optional for noisy environments. Whenever the input supply falls below the under−voltage threshold, all LED channels are automatically disabled. EN/PWM is the enable and one wire dimming input for all LED channels. Guaranteed levels of logic high and logic low are set at 1.3 V and 0.4 V respectively. When EN/PWM is initially taken high, the device becomes enabled and all LED currents are set at a gain of 100 times the current in RSET. To place the device into zero current shutdown mode, the EN/PWM pin must be held low for 4 ms typical.LED1 to LED4 provide individual regulated currents for each of the LED cathodes. There pins enter a high impedance zero current state whenver the device is placed in shutdown mode.RSET pin is connected to an external resistor to set the LED channel current. The ground side of the external resistor should be star connected to the GND of the PCB. The pin source current mirrors the current to the LED sinks. The voltage at this pin is regulated to 1.2 V.GND is the ground reference for the device. The pin must be connected to the ground plane on the PCB.TAB (TDFN 8−Lead Only) is the exposed pad underneath the package. For best thermal performance, the tab should be soldered to the PCB and connected to the ground plane.Block DiagramFigure 19. CAT4104 Functional Block Diagram4 Current Sink RegulatorsVINBasic OperationThe CAT4104 has four tightly matched current sinks to regulate LED current in each channel. The LED current in the four channels is mirrored from the current flowing through the RSET pin according to the following formula:I LED ^1001.2V R SETTable 6 shows standard resistor values for RSET and the corresponding LED current.Table 6. RSET RESISTOR SETTINGSLED Current [mA]RSET [k W ]20 6.3460 2.10100 1.271750.768Tight current regulation for all channels is possible over a wide range of input voltages and LED voltages due to independent current sensing circuitry on each channel.Each LED channel needs a minimum of 400 mV headroom to sink constant regulated current up to 175 mA.If the input supply falls below 2 V , the under −voltage lockout circuit disables all LED channels. Any unused LED channels should be left open.For applications requiring more than 175 mA current,LED channels can be tied together to sink up to a total of 700 mA from the one device.The LED channels can withstand voltages up to 25 V . This makes the device ideal for driving long strings of high power LEDs from a high voltage source.Application InformationSingle 12 V SupplyThe circuit shown in Figure 20 shows how to power the LEDs from a single 12 V supply using the CA T4104. Three external components are needed to create a lower voltage necessary for the VIN pin (below 5.5 V). The resistor R2 and zener diode Z provide a regulated voltage while the quiescent current runs through the N −Channel transistor M.The recommended parts are ON Semiconductor MM3Z6V2zener diode (in SOD −323 package), and 2N7002L N −Channel transistor (in SOT23).Figure 20. Single Supply Driving 12 LEDsDaylight DetectionThe circuit in Figure 21 shows how to use CA T4104 in an automatic light sensor application. The light sensor allows the CAT4104 to be enabled during the day and disabled during the night. Two external components are required to configure the part for ambient light detection and conserve power. Resistor R1 sets the bias for the light sensor. The recommended part is Microsemi LX1972 light sensor. For best performance, the LED light should not interfere with the light sensor.Figure 21. Daylight DetectionNightlight DetectionThe circuit shown in Figure 22 illustrates how to use the CAT4104 in an automatic night light application. The light sensor allows the CA T4104 to be disabled during the day and enabled during the night. Five external components are needed to properly configure the part for night detection.Resistor R3 limits the quiescent current through the N −Channel transistor M. Resistors R1 and R2 act as avoltage divider to create the required voltage to turn on transistor M, which disables the CAT4104. The recommended parts are ON Semiconductor 2N7002L N −Channel transistor (in SOT23) and the Microsemi LX1972 light sensor. For best performance, the LED light should not interfere with the light sensor.Figure 22. Nightlight DetectionLED Current DeratingThe circuit shown in Figure 23 provides LED temperature derating to avoid over −driving the LED under high ambient temperatures, by reducing the LED current to protect the LED from over −heating. The positive thermo coefficient (PTC) thermistor RPTC is used for temperature sensing and should be located near the LED. As the temperature of RPTC increases, the gate voltage of the MOSFET M1decreases. This causes the transistor M1 on −resistance to increase which results in a reduction of the LED current. The circuit is powered from a single VCC voltage of 5 V . The recommended parts are Vishay 70°C thermistor PTCSS12T071DTE and ON Semiconductor 2N7002L N −Channel transistor (in SOT23).The PCB and heatsink for the LED should be designed such that the LED current is constant within the normal temperature range. But as soon as the ambient temperature exceeds a max threshold, the LED current drops to protect the LEDs from overheating.Figure 23. LED Current DeratingPower DissipationThe power dissipation (P D) of the CAT4104 can be calculated as follows:P D+(V IN I IN))S(V LEDN I LEDN)where V LEDN is the voltage at the LED pin, and I LEDN is theLED current. Combinations of high V LEDN voltage and high ambient temperature can cause the CAT4104 to enter thermal shutdown. In applications where V LEDN is high, a resistor can be inserted in series with the LED string to lower the power dissipation P D.Thermal dissipation of the junction heat consists primarily of two paths in series. The first path is the junction to the case (q JC) thermal resistance which is defined by the package style, and the second path is the case to ambient (q CA) thermal resistance, which is dependent on board layout. The overall junction to ambient (q JA) thermal resistance is equal to:q JA+q JC)q CAFor a given package style and board layout, the operating junction temperature T J is a function of the power dissipation P D, and the ambient temperature, resulting in the following equation:T J+T AMB)P D(q JC)q CA)+T AMB)P D q JA When mounted on a double−sided printed circuit board with two square inches of copper allocated for “heat spreading”, the resulting q JA is about 90°C/W for the TDFN−8 package, and 160°C/W for the SOIC−8 package. For example, at 60°C ambient temperature, the maximum power dissipation for the TDFN−8 is calculated as follow: P Dmax+T Jmax*T AMBq JA+150*6090+1WRecommended LayoutA small ceramic capacitor should be placed as close as possible to the driver VIN pin. The RSET resistor should have a Kelvin connection to the GND pin of the CAT4104. The board layout should provide good thermal dissipation through the PCB. In the case of the CAT4104VP2 in the TDFN package, a via can be used to connect the center tab to a large ground plane underneath as shown on Figure 24.Figure 24. CAT4104 Recommended LayoutSOIC 8, 150 mils CASE 751BD −01ISSUE OIDENTIFICATIONTOP VIEWSIDE VIEWEND VIEWNotes:(1) All dimensions are in millimeters. Angles in degrees.(2) Complies with JEDEC MS-012.SYMBOLMIN NOMMAX θA A1b cD E E1e h 0º8º0.100.330.190.254.805.803.801.27 BSC1.750.250.510.250.505.006.204.00L0.40 1.271.35TDFN8, 2x3CASE 511AK −01ISSUE ATOP VIEW SIDE VIEW BOTTOM VIEWFRONT VIEWA1Notes:(1) All dimensions are in millimeters.(2) Complies with JEDEC MO-229.SYMBOLMIN NOM MAX A 0.700.750.80A10.000.020.05A30.20 REF b 0.200.250.30D 1.90 2.00 2.10D2 1.30 1.40 1.50E 3.00E2 1.20 1.30 1.40e 2.900.50 TYP 3.10L0.200.300.40A20.450.550.65Example of Ordering Information (Note 6)Prefix Device #Suffix 4.All packages are RoHS −compliant (Lead −free, Halogen −free).5.The standard plated finish is NiPdAu.6.The device used in the above example is a CAT4104V −GT3 (SOIC, NiPdAu, Tape & Reel, 3,000/Reel).7.For additional temperature options, please contact your nearest ON Semiconductor Sales office.8.For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.PUBLICATION ORDERING INFORMATION。

IC datasheet pdf-CD4046B,pdf(TYPES)

The CD4046B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (NSR suffix), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).PACKAGING INFORMATIONOrderable Device Status(1)PackageType PackageDrawingPins PackageQtyEco Plan(2)Lead/Ball Finish MSL Peak Temp(3)5962-9466401MEA ACTIVE CDIP J161TBD A42N/A for Pkg Type CD4046BE ACTIVE PDIP N1625Pb-Free(RoHS)CU NIPDAU N/A for Pkg TypeCD4046BEE4ACTIVE PDIP N1625Pb-Free(RoHS)CU NIPDAU N/A for Pkg Type CD4046BF ACTIVE CDIP J161TBD A42N/A for Pkg Type CD4046BF3A ACTIVE CDIP J161TBD A42N/A for Pkg Type CD4046BNSR ACTIVE SO NS162000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMCD4046BNSRE4ACTIVE SO NS162000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMCD4046BNSRG4ACTIVE SO NS162000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMCD4046BPW ACTIVE TSSOP PW1690Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMCD4046BPWE4ACTIVE TSSOP PW1690Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMCD4046BPWG4ACTIVE TSSOP PW1690Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMCD4046BPWR ACTIVE TSSOP PW162000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMCD4046BPWRE4ACTIVE TSSOP PW162000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMCD4046BPWRG4ACTIVE TSSOP PW162000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIM(1)The marketing status values are defined as follows:ACTIVE:Product device recommended for new designs.LIFEBUY:TI has announced that the device will be discontinued,and a lifetime-buy period is in effect.NRND:Not recommended for new designs.Device is in production to support existing customers,but TI does not recommend using this part in a new design.PREVIEW:Device has been announced but is not in production.Samples may or may not be available.OBSOLETE:TI has discontinued the production of the device.(2)Eco Plan-The planned eco-friendly classification:Pb-Free(RoHS),Pb-Free(RoHS Exempt),or Green(RoHS&no Sb/Br)-please check /productcontent for the latest availability information and additional product content details.TBD:The Pb-Free/Green conversion plan has not been defined.Pb-Free(RoHS):TI's terms"Lead-Free"or"Pb-Free"mean semiconductor products that are compatible with the current RoHS requirements for all6substances,including the requirement that lead not exceed0.1%by weight in homogeneous materials.Where designed to be soldered at high temperatures,TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free(RoHS Exempt):This component has a RoHS exemption for either1)lead-based flip-chip solder bumps used between the die and package,or2)lead-based die adhesive used between the die and leadframe.The component is otherwise considered Pb-Free(RoHS compatible)as defined above.Green(RoHS&no Sb/Br):TI defines"Green"to mean Pb-Free(RoHS compatible),and free of Bromine(Br)and Antimony(Sb)based flame retardants(Br or Sb do not exceed0.1%by weight in homogeneous material)(3)MSL,Peak Temp.--The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications,and peak solder temperature.Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.TI bases its knowledge and belief on information provided by third parties,and makes no representation or warranty as to the accuracy of such information.Efforts are underway to better integrate information from third parties.TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis onincoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary,and thus CAS numbers and other limited information may not be available for release.In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s)at issue in this document sold by TI to Customer on an annual basis.TAPE AND REEL INFORMATION*All dimensions are nominal Device Package Type Package DrawingPinsSPQ Reel Diameter (mm)Reel Width W1(mm)A0(mm)B0(mm)K0(mm)P1(mm)W (mm)Pin1Quadrant CD4046BNSR SONS 162000330.016.48.210.5 2.512.016.0Q1CD4046BPWR TSSOP PW 162000330.012.4 6.9 5.6 1.68.012.0Q1*All dimensions are nominalDevice Package Type Package Drawing Pins SPQ Length(mm)Width(mm)Height(mm) CD4046BNSR SO NS162000346.0346.033.0CD4046BPWR TSSOP PW162000346.0346.029.0IMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries(TI)reserve the right to make corrections,modifications,enhancements,improvements, and other changes to its products and services at any time and to discontinue any product or service without notice.Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.All 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MC74AC541资料

IOL
24 mA
24 mA
VI = VCC, GND
VI (OE) = VIL, VIH VI = VCC, GND VO = VCC, GND VOLD = 1.65 V Max VOHD = 3.85 V Min
VIN = VCC or GND
3
MC74AC540, MC74ACT540, MC74AC541, MC74ACT541
tr, tf
′ACT Devices except Schmitt Inputs
VCC @ 4.5 V
−
10
−
VCC @ 5.5 V
−
8.0
−
TJ
Junction Temperature (PDIP)
−
−
140
TA
Operating Ambient Temperature RangCHARACTERISTICS (For Figures and Waveforms − See AND8277/D at )
74AC
74AC
Symbol
Parameter
TA = +25°C
TA = −40°C to +85°C
VCC*
CL = 50 pF
CL = 50 pF
These devices are similar in function to the MC74AC240/74ACT240 and MC74AC244/74ACT244 while providing flow−through architecture (inputs on opposite side from outputs). This pinout arrangement makes these devices especially useful as output ports for microprocessors, allowing ease of layout and greater PC board density.

IC datasheet pdf-CD54AC245,CD74AC245,CD54ACT245,CD74ACT245,pdf(Octal-Bus Transceiver,Three-State, No

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
FAST™ is a Trademark of Fairchild Semiconductor.
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA DC Output Source or Sink Current per Output Pin, IO
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
Operating Conditions
Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC (Note 4)
AC Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5V to 5.5V ACT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Slew Rate, dt/dv AC Types, 1.5V to 3V . . . . . . . . . . . . . . . . . . . . . . . . . 50ns (Max) AC Types, 3.6V to 5.5V . . . . . . . . . . . . . . . . . . . . . . . . 20ns (Max) ACT Types, 4.5V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . 10ns (Max)

74HC540中文资料

GENERAL DESCRIPTION The 74HC/HCT540 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.
(1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.7 Waveforms showing the 3-state enable and disable times.
PACKAGE OUTLINES See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.
元器件交易网
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
SYMBOL
PARAMETER
CONDITIONS
tPHL/ tPLH CI CPD

IC datasheet pdf-TPA6011A4,pdf(3-W Stereo Audio Power Amplifier)

FEATURES DESCRIPTIONAPPLICATIONS-90-80-70-60-50-40-30-20-1010203000.51 1.52 2.53 3.54 4.55Volume [Pin 21] - VDC VOLUME CONTROLVolume-dBTPA6011A4SLOS392A–FEBRUARY2002–REVISED JULY20043-W STEREO AUDIO POWER AMPLIFIERWITH ADVANCED DC VOLUME CONTROL•Advanced DC Volume Control With2-dB The TPA6011A4is a stereo audio power amplifier Steps that drives3W/channel of continuous RMS power From-40dB to20dB into a3-Ωload.Advanced dc volume controlminimizes external components and allows BTL –Fade Mode(speaker)volume control and SE(headphone)vol-–Maximum Volume Setting for SE Mode ume control.Notebook and pocket PCs benefit from–Adjustable SE Volume Control the integrated feature set that minimizes external Referenced to BTL Volume Control components without sacrificing functionality.•3W Into3-ΩSpeakers To simplify design,the speaker volume level isadjusted by applying a dc voltage to the VOLUME •Stereo Input MUXterminal.Likewise,the delta between speaker volume •Differential Inputsand headphone volume can be adjusted by applyinga dc voltage to the SEDIFF terminal.To avoid anunexpected high volume level through the •Notebook PC headphones,a third terminal,SEMAX,limits the •LCD Monitors headphone volume level when a dc voltage is ap-plied.Finally,to ensure a smooth transition between •Pocket PCactive and shutdown modes,a fade mode ramps thevolume up and down.Please be aware that an important notice concerning availability,standard warranty,and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.PRODUCTION DATA information is current as of publication date.Copyright©2002–2004,Texas Instruments Incorporated Products conform to specifications per the terms of the TexasInstruments standard warranty.Production processing does notnecessarily include testing of all parameters.ABSOLUTE MAXIMUM RATINGSDISSIPATION RATING TABLERECOMMENDED OPERATING CONDITIIONSTPA6011A4SLOS392A–FEBRUARY 2002–REVISED JULY 2004AVAILABLE OPTIONSPACKAGET A24-PIN TSSOP (PWP)(1)40°C to 85°CTPA6011A4PWP(1)The PWP package is available taped and reeled.To order a taped and reeled part,add the suffix R to the part number (e.g.,TPA6011A4PWPR).over operating free-air temperature range (unless otherwise noted)(1)UNITV SS Supply voltage,V DD ,PV DD -0.3V to 6V V I Input voltage-0.3V to V DD +0.3V Continuous total power dissipation See Dissipation Rating TableT A Operating free-air temperature range -40°C to 85°C T J Operating junction temperature range -40°C to 150°C T stg Storage temperature range-65°C to 150°CLead temperature 1,6mm (1/16inch)from case for 10seconds260°C(1)Stresses beyond those listed under "absolute maximum ratings"may cause permanent damage to the device.These are stress ratings only,and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions"is not implied.Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.T A ≤25°C DERATING FACTOR T A =70°C T A =85°C PACKAGE POWER RATINGABOVE T A =25°CPOWER RATINGPOWER RATINGPWP2.7mW21.8mW/°C1.7W1.4WMINMAX UNIT V SS Supply voltage,V DD ,PV DD 4.0 5.5V SE/BTL,HP/LINE,FADE 0.8×V DDV V IH High-level input voltage SHUTDOWN2V SE/BTL,HP/LINE,FADE 0.6×V DDV V IL Low-level input voltage SHUTDOWN0.8V T AOperating free-air temperature-4085°C2ELECTRICAL CHARACTERISTICSOPERATING CHARACTERISTICSTPA6011A4SLOS392A–FEBRUARY 2002–REVISED JULY 2004T A =25°C,V DD =PV DD =5.5V (unless otherwise noted)PARAMETERTEST CONDITIONSMINTYPMAX UNIT V DD =5.5V,Gain =0dB,SE/BTL =0V 30mV |V OO |Output offset voltage (measured differentially)V DD =5.5V,Gain =20dB,SE/BTL =0V 50mV PSRR Power supply rejection ratioV DD =PV DD =4.0V to 5.5V -42-70dB High-level input current (SE/BTL,FADE,HP/LINE,V DD =PV DD =5.5V,|I IH |1µA SHUTDOWN,SEDIFF,SEMAX,VOLUME)V I =V DD =PV DDLow-level input current (SE/BTL,FADE,HP/LINE,|I IL |V DD =PV DD =5.5V,V I =0V 1µASHUTDOWN,SEDIFF,SEMAX,VOLUME)V DD =PV DD =5.5V,SE/BTL =0V, 6.07.59.0SHUTDOWN =2VI DDSupply current,no loadmA V DD =PV DD =5.5V,SE/BTL =5.5V, 3.056SHUTDOWN =2VV DD =5V =PV DD ,SE/BTL =0V,I DD Supply current,max power intoa 3-Ωload SHUTDOWN =2V,R L =3Ω, 1.5A RMS P O =2W,stereo I DD(SD)Supply current,shutdown modeSHUTDOWN =0.0V120µAT A =25°C,V DD =PV DD =5V,R L =3Ω,Gain =6dB (unless otherwise noted)3PGND ROUT-PV DD RHPIN RLINEINRIN V DD LIN LLINEIN LHPIN PV DD LOUT-PWP PACKAGE (TOP VIEW)TPA6011A4SLOS392A–FEBRUARY 2002–REVISED JULY 2004Terminal FunctionsTERMINAL I/O DESCRIPTIONNAME NO.PGND 1,13-Power groundLOUT-12O Left channel negative audio output PV DD 3,11-Supply voltage terminal for power stageLHPIN 10I Left channel headphone input,selected when HP/LINE is held high LLINEIN 9I Left channel line input,selected when HP/LINE is held lowLIN 8I Common left channel input for fully differential input.AC ground for single-ended inputs.V DD 7-Supply voltage terminalRIN 6I Common right channel input for fully differential input.AC ground for single-ended inputs.RLINEIN 5I Right channel line input,selected when HP/LINE is held low RHPIN 4I Right channel headphone input,selected when HP/LINE is held high ROUT-2O Right channel negative audio output ROUT+24O Right channel positive audio outputSHUTDOWN 15I Places the amplifier in shutdown mode if a TTL logic low is placed on this terminalPlaces the amplifier in fade mode if a logic low is placed on this terminal;normal operation if a logic high is FADE 16I placed on this terminalBYPASS 17I Tap to voltage divider for internal midsupply bias generator used for analog reference AGND 18-Analog power supply groundSEMAX 19I Sets the maximum volume for single ended operation.DC voltage range is 0to V DD .SEDIFF 20I Sets the difference between BTL volume and SE volume.DC voltage range is 0to V DD .VOLUME 21I Terminal for dc volume control.DC voltage range is 0to V DD .Input MUX control.When logic high,RHPIN and LHPIN inputs are selected.When logic low,RLINEIN and HP/LINE 22I LLINEIN inputs are selected.Output MUX control.When this terminal is high,SE outputs are selected.When this terminal is low,BTL SE/BTL 23I outputs are selected.LOUT+14OLeft channel positive audio output.4FUNCTIONAL BLOCK DIAGRAMROUT+SHUTDOWN ROUT-PV DD PGND V DD BYPASS AGNDLOUT+LOUT-TPA6011A4SLOS392A–FEBRUARY 2002–REVISED JULY 2004NOTE:All resistor wipers are adjusted with 32step volume control.5TPA6011A4SLOS392A–FEBRUARY 2002–REVISED JULY 2004Table 1.DC Volume Control (BTL Mode,V DD =5V)(1)VOLUME (PIN 21)GAIN OF AMPLIFIER(Typ)FROM (V)TO (V)0.000.26-85(2)0.330.37-400.440.48-380.560.59-360.670.70-340.780.82-320.890.93-301.01 1.04-281.12 1.16-261.23 1.27-241.35 1.38-221.46 1.49-201.57 1.60-181.68 1.72-161.79 1.83-141.91 1.94-122.02 2.06-102.13 2.17-82.25 2.28-6(2)2.36 2.39-42.47 2.50-22.58 2.6102.70 2.7322.81 2.8342.92 2.9563.04 3.0683.15 3.17103.26 3.29123.38 3.40143.49 3.51163.60 3.63183.715.0020(2)(1)For other values of V DD ,scale the voltage values in the table by a factor of V DD /5.(2)Tested in production.Remaining gain steps are specified by design.6TPA6011A4SLOS392A–FEBRUARY2002–REVISED JULY2004 Table2.DC Volume Control(SE Mode,V DD=5V)(1)SE_VOLUME=VOLUME-SEDIFF or SEMAX GAIN OF AMPLIFIER(Typ)FROM(V)TO(V)0.000.26-85(2)0.330.37-460.440.48-440.560.59-420.670.70-400.780.82-380.890.93-361.01 1.04-341.12 1.16-321.23 1.27-301.35 1.38-281.46 1.49-261.57 1.60-241.68 1.72-221.79 1.83-201.91 1.94-182.02 2.06-162.13 2.17-142.25 2.28-122.36 2.39-102.47 2.50-82.58 2.61-6(2)2.70 2.73-42.81 2.83-22.92 2.950(2)3.04 3.0623.15 3.1743.26 3.296(2)3.38 3.4083.49 3.51103.60 3.63123.71 5.0014(1)For other values of V DD,scale the voltage values in the table by a factor of V DD/5.(2)Tested in production.Remaining gain steps are specified by design.7TYPICAL CHARACTERISTICSTable of GraphsT H D +N − T o t a l H a r m o n i c D i s t o r t i o n + N o i s e (B T L ) − %f − Frequency − Hzf − Frequency − HzT H D +N − T o t a l H a r m o n i c D i s t o r t i o n + N o i s e (B T L ) − %TPA6011A4SLOS392A–FEBRUARY 2002–REVISED JULY 2004FIGUREvs Frequency 1,23THD+NTotal harmonic distortion plus noise (BTL)vs Output power 6,7,8vs Frequency4,5THD+NTotal harmonic distortion plus noise (SE)vs Output power 9vs Output voltage10Closed loop response11,12vs Temperature 13I CC Supply current vs Supply voltage 14,15,16P D Power Dissipation vs Output power 17,18P OOutput power vs Load resistance 19,20Crosstalkvs Frequency 21,22HP/LINE attenuationvs Frequency 23PSRR Power supply ripple rejection (BTL)vs Frequency 24PSRR Power supply ripple rejection (SE)vs Frequency 25Z I Input impedance vs BTL gain 26V nOutput noise voltagevs Frequency 27TOTAL HARMONIC DISTORTION +NOISE (BTL)TOTAL HARMONIC DISTORTION +NOISE (BTL)vsvsFREQUENCYFREQUENCYFigure 1.Figure 2.8f − Frequency − HzT H D +N − T o t a l H a r m o n i c D i s t o r t i o n + N o i s e (S E ) − %f − Frequency − HzT H D +N − T o t a l H a r m o n i c D i s t o r t i o n + N o i s e (B T L ) − %f − Frequency − HzT H D +N − T o t a l H a r m o n i c D i s t o r t i o n + N o i s e (S E ) −%P O − Output Power − WT H D +N − T o t a l H a r m o n i c D i s t o r t i o n + N o i s e (B T L ) − %TPA6011A4SLOS392A–FEBRUARY 2002–REVISED JULY 2004TOTAL HARMONIC DISTORTION +NOISE (BTL)TOTAL HARMONIC DISTORTION +NOISE (SE)vsvsFREQUENCYFREQUENCYFigure 3.Figure 4.TOTAL HARMONIC DISTORTION +NOISE (SE)TOTAL HARMONIC DISTORTION +NOISE (BTL)vsvsFREQUENCYOUTPUT POWERFigure 5.Figure 6.9P O − Output Power − WT H D +N − T o t a l H a r m o n i c D i s t o r t i o n + N o i s e (B T L ) − %P O − Output Power − WT H D +N − T o t a l H a r m o n i c D i s t o r t i o n + N o i s e (B T L ) − %V O − Output Voltage − rmsT H D +N − T o t a l H a r m o n i c D i s t o r t i o n + N o i s e (S E ) − %P O − Output Power − WT H D +N − T o t a l H a r m o n i c D i s t o r t i o n + N o i s e (S E ) − %TPA6011A4SLOS392A–FEBRUARY 2002–REVISED JULY 2004TOTAL HARMONIC DISTORTION +NOISE (BTL)TOTAL HARMONIC DISTORTION +NOISE (BTL)vsvsOUTPUT POWEROUTPUT POWERFigure 7.Figure 8.TOTAL HARMONIC DISTORTION +NOISE (SE)TOTAL HARMONIC DISTORTION +NOISE (SE)vsvsOUTPUT POWEROUTPUT VOLTAGEFigure 9.Figure 10.10f − Frequency − HzC l o s e d L o o p G a i n − d BP h a s e − D e g r e es f − Frequency − HzC l o s e d L o o p G a i n − d BP h a s e − D e g r e e s− S u p p l y C u r r e n t − m AT A − Free-Air Temperature − °C I D DV DD − Supply Voltage − V− S u p p l y C u r r e n t − m AI D D CLOSED LOOP RESPONSECLOSED LOOP RESPONSEFigure 11.Figure 12.SUPPLY CURRENTSUPPLY CURRENTvsvsFREE-AIR TEMPERATURESUPPLY VOLTAGEFigure 13.Figure 14.V DD − Supply Voltage − V− S u p p l y C u r r e n t − I D D nAV DD − Supply Voltage − V− S u p p l y C u r r e n t − m AI D DP O − Output Power − W− P o w e r D i s s i p a t i o n (P E R C H A N N E L ) − WP DP O − Output Power − mW− P o w e r D i s s i p a t i o n (P E R C H A N N E L ) − m WP D SLOS392A–FEBRUARY 2002–REVISED JULY 2004SUPPLY CURRENTSUPPLY CURRENTvsvsSUPPLY VOLTAGESUPPLY VOLTAGEFigure 15.Figure 16.POWER DISSIPATION (PER CHANNEL)POWER DISSIPATION (PER CHANNEL)vsvsOUTPUT POWEROUTPUT POWERFigure 17.Figure 18.R L − Load Resistance − Ω− O u t p u t P o w e r − WP OR L − Load Resistance − Ω− O u t p u t P o w e r − WP O−1 f − Frequency − HzC r o s s t a l k − d B−1 f − Frequency − HzC r o s s t a l k − d BOUTPUT POWEROUTPUT POWERvsvsLOAD RESISTANCELOAD RESISTANCEFigure 19.Figure 20.CROSSTALKCROSSTALKvsvsFREQUENCYFREQUENCYFigure 21.Figure 22.f − Frequency − HzP S R R − P o w e r S u p p l y R e j e c t i o n R a t i o (B T L ) − d Bf − Frequency − HzH P /L i n e A t t e n u a t i o n − d Bf − Frequency − HzP S R R − P o w e r S u p p l y R e j e c t i o n R a t i o (S E ) − d B01020304050607080900BTL Gain − dB− I n p u t I m p e d a m c e − Z I k ΩSLOS392A–FEBRUARY 2002–REVISED JULY 2004HP/LINE ATTENUATIONPOWER SUPPLY REJECTION RATIO (BTL)vsvsFREQUENCYFREQUENCYFigure 23.Figure 24.POWER SUPPLY REJECTION RATIO (SE)INPUT IMPEDANCEvsvs FREQUENCYBTL GAINFigure 25.Figure 26.1008020− O u t p u t N o i s e V o l t a g e −12014018040060160V n V µR M Sf − Frequency − HzOUTPUT NOISE VOLTAGEvsFREQUENCYFigure 27.SLOS392A–FEBRUARY2002–REVISED JULY2004APPLICATION INFORMATIONSELECTION OF COMPONENTSFigure28and Figure29are schematic diagrams of typical notebook computer application circuits.A.A0.1-µF ceramic capacitor should be placed as close as possible to the IC.For filtering lower-frequency noisesignals,a larger electrolytic capacitor of10µF or greater should be placed near the audio power amplifier.Figure28.Typical TPA6011A4Application Circuit Using Single-Ended Inputs and Input MUXAPPLICATION INFORMATION(continued)A.A0.1-µF ceramic capacitor should be placed as close as possible to the IC.For filtering lower-frequency noisesignals,a larger electrolytic capacitor of10µF or greater should be placed near the audio power amplifier.Figure29.Typical TPA6011A4Application Circuit Using Differential InputsSE/BTL OPERATIONThe ability of the TPA6011A4to easily switch between BTL and SE modes is one of its most important cost saving features.This feature eliminates the requirement for an additional headphone amplifier in applications where internal stereo speakers are driven in BTL mode but external headphone or speakers must be accommodated.Internal to the TPA6011A4,two separate amplifiers drive OUT+and OUT-.The SE/BTL input controls the operation of the follower amplifier that drives LOUT-and ROUT-.When SE/BTL is held low,the amplifier is on and the TPA6011A4is in the BTL mode.When SE/BTL is held high,the OUT-amplifiers are in a high output impedance state,which configures the TPA6011A4as an SE driver from LOUT+and ROUT+.I DD is reduced by approximately one-third in SE mode.Control of the SE/BTL input can be from a logic-level CMOS source or,more typically,from a resistor divider network as shown in Figure30.The trip level for the SE/BTL input can be found in the recommended operating conditions table.SLOS392A–FEBRUARY2002–REVISED JULY2004APPLICATION INFORMATION(continued)Figure30.TPA6011A4Resistor Divider Network CircuitUsing a1/8-in.(3,5mm)stereo headphone jack,the control switch is closed when no plug is inserted.When closed the100-kΩ/1-kΩdivider pulls the SE/BTL input low.When a plug is inserted,the1-kΩresistor is disconnected and the SE/BTL input is pulled high.When the input goes high,the OUT-amplifier is shut down causing the speaker to mute(open-circuits the speaker).The OUT+amplifier then drives through the output capacitor(C o)into the headphone jack.HP/LINE OPERATIONThe HP/LINE input controls the internal input multiplexer(MUX).Refer to the block diagram in Figure30.This allows the device to switch between two separate stereo inputs to the amplifier.For design flexibility,the HP/LINE control is independent of the output mode,SE or BTL,which is controlled by the aforementioned SE/BTL pin.To allow the amplifier to switch from the LINE inputs to the HP inputs when the output switches from BTL mode to SE mode,simply connect the SE/BTL control input to the HP/LINE input.When this input is logic high,the RHPIN and LHPIN inputs are selected.When this terminal is logic low,the RLINEIN and LLINEIN inputs are selected.This operation is also detailed in Table3and the trip levels for a logic low(V IL)or logic high(V IH)can be found in the recommended operating conditions table.SHUTDOWN MODESThe TPA6011A4employs a shutdown mode of operation designed to reduce supply current(I DD)to the absolute minimum level during periods of nonuse for battery-power conservation.The SHUTDOWN input terminal should be held high during normal operation when the amplifier is in use.Pulling SHUTDOWN low causes the outputs to mute and the amplifier to enter a low-current state,I DD=20µA.SHUTDOWN should never be left unconnected because amplifier operation would be unpredictable.FADE OPERATION Table3.HP/LINE,SE/BTL,and Shutdown Functions INPUTS(1)AMPLIFIER STATEHP/LINE SE/BTL SHUTDOWN INPUT OUTPUTX X Low X MuteLow Low High Line BTLLow High High Line SEHigh Low High HP BTLHigh High High HP SE(1)Inputs should never be left unconnected.For design flexibility,a fade mode is provided to slowly ramp up the amplifier gain when coming out of shutdown mode and conversely ramp the gain down when going into shutdown.This mode provides a smooth transition between the active and shutdown states and virtually eliminates any pops or clicks on the outputs.When the FADE input is a logic low,the device is placed into fade-on mode.A logic high on this pin places the amplifier in the fade-off mode.The voltage trip levels for a logic low(V IL)or logic high(V IH)can be found in the recommended operating conditions table.When a logic low is applied to the FADE pin and a logic low is then applied on the SHUTDOWN pin,the channel gain steps down from gain step to gain step at a rate of two clock cycles per step.With a nominal internal clock frequency of58Hz,this equates to34ms(1/24Hz)per step.The gain steps down until the lowest gain step is reached.The time it takes to reach this step depends on the gain setting prior to placing the device in shutdown. For example,if the amplifier is in the highest gain mode of20dB,the time it takes to ramp down the channel gain is1.05seconds.This number is calculated by taking the number of steps to reach the lowest gain from the highest gain,or31steps,and multiplying by the time per step,or34ms.After the channel gain is stepped down to the lowest gain,the amplifier begins discharging the bypass capacitor from the nominal voltage of V DD/2to ground.This time is dependent on the value of the bypass capacitor.For a 0.47-µF capacitor that is used in the application diagram in Figure28,the time is approximately500ms.This time scales linearly with the value of bypass capacitor.For example,if a1-µF capacitor is used for bypass,the time period to discharge the capacitor to ground is twice that of the0.47-µF capacitor,or1second.Figure30 below is a waveform captured at the output during the shutdown sequence when the part is in fade-on mode. The gain is set to the highest level and the output is at V DD when the amplifier is shut down.When a logic high is placed on the SHUTDOWN pin and the FADE pin is still held low,the device begins the start-up process.The bypass capacitor will begin charging.Once the bypass voltage reaches the final value of V DD/2,the gain increases in2-dB steps from the lowest gain level to the gain level set by the dc voltage applied to the VOLUME,SEDIFF,and SEMAX pins.In the fade-off mode,the amplifier stores the gain value prior to starting the shutdown sequence.The output of the amplifier immediately drops to V DD/2and the bypass capacitor begins a smooth discharge to ground.When shutdown is released,the bypass capacitor charges up to V DD/2and the channel gain returns immediately to the value stored in memory.Figure31below is a waveform captured at the output during the shutdown sequence when the part is in the fade-off mode.The gain is set to the highest level,and the output is at V DD when the amplifier is shut down.The power-up sequence is different from the shutdown sequence and the voltage on the FADE pin does not change the power-up sequence.Upon a power-up condition,the TPA6011A4begins in the lowest gain setting and steps up2dB every2clock cycles until the final value is reached as determined by the dc voltage applied to the VOLUME,SEDIFF,and SEMAX pins.ROUT+VOLUME,SEDIFF,AND SEMAX OPERATIONSLOS392A–FEBRUARY 2002–REVISED JULY 2004Figure 31.Shutdown Sequence in theFigure 32.Shutdown Sequence in theFade-on Mode Fade-off ModeThree pins labeled VOLUME,SEDIFF,and SEMAX control the BTL volume when driving speakers and the SE volume when driving headphones.All of these pins are controlled with a dc voltage,which should not exceed V DD .When driving speakers in BTL mode,the VOLUME pin is the only pin that controls the gain.Table 1shows the gain for the BTL mode.The voltages listed in the table are for V DD =5V.For a different V DD ,the values in the table scale linearly.If V DD =4V,multiply all the voltages in the table by 4V/5V,or 0.8.The TPA6011A4allows the user to specify a difference between BTL gain and SE gain.This is desirable to avoid any listening discomfort when plugging in headphones.When switching to SE mode,the SEDIFF and SEMAX pins control the singe-ended gain proportional to the gain set by the voltage on the VOLUME pin.When SEDIFF =0V,the difference between the BTL gain and the SE gain is 6dB.Refer to the section labeled bridged-tied load versus single-ended load for an explanation on why the gain in BTL mode is 2x that of single-ended mode,or 6dB greater.As the voltage on the SEDIFF terminal is increased,the gain in SE mode decreases.The voltage on the SEDIFF terminal is subtracted from the voltage on the VOLUME terminal and this value is used to determine the SE gain.Some audio systems require that the gain be limited in the single-ended mode to a level that is comfortable for headphone listening.Most volume control devices only have one terminal for setting the gain.For example,if the speaker gain is 20dB,the gain in the headphone channel is fixed at 14dB.This level of gain could cause discomfort to listeners and the SEMAX pin allows the designer to limit this discomfort when plugging in headphones.The SEMAX terminal controls the maximum gain for single-ended mode.The functionality of the SEDIFF and SEMAX pin are combined to set the SE gain.A block diagram of the combined functionality is shown in Figure 33.The value obtained from the block diagram for SE_VOLUME is a dc voltage that can be used in conjunction with Table 2to determine the SE gain.Again,the voltages listed in the table are for V DD =5V.The values must be scaled for other values of V DD .Table 1and Table 2show a range of voltages for each gain step.There is a gap in the voltage between each gain step.This gap represents the hysteresis about each trip point in the internal comparator.The hysteresis ensures that the gain control is monotonic and does not oscillate from one gain step to another.If a potentiometer is used to adjust the voltage on the control terminals,the gain increases as the potentiometer is turned in one direction and decreases as it is turned back the other direction.The trip point,where the gainSEDIFF (V)VOLUME (V)0242.702.61 2.732.81B T L G a i n - d B Voltage on VOLUME Pin - VTPA6011A4SLOS392A–FEBRUARY 2002–REVISED JULY 2004actually changes,is different depending on whether the voltage is increased or decreased as a result of the hysteresis about each trip point.The gaps in Table 1and Table 2can also be thought of as indeterminate states where the gain could be in the next higher gain step or the lower gain step depending on the direction the voltage is changing.If using a DAC to control the volume,set the voltage in the middle of each range to ensure that the desired gain is achieved.A pictorial representation of the volume control can be found in Figure 34.The graph focuses on three gain steps with the trip points defined in Table 1for BTL gain.The dotted line represents the hysteresis about each gain step.Figure 33.Block Diagram of SE Volume ControlFigure 34.DC Volume Control Operation21 INPUTRESISTANCEInput Signal ƒ*3dB +12p CR i (1)INPUT CAPACITOR,C if c(highpass)+12p R i C i −3 dBf c (2)C i +12p R i f c (3)TPA6011A4SLOS392A–FEBRUARY 2002–REVISED JULY 2004Each gain setting is achieved by varying the input resistance of the amplifier,which can range from its smallest value to over six times that value.As a result,if a single capacitor is used in the input high-pass filter,the -3dB or cutoff frequency also changes by over six times.Figure 35.Resistor on Input for Cut-Off FrequencyThe input resistance at each gain setting is given in Figure 26.The -3-dB frequency can be calculated using Equation 1.In the typical application an input capacitor (C i )is required to allow the amplifier to bias the input signal to the proper dc level for optimum operation.In this case,C i and the input impedance of the amplifier (R i )form a high-pass filter with the corner frequency determined in Equation 2.The value of C i is important to consider as it directly affects the bass (low frequency)performance of the circuit.Consider the example where R i is 70k Ωand the specification calls for a flat-bass response down to 40Hz.Equation 2is reconfigured as Equation 3.In this example,C i is 56.8nF,so one would likely choose a value in the range of 56nF to 1µF.A further consideration for this capacitor is the leakage path from the input source through the input network (C i )and the feedback network to the load.This leakage current creates a dc offset voltage at the input to the amplifier that reduces useful headroom,especially in high gain applications.For this reason,a low-leakage tantalum or ceramic capacitor is the best choice.When polarized capacitors are used,the positive side of the capacitor should face the amplifier input in most applications as the dc level there is held at V DD /2,which is likely higher than the source dc level.Note that it is important to confirm the capacitor polarity in the application.22POWER SUPPLY DECOUPLING,C(S) MIDRAIL BYPASS CAPACITOR,C(BYP) OUTPUT COUPLING CAPACITOR,C(C)f c(high)+12p RL C(C)−3 dBf c(4)TPA6011A4SLOS392A–FEBRUARY2002–REVISED JULY2004The TPA6011A4is a high-performance CMOS audio amplifier that requires adequate power supply decoupling to ensure the output total harmonic distortion(THD)is as low as possible.Power supply decoupling also prevents oscillations for long lead lengths between the amplifier and the speaker.The optimum decoupling is achieved by using two capacitors of different types that target different types of noise on the power supply leads.For higher frequency transients,spikes,or digital hash on the line,a good low equivalent-series-resistance(ESR)ceramic capacitor,typically0.1µF placed as close as possible to the device V DD lead,works best.For filtering lower-frequency noise signals,a larger aluminum electrolytic capacitor of10µF or greater placed near the audio power amplifier is recommended.The midrail bypass capacitor(C(BYP))is the most critical capacitor and serves several important functions.During start-up or recovery from shutdown mode,C(BYP)determines the rate at which the amplifier starts up.The second function is to reduce noise produced by the power supply caused by coupling into the output drive signal.This noise is from the midrail generation circuit internal to the amplifier,which appears as degraded PSRR and THD+N.Bypass capacitor(C(BYP))values of0.47-µF to1-µF ceramic or tantalum low-ESR capacitors are recommended for the best THD and noise performance.For the best pop performance,choose a value for C(BYP)that is equal to or greater than the value chosen for C i.This ensures that the input capacitors are charged up to the midrail voltage before C(BYP)is fully charged to the midrail voltage.In the typical single-supply SE configuration,an output coupling capacitor(C(C))is required to block the dc bias at the output of the amplifier,thus preventing dc currents in the load.As with the input coupling capacitor,the output coupling capacitor and impedance of the load form a high-pass filter governed by Equation4.The main disadvantage,from a performance standpoint,is the load impedances are typically small,which drives the low-frequency corner higher,degrading the bass rge values of C(C)are required to pass low frequencies into the load.Consider the example where a C(C)of330µF is chosen and loads vary from3Ω,4Ω, 8Ω,32Ω,10kΩ,and47kΩ.Table4summarizes the frequency response characteristics of each configuration.mon Load Impedances vs Low FrequencyOutput Characteristics in SE ModeLOWESTR L C(C)FREQUENCY3Ω330µF161Hz4Ω330µF120Hz8Ω330µF60Hz32Ω330µF15Hz10,000Ω330µF0.05Hz47,000Ω330µF0.01Hz23。

IC datasheet pdf-CD54ACT109, CD74ACT109,pdf(DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS)

CD54ACT109, CD74ACT109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPSWITH CLEAR AND PRESETCD54ACT109, CD74ACT109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPSWITH CLEAR AND PRESETCD54ACT109, CD74ACT109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPSWITH CLEAR AND PRESETIMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries(TI)reserve the right to make corrections,modifications,enhancements, improvements,and other changes to its products and services at any time and to discontinue any product or service without notice. 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Following are URLs where you can obtain information on other Texas Instruments products and application solutions:Products ApplicationsAmplifiers AudioData Converters AutomotiveDSP BroadbandInterface Digital ControlLogic MilitaryPower Mgmt Optical NetworkingMicrocontrollers SecurityLow Power TelephonyWirelessVideo&ImagingWirelessMailing Address:Texas Instruments,Post Office Box655303,Dallas,Texas75265Copyright©2007,Texas Instruments IncorporatedPACKAGING INFORMATION Orderable DeviceStatus (1)Package Type Package Drawing Pins Package Qty Eco Plan (2)Lead/Ball Finish MSL Peak Temp (3)CD54ACT109F3AACTIVE CDIP J 161TBD A42N /A for Pkg Type CD74ACT109EACTIVE PDIP N 1625Pb-Free (RoHS)CU NIPDAU N /A for Pkg Type CD74ACT109EE4ACTIVE PDIP N 1625Pb-Free (RoHS)CU NIPDAU N /A for Pkg Type CD74ACT109MACTIVE SOIC D 1640Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM CD74ACT109M96ACTIVE SOIC D 162500Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM CD74ACT109M96E4ACTIVE SOIC D 162500Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM CD74ACT109M96G4ACTIVE SOIC D 162500Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM CD74ACT109ME4ACTIVE SOIC D 1640Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM CD74ACT109MG4ACTIVE SOIC D 1640Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM (1)The marketing status values are defined as follows:ACTIVE:Product device recommended for new designs.LIFEBUY:TI has announced that the device will be discontinued,and a lifetime-buy period is in effect.NRND:Not recommended for new designs.Device is in production to support existing customers,but TI does not recommend using this part in a new design.PREVIEW:Device has been announced but is not in production.Samples may or may not be available.OBSOLETE:TI has discontinued the production of the device.(2)Eco Plan -The planned eco-friendly classification:Pb-Free (RoHS),Pb-Free (RoHS Exempt),or Green (RoHS &no Sb/Br)-please check /productcontent for the latest availability information and additional product content details.TBD:The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS):TI's terms "Lead-Free"or "Pb-Free"mean semiconductor products that are compatible with the current RoHS requirements for all 6substances,including the requirement that lead not exceed 0.1%by weight in homogeneous materials.Where designed to be soldered at high temperatures,TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free (RoHS Exempt):This component has a RoHS exemptionfor either 1)lead-based flip-chip solder bumps used between the die and package,or 2)lead-based die adhesive used between the die and leadframe.The component is otherwise considered Pb-Free (RoHS compatible)as defined above.Green (RoHS &no Sb/Br):TI defines "Green"to mean Pb-Free (RoHS compatible),and free of Bromine (Br)and Antimony (Sb)based flame retardants (Br or Sb do not exceed 0.1%by weight in homogeneous material)(3)MSL,Peak Temp.--The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications,and peak solder temperature.Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.TI bases its knowledge and belief on information provided by third parties,and makes no representation or warranty as to the accuracy of such information.Efforts are underway to better integrate information from third parties.TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary,and thus CAS numbers and other limited information may not be available for release.In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s)at issue in this document sold by TI to Customer on an annual basis.PACKAGE OPTION ADDENDUM 15-Oct-2009TAPE AND REEL INFORMATION*All dimensions are nominal Device Package Type Package DrawingPinsSPQ Reel Diameter (mm)Reel Width W1(mm)A0(mm)B0(mm)K0(mm)P1(mm)W (mm)Pin1Quadrant CD74ACT109M96SOIC D 162500330.016.4 6.510.3 2.18.016.0Q1*All dimensions are nominalDevice Package Type Package Drawing Pins SPQ Length(mm)Width(mm)Height(mm) CD74ACT109M96SOIC D162500333.2345.928.6IMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries(TI)reserve the right to make corrections,modifications,enhancements,improvements, and other changes to its products and services at any time and to discontinue any product or service without notice.Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty.Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty.Except where mandated by government requirements,testing of all parameters of each product is not necessarily performed.TI assumes no liability for applications assistance or customer product design.Customers are responsible for their products and applications using TI components.To minimize the risks associated with customer products and applications,customers should provide adequate design and operating safeguards.TI does not warrant or represent that any license,either express or implied,is granted under any TI patent right,copyright,mask work right, or other TI intellectual property right relating to any combination,machine,or process in which TI products or services are rmation published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement e of such information may require a license from a third party under the patents or other intellectual property of the third party,or a license from TI under the patents or other intellectual property of TI.Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties,conditions,limitations,and notices.Reproduction of this information with alteration is an unfair and deceptive business practice.TI is not responsible or liable for such altered rmation of third parties may be subject to additional restrictions.Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice.TI is not responsible or liable for any such statements.TI products are not authorized for use in safety-critical applications(such as life support)where a failure of the TI product would reasonably be expected to cause severe personal injury or death,unless officers of the parties have executed an agreement specifically governing such use.Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications,and acknowledge and agree that they are solely responsible for all legal,regulatory and safety-related requirements concerning their products and any use of TI products in such safety-critical applications,notwithstanding any applications-related information or support that may be provided by TI.Further,Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in such safety-critical applications.TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are specifically designated by TI as military-grade or"enhanced plastic."Only products designated by TI as military-grade meet military specifications.Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at the Buyer's risk,and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are designated by TI as compliant with ISO/TS16949requirements.Buyers acknowledge and agree that,if they use any non-designated products in automotive applications,TI will not be responsible for any failure to meet such requirements.Following are URLs where you can obtain information on other Texas Instruments products and application solutions:Products ApplicationsAmplifiers AudioData Converters AutomotiveDLP®Products BroadbandDSP Digital ControlClocks and Timers MedicalInterface MilitaryLogic Optical NetworkingPower Mgmt SecurityMicrocontrollers TelephonyRFID Video&ImagingRF/IF and ZigBee®Solutions WirelessMailing Address:Texas Instruments,Post Office Box655303,Dallas,Texas75265Copyright©2009,Texas Instruments Incorporated。

IC datasheet pdf-CD74AC10,pdf(TRIPLE 3-INPUT POSITIVE-NAND GATES)

TRIPLE 3-INPUT POSITIVE-NAND GATESTRIPLE 3-INPUT POSITIVE-NAND GATESTRIPLE 3-INPUT POSITIVE-NAND GATESIMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries(TI)reserve the right to make corrections,modifications,enhancements, improvements,and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty.Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty.Except where mandated by government requirements,testing of all parameters of each product is not necessarily performed.TI assumes no liability for applications assistance or customer product design.Customers are responsible for their products and applications using TI components.To minimize the risks associated with customer products and applications,customers should provide adequate design and operating safeguards.TI does not warrant or represent that any license,either express or implied,is granted under any TI patent right,copyright,mask work right,or other TI intellectual property right relating to any combination,machine,or process in which TI products or services are rmation published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement e of such information may require a license from a third party under the patents or other intellectual property of the third party,or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties,conditions,limitations,and notices.Reproduction of this information with alteration is an unfair and deceptive business practice.TI is not responsible or liable for such altered documentation.Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice.TI is not responsible or liable for any such statements.TI products are not authorized for use in safety-critical applications(such as life support)where a failure of the TI product would reasonably be expected to cause severe personal injury or death,unless officers of the parties have executed an agreement specifically governing such use.Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications,and acknowledge and agree that they are solely responsible for all legal,regulatory and safety-related requirements concerning their products and any use of TI products in such safety-critical applications,notwithstanding any applications-related information or support that may be provided by TI.Further,Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in such safety-critical applications.TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are specifically designated by TI as military-grade or"enhanced plastic."Only products designated by TI as military-grade meet military specifications.Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at the Buyer's risk,and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are designated by TI as compliant with ISO/TS16949requirements.Buyers acknowledge and agree that,if they use anynon-designated products in automotive applications,TI will not be responsible for any failure to meet such requirements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions:Products ApplicationsAmplifiers AudioData Converters AutomotiveDSP BroadbandInterface Digital ControlLogic MilitaryPower Mgmt Optical NetworkingMicrocontrollers SecurityLow Power TelephonyWirelessVideo&ImagingWirelessMailing Address:Texas Instruments,Post Office Box655303,Dallas,Texas75265Copyright©2007,Texas Instruments IncorporatedPACKAGING INFORMATION Orderable DeviceStatus (1)Package Type Package Drawing Pins Package Qty Eco Plan (2)Lead/Ball Finish MSL Peak Temp (3)CD74AC10EACTIVE PDIP N 1425Pb-Free (RoHS)CU NIPDAU N /A for Pkg Type CD74AC10EE4ACTIVE PDIP N 1425Pb-Free (RoHS)CU NIPDAU N /A for Pkg Type CD74AC10MACTIVE SOIC D 1450Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM CD74AC10M96ACTIVE SOIC D 142500Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM CD74AC10M96E4ACTIVE SOIC D 142500Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM CD74AC10M96G4ACTIVE SOIC D 142500Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM CD74AC10ME4ACTIVE SOIC D 1450Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM CD74AC10MG4ACTIVE SOIC D 1450Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM (1)The marketing status values are defined as follows:ACTIVE:Product device recommended for new designs.LIFEBUY:TI has announced that the device will be discontinued,and a lifetime-buy period is in effect.NRND:Not recommended for new designs.Device is in production to support existing customers,but TI does not recommend using this part in a new design.PREVIEW:Device has been announced but is not in production.Samples may or may not be available.OBSOLETE:TI has discontinued the production of the device.(2)Eco Plan -The planned eco-friendly classification:Pb-Free (RoHS),Pb-Free (RoHS Exempt),or Green (RoHS &no Sb/Br)-please check /productcontent for the latest availability information and additional product content details.TBD:The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS):TI's terms "Lead-Free"or "Pb-Free"mean semiconductor products that are compatible with the current RoHS requirements for all 6substances,including the requirement that lead not exceed 0.1%by weight in homogeneous materials.Where designed to be soldered at high temperatures,TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1)lead-based flip-chip solder bumps used between the die and package,or 2)lead-based die adhesive used between the die and leadframe.The component is otherwise considered Pb-Free (RoHS compatible)as defined above.Green (RoHS &no Sb/Br):TI defines "Green"to mean Pb-Free (RoHS compatible),and free of Bromine (Br)and Antimony (Sb)based flame retardants (Br or Sb do not exceed 0.1%by weight in homogeneous material)(3)MSL,Peak Temp.--The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications,and peak solder temperature.Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.TI bases its knowledge and belief on information provided by third parties,and makes no representation or warranty as to the accuracy of such information.Efforts are underway to better integrate information from third parties.TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary,and thus CAS numbers and other limited information may not be available for release.In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s)at issue in this document sold by TI to Customer on an annual basis.PACKAGE OPTION ADDENDUM 23-Apr-2007TAPE AND REEL INFORMATION*All dimensions are nominal Device Package Type Package DrawingPinsSPQ Reel Diameter (mm)Reel Width W1(mm)A0(mm)B0(mm)K0(mm)P1(mm)W (mm)Pin1Quadrant CD74AC10M96SOIC D 142500330.016.4 6.59.0 2.18.016.0Q1*All dimensions are nominalDevice Package Type Package Drawing Pins SPQ Length(mm)Width(mm)Height(mm) CD74AC10M96SOIC D142500346.0346.033.0IMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries(TI)reserve the right to make corrections,modifications,enhancements,improvements, and other changes to its products and services at any time and to discontinue any product or service without notice.Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty.Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty.Except where mandated by government requirements,testing of all parameters of each product is not necessarily performed.TI assumes no liability for applications assistance or customer product design.Customers are responsible for their products and applications using TI components.To minimize the risks associated with customer products and applications,customers should provide adequate design and operating safeguards.TI does not warrant or represent that any license,either express or implied,is granted under any TI patent right,copyright,mask work right, or other TI intellectual property right relating to any combination,machine,or process in which TI products or services are rmation published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement e of such information may require a license from a third party under the patents or other intellectual property of the third party,or a license from TI under the patents or other intellectual property of TI.Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties,conditions,limitations,and notices.Reproduction of this information with alteration is an unfair and deceptive business practice.TI is not responsible or liable for such altered rmation of third parties may be subject to additional restrictions.Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice.TI is not responsible or liable for any such statements.TI products are not authorized for use in safety-critical applications(such as life support)where a failure of the TI product would reasonably be expected to cause severe personal injury or death,unless officers of the parties have executed an agreement specifically governing such use.Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications,and acknowledge and agree that they are solely responsible for all legal,regulatory and safety-related requirements concerning their products and any use of TI products in such safety-critical applications,notwithstanding any applications-related information or support that may be provided by TI.Further,Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in such safety-critical applications.TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are specifically designated by TI as military-grade or"enhanced plastic."Only products designated by TI as military-grade meet military specifications.Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at the Buyer's risk,and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are designated by TI as compliant with ISO/TS16949requirements.Buyers acknowledge and agree that,if they use any non-designated products in automotive applications,TI will not be responsible for any failure to meet such requirements.Following are URLs where you can obtain information on other Texas Instruments products and application solutions:Products ApplicationsAmplifiers AudioData Converters AutomotiveDLP®Products BroadbandDSP Digital ControlClocks and Timers MedicalInterface MilitaryLogic Optical NetworkingPower Mgmt SecurityMicrocontrollers TelephonyRFID Video&ImagingRF/IF and ZigBee®Solutions WirelessMailing Address:Texas Instruments,Post Office Box655303,Dallas,Texas75265Copyright©2009,Texas Instruments Incorporated。

74AC273、74ACT273Octal D-Type Flip-Flop说明书

74AC273, 74ACT273 — Octal D-Type Flip-FlopOctal D-Type Flip-FlopFeatures■ Ideal buffer for microprocessor or memory ■ Eight edge-triggered D-type flip-flops ■ Buffered common clock■ Buffered, asynchronous master reset ■ See 377 for clock enable version ■ See 373 for transparent latch version ■ See 374 for 3-STATE version ■ Outputs source/sink 24mA■ 74ACT273 has TTL-compatible inputsGeneral DescriptionThe AC273 and ACT273 have eight edge-triggered D-type flip-flops with individual D-type inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR) input load and reset (clear) all flip-flops simultaneously.The register is fully edge-triggered. The state of each D-type input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop's Q output.All outputs will be forced LOW independently of Clock or Data inputs by a LOW voltage level on the MR input. The device is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements.Ordering InformationDevice also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.All packages are lead free per JEDEC: J-STD-020B standard.Order NumberPackage NumberPackage Description74AC273SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 74AC273SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide74AC273MTC MTC2020-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide74AC273PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide 74ACT273SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 74ACT273SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide74ACT273MTCMTC2020-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide74AC273, 74ACT273 — Octal D-Type Flip-FlopPin DescriptionIEEE/IECMode Select-Function TableH = HIGH Voltage Level L = LOW Voltage Level X = Immaterial= LOW-to-HIGH TransitionLogic DiagramPin NamesDescriptionD 0 –D 7 Data Inputs MR Master Reset CP Clock Pulse Input Q 0 –Q 7Data OutputsOperating ModeInputsOutputs MRCPD nQ nReset (Clear)L XX L Load ‘1'H H H Load ‘0'HLL74AC273, 74ACT273 — Octal D-Type Flip-FlopRecommended Operating ConditionsThe Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings.V CC Supply Voltage –0.5V to +7.0VI IKDC Input Diode Current V I = –0.5V –20mA V I = V CC + 0.5+20mAV I DC Input Voltage –0.5V to V CC + 0.5VI OKDC Output Diode Current V O = –0.5V –20mA V O = V CC + 0.5V+20mAV O DC Output Voltage–0.5V to V CC + 0.5VI O DC Output Source or Sink Current ±50mA I CC or I GND DC V CC or Ground Current per Output Pin±50mAT STG Storage Temperature –65°C to +150°CT JJunction Temperature140°CSymbol ParameterRatingV CCSupply Voltage AC 2.0V to 6.0V ACT4.5V to5.5V V I Input Voltage 0V to V CC V O Output Voltage 0V to V CCT A Operating Temperature–40°C to +85°C∆ V / ∆ t Minimum Input Edge Rate, AC Devices:V IN from 30% to 70% of V CC , V CC @ 3.3V , 4.5V , 5.5V 125mV/ns ∆ V / ∆ tMinimum Input Edge Rate, ACT Devices: V IN from 0.8V to 2.0V , V CC@ 4.5V , 5.5V125mV/ns74AC273, 74ACT273 — Octal D-Type Flip-FlopNotes:1.All outputs loaded; thresholds on input associated with output under test.2.I IN and I CC @************************************************************** CC .3.Maximum test duration 2.0ms, one output loaded at a time.4.5 2.25 3.15 3.155.5 2.75 3.85 3.85V ILMaximum LOW Level Input Voltage3.0V OUT = 0.1V or V CC – 0.1V1.50.90.9V4.5 2.25 1.35 1.355.5 2.75 1.65 1.65V OHMinimum HIGH Level Output Voltage3.0I OUT = –50µA2.99 2.9 2.9V 4.5 4.49 4.4 4.45.5 5.495.4 5.43.0V IN = V IL or V IH ,I OH = –12mA 2.56 2.464.5V IN = V IL or V IH ,I OH = –24mA 3.86 3.765.5V IN = V IL or V IH ,I OH = –24mA (1) 4.864.76V OLMaximum LOW Level Output Voltage3.0I OUT = 50µA0.0020.10.1V 4.50.0010.10.15.50.0010.10.13.0V IN = V IL or V IH ,I OL = 12mA 0.360.444.5V IN = V IL or V IH,I OL = 24mA 0.360.445.5V IN = V IL or V IH ,I OL = 24mA (1)0.360.44I IN (2)Maximum Input Leakage Current 5.5V I = V CC , GND ±0.1±1.0µA I OLD Minimum Dynamic Output Current (3) 5.5V OLD = 1.65V Max.75mA I OHD 5.5V OHD = 3.85V Min.–75mA I CC (2)Maximum Quiescent Supply Current5.5V IN = V CC or GND4.040.0µANotes:4.All outputs loaded; thresholds on input associated with output under test.5.Maximum test duration 2.0ms, one output loaded at a time.I OL = 24mA 5.5V IN = V IL or V IH ,I OL = 24mA (4)0.360.44I IN Maximum Input Leakage Current 5.5V I = V CC , GND ±0.1±1.0µA I CCT Maximum I CC /Input 5.5V I = V CC – 2.1V 0.61.5mA I OLD Minimum Dynamic Output Current (5) 5.5V OLD = 1.65V Max.75mA I OHD 5.5V OHD = 3.85V Min.–75mA I CCMaximum Quiescent Supply Current5.5V IN = V CC or GND4.040.0µANote:7.Voltage range 3.3 is 3.3V ± 0.3V. Voltage range 5.0 is 5.0V ± 0.5V.SymbolParameterV CC (V)(7)T A = +25°C,C L = 50pFT A = –40°C to +85°C,C L = 50pFUnitsTyp.Guaranteed Minimumt S Setup Time, HIGH or LOW, Data to CP3.3 3.5 5.5 6.0ns 5.0 2.54.0 4.5t H Hold Time, HIGH or LOW, Data to CP3.3–2.000ns 5.0–1.0 1.0 1.0t W Clock Pulse Width, HIGH or LOW 3.3 3.5 5.5 6.0ns 5.0 2.54.0 4.5t W MR Pulse Width, HIGH or LOW 3.3 2.05.56.0ns 5.0 1.5 4.0 4.5t recRecovery Time, MR to CP3.3 1.5 3.54.5ns5.01.02.03.0Note:9.Voltage range 5.0 is 5.0V ± 0.5V.CapacitanceSymbolParameterV CC (V)UnitsTyp.Guaranteed Minimumt S Setup Time, HIGH or LOW, D n to CP5.0 1.0 3.5 3.5ns t H Hold Time, HIGH or LOW, D n to CP5.0–0.5 1.5 1.5ns t W Clock Pulse Width, HIGH or LOW 5.0 2.0 4.0 4.0ns t W MR Pulse Width, HIGH or LOW 5.0 1.5 4.0 4.0ns t WRecovery Time, MR to CP5.00.53.03.0nsSymbolParameterConditionsTyp.UnitsC IN Input CapacitanceV CC = OPEN 4.5pF C PDPower Dissipation Capacitance for AC V CC = 5.0V50.0pFPower Dissipation Capacitance for ACT40.0Figure 1. 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" WidePackage drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package speciﬁcations do not expand the terms of Fairchild’s worldwide terms and conditions, speciﬁcally the warranty therein, which covers Fairchild products.Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:/packaging/0.10CCSEE DETAIL ANOTES:UNLESS OTHERWISE SPECIFIEDA)THIS PACKAGE CONFORMS TO JEDEC MS-013,VARIATION AC,ISSUE EB)ALL DIMENSIONS ARE IN MILLIMETERS.C)DIMENSIONS DO NOT INCLUDE MOLDFLASH OR BURRS.E)LANDPATTERN STANDARD:SOIC127P1030X265-20L X 45°8°0°SEATING PLANEGAGE PLANEDETAIL ASCALE:2:1SEATING PLANEF)DRAWING FILENAME:MKT-M20BREV32.65MAX0.300.100.330.200.750.25(R0.10)(R0.10) 1.270.40(1.40)0.25D)CONFORMS TO ASME Y14.5M-1994Figure 2. 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm WidePackage drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package speciﬁcations do not expand the terms of Fairchild’s worldwide terms and conditions,Figure 3. 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm WidePackage drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package speciﬁcations do not expand the terms of Fairchild’s worldwide terms and conditions,74AC273, 74ACT273 — Octal D-Type Flip-FlopFigure 4. 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" WidePackage drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package speciﬁcations do not expand the terms of Fairchild’s worldwide terms and conditions, speciﬁcally the warranty therein, which covers Fairchild products.Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:.001[.025]C7°TYP7°TYP10.92MAX7.116.091.781.142.547.627.873.433.175.33MAX3.553.170.38MIN0.360.560.200.35PIN #1NOTES:(0.97)subsidiaries,and is not intended to be an exhaustive list of all such trademarks.ACEx ®Build it Now ™CorePLUS ™CROSSVOLT ™CTL™Current Transfer Logic™EcoSPARK ®EZSWITCH™*™®Fairchild®Fairchild Semiconductor ®FACT Quiet Series™FACT ®FAST ®FastvCore ™FlashWriter ®*FPS ™FRFET ®Global Power Resource SM Green FPS ™Green FPS ™e-Series ™GTO ™i-Lo ™IntelliMAX ™ISOPLANAR ™MegaBuck™MICROCOUPLER ™MicroFET ™MicroPak ™MillerDrive™Motion-SPM™OPTOLOGIC ®OPTOPLANAR ®®PDP-SPM™Power220®Power247®POWEREDGE ®Power-SPM ™PowerTrench ®Programmable Active Droop ™QFET ®QS ™QT Optoelectronics ™Quiet Series ™RapidConfigure ™SMART START ™SPM ®STEALTH™SuperFET ™SuperSOT ™-3SuperSOT ™-6SuperSOT ™-8SyncFET™®The Power Franchise ®TinyBoost ™TinyBuck ™TinyLogic ®TINYOPTO ™TinyPower ™TinyPWM ™TinyWire ™µSerDes ™UHC ®Ultra FRFET ™UniFET ™VCX ™*EZSWITCH™and FlashWriter ®are trademarks of System General Corporation,used under license by Fairchild Semiconductor.DISCLAIMERFAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY,FUNCTION,OR DESIGN.FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS,NOR THE RIGHTS OF OTHERS.THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS,SPECIFICALLY THE WARRANTY THEREIN,WHICH COVERS THESE PRODUCTS.LIFE SUPPORT POLICYFAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.As used herein:1.Life support devices or systems are devices or systems which,(a)are intended for surgical implant into the body or (b)support or sustain life,and (c)whose failure to perform when properly used in accordance with instructions for use provided in the labeling,can be reasonably expected to result in a significant injury of the user.2.A critical component in any component of a life support,device,or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system,or to affect its safety or effectiveness.PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status DefinitionAdvance InformationForm First Productionative or In DesignThis datasheet contains the design specifications for productdevelopment.Specifications may change in any manner without notice.PreliminaryThis datasheet contains preliminary data;supplementary data will be published at a later date.Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design.74AC273, 74ACT273 — Octal D-Type Flip-Flop。

HD74BC540AFP资料

HD74BC540AOctal Buffers/Line Drivers With 3 State OutputsADE-205-031 (Z)1st. EditionJan. 1993 DescriptionThe HD74BC540A provides high drivability and operation equal to or better than high speed bipolar standard logic IC by using Bi-CMOS process. The device features low power dissipation that is about 1/5 of high speed bipolar logic IC, when the frequency is 10 MHz. The device has eight inverter drivers with three state outputs in a 20 pin package. When G1 and G2 is low level, this drivers set up output is enable. Features• Input/Output are at high impedance state when power supply is off.• Built in input pull up circuit can make input pins be open, when not used.• Input is TTL level.• Wide operating temperature rangeTa = –40 to +85°CFunction TableInputsG1G2A Output YL L L HL L H LH X X ZX H X ZH:High levelL:Low levelX:ImmaterialZ:High impedanceHD74BC540A2Pin ArrangementAbsolute Maximum RatingsItemSymbol Rating Unit Supply voltage V CC –0.5 to +7.0V Input diode current I IK ±30mA Input voltage V IN –0.5 to +7.5V Output voltage V OUT –0.5 to +7.5V Off state output voltage V OUT(off)–0.5 to +5.5V Storage temperature Tstg–65 to +150°CNote:1.The absolute maximum ratings are values which must not individually be exceeded, andfurthermore, no two of which may be realized at the same time.HD74BC540A3Recommended Operating ConditionsItemSymbol Min Typ Max Unit Supply voltage V CC 4.5 5.0 5.5V Input voltage V IN 0—V CC V Ouput voltage V OUT 0—V CC V Operating temperature Topr –40—85°C Input rise/fall time*1t r , t f—8ns/VNote:1.This item guarantees maximum limit when one input switches.Waveform: Refer to test circuit of switching characteristics.Logic DiagramHD74BC540A4Electrical Characteristics (Ta = –40 to +85°C)Item Symbol V CC (V)Min Max Unit Test ConditionsInput voltage V IH 2.0—V V IL —0.8V Output voltageV OH 4.5 2.4—V I OH = –3 mA 4.5 2.0—V I OH = –15 mA V OL4.5—0.5V I OL = 48 mA 4.5—0.55V I OL = 64 mA Input diode voltage V IK 4.5—–1.2V I IN = –18 mA Input currentI I5.5—–250µA V IN = 0 V 5.5— 1.0µA V IN = 5.5 V 5.5—100µA V IN = 7.0 V Short circuit output current*1I OS 5.5–100–225mA V IN = 0 or 5.5 V Off state output current I OZH 5.5—50µA V O = 2.7 V I OZL 5.5—–50µA V O = 0.5 V Supply currentI CCL 5.5—27.5mA V IN = 0 or 5.5 V All outputs is “L”I CCH 5.5— 2.5mA V IN = 0 or 5.5 V All outputs is “H”I CCZ 5.5— 2.5mA V IN = 0 or 5.5 V All outputs is “Z”I CCT *25.5—1.5mAV IN = 3.4V or 0.5V Notes: 1.Not more than one output should be shorted at a time and duration of the short circuit should notexceed one second.2.When input by the TTL level, it shows I CC increase at per one input pin.HD74BC540A5Switching Characteristics (C L = 50 pF)Ta = 25°C V CC = 5.0 VTa = –40 to +85°C V CC = 5.0 V ±10ItemSymbol Min Max Min Max Unit Test Conditions Propagation delay time t PLH 3.0 6.0 3.07.0nsSee under figuret PHL 3.0 6.0 3.07.0Output enable time t ZH 3.09.0 3.011.0ns t ZL 3.09.0 3.011.0Output disable time t HZ 3.08.0 3.010.0ns t LZ 3.08.03.010.0Input capacitance C IN 3.0(Typ)—pF V IN = V CC or GND Output capacitanceC O15.0(Typ)—pFV O = V CC or GNDTest circuitHD74BC540A Waveforms-1Waveforms-26HD74BC540A Package Dimensions7HD74BC540A8HD74BC540A9Cautions1.Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,copyright, trademark, or other intellectual property rights for information contained in this document.Hitachi bears no responsibility for problems that may arise with third party’s rights, includingintellectual property rights, in connection with use of the information contained in this document.2.Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use.3.Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,contact Hitachi’s sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,traffic, safety equipment or medical equipment for life support.4.Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installationconditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product.5.This product is not designed to be radiation resistant.6.No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi.7.Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor products.Hitachi, Ltd.Semiconductor & Integrated Circuits.Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109Copyright © Hitachi, Ltd., 2000. All rights reserved. Printed in Japan.Hitachi Asia Ltd. Hitachi Tower16 Collyer Quay #20-00, Singapore 049318Tel : <65>-538-6533/538-8577 Fax : <65>-538-6933/538-3877URL : .sg URLNorthAmerica : /Europe : /hel/ecg Asia : Japan : http://www.hitachi.co.jp/Sicd/indx.htmHitachi Asia Ltd.(Taipei Branch Office)4/F, No. 167, Tun Hwa North Road, Hung-Kuo Building, Taipei (105), Taiwan Tel : <886>-(2)-2718-3666 Fax : <886>-(2)-2718-8180 Telex : 23222 HAS-TPURL : Hitachi Asia (Hong Kong) Ltd. Group III (Electronic Components) 7/F., North Tower, World Finance Centre,Harbour City, Canton Road Tsim Sha Tsui, Kowloon, Hong KongTel : <852>-(2)-735-9218 Fax : <852>-(2)-730-0281URL : Hitachi Europe Ltd.Electronic Components Group.Whitebrook ParkLower Cookham Road MaidenheadBerkshire SL6 8YA, United Kingdom Tel: <44> (1628) 585000Fax: <44> (1628) 585160Hitachi Europe GmbHElectronic Components Group Dornacher Stra βe 3D-85622 Feldkirchen, Munich GermanyTel: <49> (89) 9 9180-0Fax: <49> (89) 9 29 30 00Hitachi Semiconductor (America) Inc.179 East Tasman Drive,San Jose,CA 95134 Tel: <1> (408) 433-1990Fax: <1>(408) 433-0223For further information write to:Colophon 2.0。

MC74LCX540DTR2资料

MC74LCX540Low−Voltage CMOSOctal BufferFlow Through PinoutWith 5 V−Tolerant Inputs and Outputs(3−State, Inverting)The MC74LCX540 is a high performance, inverting octal buffer operating from a 2.3 to 3.6 V supply. This device is similar in function to the MC74LCX240, while providing flow through architecture. High impedance TTL compatible inputs significantly reduce current loading to input drivers while TTL compatible outputs offer improved switching noise performance. A V I specification of 5.5 V allows MC74LCX540 inputs to be safely driven from 5 V devices. The MC74LCX540 is suitable for memory address driving and all TTL level bus oriented transceiver applications.Current drive capability is 24 mA at the outputs. The Output Enable (OE1, OE2) inputs, when HIGH, disables the outputs by placing them in a HIGH Z condition.Features•Designed for 2.3 to 3.6 V V CC Operation•5 V Tolerant − Interface Capability With 5 V TTL Logic •Supports Live Insertion and Withdrawal•I OFF Specification Guarantees High Impedance When V CC = 0 V •L VTTL Compatible•L VCMOS Compatible•24 mA Balanced Output Sink and Source Capability•Near Zero Static Supply Current in All Three Logic States (10 m A) Substantially Reduces System Power Requirements•Latchup Performance Exceeds 500 mA•ESD Performance:Human Body Model >2000 VMachine Model >200 V•Pb−Free Packages are Available**For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.See detailed ordering and shipping information in the package dimensions section on page 3 of this data sheet.ORDERING INFORMATIONO0 O1O2O3O4O5O6O7 TRUTH TABLEH = High Voltage LevelL = Low Voltage LevelZ = High Impedance StateX = High or Low Voltage Level and Transitions are AcceptableFor I CC reasons, DO NOT FLOAT InputsMAXIMUM RATINGSvalues (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected.1.Output in HIGH or LOW State. I O absolute maximum rating must be observed.RECOMMENDED OPERATING CONDITIONSORDERING INFORMATIONSpecifications Brochure, BRD8011/D.*This package is inherently Pb−Free.DC ELECTRICAL CHARACTERISTICSIAC CHARACTERISTICS (t = t = 2.5ns; C = 50pF; R = 500W)The specification applies to any outputs switching in the same direction, either HIGH−to−LOW (t OSHL) or LOW−to−HIGH (t OSLH); parameter guaranteed by design.DYNAMIC SWITCHING CHARACTERISTICSmeasured in the LOW state.CAPACITIVE CHARACTERISTICSWAVEFORM 1 − PROPAGATION DELAYS t R = t F = 2.5 ns, 10% to 90%; f = 1 MHz; t W = 500 ns2.7 V0 VV OHV OLDnOnWAVEFORM 2 − OUTPUT ENABLE AND DISABLE TIMES t R = t F = 2.5 ns, 10% to 90%; f = 1 MHz; t W = 500 ns2.7 V0 V ≈ 0 VOEnOn≈ 3.0 VOnFigure 3. AC WaveformsV CCV OH − 0.3 V V OL + 0.3 V GNDOPEN6 V GNDC L = 50 pF or equivalent (Includes jig and probe capacitance)R L = R 1 = 500 W or equivalentR T = Z OUT of pulse generator (typically 50 W )Figure 4. Test CircuitPACKAGE DIMENSIONSSOIC−20DW SUFFIX CASE 751D−05ISSUE GTSSOP−20DT SUFFIX CASE 948E−02ISSUE BDIM A MIN MAX MIN MAX INCHES 6.600.260MILLIMETERS B 4.30 4.500.1690.177C 1.200.047D 0.050.150.0020.006F 0.500.750.0200.030G 0.65 BSC 0.026 BSC H 0.270.370.0110.015J 0.090.200.0040.008J10.090.160.0040.006K 0.190.300.0070.012K10.190.250.0070.010L 6.40 BSC 0.252 BSCM0 8 0 8 ____1.DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.2.CONTROLLING DIMENSION:MILLIMETER.3.DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE.4.DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION.INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE.5.DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08(0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION.6.TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY .7.DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−.6.400.252−−−−−−PACKAGE DIMENSIONSSOEIAJ−20M SUFFIX CASE 967−01ISSUE ODIM MIN MAX MIN MAX INCHES−−− 2.05−−−0.081MILLIMETERS 0.050.200.0020.0080.350.500.0140.0200.180.270.0070.01112.3512.800.4860.5045.10 5.450.2010.2151.27 BSC 0.050 BSC 7.408.200.2910.3230.500.850.0200.0331.10 1.500.0430.0590 0.700.900.0280.035−−−0.81−−−0.032A 1H E Q 1L E _10 _0 _10 _NOTES:1.DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.2.CONTROLLING DIMENSION: MILLIMETER.3.DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH ORPROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)PER SIDE.4.TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY.5.THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003)TOTAL IN EXCESS OF THE LEAD WIDTHDIMENSION AT MAXIMUM MATERIAL CONDITION.DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACEBETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018).A b c D E e L M ZON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.PUBLICATION ORDERING INFORMATION。