GS88136BT-200中文资料

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GS8640V18GT-167中文资料

GS8640V18/32/36T-300/250/200/1674M x 18, 2M x 32, 2M x 3672Mb Sync Burst SRAMs 300 MHz –167 MHz1.8 V V DD 1.8 V I/O100-Pin TQFP Commercial Temp Industrial Temp Features• FT pin for user-configurable flow through or pipeline operation• Single Cycle Deselect (SCD) operation • 1.8 V +10%/–10% core power supply • 1.8 V I/O supply• LBO pin for Linear or Interleaved Burst mode• Internal input resistors on mode pins allow floating mode pins • Default to Interleaved Pipeline mode• Byte Write (BW) and/or Global Write (GW) operation • Internal self-timed write cycle• Automatic power-down for portable applications • JEDEC-standard 100-lead TQFP package • Pb-Free 100-lead TQFP package availableFunctional DescriptionApplicationsThe GS8640V18/32/36T is a 75,497,472-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support. ControlsAddresses, data I/Os, chip enables (E1, E2, E3), address burst control inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive-edge-triggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burstcycles can be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by ADV. The burst address counter may be configured to count in either linear orinterleave order with the Linear Burst Order (LBO) input. The Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance.Flow Through/Pipeline ReadsThe function of the Data Output register can be controlled by the user via the FT mode pin (Pin 14). Holding the FT mode pin low places the RAM in Flow Through mode, causing output data to bypass the Data Output Register. Holding FT high places the RAM in Pipeline mode, activating the rising-edge-triggered Data Output Register.Byte Write and Global WriteByte write operation is performed by using Byte Write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the Byte Write control inputs.Sleep ModeLow power (Sleep mode) is attained through the assertion (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode.Core and Interface VoltagesThe GS8640V18/32/36T operates on a 1.8 V power supply. All input are 1.8 V compatible. Separate output power (V DDQ ) pins are used to decouple output noise from the internal circuits and are 1.8 V compatible.Parameter Synopsis-300-250-200-167Unit Pipeline 3-1-1-1KQ tCycle 3.3 4.0 5.0 6.0ns (x18)Curr (x32/x36)480410350305mA Flow Through 2-1-1-1t KQ tCycle 5.55.5 6.56.57.57.58.08.0ns ns Curr (x18)Curr (x32/x36)285330245280220250210240mA mAGS8640V18/32/36T-300/250/200/167GS8640V18 100-Pin TQFP Pinout (Package T)807978777675747372717069686766656463626160595857565554535251123456789101112131415161718192021222324252627282930V DDQ V SS DQ B DQ B V SS V DDQ DQ B DQ B V DD NC V SS DQ B DQ B V DDQ V SS DQ B DQ B DQP BV SS V DDQ V DDQ V SS DQ A DQ A V SS V DDQ DQ A DQ A V SS NC V DD ZZ DQ A DQ A V DDQ V SS DQ A DQ A V SS V DDQ L B O A A A A A 1A 0A A V S SV D DA A A A A A A AA A E 1E 2 N C N C B BB AE 3C K G W B W VD DV S SG A D S C A D S P A D V A AA 4M x 18Top View DQP A A NC NC NC NC NC NC NC NCNC NC NC NC NC NC NCNC NC 100999897969594939291908988878685848382813132333435363738394041424344454647484950FTGS8640V18/32/36T-300/250/200/167GS8640V32 100-Pin TQFP Pinout (Package T)807978777675747372717069686766656463626160595857565554535251123456789101112131415161718192021222324252627282930V DDQ V SS DQ C DQ C V SS V DDQ DQ C DQ C V DD NC V SS DQ D DQ D V DDQ V SS DQ D DQ D DQ D V SS V DDQ V DDQ V SS DQ B DQ B V SS V DDQ DQ B DQ B V SS NC V DD ZZ DQ A DQ A V DDQ V SS DQ A DQ A V SS V DDQ L B O A A A A A 1A 0A A V S SV D DA A A A A A A AA A E 1E 2 B DB CB BB AE 3C K G W B W VD DV S SG A D S C A D S P A D V A AA 2M x 32Top View DQB NC DQ B DQ B DQ B DQ A DQ A DQ A DQ A NCDQ C DQ C DQ C DQ D DQ D DQ D NCDQ C NC 100999897969594939291908988878685848382813132333435363738394041424344454647484950FTGS8640V18/32/36T-300/250/200/167GS8640V36 100-Pin TQFP Pinout (Package T)807978777675747372717069686766656463626160595857565554535251123456789101112131415161718192021222324252627282930V DDQ V SS DQ C DQ C3V SS V DDQ DQ C DQ C V DD NC V SS DQ D DQ D V DDQ V SS DQ D DQ D DQ D V SS V DDQ V DDQ V SS DQ B DQ B V SS V DDQ DQ B DQ B V SS NC V DD ZZ DQ A DQ A V DDQ V SS DQ A DQ A V SS V DDQ L B O A A A A A 1A 0A A V S SV D DA A A A A A A AA A E 1E 2 B DB CB BB AE 3C K G W B W VD DV S SG A D S C A D S P A D V A AA 2M x 36Top View DQB DQP B DQ B DQ B DQ B DQ A DQ A DQ A DQ A DQP ADQ C DQ C DQ C DQ D DQ D DQ D DQP DDQ C DQP C 100999897969594939291908988878685848382813132333435363738394041424344454647484950GS8640V18/32/36T-300/250/200/167TQFP Pin DescriptionSymbol Type DescriptionA0, A1I Address field LSBs and Address Counter preset InputsA I Address InputsDQ ADQ BI/O Data Input and Output pinsDQ CDQ DNC No ConnectBW I Byte Write—Writes all enabled bytes; active lowB A, B B I Byte Write Enable for DQ A, DQ B Data I/Os; active lowB C, B D I Byte Write Enable for DQ C, DQ D Data I/Os; active lowCK I Clock Input Signal; active highGW I Global Write Enable—Writes all bytes; active lowE1, E3I Chip Enable; active lowE2I Chip Enable; active highG I Output Enable; active lowADV I Burst address counter advance enable; active low ADSP, ADSC I Address Strobe (Processor, Cache Controller); active low ZZ I Sleep Mode control; active highFT I Flow Through or Pipeline mode; active lowLBO I Linear Burst Order mode; active lowV DD I Core power supplyV SS I I/O and Core GroundV DDQ I Output driver power supplyGS8640V18/32/36T-300/250/200/167GS8640V18/32/36 Block DiagramA1A0A0A1D0D1Q1Q0Counter LoadD QDQRegisterRegisterDQRegisterDQRegisterDQRegisterD QRegisterD QRegisterD QRegisterDQR e g i s t e rDQRegisterA0–AnLBO ADV CK ADSC ADSP GW BW E 1GZZPower Down ControlMemory Array36364AQDE 2E 3DQx1–DQx9Note: Only x36 version shown for simplicity.B AB BB CB DFTGS8640V18/32/36T-300/250/200/167Note:There is a pull-up device on the FT pin and a pull-down device on the ZZ pin, so those input pins can be unconnected and the chip will operate in the default states as specified in the above tables.Burst Counter SequencesBPR 1999.05.18Mode Pin FunctionsMode NamePin NameStateFunctionBurst Order Control LBO L Linear Burst H Interleaved Burst Output Register Control FT L Flow Through H or NC Pipeline Power Down ControlZZL or NC Active HStandby, I DD = I SBNote:The burst counter wraps to initial state on the 5th clock.Note:The burst counter wraps to initial state on the 5th clock.Linear Burst SequenceA[1:0]A[1:0]A[1:0]A[1:0]1st address 000110112nd address 011011003rd address 101100014th address11000110Interleaved Burst SequenceA[1:0]A[1:0]A[1:0]A[1:0]1st address 000110112nd address 010011103rd address 101100014th address11100100GS8640V18/32/36T-300/250/200/1671.All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.2.Byte Write Enable inputs B A , B B , B C and/or B D may be used in any combination with BW to write single or multiple bytes.3.All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.4.Bytes “C ” and “D ” are only available on the x32 and x36 versions.Byte Write Truth TableFunctionGWBWB AB BB CB DNotesRead H H X X X X 1Read H L H H H H 1Write byte a H L L H H H 2, 3Write byte b H L H L H H 2, 3Write byte c H L H H L H 2, 3, 4Write byte d H L H H H L 2, 3, 4Write all bytesHLLLLL2, 3, 4Write all bytes L X X X X XGS8640V18/32/36T-300/250/200/167Synchronous Truth TableOperation AddressUsedStateDiagramKey5E1E2ADSP ADSC ADV W3DQ4Deselect Cycle, Power Down None X H X X L X X High-Z Deselect Cycle, Power Down None X L F L X X X High-Z Deselect Cycle, Power Down None X L F H L X X High-Z Read Cycle, Begin Burst External R L T L X X X Q Read Cycle, Begin Burst External R L T H L X F Q Write Cycle, Begin Burst External W L T H L X T D Read Cycle, Continue Burst Next CR X X H H L F Q Read Cycle, Continue Burst Next CR H X X H L F Q Write Cycle, Continue Burst Next CW X X H H L T D Write Cycle, Continue Burst Next CW H X X H L T D Read Cycle, Suspend Burst Current X X H H H F Q Read Cycle, Suspend Burst Current H X X H H F Q Write Cycle, Suspend Burst Current X X H H H T D Write Cycle, Suspend Burst Current H X X H H T D1.X = Don’t Care, H = High, L = Low2. E = T (True) if E2 = 1 and E3 = 0; E = F (False) if E2 = 0 or E3 = 13.W = T (True) and F (False) is defined in the Byte Write Truth Table preceding.4.G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shownas “Q” in the Truth Table above).5.All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplishbasic synchronous or synchronous burst operations and may be avoided for simplicity.6.Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.7.Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.GS8640V18/32/36T-300/250/200/167Simplified State DiagramFirst WriteFirst ReadBurst WriteBurst ReadDeselect R WCRCWX XWRRWRXXX S i m p l e S y n c h r o n o u s O p e r a t i o nS i m p l e B u r s t S y n c h r o n o u s O p e r a t i o nCR RCWCRCRNotes:1.The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low.2.The upper portion of the diagram assumes active use of only the Enable (E1) and Write (B A , B B , B C , B D , BW, and GW) control inputs, andthat ADSP is tied high and ADSC is tied low.3.The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs, andassumes ADSP is tied high and ADV is tied low.GS8640V18/32/36T-300/250/200/167Simplified State Diagram with GFirst WriteFirst ReadBurst WriteBurst ReadDeselect R WCRCWXXWRRWRXXX CRR CW CRCRW CWW CWNotes:1.The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.e of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from Read cycles to Write cycles without passingthrough a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles.3.Transitions shown in gray tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meetData Input Set Up Time.GS8640V18/32/36T-300/250/200/167Note:Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component.Absolute Maximum Ratings(All voltages reference to V SS )SymbolDescriptionValueUnitV DD Voltage on V DD Pins –0.5 to 3.6V V DDQ Voltage in V DDQ Pins –0.5 to 3.6V V I/O Voltage on I/O Pins –0.5 to V DDQ +0.5 (≤ 3.6 V max.)V V IN Voltage on Other Input Pins –0.5 to V DD +0.5 (≤ 3.6 V max.)V I IN Input Current on Any Pin +/–20mA I OUT Output Current on Any I/O Pin +/–20mA P D Package Power Dissipation 1.5WT STG Storage Temperature –55 to 125o C T BIASTemperature Under Bias–55 to 125o CPower Supply Voltage RangesParameterSymbolMin.Typ.Max.UnitNotes1.8 V Supply Voltage V DD1 1.6 1.82.0V 1.8 V V DDQ I/O Supply VoltageV DDQ11.61.82.0VNotes:1.The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-tions quoted are evaluated for worst case in the temperature range marked on the device.2.Input Under/overshoot voltage must be –2 V > Vi < V DDn +2 V not to exceed3.6 V maximum, with a pulse width not to exceed 20% tKC.GS8640V18/32/36T-300/250/200/167Note:These parameters are sample tested.Logic LevelsParameterSymbolMin.Typ.Max.UnitNotesV DD Input High Voltage V IH 0.6*V DD —V DD + 0.3V 1V DD Input Low Voltage V IL –0.3—0.3*V DD V 1V DDQ I/O Input High Voltage V IHQ 0.6*V DD —V DDQ + 0.3V 1,3V DDQ I/O Input Low VoltageV ILQ–0.3—0.3*V DDV1,3Notes:1.The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-tions quoted are evaluated for worst case in the temperature range marked on the device.2.Input Under/overshoot voltage must be –2 V > Vi < V DDn +2 V not to exceed3.6 V maximum, with a pulse width not to exceed 20% tKC.3.V IHQ (max) is voltage on V DDQ pins plus 0.3 V.Capacitance(T A = 25o C, f = 1 MH Z , V DD = 2.5 V)ParameterSymbolTest conditionsTyp.Max.UnitInput Capacitance C IN V IN = 0 V 45pF Input/Output Capacitance C I/OV OUT = 0 V67pF20% tKCV SS – 2.0 V50%V SS V IHUndershoot Measurement and TimingOvershoot Measurement and Timing20% tKCV DD + 2.0 V50%V DDV ILGS8640V18/32/36T-300/250/200/167AC Test ConditionsParameterConditionsInput high level V DD – 0.2 V Input low level 0.2 V Input slew rate 1 V/ns Input reference level V DD /2Output reference levelV DDQ /2Output loadFig. 11.Include scope and jig capacitance.2.Test conditions as specified with output loading as shown in Fig. 1unless otherwise noted.3.Device is deselected as defined by the Truth Table. DC Electrical CharacteristicsParameterSymbolTest ConditionsMinMaxInput Leakage Current (except mode pins)I IL V IN = 0 to V DD –1 uA 1 uA ZZ Input Current I IN1V DD ≥ V IN ≥ V IH 0 V ≤ V IN ≤ V IH –1 uA –1 uA 1 uA 100 uA FT Input Current I IN2V DD ≥ V IN ≥ V IL 0 V ≤ V IN ≤ V IL–100 uA –1 uA 1 uA 1 uA Output Leakage Current I OL Output Disable, V OUT = 0 to V DD –1 uA 1 uA Output High Voltage V OH1I OH = –4 mA, V DDQ = 1.6 V V DDQ – 0.4 V—Output Low VoltageV OL1I OL = 4 mA, V DD = 1.6 V—0.4 VDQV DDQ/250Ω30pF *Output Load 1* Distributed Test Jig CapacitanceGS8640V18/32/36T-300/250/200/167Notes:1.I DD and I DDQ apply to any combination of V DD and V DDQ operation.2.All parameters listed are worst case scenario.Operating CurrentsParameterTest ConditionsModeSymbol-300-250-200-167Unit0to 70°C –40 to 85°C 0to 70°C –40 to 85°C 0to 70°C –40to 85°C 0 to 70°C –40to 85°C Operating CurrentDevice Selected; All other inputs ≥V IH o r ≤ V IL Output open(x32/x36)Pipeline I DD I DDQ 4206044060360503805031040330402703529035mA Flow Through I DD I DDQ 3003032030255252752523020250202202024020mA (x18)PipelineI DD I DDQ 3703039030315253352527020290202402026020mA Flow Through I DD I DDQ 2701529015230152501520515225151951521515mA Standby Current ZZ ≥ V DD – 0.2 V —PipelineI SB 100120100120100120100120mA Flow Through I SB 100120100120100120100120mA Deselect CurrentDevice Deselected; All other inputs ≥ V IH or ≤ V IL—Pipeline I DD 150165140155130146125140mA Flow ThroughI DD135150125140120135120135mAGS8640V18/32/36T-300/250/200/167Notes:1.These parameters are sampled and are not 100% tested.2.ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and holdtimes as specified above.AC Electrical CharacteristicsParameter Symbol -300-250-200-167Unit Min Max MinMax MinMax MinMax PipelineClock Cycle Time tKC 3.3— 4.0— 5.0— 6.0—ns Clock to Output ValidtKQ — 2.3— 2.5— 3.0— 3.5ns Clock to Output Invalid tKQX 1.5— 1.5— 1.5— 1.5—ns Clock to Output in Low-ZtLZ 1 1.5— 1.5— 1.5— 1.5—ns Setup time tS 1.1— 1.2— 1.4— 1.5—ns Hold time tH 0.1—0.2—0.4—0.5—ns Flow ThroughClock Cycle Time tKC 5.5— 6.5—7.5—8.0—ns Clock to Output ValidtKQ — 5.5— 6.5—7.5—8.0ns Clock to Output Invalid tKQX 3.0— 3.0— 3.0— 3.0—ns Clock to Output in Low-ZtLZ 1 3.0— 3.0— 3.0— 3.0—ns Setup time tS 1.5— 1.5— 1.5— 1.5—ns Hold time tH 0.5—0.5—0.5—0.5—ns Clock HIGH Time tKH 1.0— 1.3— 1.3— 1.3—ns Clock LOW Time tKL 1.2—1.5—1.5—1.5—ns Clock to Output inHigh-Z tHZ 1 1.5 2.3 1.5 2.5 1.5 3.0 1.5 3.0ns G to Output Valid tOE — 2.3— 2.5— 3.0— 3.5ns G to output in Low-Z tOLZ 10—0—0—0—ns G to output in High-Z tOHZ 1— 2.3— 2.5— 3.0— 3.0ns ZZ setup time tZZS 25—5—5—5—ns ZZ hold time tZZH 21—1—1—1—ns ZZ recoverytZZR20—20—20—20—nsGS8640V18/32/36T-300/250/200/167Pipeline Mode Timing (SCD)Begin Read A Cont Cont Deselect Write B Read C Read C+1Read C+2Read C+3ContDeselecttHZtKQX tKQtLZtHtStOHZtOEtHtStHtStHtStHtStHtStStHtStHtStHtSBurst ReadtKCtKL Single Write tKH Single ReadQ(A)D(B)Q(C)Q(C+1)Q(C+2)Q(C+3)ABCDeselected with E1E1 masks ADSPE2 and E3 only sampled with ADSP and ADSCADSC initiated readCK ADSPADSCADVA0–AnGWBWBa–BdE1E2E3GDQa–DQdGS8640V18/32/36T-300/250/200/167Flow Through Mode Timing (SCD)Begin Read A ContCont Write B Read C Read C+1Read C+2Read C+3Read C Cont DeselecttHZtKQXtKQ tLZtH tStOHZtOEtHtS tHtS tHtStHtS tHtS tHtStHtS tHtS tH tS tHtS tKCtKL tKHABCQ(A)D(B)Q(C)Q(C+1)Q(C+2)Q(C+3)Q(C)E2 and E3 only sampled with ADSCADSC initiated readDeselected with E1Fixed HighCK ADSPADSCADVA0–AnGWBWBa–BdE1E2E3GDQa–DQdGS8640V18/32/36T-300/250/200/167Sleep ModeDuring normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high, the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM operates normally after 2 cycles of wake up time.Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to I SB 2. The duration of Sleep mode is dictated by the length of time the ZZ is in a High state. After entering Sleep mode, all inputs except ZZ become disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode. When the ZZ pin is driven high, I SB 2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands may be applied while the SRAM is recovering from Sleep mode.Sleep Mode Timing DiagramtZZRtZZHtZZSHoldSetup tKLtKHtKCCKADSP ADSCZZGS8640V18/32/36T-300/250/200/167TQFP Package Drawing (Package T)D1D E1EPin 1be cLL1A2A1YθNotes:1.All dimensions are in millimeters (mm).2.Package width and length do not include mold protrusion.SymbolDescriptionMin.Nom.MaxA1Standoff 0.050.100.15A2Body Thickness 1.35 1.40 1.45b Lead Width 0.200.300.40c Lead Thickness 0.09—0.20D Terminal Dimension 21.922.022.1D1Package Body 19.920.020.1E Terminal Dimension 15.916.016.1E1Package Body 13.914.014.1e Lead Pitch —0.65—L Foot Length 0.450.600.75L1Lead Length —1.00—Y Coplanarity 0.10θLead Angle0°—7°GS8640V18/32/36T-300/250/200/167Ordering Information for GSI Synchronous Burst RAMs OrgPart Number1TypePackageSpeed 2(MHz/ns)T A 3Status4M x 18GS8640V18T-300Pipeline/Flow Through TQFP 300/5.5C 4M x 18GS8640V18T-250Pipeline/Flow Through TQFP 250/6.5C 4M x 18GS8640V18T-200Pipeline/Flow Through TQFP 200/7.5C 4M x 18GS8640V18T-167Pipeline/Flow Through TQFP 167/8C 2M x 32GS8640V32T-300Pipeline/Flow Through TQFP 300/5.5C 2M x 32GS8640V32T-250Pipeline/Flow Through TQFP 250/6.5C 2M x 32GS8640V32T-200Pipeline/Flow Through TQFP 200/7.5C 2M x 32GS8640V32T-167Pipeline/Flow Through TQFP 167/8C 2M x 36GS8640V36T-300Pipeline/Flow Through TQFP 300/5.5C 2M x 36GS8640V36T-250Pipeline/Flow Through TQFP 250/6.5C 2M x 36GS8640V36T-200Pipeline/Flow Through TQFP 200/7.5C 2M x 36GS8640V36T-167Pipeline/Flow Through TQFP 167/8C 4M x 18GS8640V18T-300I Pipeline/Flow Through TQFP 300/5.5I 4M x 18GS8640V18T-250I Pipeline/Flow Through TQFP 250/6.5I 4M x 18GS8640V18T-200I Pipeline/Flow Through TQFP 200/7.5I 4M x 18GS8640V18T-167I Pipeline/Flow Through TQFP 167/8I 2M x 32GS8640V32T-300I Pipeline/Flow Through TQFP 300/5.5I 2M x 32GS8640V32T-250I Pipeline/Flow Through TQFP 250/6.5I 2M x 32GS8640V32T-200I Pipeline/Flow Through TQFP 200/7.5I 2M x 32GS8640V32T-167I Pipeline/Flow Through TQFP 167/8I 2M x 36GS8640V36T-300I Pipeline/Flow Through TQFP 300/5.5I 2M x 36GS8640V36T-250I Pipeline/Flow Through TQFP 250/6.5I 2M x 36GS8640V36T-200I Pipeline/Flow Through TQFP 200/7.5I 2M x 36GS8640V36T-167I Pipeline/Flow Through TQFP 167/8I 4M x 18GS8640V18GT-250Pipeline/Flow Through Pb-Free TQFP 250/6.5C 4M x 18GS8640V18GT-200Pipeline/Flow Through Pb-Free TQFP 200/7.5C 4M x 18GS8640V18GT-167Pipeline/Flow Through Pb-Free TQFP 167/8C 2M x 32GS8640V32GT-300Pipeline/Flow ThroughPb-Free TQFP300/5.5C2M x 32GS8640V32GT-250Pipeline/Flow Through Pb-Free TQFP 250/6.5C Notes:1.Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8640V18T-300IT.2.The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Eachdevice is Pipeline/Flow Through mode-selectable by the user.3.T A = C = Commercial Temperature Range. T A = I = Industrial Temperature Range.4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which arecovered in this data sheet. See the GSI Technology web site () for a complete listing of current offerings.GS8640V18/32/36T-300/250/200/1672M x 32GS8640V32GT-200Pipeline/Flow Through Pb-Free TQFP 200/7.5C 2M x 32GS8640V32GT-167Pipeline/Flow Through Pb-Free TQFP 167/8C 2M x 36GS8640V36GT-250Pipeline/Flow Through Pb-Free TQFP 250/6.5C 2M x 36GS8640V36GT-200Pipeline/Flow Through Pb-Free TQFP 200/7.5C 2M x 36GS8640V36GT-167Pipeline/Flow Through Pb-Free TQFP 167/8C 4M x 18GS8640V18GT-300I Pipeline/Flow Through Pb-Free TQFP 300/5.5I 4M x 18GS8640V18GT-250I Pipeline/Flow Through Pb-Free TQFP 250/6.5I 4M x 18GS8640V18GT-200I Pipeline/Flow Through Pb-Free TQFP 200/7.5I 4M x 18GS8640V18GT-167I Pipeline/Flow Through Pb-Free TQFP 167/8I 2M x 32GS8640V32GT-300I Pipeline/Flow Through Pb-Free TQFP 300/5.5I 2M x 32GS8640V32GT-250I Pipeline/Flow Through Pb-Free TQFP 250/6.5I 2M x 32GS8640V32GT-200I Pipeline/Flow Through Pb-Free TQFP 200/7.5I 2M x 32GS8640V32GT-167I Pipeline/Flow Through Pb-Free TQFP 167/8I 2M x 36GS8640V36GT-300I Pipeline/Flow Through Pb-Free TQFP 300/5.5I 2M x 36GS8640V36GT-250I Pipeline/Flow Through Pb-Free TQFP 250/6.5I 2M x 36GS8640V36GT-200IPipeline/Flow ThroughPb-Free TQFP200/7.5I2M x 36GS8640V36GT-167I Pipeline/Flow Through Pb-Free TQFP 167/8I Ordering Information for GSI Synchronous Burst RAMs (Continued)OrgPart Number1TypePackageSpeed 2(MHz/ns)T A 3StatusNotes:1.Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8640V18T-300IT.2.The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Eachdevice is Pipeline/Flow Through mode-selectable by the user.3.T A = C = Commercial Temperature Range. T A = I = Industrial Temperature Range.4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which arecovered in this data sheet. See the GSI Technology web site () for a complete listing of current offerings.GS8640V18/32/36T-300/250/200/167 72Mb Sync SRAM Datasheet Revision HistoryDS/DateRev. Code: Old;New Types of ChangesFormat or ContentPage;Revisions;Reason8640Vxx_r1• Creation of new datasheet。

GS864436B-166I中文资料

Product PreviewGS864418(B/E)/GS864436(B/E)/GS864472(C)4M x 18, 2M x 36, 1M x 7272Mb S/DCD Sync Burst SRAMs250 MHz –133MHz 2.5 V or 3.3 V V DD 2.5 V or 3.3 V I/O119-, 165-, & 209-Pin BGA Commercial Temp Industrial Temp Features• FT pin for user-configurable flow through or pipeline operation • Single/Dual Cycle Deselect selectable• IEEE 1149.1 JTAG-compatible Boundary Scan• ZQ mode pin for user-selectable high/low output drive • 2.5 V or 3.3 V +10%/–10% core power supply • LBO pin for Linear or Interleaved Burst mode• Internal input resistors on mode pins allow floating mode pins • Default to SCD x18/x36 Interleaved Pipeline mode • Byte Write (BW) and/or Global Write (GW) operation • Internal self-timed write cycle• Automatic power-down for portable applications• JEDEC-standard 119-, 165-, and 209-bump BGA packageFunctional DescriptionApplicationsThe GS864418/36/72 is a 75,497,472-bit high performancesynchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application insynchronous SRAM applications, ranging from DSP main store to networking chip set support.ControlsAddresses, data I/Os, chip enable (E1), address burst control inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive-edge-triggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burst cycles can be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by ADV. The burst address counter may be configured to count in either linear or interleave order with the Linear Burst Order (LBO) input. The Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance.Flow Through/Pipeline ReadsThe function of the Data Output register can be controlled by the user via the FT mode . Holding the FT mode pin low places the RAM in Flow Through mode, causing output data to bypass the Data Output Register. Holding FT high places the RAM in Pipeline mode, activating the rising-edge-triggered Data Output Register.SCD and DCD Pipelined ReadsThe GS864418/36/72 is a SCD (Single Cycle Deselect) and DCD (Dual Cycle Deselect) pipelined synchronous SRAM. DCD SRAMs pipeline disable commands to the same degree as read commands. SCD SRAMs pipeline deselect commands one stage less than read commands. SCD RAMs begin turning off their outputs immediately after the deselect command has been captured in the input registers. DCD RAMs hold the deselect command for one full cycle and then begin turning off their outputs just after the second rising edge of clock. The user may configure this SRAM for either mode of operation using the SCD mode input.Byte Write and Global WriteByte write operation is performed by using Byte Write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the Byte Write control inputs.FLXDrive™The ZQ pin allows selection between high drive strength (ZQ low) for multi-drop bus applications and normal drive strength (ZQ floating or high) point-to-point applications. See the Output Driver Characteristics chart for details.Sleep ModeLow power (Sleep mode) is attained through the assertion (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode.Core and Interface VoltagesThe GS864418/36/72 operates on a 2.5 V or 3.3 V power supply. All input are 3.3 V and 2.5 V compatible. Separate output power (V DDQ ) pins are used to decouple output noise from the internal circuits and are 3.3 V and 2.5 V compatible.Parameter Synopsis-250-225-200-166-150-133UnitPipeline 3-1-1-1t KQ (x18/x36)t KQ (x72)tCycle 2.53.04.0 2.73.04.4 3.03.05.0 3.53.56.0 3.83.86.7 4.04.07.5ns ns ns Curr (x36)Curr (x72)450540415505385460345405325385295345mA mA Flow Through 2-1-1-1t KQ tCycle 6.5 6.5 6.57.07.58.5ns Curr (x36)Curr (x72)290345290345290345280335265315245300mA mAGS864418(B/E)/GS864436(B/E)/GS864472(C) GS864472C Pad Out—209-Bump BGA—Top View (Package C)1234567891011A DQ G DQ G A E2ADSP ADSC ADV E3A DQB DQ B AB DQ G DQ G BC BG NC BW A BB BF DQ B DQ B BC DQ G DQ G BH BD NC E1NC BE BA DQ B DQ B CD DQ G DQ G V SS NC NC G GW NC V SS DQ B DQ B DE DQP G DQP C V DDQ V DDQ V DD V DD V DD V DDQ V DDQ DQPF DQP B EF DQ C DQ C V SS V SS V SS ZQ V SS V SS V SS DQ F DQ F FG DQ C DQ C V DDQ V DDQ V DD MCH V DD V DDQ V DDQ DQ F DQ F GH DQ C DQ C V SS V SS V SS MCL V SS V SS V SS DQ F DQ F H J DQ C DQ C V DDQ V DDQ V DD MCL V DD V DDQ V DDQ DQ F DQ F J K NC NC CK NC V SS MCL V SS NC NC NC NC K L DQ H DQ H V DDQ V DDQ V DD FT V DD V DDQ V DDQ DQ A DQ A L M DQ H DQ H V SS V SS V SS MCL V SS V SS V SS DQ A DQ A M N DQ H DQ H V DDQ V DDQ V DD SCD V DD V DDQ V DDQ DQ A DQ A N P DQ H DQ H V SS V SS V SS ZZ V SS V SS V SS DQ A DQ A P R DQP D DQP H V DDQ V DDQ V DD V DD V DD V DDQ V DDQ DQP A DQP E R T DQ D DQ D V SS NC NC LBO NC NC V SS DQ E DQ E T U DQ D DQ D A A A A A A A DQ E DQ E U V DQ D DQ D A A A A1A A A DQ E DQ E V W DQ D DQ D TMS TDI A A0A TDO TCK DQ E DQ E W11 x 19 Bump BGA—14 x 22 mm2 Body—1 mm Bump PitchGS864418(B/E)/GS864436(B/E)/GS864472(C)GS864472 209-Bump BGA Pin DescriptionSymbol Type DescriptionA0, A1I Address field LSBs and Address Counter Preset Inputs.A I Address InputsDQ ADQ BDQ CDQ DI/O Data Input and Output pinsDQ EDQ FDQ GDQ HB A, B B I Byte Write Enable for DQ A, DQ B I/Os; active lowB C,B D I Byte Write Enable for DQ C, DQ D I/Os; active lowB E, B F, B G,B H I Byte Write Enable for DQ E, DQ F, DQ G, DQ H I/Os; active lowNC—No ConnectCK I Clock Input Signal; active highGW I Global Write Enable—Writes all bytes; active lowE1I Chip Enable; active lowE3I Chip Enable; active lowE2I Chip Enable; active highG I Output Enable; active lowADV I Burst address counter advance enable; active low ADSP, ADSC I Address Strobe (Processor, Cache Controller); active low ZZ I Sleep Mode control; active highFT I Flow Through or Pipeline mode; active lowLBO I Linear Burst Order mode; active lowSCD I Single Cycle Deselect/Dual Cycle Deselect Mode ControlMCH I Must Connect HighGS864418(B/E)/GS864436(B/E)/GS864472(C)MCL Must Connect Low BW I Byte Enable; active lowZQ I FLXDrive Output Impedance Control(Low = Low Impedance [High Drive], High = High Impedance [Low Drive])TMS I Scan Test Mode Select TDI I Scan Test Data In TDO O Scan Test Data Out TCK I Scan Test Clock V DD I Core power supply V SS I I/O and Core Ground V DDQIOutput driver power supplyGS864472 209-Bump BGA Pin Description (Continued)SymbolType DescriptionGS864418(B/E)/GS864436(B/E)/GS864472(C) 165-Bump BGA—x18 Commom I/O—Top View (Package E)1234567891011A NC A E1BB NC E3BW ADSC ADV A A AB NC A E2NC BA CK GW G ADSP A NC BC NC NC V DDQ V SS V SS V SS V SS V SS V DDQ NC DQPA CD NC DQB V DDQ V DD V SS V SS V SS V DD V DDQ NC DQA DE NC DQB V DDQ V DD V SS V SS V SS V DD V DDQ NC DQA EF NC DQB V DDQ V DD V SS V SS V SS V DD V DDQ NC DQA FG NC DQB V DDQ V DD V SS V SS V SS V DD V DDQ NC DQA GH FT MCL NC V DD V SS V SS V SS V DD NC ZQ ZZ HJ DQB NC V DDQ V DD V SS V SS V SS V DD V DDQ DQA NC JK DQB NC V DDQ V DD V SS V SS V SS V DD V DDQ DQA NC KL DQB NC V DDQ V DD V SS V SS V SS V DD V DDQ DQA NC LM DQB NC V DDQ V DD V SS V SS V SS V DD V DDQ DQA NC MN DQPB SCD V DDQ V SS NC A NC V SS V DDQ NC NC NP NC A A A TDI A1TDO A A A A PR LBO A A A TMS A0TCK A A A A R11 x 15 Bump BGA—15 mm x 17 mm Body—1.0 mm Bump PitchGS864418(B/E)/GS864436(B/E)/GS864472(C) 165-Bump BGA—x36 Common I/O—Top View (Package E)1234567891011A NC A E1BC BB E3BW ADSC ADV A NC AB NC A E2BD BA CK GW G ADSP A NC BC DQPC NC V DDQ V SS V SS V SS V SS V SS V DDQ NC DQPB CD DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB DE DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB EF DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB FG DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB GH FT MCL NC V DD V SS V SS V SS V DD NC ZQ ZZ HJ DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA JK DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA KL DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA LM DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA MN DQPD SCD V DDQ V SS NC A NC V SS V DDQ NC DQPA NP NC A A A TDI A1TDO A A A A PR LBO A A A TMS A0TCK A A A A R11 x 15 Bump BGA—15 mm x 17 mm Body—1.0 mm Bump PitchGS864418(B/E)/GS864436(B/E)/GS864472(C)GS864418/36 165-Bump BGA Pin DescriptionSymbol Type DescriptionA0, A1I Address field LSBs and Address Counter Preset InputsA I Address InputsDQ ADQ BDQ CDQ DI/O Data Input and Output pinsB A, B B, B C, B D I Byte Write Enable for DQ A, DQ B, DQ C, DQ D I/Os; active low (x36 Version)NC—No ConnectCK I Clock Input Signal; active highBW I Byte Write—Writes all enabled bytes; active lowGW I Global Write Enable—Writes all bytes; active lowE1I Chip Enable; active lowE3I Chip Enable; active lowE2I Chip Enable; active highG I Output Enable; active lowADV I Burst address counter advance enable; active l0w ADSC, ADSP I Address Strobe (Processor, Cache Controller); active low ZZ I Sleep mode control; active highFT I Flow Through or Pipeline mode; active lowLBO I Linear Burst Order mode; active lowZQ I FLXDrive Output Impedance Control (Low = Low Impedance [High Drive], High = High Impedance [LowDrive])TMS I Scan Test Mode SelectTDI I Scan Test Data InTDO O Scan Test Data OutTCK I Scan Test ClockMCL—Must Connect Low SCD—Single Cycle Deselect/Dual Cyle Deselect Mode Control V DD I Core power supplyV SS I I/O and Core GroundV DDQ I Output driver power supplyGS864418(B/E)/GS864436(B/E)/GS864472(C) GS864436B Pad Out—119-Bump BGA—Top View (Package B)1234567A V DDQ A A ADSP A A V DDQ AB NC A A ADSC A A NC BC NC A A V DD A A NC CD DQ C DQP C V SS ZQ V SS DQP B DQ B DE DQ C DQ C V SS E1V SS DQ B DQ B EF V DDQ DQ C V SSG V SS DQ B V DDQ FG DQ C DQ C BC ADV BB DQ B DQ B GH DQ C DQ C V SS GW V SS DQ B DQ B HJ V DDQ V DD NC V DD NC V DD V DDQ JK DQ D DQ D V SS CK V SS DQ A DQ A KL DQ D DQ D BD SCD BA DQ A DQ A LM V DDQ DQ D V SS BW V SS DQ A V DDQ MN DQ D DQ D V SS A1V SS DQ A DQ A NP DQ D DQP D V SS A0V SS DQP A DQ A PR NC A LBO V DD FT A NC RT NC A A A A A ZZ TU V DDQ TMS TDI TCK TDO NC V DDQ U7 x 17 Bump BGA—14 x 22 mm2 Body—1.27 mm Bump PitchGS864418(B/E)/GS864436(B/E)/GS864472(C) GS864418B Pad Out—119-Bump BGA—Top View (Package B)1234567A V DDQ A A ADSP A A V DDQ AB NC A A ADSC A A NC BC NC A A V DD A A NC CD DQ B NC V SS ZQ V SS DQP A NC DE NC DQ B V SS E1V SS NC DQ A EF V DDQ NC V SSG V SS DQ A V DDQ FG NC DQ B BB ADV NC NC DQ A GH DQ B NC V SS GW V SS DQ A NC HJ V DDQ V DD NC V DD NC V DD V DDQ JK NC DQ B V SS CK V SS NC DQ A KL DQ B NC NC SCD BA DQ A NC LM V DDQ DQ B V SS BW V SS NC V DDQ MN DQ B NC V SS A1V SS DQ A NC NP NC DQP B V SS A0V SS NC DQ A PR NC A LBO V DD FT A NC RT A A A A A A ZZ TU V DDQ TMS TDI TCK TDO NC V DDQ U7 x 17 Bump BGA—14 x 22 mm2 Body—1.27 mm Bump PitchGS864418(B/E)/GS864436(B/E)/GS864472(C)GS864418/36 119-Bump BGA Pin DescriptionSymbol Type DescriptionA0, A1I Address field LSBs and Address Counter Preset InputsA I Address InputsDQ ADQ BDQ CDQ DI/O Data Input and Output pinsB A, B B, B C, B D I Byte Write Enable for DQ A, DQ B, DQ C, DQ D I/Os; active lowNC—No ConnectCK I Clock Input Signal; active highBW I Byte Write—Writes all enabled bytes; active lowGW I Global Write Enable—Writes all bytes; active lowE1I Chip Enable; active lowG I Output Enable; active lowADV I Burst address counter advance enable; active low ADSP, ADSC I Address Strobe (Processor, Cache Controller); active low ZZ I Sleep mode control; active highFT I Flow Through or Pipeline mode; active lowLBO I Linear Burst Order mode; active lowZQ I FLXDrive Output Impedance Control (Low = Low Impedance [High Drive], High = High Impedance [LowDrive])SCD I Single Cycle Deselect/Dual Cyle Deselect Mode Control TMS I Scan Test Mode SelectTDI I Scan Test Data InTDO O Scan Test Data OutTCK I Scan Test ClockV DD I Core power supplyV SS I I/O and Core GroundV SS I I/O and Core GroundV DDQ I Output driver power supplyGS864418(B/E)/GS864436(B/E)/GS864472(C)GS864418/36/72 Block DiagramA1A0A0A1D0D1Q1Q0Counter LoadD QDQRegisterRegisterDQRegisterDQRegisterDQRegisterD QRegisterD QRegisterD QRegisterDQR e g i s t e rDQRegisterA0–An LBO ADV CK ADSC ADSP GW BW E 1FT GZZPower Down ControlMemory Array36364AQD DQx1–DQx93636Note: Only x36 version shown for simplicity.SCD3636B AB BB CB DGS864418(B/E)/GS864436(B/E)/GS864472(C)Note:There are pull-up devices onthe ZQ, SCD, and FT pins and a pull-down device on the ZZ pin, so those input pins can be unconnected and the chip will operate in the default states as specified in the above tables.Burst Counter SequencesBPR 1999.05.18Mode Pin FunctionsMode NamePin NameStateFunctionBurst Order Control LBO L Linear Burst H Interleaved Burst Output Register Control FT L Flow Through H or NC Pipeline Power Down Control ZZ L or NC Active H Standby, I DD = I SB Single/Dual Cycle Deselect Control SCD L Dual Cycle Deselect H or NC Single Cycle Deselect FLXDrive Output Impedance ControlZQL High Drive (Low Impedance)H or NCLow Drive (High Impedance)Note:The burst counter wraps to initial state on the 5th clock.Note:The burst counter wraps to initial state on the 5th clock.Linear Burst SequenceA[1:0]A[1:0]A[1:0]A[1:0]1st address 000110112nd address 011011003rd address 101100014th address11000110Interleaved Burst SequenceA[1:0]A[1:0]A[1:0]A[1:0]1st address 000110112nd address 010011103rd address 101100014th address11100100GS864418(B/E)/GS864436(B/E)/GS864472(C)1.All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.2.Byte Write Enable inputs B A , B B , B C , and/or B D may be used in any combination with BW to write single or multiple bytes.3.All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.4.Bytes “C ” and “D ” are only available on the x36 version.Byte Write Truth TableFunctionGWBWB AB BB CB DNotesRead H H X X X X 1Read H L H H H H 1Write byte a H L L H H H 2, 3Write byte b H L H L H H 2, 3Write byte c H L H H L H 2, 3, 4Write byte d H L H H H L 2, 3, 4Write all bytesHLLLLL2, 3, 4Write all bytes L X X X X XGS864418(B/E)/GS864436(B/E)/GS864472(C) Synchronous Truth TableOperation Address UsedStateDiagramKey5E1ADSP ADSC ADV W3DQ4Deselect Cycle, Power Down None X H X L X X High-Z Read Cycle, Begin Burst External R L L X X X Q Read Cycle, Begin Burst External R L H L X F Q Write Cycle, Begin Burst External W L H L X T D Read Cycle, Continue Burst Next CR X H H L F Q Read Cycle, Continue Burst Next CR H X H L F Q Write Cycle, Continue Burst Next CW X H H L T D Write Cycle, Continue Burst Next CW H X H L T D Read Cycle, Suspend Burst Current X H H H F Q Read Cycle, Suspend Burst Current H X H H F Q Write Cycle, Suspend Burst Current X H H H T D Write Cycle, Suspend Burst Current H X H H T D Notes:1.X = Don’t Care, H = High, L = Low2.W = T (True) and F (False) is defined in the Byte Write Truth Table preceding3.G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shownas “Q” in the Truth Table above).4.All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplishbasic synchronous or synchronous burst operations and may be avoided for simplicity.5.Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.6.Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.GS864418(B/E)/GS864436(B/E)/GS864472(C)Simplified State DiagramFirst WriteFirst ReadBurst WriteBurst ReadDeselect R WCRCWX XWRRWRXXX S i m p l e S y n c h r o n o u s O p e r a t i o nS i m p l e B u r s t S y n c h r o n o u s O p e r a t i o nCR RCWCRCRNotes:1.The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low.2.The upper portion of the diagram assumes active use of only the Enable (E1) and Write (B A , B B , B C , B D , BW, and GW) control inputs, andthat ADSP is tied high and ADSC is tied low.3.The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs andassumes ADSP is tied high and ADV is tied low.GS864418(B/E)/GS864436(B/E)/GS864472(C)Simplified State Diagram with GFirst WriteFirst ReadBurst WriteBurst ReadDeselect R WCRCWXXWRRWRXXX CRR CW CRCRW CWW CWNotes:1.The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.e of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from read cycles to write cycles without passingthrough a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles.3.Transitions shown in grey tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meetData Input Set Up Time.GS864418(B/E)/GS864436(B/E)/GS864472(C)Note:Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component.Absolute Maximum Ratings(All voltages reference to V SS )SymbolDescriptionValueUnitV DD Voltage on V DD Pins –0.5 to 4.6V V DDQ Voltage in V DDQ Pins –0.5 to 4.6V V I/O Voltage on I/O Pins –0.5 to V DDQ +0.5 (≤ 4.6 V max.)V V IN Voltage on Other Input Pins –0.5 to V DD +0.5 (≤ 4.6 V max.)V I IN Input Current on Any Pin +/–20mA I OUT Output Current on Any I/O Pin +/–20mA P D Package Power Dissipation 1.5WT STG Storage Temperature –55 to 125o C T BIASTemperature Under Bias–55 to 125oCPower Supply Voltage RangesParameterSymbolMin.Typ.Max.UnitNotes3.3 V Supply Voltage V DD3 3.0 3.3 3.6V 2.5 V Supply Voltage V DD2 2.3 2.5 2.7V 3.3 V V DDQ I/O Supply Voltage V DDQ3 3.0 3.3 3.6V 2.5 V V DDQ I/O Supply VoltageV DDQ22.32.52.7VNotes:1.The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-tions quoted are evaluated for worst case in the temperature range marked on the device.2.Input Under/overshoot voltage must be –2 V > Vi < V DDn +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.GS864418(B/E)/GS864436(B/E)/GS864472(C)V DDQ3 Range Logic LevelsParameter Symbol Min.Typ.Max.Unit Notes V DD Input High Voltage V IH 2.0—V DD + 0.3V1V DD Input Low Voltage V IL–0.3—0.8V1V DDQ I/O Input High Voltage V IHQ 2.0—V DDQ + 0.3V1,3V DDQ I/O Input Low Voltage V ILQ–0.3—0.8V1,3 Notes:1.The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-tions quoted are evaluated for worst case in the temperature range marked on the device.2.Input Under/overshoot voltage must be –2 V > Vi < V DDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.3.V IHQ (max) is voltage on V DDQ pins plus 0.3 V.V DDQ2 Range Logic LevelsParameter Symbol Min.Typ.Max.Unit Notes V DD Input High Voltage V IH0.6*V DD—V DD + 0.3V1V DD Input Low Voltage V IL–0.3—0.3*V DD V1V DDQ I/O Input High Voltage V IHQ0.6*V DD—V DDQ + 0.3V1,3V DDQ I/O Input Low Voltage V ILQ–0.3—0.3*V DD V1,3 Notes:1.The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-tions quoted are evaluated for worst case in the temperature range marked on the device.2.Input Under/overshoot voltage must be –2 V > Vi < V DDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.3.V IHQ (max) is voltage on V DDQ pins plus 0.3 V.Recommended Operating TemperaturesParameter Symbol Min.Typ.Max.Unit Notes Ambient Temperature (Commercial Range Versions)T A02570°C2 Ambient Temperature (Industrial Range Versions)T A–402585°C2 Notes:1.The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-tions quoted are evaluated for worst case in the temperature range marked on the device.2.Input Under/overshoot voltage must be –2 V > Vi < V DDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.GS864418(B/E)/GS864436(B/E)/GS864472(C)Note:These parameters are sample tested.Capacitance(T A = 25o C, f = 1 MH Z , V DD = 2.5 V)ParameterSymbolTest conditionsTyp.Max.UnitInput Capacitance C IN V IN = 0 V 810pF Input/Output Capacitance C I/OV OUT = 0 V1214pFAC Test ConditionsParameterConditionsInput high level V DD – 0.2 V Input low level 0.2 V Input slew rate 1 V/ns Input reference level V DD /2Output reference levelV DDQ /2Output loadFig. 1Notes:1.Include scope and jig capacitance.2.Test conditions as specified with output loading as shown in Fig. 1unless otherwise noted.3.Device is deselected as defined by the Truth Table. 20% tKCV SS – 2.0 V50%V SS V IHUndershoot Measurement and TimingOvershoot Measurement and Timing20% tKCV DD + 2.0 V50%V DDV ILDQV DDQ/250Ω30pF *Output Load 1* Distributed Test Jig CapacitanceGS864418(B/E)/GS864436(B/E)/GS864472(C)DC Electrical CharacteristicsParameter Symbol Test Conditions Min Max Input Leakage Current(except mode pins)I IL V IN = 0 to V DD–1 uA 1 uAZZ Input Current I IN1V DD≥V IN ≥V IH0 V≤ V IN ≤ V IH–1 uA–1 uA1 uA100 uAFT, SCD, and ZQ Input Current I IN2V DD≥V IN ≥V IL0 V≤ V IN ≤ V IL–100 uA–1 uA1 uA1 uAOutput Leakage Current I OL Output Disable, V OUT = 0 to V DD–1 uA 1 uA Output High Voltage V OH2I OH = –8 mA, V DDQ = 2.375 V 1.7 V—Output High Voltage V OH3I OH = –8 mA, V DDQ = 3.135 V 2.4 V—Output Low Voltage V OL I OL = 8 mA—0.4 VGS864418(B/E)/GS864436(B/E)/GS864472(C)N o t e s : 1.I D D a n d I D D Q a p p l y t o a n y c o m b i n a t i o n o f V D D 3, V D D 2, V D D Q 3, a n d V D D Q 2 o p e r a t i o n .2.A l l p a r a m e t e r s l i s t e d a r e w o r s t c a s e s c e n a r i o .O p e r a t i n g C u r r e n t sP a r a m e t e r T e s t C o n d i t i o n s M o d eS y m b o l -250-225-200-166-150-133U n i t0t o 70°C –40 t o 85°C0t o 70°C–40 t o 85°C 0t o 70°C –40t o 85°C 0 t o 70°C –40t o 85°C 0 t o 70°C –40t o 85°C 0 t o 70°C –40t o 85°C O p e r a t i n g C u r r e n tD e v i c e S e l e c t e d ; A l l o t h e r i n p u t s ≥V I H o r ≤ V I LO u t p u t o p e n(x 72)P i p e l i n eI D DI D D Q480605156044560480604105044550365404004034540380403153035030m AF l o w T h r o u g hI D DI D D Q315303403031530340303153034030305303303028530310302802030520m A(x 36)P i p e l i n eI D DI D D Q400504355037045405453454038040310353453529530330302702530525m AF l o w T h r o u g hI D DI D D Q270202952027020295202702029520260202852024520270202301525515m A(x 18)P i p e l i n eI D DI D D Q360253952533525370253152035020285203202027520310202501528515m AF l o w T h r o u g hI D DI D D Q250152751525015275152501527515240152601522515250152101523515m AS t a n d b y C u r r e n tZ Z ≥ V D D – 0.2 V—P i p e l i n eI S B 120160120160120160120160120160120160m AF l o w T h r o u g hI S B120160120160120160120160120160120160m AD e s e l e c t C u r r e n tD e v i c e D e s e l e c t e d ; A l l o t h e r i n p u t s ≥ V I H o r ≤ V I L—P i p e l i n eI D D200230190220180210170200170200160190m AF l o w T h r o u g hI D D170200170200160190160190150180140170m AGS864418(B/E)/GS864436(B/E)/GS864472(C)Notes:1.These parameters are sampled and are not 100% tested.2.ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and holdtimes as specified above.AC Electrical CharacteristicsParameterSymbol-250-225-200-166-150-133UnitMinMaxMinMaxMinMaxMinMaxMinMaxMinMaxPipelineClock Cycle Time tKC 4.0— 4.4— 5.0— 6.0— 6.7—7.5—ns Clock to Output Valid(x18/x36)tKQ — 2.5— 2.7— 3.0— 3.5— 3.8— 4.0ns Clock to Output Valid(x72)tKQ — 3.0— 3.0— 3.0— 3.5— 3.8— 4.0ns Clock to Output Invalid tKQX 1.5— 1.5— 1.5— 1.5— 1.5— 1.5—ns Clock to Output in Low-ZtLZ 1 1.5— 1.5— 1.5— 1.5— 1.5— 1.5—ns Setup time tS 1.3— 1.3— 1.4— 1.5— 1.5— 1.5—ns Hold Time tH 0.2—0.3—0.4—0.5—0.5—0.5—ns Flow ThroughClock Cycle Time tKC 6.5— 6.5— 6.5—7.0—7.5—8.5—ns Clock to Output ValidtKQ — 6.5— 6.5— 6.5—7.0—7.5—8.5ns Clock to Output Invalid tKQX 3.0— 3.0— 3.0— 3.0— 3.0— 3.0—ns Clock to Output in Low-ZtLZ 1 3.0— 3.0— 3.0— 3.0— 3.0— 3.0—ns Setup time tS 1.5— 1.5— 1.5— 1.5— 1.5— 1.5—ns Hold time tH 0.5—0.5—0.5—0.5—0.5—0.5—ns Clock HIGH Time tKH 1.3— 1.3— 1.3— 1.3— 1.5— 1.7—ns Clock LOW Time tKL 1.5—1.5—1.5—1.5— 1.7—2—ns Clock to Output inHigh-Z (x18/x36)tHZ 1 1.5 2.5 1.5 2.7 1.5 3.0 1.5 3.0 1.5 3.0 1.5 3.0ns Clock to Output in High-Z (x72)tHZ 1 1.5 3.0 1.5 3.0 1.5 3.0 1.5 3.0 1.5 3.0 1.5 3.0ns G to Output Valid (x18/x36)tOE — 2.5— 2.7— 3.2— 3.5— 3.8— 4.0ns G to Output Valid(x72)tOE — 3.0— 3.0— 3.2— 3.5— 3.8— 4.0ns G to output in Low-Z tOLZ 10—0—0—0—0—0—ns G to output in High-Z (x18/x36)tOHZ 1— 2.5— 2.7— 3.0— 3.0— 3.0— 3.0ns G to output in High-Z (x72)tOHZ 1— 3.0— 3.0— 3.0— 3.0— 3.0— 3.0ns ZZ setup time tZZS 25—5—5—5—5—5—ns ZZ hold time tZZH 21—1—1—1—1—1—ns ZZ recoverytZZR20—20—20—20—20—20—ns。

BT 200 产品说明书

Physical Bus Test Device for PROFIBUS-DPBT 200 03/99 EnglishBT 200Physical Bus Test Devicefor PROFIBUS-DPTable of Contents1 DESCRIPTION (2)2 COMMISSIONING (3)3 NORMAL MODE (4)3.1 W IRING T EST (5)3.2 E RROR M ESSAGES OF THE W IRING T EST (6)4 SPECIALIST MODE (8)4.1 O PERATOR C ONTROL (8)4.2 S TATION (RS 485) T EST (10)4.3 B RANCH T EST (11)4.4 D ISTANCE (12)4.5 R EFLECTION T EST (13)4.6 S ERVICE (14)5 MAINTENANCE AND TROUBLE-SHOOTING (15)5.1 C HARGING S TATUS OF THE B ATTERY (15)5.2 C HANGING THE B ATTERY (15)5.3 S ELF-T ESTS (16)5.4 E RROR C ORRECTION T ABLE (17)6 ACCESSORIES AND REPLACEMENT PARTS (18)7 TECHNICAL DATA (19)(S)J31069-D0075-U001-A1-7618 Page 1English 03/99 BT 200 (S)J31069-D0075-U001-A1-7618Page 21 DescriptionPurpose of the BT 200The BT 200 offers diagnostics for PROFIBUS-DP systems without having to use additional measuring aids (e.g., PC or oscilloscope).Operator control elements and displayFig. 1BT 200 operator control elements and display1)PROFIBUS-DP connection (9-pin sub D)2)LC display (2 x 16 characters)3)ON/OFF button 4)TEST key (start test)5)CURSOR keys 6)OK key (various functions)7)ESCAPE key (terminate)8) Charging contactsBT 200 03/99 English (S)J31069-D0075-U001-A1-7618 Page 32 CommissioningBefore initial commissioning, check your de-livery, and charge the battery.Scope of deliveryThe delivery includes:- 1 BT 200- 1 battery- 1 test plug connector (wiring test)- 1 test cable, length: 2 m- 1 user's guideCharging the battery- Open the battery compartment (seechapter on changing the battery), andcheck to detemine whether the battery isinstalled. Install the battery if necessary.- Charge battery of the BT 200 via char-ging shell (approx. 4 hours).U Attention!The battery is always delivered uncharged.The charging shell is not included and must be ordered separately.- Remove the BT 200 from the chargingshell. The device is ready for operation.English 03/99 BT 200 (S)J31069-D0075-U001-A1-7618Page 43 Normal ModeThe BT 200 is turned on with the ON/OFFbutton.Keep the ON/OFF button pressed until you see a reaction on the display.Standby displayThe following display appears for approx. 3seconds after the device is turned on.Battery displayThe battery capacity display is then shown forapprox. 3 seconds.Operational displayAfter the battery display disappears, the BT 200 assumes normal mode and displays thestart screen for the wiring test.Only the wiring test can be performed in nor-mal mode.Energy saver modeIf no keys are pressed for approx. 3 minutes and no measurements are being performed,the BT 200 goes off automatically.BT 200 03/99 English 3.1 Wiring TestPrinciple of measuringThe wiring test for a bus segment is per-formed between the BT 200 and the test plugconnector. During the initialization phase, atest can be performed from connector to con-nector. See figure 2. The test connector isalways installed on the one end of the bussegment.Short circuits can also be determined outsidethe test path. The bus segment may only beequipped with a terminating resistor at thebeginning and at the end.Fig. 2 Step-by-step measuring principlePerforming the testNo stations may be connected to the bus line.The test is started by pressing the TEST key.One of the following two messages is dis-played if the test was concluded successfully.For one terminating resistor (as long as in-stallation has not been completed, only oneterminal resistor is present)After installation has been concluded, two re-sistors must be inserted.The test is concluded by pressing the OK key,and a new wiring test can be started.The wiring test can also be concluded or ter-minated at any time by pressing the ESC key. (S)J31069-D0075-U001-A1-7618 Page 5English 03/99 BT 200(S)J31069-D0075-U001-A1-7618Page 63.2 Error Messages of the Wiring TestStation testCheck to determine whether all plug connec-tors have been disconnected from the sta-tions.Wire mix-upExchange the cores in the corresponding plug connector.U The wiring test must be performed eachtime a new PROFIBUS plug connector isconnected. Otherwise an even numberof wire mix-ups will not be recognized.Short circuitLocate and correct the short circuit.A frequent cause (e.g., of shield short circuits)is the incorrect application of shield braiding in the plug connectors.BT 200 03/99 English Line or shield breakIf several cores or at least one core and theshield are broken or not connected, the BT200 cannot identify the interruption unambi-guously.To obtain a correct measuring result for shieldbreak, the shield may not be connected withground.With all four messages, first check the plugconnectors in question. If these are okay, re-place the cable.None or more than two terminating resistors Page with the "→""←" keys.Place a terminating resistor at the beginningand end of the bus segment.Page with the "→""←" keys.Remove or deactivate all terminating resistorsexcept the two at the beginning and end ofthe bus segment.(S)J31069-D0075-U001-A1-7618 Page 7English 03/99 BT 200 (S)J31069-D0075-U001-A1-7618Page 84 Specialist ModeYou can switch from normal mode to special-ist mode by pressing ESC and OK at thesame time.The following functions are available in spe-cialist mode.- Wiring test. See normal mode.- Station test- Wire mix-up- Short circuit- Line or shield break- None or more than two- Station test (RS 485 test)- Branch test- Distance measurement- Reflection test- Service menu4.1 Operator ControlThe BT 200 is menu-controlled via the input keys of the sealed keyboard (figure 1).CursorThe current cursor position in the display is shown as a flashing arrow and indicates the function which is being performed.BT 200 03/99 EnglishMenu itemsMenu items are selected with the cursor andactivated with the OK key. The ESC key canbe used to terminate a running function or tojump back to the higher-level menu item. Menu structure(S)J31069-D0075-U001-A1-7618 Page 94.2 Station (RS 485) TestThis test is used to test the RS 485 interfaceof a single slave.Performing the testDisconnect bus connector from the slave.Establish point-to-point connection betweenslave and BT 200. See figure 4.U Only the included test cable may be used for this connection.Fig. 4 Point-to-point connectionTurn on the slave since the test must be per-formed with an active slave.Start station test.Set address of the slave to be tested asshown below."←" "→" Change cursor position."↑" "↓" Increment/decrement number.Accept the set three-position number with OK,and start test.Test resultsPossible test results are listed below.- RS 485 okay (slave okay)- RS 485 defective. (No continuous signal receipt; repeat test.)- No response. (Nothing received; wrong slave address may have been set.)- 5V : (corresponding measured value)- RTS signal (YES or NO)4.3 Branch TestThis can be used to check the availability ofall slaves on PROFIBUS or to address an in-dividual slave.The branch test can also be performed be-yond repeaters/LWL.Performing the testDisconnect all masters from the bus (e.g., PG,OP and CP). See figure 5.Connect BT 200 to the bus.Set the baud rate configured on the bus onthe BT 200.Set the desired address for individual slavetest.Set address to "000" for the total test.Start test.Fig. 5 Measuring principle of the branch testTest resultsDuring the total branch test, each availableslave is indicated in a list of available stations(i.e., LIFE LIST).- LIFE LISTFor an individual test- No response. (e.g., No station with thisbus address on the bus.)- Faulty station. (e.g., a slave number has been assigned twice.)4.4 DistanceThe distance can be measured to determinethe length of the PROFIBUS cable.Performing the testDisconnect all bus stations from the bus.Connect test plug connector to one end of theline and the BT 200 to the other end. (Re-move termination for BT 200.)Start distance measurement.After the start, the BT 200 requests three val-ues which must be entered on the keyboard.- Loop resistance (default = 110 Ω/km)The default value can be changed viamenu item Service.- Number of plug connectors with longitu-dinal inductivity (12 Mbaud connector) - Resistance value per connector(default = 0.32 Ω)After entry of the last value and confirmationwith OK, measurement is performed. Measurement resultsThe following appears on the display.The following error messages can occur dur-ing measurement.- No resistor inserted.- Display "0 m" (no plausible length deter-mined)- More than 1 resistor inserted.Possible causes of errors:-Distance < 15 m-Stub lines, located on the measuring pathCorrect the error, and repeat the measure-ment.4.5 Reflection TestThe reflection test can be used to determinefaults (e.g., short circuits and interruptions) orto confirm the distance measurement.Reflexions can occur in the following situa-tions:-Stub lines exist.-Too many terminating resistors havebeen inserted, or none have been in-serted.-Change to a wrong type of cable occurs within the measuring path.-Cable installation is not correct (e.g.,luster terminal connection and so on).Performing the testDisconnect master from the bus, and makesure that no bus communication occurs.Connect BT 200 to one end of the line.Start reflection measurement.Test resultsIf no reflection (i.e., fault) is detected, the fol-lowing message appears.If a reflection is detected, the following mes-sage appears.The number in the display specifies the dis-tance in meters from the measuring point tothe faulty point.If the distance of the reflection measurementcorresponds to a previous distance meas-urement, this distance measurement is con-firmed. The wiring of the bus segment whichwas measured is correct.4.6 ServiceSettingsThe following settings can be changed in theService menu.-Language (German/English)-Loop resistance (50 to 200 Ω/km)-Baud rate (9600 baud to 12 Mbaud)-Contrast (↑↓)Default valuesIf you want to reset all values to their statuson delivery, keep both cursor keys pressedfor approx. three seconds after turning on thedevice.DisplaysThe Service menu gives you the following in-formation.-Firmware version-Battery capacityHardware testThis tests the internal hardware.CalibrationCalibration is not necessary when the stan-dard type-A PROFIBUS cable is used.The accuracy of distance and reflectionmeasurement is achieved by calibration with 2test cables of different known lengths.Fig. 6 Principle of calibration5 Maintenance and Trouble-Shooting5.1 Charging Status of the BatteryThe charging status of the battery is indicatedfor approximately 3 seconds during startup.This display then disappears.The charging status can also be indicated viathe service menu during operation.I f the battery goes dead during operation, thecharging status begins to flash.5.2 Changing the BatteryU Attention! When changing the battery (2), make absolutely sure that the battery con-nector (1) with the red cable (light-colored ca-ble) is inserted to the right.Fig. 7 Changing the battery5.3 Self-TestsT he BT 200 performs self-tests automaticallyand on request (hardware test).- Internal RS 485 driver testThe test is performed each time the sta-tion and branch test is called.- RAM testA cyclic RAM test is performed.- Flash EPROM testA cyclic EPROM test is performed.- RS 485 driver testThe individual tests (e.g., RAM test, flashEPROM test and display key test) can also beselected from specialist mode via the HW testservice menu.If an error is detected during the self-test, youmust proceed as shown in the error correc-tion table.5.4 Error Correction TableFault during startupDisplay Fault Reason Effect Correc-tionNone No dis-play afterswitch-on BatterydeadHard-waredoes notstart up.Chargebatteryor in-stallnewbattery.If possi-ble: "internal error" message Afterswitch-on, "in-ternalerror"messageappears.RAM/EPROMerrordiplay/keyboarddefectiveNo meas-uringpossibleRe-placeBT 200.Fault during operationDisplay Fault Reason Effect Correc-tionBattery display flashes before.Devicegoes off.Battery isdead.No meas-uringpossibleChargebattery/installnewone.None Devicegoes off.Time withno useractivitywas ex-ceeded.None PressONbutton.Internal driver defect Internaldriver isdefective.HW de-fectNo sta-tion/branch testpossibleRe-placeBT 200.6 Accessories and Replacement PartsThe following components can be ordered under their MLFB number.Designation/Picture MLFB NumberTest connector 6EP8106-0AC20Charging shell w. power pack for:230 V AC110 V AC 6GT2003-1AA00 6EP8106-0HB01Battery with connectioncable6EP8106-HA01Test cable9-pin sub D on9-pin sub D (1 to 1)6EP8106-OHC017 Technical DataGeneralDimensions210 * 100 * 55 mm²Weight400 gBattery capacity≥ 720 mAhLife≥ 8 hVoltage supply NiCd, 4.8 V battery Display LCD, 2 * 16 charac-tersBaud rate9600 Bd to 12 MBd Protection class IP 30Measuring accuracy Length measurement(+/-3m) Environmental RequirementsOperating temperature+ 5°C to +45°C Storage temperature-20°C to +60°C Relative humidity Maximal 95% / 24°CMiddle 75% / 17°C(withoutcondensation)Air pressureoperation storage 795 to 1080 hPa 660 to 1080 hPaEMC guidelinesCE labelling DIN EN 61326-1:1998EN 50 081-1EN 50 082-2 Physical RequirementsVibration during operation IEC 1131-2Shock stress during operation IEC 1131-2Free fall IEC 1131-2/68-2-32English 03/99 BT 200 (S)J31069-D0075-U001-A1-7618Page 20Abbreviations Bd Baud (1 Bd = 1 character (bit/second)BTPhysical bus test device CPCommunications processor EMCElectromagnetic compatibility MBd1 MBd = 106 baud NiCdNickel cadmium NNMiles above sea level OPOperator panel PGProgrammer RTS Request to sendInfo Info Info Info Info Info Info This document can be downloaded free of charge from the Internet under the following URL:http:\\www.ad.siemens.de\simatic-csContinuous current information on SIMATIC products is available on the Internet under:http:\\www.ad.siemens.de\simaticSIMATIC Customer Support can be reached under:Tel. +49 (911) 895 7000Fax. +49 (911) 895 7002Siemens AGBereich Automatisierungs- und Antriebstecnik Geschäftsgebiet KombinationstechnikA&D SEPostfach 2355, D-90713 Fürth©Siemens AG 1999Subject to change without prior noticeSiemens AktiengesellschaftOrder-no.: (S)J13069-D0075-U001-A1-7618Printed in the Federal Republic of Germany。

GS8160Z36中文资料

A6 A7 E1 E2 NC NC BB BA E3 VDD VSS CK W CKE G ADV A18 A17 A8 A9
A19 NC NC VDDQ VSS NC DQA9 DQA8 DQA7 VSS VDDQ DQA6 DQA5 VSS NC VDD ZZ DQA4 DQA3 VDDQ VSS DQA2 DQA1 NC NC VSS VDDQ NC NC NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 1M x 18 10 71 Top View 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
元器件交易网
Preliminary GS8160Z18/36T-225/200/180/166/150/133 GS8160Z36T Pinout
DQC9 DQC8 DQC7 VDDQ VSS DQC6 DQC5 DQC4 DQC3 VSS VDDQ DQC2 DQC1 FT VDD VDD VSS DQD1 DQD2 VDDQ VSS DQD3 DQD4 DQD5 DQD6 VSS VDDQ DQD7 DQD8 DQD9
NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.

GS881Z36T-66I中文资料

Rev: 1.10 8/20001/34© 1998, Giga Semiconductor, Inc.Specifications cited are subject to change without notice. For latest documentation see .NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.PreliminaryGS881Z18/36T-11/100/80/668Mb Pipelined and Flow Through Synchronous NBT SRAMs 100 MHz–66 MHz3.3 V V DD2.5 V and3.3 V V DDQ100-Pin TQFP Commercial Temp Industrial TempRev: 1.10 8/20002/34© 1998, Giga Semiconductor, Inc.Specifications cited are subject to change without notice. For latest documentation see Preliminary.GS881Z18/36T-11/100/80/66Rev: 1.10 8/20003/34© 1998, Giga Semiconductor, Inc.Specifications cited are subject to change without notice. For latest documentation see Preliminary.GS881Z18/36T-11/100/80/66Rev: 1.10 8/20004/34© 1998, Giga Semiconductor, Inc.Specifications cited are subject to change without notice. For latest documentation see Preliminary.GS881Z18/36T-11/100/80/66Rev: 1.10 8/20005/34© 1998, Giga Semiconductor, Inc.Specifications cited are subject to change without notice. For latest documentation see Preliminary.GS881Z18/36T-11/100/80/66Rev: 1.10 8/20006/34© 1998, Giga Semiconductor, Inc.Specifications cited are subject to change without notice. For latest documentation see Preliminary.GS881Z18/36T-11/100/80/66Rev: 1.10 8/20007/34© 1998, Giga Semiconductor, Inc.Specifications cited are subject to change without notice. For latest documentation see Preliminary.GS881Z18/36T-11/100/80/66Rev: 1.10 8/20008/34© 1998, Giga Semiconductor, Inc.Specifications cited are subject to change without notice. For latest documentation see Preliminary.GS881Z18/36T-11/100/80/66Rev: 1.10 8/20009/34© 1998, Giga Semiconductor, Inc.Specifications cited are subject to change without notice. For latest documentation see Preliminary.GS881Z18/36T-11/100/80/66Rev: 1.10 8/200010/34© 1998, Giga Semiconductor, Inc.Specifications cited are subject to change without notice. For latest documentation see Preliminary.GS881Z18/36T-11/100/80/66Rev: 1.10 8/200011/34© 1998, Giga Semiconductor, Inc.Specifications cited are subject to change without notice. For latest documentation see Preliminary.GS881Z18/36T-11/100/80/66Rev: 1.10 8/200012/34© 1998, Giga Semiconductor, Inc.Specifications cited are subject to change without notice. For latest documentation see Preliminary.GS881Z18/36T-11/100/80/66Rev: 1.10 8/200013/34© 1998, Giga Semiconductor, Inc.Specifications cited are subject to change without notice. For latest documentation see Preliminary.GS881Z18/36T-11/100/80/66Rev: 1.10 8/200014/34© 1998, Giga Semiconductor, Inc.Specifications cited are subject to change without notice. For latest documentation see Preliminary.GS881Z18/36T-11/100/80/66Rev: 1.10 8/200015/34© 1998, Giga Semiconductor, Inc.Specifications cited are subject to change without notice. For latest documentation see Preliminary.GS881Z18/36T-11/100/80/66Rev: 1.10 8/200016/34© 1998, Giga Semiconductor, Inc.Specifications cited are subject to change without notice. For latest documentation see Preliminary.GS881Z18/36T-11/100/80/66Rev: 1.10 8/200017/34© 1998, Giga Semiconductor, Inc.Specifications cited are subject to change without notice. For latest documentation see Preliminary.GS881Z18/36T-11/100/80/66Rev: 1.10 8/200018/34© 1998, Giga Semiconductor, Inc.Specifications cited are subject to change without notice. For latest documentation see Preliminary.GS881Z18/36T-11/100/80/66Rev: 1.10 8/200019/34© 1998, Giga Semiconductor, Inc.Specifications cited are subject to change without notice. For latest documentation see Preliminary.GS881Z18/36T-11/100/80/66Rev: 1.10 8/200020/34© 1998, Giga Semiconductor, Inc.Specifications cited are subject to change without notice. For latest documentation see Preliminary.GS881Z18/36T-11/100/80/66Rev: 1.10 8/200021/34© 1998, Giga Semiconductor, Inc.Specifications cited are subject to change without notice. For latest documentation see Preliminary.GS881Z18/36T-11/100/80/66Rev: 1.10 8/200022/34© 1998, Giga Semiconductor, Inc.Specifications cited are subject to change without notice. For latest documentation see Preliminary.GS881Z18/36T-11/100/80/66Rev: 1.10 8/200023/34© 1998, Giga Semiconductor, Inc.Specifications cited are subject to change without notice. For latest documentation see Preliminary.GS881Z18/36T-11/100/80/66Rev: 1.10 8/200024/34© 1998, Giga Semiconductor, Inc.Specifications cited are subject to change without notice. For latest documentation see Preliminary.GS881Z18/36T-11/100/80/66Rev: 1.10 8/200025/34© 1998, Giga Semiconductor, Inc.Specifications cited are subject to change without notice. For latest documentation see Preliminary.GS881Z18/36T-11/100/80/66Rev: 1.10 8/200026/34© 1998, Giga Semiconductor, Inc.Specifications cited are subject to change without notice. For latest documentation see Preliminary.GS881Z18/36T-11/100/80/66Rev: 1.10 8/200027/34© 1998, Giga Semiconductor, Inc.Specifications cited are subject to change without notice. For latest documentation see Preliminary.GS881Z18/36T-11/100/80/66Rev: 1.10 8/200028/34© 1998, Giga Semiconductor, Inc.Specifications cited are subject to change without notice. For latest documentation see Preliminary.GS881Z18/36T-11/100/80/66Rev: 1.10 8/200029/34© 1998, Giga Semiconductor, Inc.Specifications cited are subject to change without notice. For latest documentation see Preliminary.GS881Z18/36T-11/100/80/66Rev: 1.10 8/200030/34© 1998, Giga Semiconductor, Inc.Specifications cited are subject to change without notice. For latest documentation see Preliminary.GS881Z18/36T-11/100/80/66Rev: 1.10 8/200031/34© 1998, Giga Semiconductor, Inc.Specifications cited are subject to change without notice. For latest documentation see Preliminary.GS881Z18/36T-11/100/80/66Rev: 1.10 8/200032/34© 1998, Giga Semiconductor, Inc.Specifications cited are subject to change without notice. For latest documentation see Preliminary.GS881Z18/36T-11/100/80/66Rev: 1.10 8/200033/34© 1998, Giga Semiconductor, Inc.Specifications cited are subject to change without notice. For latest documentation see Preliminary.GS881Z18/36T-11/100/80/66Rev: 1.10 8/200034/34© 1998, Giga Semiconductor, Inc.Specifications cited are subject to change without notice. For latest documentation see Preliminary.GS881Z18/36T-11/100/80/66。

GS881Z36BGD-200V中文资料

GS881Z18/32/36B(T/D)-xxxV9Mb Pipelined and Flow ThroughSynchronous NBT SRAM250 MHz–150 MHz 1.8 V or 2.5 V V DD 1.8 V or 2.5 V I/O100-Pin TQFP & 165-Bump BGA Commercial Temp Industrial Temp Features• User-configurable Pipeline and Flow Through mode• NBT (No Bus Turn Around) functionality allows zero wait read-write-read bus utilization• Fully pin-compatible with both pipelined and flow through NtRAM™, NoBL™ and ZBT™ SRAMs• IEEE 1149.1 JTAG-compatible Boundary Scan• On-chip write parity checking; even or odd selectable • 1.8 V or 2.5 V core power supply • 1.8 V or 2.5 V I/O supply• LBO pin for Linear or Interleave Burst mode • Pin-compatible with 2M, 4M, and 18M devices • Byte write operation (9-bit Bytes)• 3 chip enable signals for easy depth expansion • ZZ pin for automatic power-down • JEDEC-standard packages• RoHS-compliant 100-lead TQFP and 165-bump BGA packages availableFunctional DescriptionThe GS881Z18/32/36B(T/D)-xxxV is a 9Mbit Synchronous Static SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other pipelined read/double late write or flow through read/single late write SRAMs, allow utilization of all available bus bandwidth by eliminating the need to insert deselect cycles when the device is switched from read to write cycles.Because it is a synchronous device, address, data inputs, and read/ write control inputs are captured on the rising edge of the input clock. Burst order control (LBO) must be tied to a power rail for proper operation. Asynchronous inputs include the Sleep mode enable, ZZ and Output Enable. Output Enable can be used to override the synchronous control of the output drivers and turn the RAM's output drivers off at any time. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex off-chip write pulse generation required by asynchronous SRAMs and simplifies input signal timing.The GS881Z18/32/36B(T/D)-xxxV may be configured by the user to operate in Pipeline or Flow Through mode. Operating as a pipelined synchronous device, in addition to the rising-edge-triggered registers that capture input signals, the device incorporates a rising-edge-triggered output register. For read cycles, pipelined SRAM output data is temporarily stored by the edge triggered output register during the access cycle and then released to the output drivers at the next rising edge of clock.The GS881Z18/32/36B(T/D)-xxxV is implemented with GSI's high performance CMOS technology and is available inJEDEC-standard 100-pin TQFP and 165-bump BGA packages.Paramter Synopsis-250-200-150UnitPipeline 3-1-1-1KQ tCycle 4.0 5.0 6.7ns Curr (x18)Curr (x32/x36)200230170195140160mA mA Flow Through 2-1-1-1t KQ tCycle 5.55.5 6.56.57.57.5ns ns Curr (x18)Curr (x32/x36)160185140160128145mA mA807978777675747372717069686766656463626160595857565554535251123456789101112131415161718192021222324252627282930V DDQ V SS DQ B DQ B V SS V DDQ DQ B DQ B FT V DD NC V SS DQ B DQ B6V DD V SS DQ B DQ B DQP BV SS V DDQ V DDQ V SS DQ A DQ A V SS V DDQ DQ A DQ A V SS NC V DD ZZ DQ A DQ A V DDQ V SS DQ A DQ A V SS V DDQ L B O A A A A A 1A 0T M S T D I V S SV D DT D O T C K A A A A A A 1A A E 1E 2 N C N C B BB AE 3C K W C K E VD DV S SG A D V N C A A AA 512K x 18Top View DQP A A NC NC NC NC NC NC NC NCNC NC NC NC NC NC NCNC NC 100999897969594939291908988878685848382813132333435363738394041424344454647484950GS881Z18/32/36B(T/D)-xxxVGS881Z18BT-xxxV 100-Pin TQFP Pinout (Package T)807978777675747372717069686766656463626160595857565554535251123456789101112131415161718192021222324252627282930V DDQ V SS DQ C DQ C V SS V DDQ DQ C DQ C FT V DD NC V SS DQ D DQ D2V DDQ V SS DQ D DQ D DQ D V SS V DDQ V DDQ V SS DQ B DQ B V SS V DDQ DQ B DQ B V SS NC V DD ZZ DQ A DQ A V DDQ V SS DQ A DQ A V SS V DDQ L B O A A A A A 1A 0T M S T D I V S SV D DT D O T C K A A A A A AA A E 1E 2 B DB CB BB AE 3C K W C K E VD DV S SG A D V N C A A AA 256K x 32Top View DQB NC DQ B DQ B DQ B DQ A DQ A DQ A DQ A NCDQ C DQ C DQ C DQ D DQ D DQ D NCDQ C NC 100999897969594939291908988878685848382813132333435363738394041424344454647484950GS881Z18/32/36B(T/D)-xxxVGS881Z32BT-xxxV 100-Pin TQFP Pinout (Package T)807978777675747372717069686766656463626160595857565554535251123456789101112131415161718192021222324252627282930V DDQ V SS DQ C DQ C V SS V DDQ DQ C DQ C FT V DD NC V SS DQ D DQ D2V DDQ V SS DQ D DQ D DQ D V SS V DDQ V DDQ V SS DQ B DQ B V SS V DDQ DQ B DQ B V SS NC V DD ZZ DQ A DQ A V DDQ V SS DQ A DQ A V SS V DDQ L B O A A A A A 1A 0T M S T D I V S SV D DT D O T C K A A A A A AA A E 1E 2 B DB CB BB AE 3C K W C K E VD DV S SG A D V N C A A AA 256K x 36Top View DQB DQP B DQ B DQ B DQ B DQ A DQ A DQ A DQ A DQP ADQ C DQ C DQ C DQ D DQ D DQ D DQP DDQ C DQP C 100999897969594939291908988878685848382813132333435363738394041424344454647484950GS881Z18/32/36B(T/D)-xxxVGS881Z36BT-xxxV 100-Pin TQFP Pinout (Package T)100-Pin TQFP Pin DescriptionsSymbolTypeDescriptionA 0, A 1In Burst Address Inputs; Preload the burst counterA In Address Inputs CK In Clock Input SignalB A In Byte Write signal for data inputs DQ A1–DQ A9; active low B B In Byte Write signal for data inputs DQ B1–DQ B9; active low BC In Byte Write signal for data inputs DQ C1–DQ C9; active low BD In Byte Write signal for data inputs DQ D1–DQ D9; active lowW In Write Enable; active low E 1In Chip Enable; active lowE 2In Chip Enable—Active High. For self decoded depth expansion E 3In Chip Enable—Active Low. For self decoded depth expansionG In Output Enable; active lowADV In Advance/Load; Burst address counter control pinCKE In Clock Input Buffer Enable; active lowNC —No ConnectDQ A I/O Byte A Data Input and Output pins DQ B I/O Byte B Data Input and Output pins DQ C I/O Byte C Data Input and Output pins DQ D I/O Byte D Data Input and Output pins ZZ In Power down control; active high FT In Pipeline/Flow Through Mode Control; active lowLBO InLinear Burst Order; active low.TMS Scan Test Mode Select TDI Scan Test Data In TDO Scan Test Data Out TCK Scan Test Clock V DD In Core power supplyV SS In GroundV DDQInOutput driver power supplyGS881Z18/32/36B(T/D)-xxxVGS881Z18/32/36B(T/D)-xxxV165 Bump BGA—x18 Commom I/O—Top View 1234567891011A NC A E1BB NC E3CKE ADV A17A A A B NC A E2NC BA CK W G NC A NC B C NC NC V DDQ V SS V SS V SS V SS V SS V DDQ NC DQA C D NC DQB V DDQ V DD V SS V SS V SS V DD V DDQ NC DQA D E NC DQB V DDQ V DD V SS V SS V SS V DD V DDQ NC DQA E F NC DQB V DDQ V DD V SS V SS V SS V DD V DDQ NC DQA F G NC DQB V DDQ V DD V SS V SS V SS V DD V DDQ NC DQA G H FT MCH NC V DD V SS V SS V SS V DD NC NC ZZ H J DQB NC V DDQ V DD V SS V SS V SS V DD V DDQ DQA NC J K DQB NC V DDQ V DD V SS V SS V SS V DD V DDQ DQA NC K L DQB NC V DDQ V DD V SS V SS V SS V DD V DDQ DQA NC L M DQB NC V DDQ V DD V SS V SS V SS V DD V DDQ DQA NC M N DQB NC V DDQ V SS NC NC NC V SS V DDQ NC NC N P NC NC A A TDI A1TDO A A A NC P RLBONCAATMSA0TCKAAAAR11 x 15 Bump BGA—13 mm x 15 mm Body—1.0 mm Bump Pitch(Package D)GS881Z18/32/36B(T/D)-xxxV165 Bump BGA—x32 Common I/O—Top View 1234567891011A NC A E1BC BB E3CKE ADV A17A NC A B NC A E2BD BA CK W G NC A NC B C NC NC V DDQ V SS V SS V SS V SS V SS V DDQ NC NC C D DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB D E DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB E F DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB F G DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB G H FT MCH NC V DD V SS V SS V SS V DD NC NC ZZ H J DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA J K DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA K L DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA L M DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA M N NC NC V DDQ V SS NC NC NC V SS V DDQ NC NC N P NC NC A A TDI A1TDO A A A NC P RLBONCAATMSA0TCKAAAAR11 x 15 Bump BGA—13 mm x 15 mm Body—1.0 mm Bump Pitch(Package D)GS881Z18/32/36B(T/D)-xxxV165 Bump BGA—x36 Common I/O—Top View 1234567891011A NC A E1BC BB E3CKE ADV A A NC A B NC A E2BD BA CK W G NC A NC B C DQPC NC V DDQ V SS V SS V SS V SS V SS V DDQ NC DQPB C D DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB D E DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB E F DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB F G DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB G H FT MCH NC V DD V SS V SS V SS V DD NC NC ZZ H J DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA J K DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA K L DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA L M DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA M N DQPD NC V DDQ V SS NC NC NC V SS V DDQ NC DQPA N P NC NC A A TDI A1TDO A A A NC P RLBONCAATMSA0TCKAAAAR11 x 15 Bump BGA—13 mm x 15 mm Body—1.0 mm Bump Pitch(Package D)GS881Z18/32/36D-xxxV165-Bump BGA Pin DescriptionSymbolTypeDescriptionA 0, A 1I Address field LSBs and Address Counter Preset InputsA I Address Inputs DQ A DQB DQC DQD I/O Data Input and Output pinsB A , B B , BC , B DI Byte Write Enable for DQ A , DQ B , DQ C , DQ D I/Os; active lowNC —No ConnectCK I Clock Input Signal; active high CKE I Clock Enable; active low W I Write Enable; active low E 1I Chip Enable; active low E 3I Chip Enable; active low E 2I Chip Enable; active high G I Output Enable; active lowADV I Burst address counter advance enable; active highZZ I Sleep mode control; active high FT I Flow Through or Pipeline mode; active low LBO I Linear Burst Order mode; active lowTMS I Scan Test Mode Select TDI I Scan Test Data In TDO O Scan Test Data Out TCK I Scan Test Clock MCH —Must Connect High DNU —Do Not Use V DD I Core power supply V SS I I/O and Core Ground V DDQIOutput driver power supplyGS881Z18/32/36B(T/D)-xxxVK18S A 1S A 0Bu r s t C o u n t e rL B OA D VM e m o r y A r r a yGC KC K ED QF TN CN CD Q a –D Q nKS A 1’S A 0’D QM a t c hW r i t e A d d r e s sR e g i s t e r 2W r i t e A d d r e s sR e g i s t e r 1W r i t e D a t aR e g i s t e r 2W r i t e D a t aR e g i s t e r 1KKKKKKS e n s e A m p sW r i t e D r i v e r sR e a d , W r i t e a n dD a t a C o h e r e n c yC o n t r o l L o g i cD QKP a r i t y C h e c kF TA 0–A nE 3E 2E 1WB DB CB BB AGS881Z18/32/36B(T/D)-xxxVGS881Z18/32/36B(T/D)-xxxV NBT SRAM Functional Block DiagramGS881Z18/32/36B(T/D)-xxxVFunctional DetailsClockingDeassertion of the Clock Enable (CKE) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in erratic operation.Pipeline Mode Read and Write OperationsAll inputs (with the exception of Output Enable, Linear Burst Order and Sleep) are synchronized to rising clock edges. Single cycle read and write operations must be initiated with the Advance/Load pin (ADV) held low, in order to load the new address. Device activation is accomplished by asserting all three of the Chip Enable inputs (E 1, E 2 and E 3). Deassertion of any one of the Enable inputs will deactivate the device. Function W B A B B B C B D Read H X X X X Write Byte “a”L L H H H Write Byte “b”L H L H H Write Byte “c”L H H L H Write Byte “d”L H H H L Write all Bytes L L L L L Write Abort/NOPLHHHHRead operation is initiated when the following conditions are satisfied at the rising edge of clock: CKE is asserted low, all three chip enables (E 1, E 2, and E 3) are active, the write enable input signals W is deasserted high, and ADV is asserted low. The address presented to the address inputs is latched in to address register and presented to the memory core and control logic. The control logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At the next rising edge of clock the read data is allowed to propagate through the output register and onto the output pins.Write operation occurs when the RAM is selected, CKE is active and the write input is sampled low at the rising edge of clock. The Byte Write Enable inputs (B A , B B , B C & B D ) determine which bytes will be written. All or none may be activated. A write cycle with no Byte Write inputs active is a no-op cycle. The pipelined NBT SRAM provides double late write functionality, matching the write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). At the first rising edge of clock, Enable, Write, Byte Write(s), and Address are registered. The Data In associated with that address is required at the third rising edge of clock.Flow Through Mode Read and Write OperationsOperation of the RAM in Flow Through mode is very similar to operations in Pipeline mode. Activation of a read cycle and the use of the Burst Address Counter is identical. In Flow Through mode the device may begin driving out new data immediately after new address are clocked into the RAM, rather than holding new data until the following (second) clock edge. Therefore, in Flow Through mode the read pipeline is one cycle shorter than in Pipeline mode.Write operations are initiated in the same way, but differ in that the write pipeline is one cycle shorter as well, preserving the ability to turn the bus from reads to writes without inserting any dead cycles. While the pipelined NBT RAMs implement a double late write protocol, in Flow Through mode a single late write protocol mode is observed. Therefore, in Flow Through mode, address and control are registered on the first rising edge of clock and data in is required at the data input pins at the second rising edge of clock.Synchronous Truth TableOperationType Address CK CKE ADV W Bx E 1E 2E 3G ZZDQNotesRead Cycle, Begin Burst R External L-H L L H X L H L L L Q Read Cycle, Continue Burst B Next L-H L H X X X X X L L Q 1,10NOP/Read, Begin Burst R External L-H L L H X L H L H L High-Z 2Dummy Read, Continue Burst B Next L-H L H X X X X X H L High-Z 1,2,10Write Cycle, Begin Burst W External L-H L L L L L H L X L D 3Write Cycle, Continue Burst B Next L-H L H X L X X X X L D1,3,10Write Abort, Continue Burst B Next L-H L H X H X X X X L High-Z 1,2,3,10Deselect Cycle, Power Down D None L-H L L X X H X X X L High-Z Deselect Cycle, Power Down D None L-H L L X X X X H X L High-Z Deselect Cycle, Power Down D None L-H L L X X X L X X L High-Z Deselect Cycle D None L-H L L L H L H L X L High-Z 1Deselect Cycle, Continue DNone L-H L H X X X X X X L High-Z 1Sleep ModeNone X X X X X X X X X H High-Z Clock Edge Ignore, StallCurrentL-HHXXXXXXXL-4Notes:1.Continue Burst cycles, whether read or write, use the same control inputs. A Deselect continue cycle can only be entered into if a Dese-lect cycle is executed first.2.Dummy Read and Write abort can be considered NOPs because the SRAM performs no operation. A Write abort occurs when the Wpin is sampled low but no Byte Write pins are active so no write operation is performed.3.G can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off duringwrite cycles.4.If CKE High occurs during a pipelined read cycle, the DQ bus will remain active (Low Z). If CKE High occurs during a write cycle, the buswill remain in High Z.5. X = Don’t Care; H = Logic High; L = Logic Low; Bx = High = All Byte Write signals are high; Bx = Low = One or more Byte/Writesignals are Low6.All inputs, except G and ZZ must meet setup and hold times of rising clock edge.7.Wait states can be inserted by setting CKE high.8.This device contains circuitry that ensures all outputs are in High Z during power-up.9. A 2-bit burst counter is incorporated.10.The address counter is incriminated for all Burst continue cycles.GS881Z18/32/36B(T/D)-xxxVGS881Z18/32/36B(T/D)-xxxVDeselectNew ReadNew WriteBurst ReadBurst WriteWRBRBWDDBBWRD BWRDDCurrent State (n)Next State (n+1)TransitionƒInput Command CodeKeyNotes:1. The Hold command (CKE Low) is notshown because it prevents any state change.2. W, R, B, and D represent input commandcodes as indicated in the Synchronous Truth Table.Clock (CK)CommandCurrent StateNext Stateƒnn+1n+2n+3ƒƒƒCurrent State and Next State Definition for Pipelined and Flow Through Read/Write Control State DiagramWRPipelined and Flow Through Read Write Control State DiagramGS881Z18/32/36B(T/D)-xxxVIntermediateIntermediateIntermediateIntermediateIntermediateIntermediateHigh Z (Data In)Data Out (Q Valid)High Z B W B R B DRW RWDDCurrent State (n)TransitionƒInput Command CodeKeyTransitionIntermediate State (N+1)Notes:1. The Hold command (CKE Low) is notshown because it prevents any state change.2. W, R, B, and D represent input command codes as indicated in the Truth Tables.Clock (CK)CommandCurrent StateIntermediate ƒn n+1n+2n+3ƒƒƒCurrent State and Next State Definition for Pipeline Mode Data I/O State DiagramNext StateStatePipeline Mode Data I/O State DiagramGS881Z18/32/36B(T/D)-xxxVFlow Through Mode Data I/O State Diagram High Z (Data In)Data Out (Q Valid)High Z B W B R B DRW RWDDCurrent State (n)Next State (n+1)TransitionƒInput Command CodeKeyNotes:1. The Hold command (CKE Low) is notshown because it prevents any state change.2. W, R, B, and D represent input command codes as indicated in the Truth Tables.Clock (CK)CommandCurrent StateNext Stateƒnn+1n+2n+3ƒƒƒCurrent State and Next State Definition for: Pipeline and Flow through Read Write Control State DiagramGS881Z18/32/36B(T/D)-xxxVBurst CyclesAlthough NBT RAMs are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from read to write, multiple back-to-back reads or writes may also be performed. NBT SRAMs provide an on-chip burst address generator that can be utilized, if desired, to further simplify burst read or write implementations. The ADV control pin, when driven high, commands the SRAM to advance the internal address counter and use the counter generated address to read or write the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into Load mode.Burst OrderThe burst address counter wraps around to its initial state after four addresses (the loaded address and three more) have beenaccessed. The burst sequence is determined by the state of the Linear Burst Order pin (LBO). When this pin is low, a linear burst sequence is selected. When the RAM is installed with the LBO pin tied high, Interleaved burst sequence is selected. See the tables below for details.Mode Pin FunctionsMode NamePin NameStateFunctionBurst Order Control LBO L Linear Burst H Interleaved Burst Output Register Control FT L Flow Through H or NC Pipeline Power Down ControlZZL or NC Active HStandby, I DD = I SBNote:There is a pull-up device on the FT pin and a pull-down device on the ZZ pin, so this input pin can be unconnected and the chip will operate in the default states as specified in the above table.Note:The burst counter wraps to initial state on the 5th clock.Note:The burst counter wraps to initial state on the 5th clock.Linear Burst SequenceA[1:0]A[1:0]A[1:0]A[1:0]1st address 000110112nd address 011011003rd address 101100014th address11000110Interleaved Burst SequenceA[1:0]A[1:0]A[1:0]A[1:0]1st address 000110112nd address 010011103rd address 101100014th address11100100Burst Counter SequencesBPR 1999.05.18GS881Z18/32/36B(T/D)-xxxVSleep ModeDuring normal operation, ZZ must be pulled low, either by the user or by it’s internal pull down resistor. When ZZ is pulled high, the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM operates normally after ZZ recovery time.Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to I SB 2. The duration of Sleep mode is dictated by the length of time the ZZ is in a high state. After entering Sleep mode, all inputs except ZZ become disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode. When the ZZ pin is driven high, I SB 2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands may be applied while the SRAM is recovering from Sleep mode.Sleep Mode Timing DiagramtZZRtZZHtZZStKLtKHtKCCKZZDesigning for CompatibilityThe GSI NBT SRAMs offer users a configurable selection between Flow Through mode and Pipelinemode via the FT signal found on Pin 14. Not all vendors offer this option, however most mark Pin 14 as V DD or V DDQ on pipelined parts and V SS on flow through parts. GSI NBT SRAMs are fully compatible with these sockets.Pin 66, a No Connect (NC) on GSI’s GS8160Z18/36 NBT SRAM, the Parity Error open drain output on GSI’s GS881Z18/36B NBT SRAM, is often marked as a power pin on other vendor’s NBT compatible SRAMs. Specifically, it is marked V DD or V DDQ on pipelined parts and V SS on flow through parts. Users of GSI NBT devices who are not actually using the ByteSafe™ parity feature may want to design the board site for the RAM with Pin 66 tied high through a 1k ohm resistor in Pipeline modeapplications or tied low in Flow Through mode applications in order to keep the option to use non-configurable devices open.Absolute Maximum Ratings(All voltages reference to V SS )SymbolDescriptionValueUnitV DD Voltage on V DD Pins –0.5 to 4.6V V DDQ Voltage on V DDQ Pins –0.5 to V DDV V I/O Voltage on I/O Pins –0.5 to V DDQ +0.5 (≤ 4.6 V max.)V V IN Voltage on Other Input Pins –0.5 to V DD +0.5 (≤ 4.6 V max.)V I IN Input Current on Any Pin +/–20mA I OUT Output Current on Any I/O Pin +/–20mA P D Package Power Dissipation 1.5WT STG Storage Temperature –55 to 125o C T BIASTemperature Under Bias–55 to 125oCGS881Z18/32/36B(T/D)-xxxVNote:Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component. Power Supply Voltage Ranges (1.8 V/2.5 V Version)ParameterSymbolMin.Typ.Max.UnitNotes1.8 V Supply Voltage V DD1 1.7 1.82.0V 2.5 V Supply Voltage V DD2 2.3 2.5 2.7V 1.8 V V DDQ I/O Supply Voltage V DDQ1 1.7 1.8V DD V 2.5 V V DDQ I/O Supply VoltageV DDQ22.32.5V DDVNotes:1.The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-tions quoted are evaluated for worst case in the temperature range marked on the device.2.Input Under/overshoot voltage must be –2 V > Vi < V DDn +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.GS881Z18/32/36B(T/D)-xxxVV DDQ2 & V DDQ1 Range Logic LevelsParameterSymbolMin.Typ.Max.UnitNotesV DD Input High Voltage V IH 0.6*V DD —V DD + 0.3V 1V DD Input Low VoltageV IL–0.3—0.3*V DDV1Notes:1.The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-tions quoted are evaluated for worst case in the temperature range marked on the device.2.Input Under/overshoot voltage must be –2 V > Vi < V DDn +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.Recommended Operating TemperaturesParameterSymbolMin.Typ.Max.UnitNotesAmbient Temperature (Commercial Range Versions)T A 02570°C 2Ambient Temperature (Industrial Range Versions)T A–402585°C2Notes:1.The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-tions quoted are evaluated for worst case in the temperature range marked on the device.2.Input Under/overshoot voltage must be –2 V > Vi < V DDn +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.20% tKCV SS – 2.0 V50%V SS V IHUndershoot Measurement and TimingOvershoot Measurement and Timing20% tKCV DD + 2.0 V50%V DDV ILCapacitanceo C, f = 1 MH Z , V DD ParameterSymbolTest conditionsTyp.Max.UnitInput Capacitance C IN V IN = 0 V 45pF Input/Output Capacitance C I/OV OUT = 0 V67pFNote:These parameters are sample tested.(T A = 25= 2.5 V)AC Test ConditionsParameterConditionsDQV DDQ/250Ω30pF *Output Load 1* Distributed Test Jig CapacitanceFigure 1Input high level V DD – 0.2 V Input low level 0.2 V Input slew rate 1 V/ns Input reference level V DD /2Output reference levelV DDQ /2Output loadFig. 11.Include scope and jig capacitance.2.Test conditions as specified with output loading as shown in Fig. 1unless otherwise noted.3.Device is deselected as defined by the Truth Table. GS881Z18/32/36B(T/D)-xxxVDC Electrical CharacteristicsParameterSymbolTest ConditionsMinMaxInput Leakage Current (except mode pins)I IL V IN = 0 to V DD –1 uA 1 uA FT, ZZ Input Current I IN V DD ≥ V IN ≥ 0 V –100 uA 100 uA Output Leakage CurrentI OLOutput Disable, V OUT = 0 to V DD–1 uA1 uADC Output Characteristics (1.8 V/2.5 V Version)ParameterSymbolTest ConditionsMinMax1.8 V Output High Voltage V OH1I OH = –4 mA, V DDQ = 1.6 V V DDQ – 0.4 V —2.5 V Output High Voltage V OH2I OH = –8 mA, V DDQ = 2.375 V1.7 V —1.8 V Output Low Voltage V OL1I OL = 4 mA —0.4 V2.5 V Output Low VoltageV OL2I OL = 8 mA—0.4 VGS881Z18/32/36B(T/D)-xxxVOperating CurrentsParameterTest ConditionsModeSymbol-250-200-150Unit0to 70°C–40 to 85°C0to 70°C –40to 85°C 0 to 70°C –40to 85°COperating CurrentDevice Selected; All other inputs ≥V IH o r ≤ V IL Output open(x32/x36)PipelineI DD I DDQ 200302203017025190251402016020mA Flow Through I DD I DDQ 160251802514020160201301515015mA (x18)PipelineI DD I DDQ 185152051515515175151301015010mA Flow ThroughI DD I DDQ 1451516515130101501012081408mA Standby Current ZZ ≥ V DD – 0.2 V —Pipeline I SB 405040504050mA Flow Through I SB 405040504050mA Deselect CurrentDevice Deselected; All other inputs ≥ V IH or ≤ V IL—PipelineI DD 859075806065mA Flow Through I DD606550555055mA1.I DD and I DDQ apply to any combination of V DD1, V DD2, V DDQ1, and V DDQ2 operation.2.All parameters listed are worst case scenario.。

SG2813中文资料

DESCRIPTIONThe SG2800 series integrates eight NPN Darlington pairs with internal suppression diodes to drive lamps, relays, and solenoids in many military, aerospace, and industrial applications that require severe environments. All units feature open collector outputs with greater than 50V breakdown voltages combined with 500mA current carrying capabilities. Five different input configurations provide optimized designs for interfacing with DTL, TTL, PMOS, or CMOS drive signals. These devices are designed to operate from -55°C to 125°C ambient temperature in a 18-pin dual in-line ceramic (J) package and 20-pin leadless chip carrier (LCC).FEATURES•Eight NPN Darlington pairs•Collector currents to 600mA•Output voltages from 50V to 95V•Internal clamping diodes for inductive loads •DTL, TTL, PMOS, or CMOS compatible inputs •Hermetic ceramic packageHIGH RELIABILITY FEATURES♦Available to MIL-STD-883 and DESC SMD♦MIL-M38510/14106BVA - JAN2801J♦MIL-M38510/14107BVA - JAN2802J♦MIL-M38510/14108BVA - JAN2803J♦MIL-M38510/14109BVA - JAN2804J♦Radiation data available♦LMI level "S" processing availableHIGH VOLTAGE MEDIUM CURRENT DRIVER ARRAYSPARTIAL SCHEMATICSABSOLUTE MAXIMUM RATINGS (Note 1)Continuous Collector Current, I C(SG2800, 2820) ......................................................(SG2810) ...............................................................Operating Junction TemperatureHermetic (J, L Packages) .........................................Plastic (N Package) ..................................................Storage Temperature Range ..........................Lead Temperature (Soldering 10 sec.) .........................Output Voltage, V CE(SG2800, 2810 series) ................................................(SG2820 series) ..........................................................Input Voltage, V IN(SG2802,3,4 series) ....................................................Continuous Input Current, I IN ........................................50V 95V 30V 25mA500mA 600mA 150°C 150°C -65°C to 150°C 300°CNote 1. Values beyond which damage may occur.J Package:Thermal Resistance-Junction to Case , θJC .................. 25°C/W Thermal Resistance-Junction to Ambient , θJA ...............70°C/W N Package:Thermal Resistance-Junction to Case , θJC .................. 30°C/W Thermal Resistance-Junction to Ambient , θJA .............. 60°C/W L Package:Thermal Resistance-Junction to Case , θJC .................. 35°C/W Thermal Resistance-Junction to Ambient , θJA .............120°C/WTHERMAL DATANote A.Junction Temperature Calculation: T J = T A + (P D x θJA ).Note B.The above numbers for θJC are maximums for the limitingthermal resistance of the package in a standard mount-ing configuration. The θJA numbers are meant to be guidelines for the thermal performance of the device/pc-board system. All of the above assume no ambient airflow.Output Voltage, V CESG2800, SG2820 series ..............................................SG2810 series .............................................................50V 95VPeak Collector Current, I CSG2800, SG2820 series .........................................SG2810 series ........................................................Operating Ambient Temperature Range ........350mA 500mA -55°C to 125°CNote 2. Range over which the device is functional.RECOMMENDED OPERATING CONDITIONS (Note 2)SELECTION GUIDEDevice V CE Max I C Max Logic Inputs SG280150V 500mA General Purpose PMOS, CMOS SG280250V 500mA 14V-25V PMOS SG280350V 500mA 5V TTL, CMOSSG280450V 500mA 6V-15V CMOS, PMOS SG281150V 600mA General Purpose PMOS, CMOS SG281250V600mA14V-25V PMOSDevice V CE Max I C Max Logic Inputs SG281350V 600mA 5V TTL, CMOSSG281450V 600mA 6V-15V CMOS, PMOS SG281550V 600mA High Output TTL SG282195V 500mA General Purpose PMOS, CMOS SG282395V 500mA 5V TTL, CMOSSG282495V500mA6V-15V CMOS, PMOSCHARACTERISTIC CURVESFIGURE 4.INPUT CHARACTERISTICS - SG2802FIGURE 5.INPUT CHARACTERISTICS - SG2803FIGURE 6.INPUT CHARACTERISTICS - SG2804FIGURE 7.PEAK COLLECTOR CURRENT VS. DUTY CYCLEFIGURE 1.OUTPUT CHARACTERISTICS FIGURE 2.OUTPUT CURRENT VS. INPUT VOLTAGE FIGURE 3.OUTPUT CURRENT VS. INPUT CURRENTNote 1. Contact factory for JAN and DESC product availability.2. All parts are viewed from the top.3. See Selection Guide for specific device types.CONNECTION DIAGRAMS & ORDERING INFORMATION (See Notes Below)AmbientTemperature Range Part No. (Note 3)PackageConnection Diagram18-PIN CERAMIC DIP J - PACKAGESG28XXJ/883B -55°C to 125°C JAN2801J -55°C to 125°C JAN2802J -55°C to 125°C JAN2803J -55°C to 125°C JAN2804J-55°C to 125°C SG2803J/DESC -55°C to 125°C SG2821J/DESC -55°C to 125°C SG2823J/DESC -55°C to 125°C SG2824J/DESC -55°C to 125°C SG28XXJ-55°C to 125°C18-PIN PLASTIC DIP N- PACKAGESG2803N 0°C to 70°C SG2823N 0°C to 70°C 20-PIN CERAMICLEADLESS CHIP CARRIER L- PACKAGESG28XXL/883B -55°C to 125°C SG2803L/DESC -55°C to 125°C SG2821L/DESC -55°C to 125°C SG2823L/DESC -55°C to 125°C SG2824L/DESC -55°C to 125°C SG28XXL-55°C to 125°C1849319201214151716876513121110176543281110121314151716918。

GS8.2E快瘦机产品说明书

GS8.2E Fast Slimm i ng MachineManualCONTENTSParts introduction 1 Annex 1 Basic Operati o n 2 Functions and operation 2 Notice 4 Forbidden group 4 Technical parameters 5 Annex List 5Parts introduction7 8Annex shelf1 2 5 364Obve r seBack910 11 12 13Annex1、M80 ultrasound head jack2、Medium supersonic head jack3、Small supersonic head jack4、Add button 、Decrease bu t ton5、f u nction6、St a rt/pause7、G e neral power switch8、Power supply line9、work t i me10、Continuous Wave 11、Out p ut intensity 12、fu n ction 13、Pulse waveM80 ultrasound headMedium supersonic headSmall supersonic head— 1 —Basic Operation1、P l ace annex well and connect to mainframe.①Insert M80 ult r asound head to [1 ].②Insert medium supersonic he a d to[2].③Insert small supersonic head to [3].2. Connect power line [8],t u rn on General power switch[ 7].3. Press[ 5] fu c tion sele c t bu t ton, move to the right place ,the light will shining, press[4] .Sett i ng funct i on s,work t i me,work mode and output intensity, p ress [8] start working.4. During operation, if you want to change to o t her functions within the sett i ng time, pleasepress [6] first, a nd press [5] to change.5. Turn off the General power switch, unplug the power line when finished. Sterilize the usedWork h e ad.Functions and operationM80 u l trasound h e ad1. Applied gel on fleshy part s(eg.abdomen,hip,t h igh) The amount depends on moving flexibiliof the ultrasoun d head.2.Set work time(10 min every part),Adjust output int e nsity(1 weak~5 strong).3.Click “Start”, put the service brake under your feet, step on to start working, move away for pause4. Beautician hold t h e ultrasound h e ad to move slowly on skin, in circle or beeline repeatly,theother han d push the fat towards t h e ultrasound head.5.Do not use o n back,aviod using on bones.6.Do not use o n uterus part when women do abdomen care. A bdomen treatment duringMenst r uat e shou l d b e avoided.* Enough gel are needed, you may feel painful if medium is not enough.* The total treat m ent time for daily care should be within 30 min.7.The machine will pau s e aut o mat i cally if th e set t ing time is over.8.Clean the lef t overs wit h hot t o wel, use warm towel to clean the ultrasou n d head.—2 —Super s onic func t ionSupersonic has a mechanical,h y perthermia and biochemical effect,make local tissue cells can be micro-massaged,promote blood circulat i o n,sof t en organizat i ons, speed up chemicalreact i ons, and promot e metabolism.It can promote blood circulation and lymph circulation,t h us has the effect of detoxification, wrinkle removal,tightening,lifting, l ightening f l e c ks and eliminating pouch and dark circles.1.To clean deeply, a pply medium（nutrition gel, extract oil a n d etc）The amou n t sh o uld be according to moving f l exibility of ultrasound head.2.Set work time. Press [ 7] to choose medium or small ultrasound head according t o parts need cared.（Medium size head suit fo r face and arms,the small size f o r eye a n d nosewing.3.Set t ing work mod（1-continous wave output ,2-pulse wave）,to regulate output int e nsity according to diff e rent parts（1weak~9strong）4.Press start t o work.5.During operation, if you want t o chan g e to ot h er functions within the sett i ng t i me, pleasepress pause and then press [ 7] to move the curso r to the right place,t h en press [4] or [5] to Change,readjust work time,work mode,out p ut intensit y and press start.6.The machine will stop aut o matically if t h e set t ing time if over.e warm water to clean skin.8.St e rilize all the used ultrasound heads.—3 —Notice1. In operation, in o r der t o maint a in sufficient ge l.2.The ultraso u nd head should not stay out of work for to o lo n g time while outpu t ting energy.Click “pause” to stop working to avoid damage.3. M50, M80 ultrasound h e ads should not stay st i ll at one part for t o o long time,and do not use it on bones.4, Please step on service brake the n there will be sound wave exist when using M80 ultrasound head.5, M80 u l t r asound head can not be used on the back, avoid on the bo n es, and daily ca r e should Be within 30 minutes every time.6. Do not use on eyeba l l top , A d am' s apple, h eart .Do not stay st i ll on one part for to o lo n g. Forbidden group1.Peo p le who has fever, inf e ct i ous diseases, acut e diseases.2. People with heart disease or co n figured cardiac p a cemaker.3. Patients with severe high blood pressure, tumor disease, asthma, deep vein thrombosis,Varix, t h yroid ,cancer, falling sickness.4. People with hemorrhagic disease, trauma, vascular rupt u re, skin inflammation, skin disease.5.Pregnant women6. Do not use at the abdomen durin g men s trual period7. Medical P l astic p a rt s, or part s with metal inside8. People with an abnormal immune syst e m—4 —Technical parametersVolt a ge：AC 220V/50Hz or AC 110V/60Hz p o wer：≤75W Operating f r e q uency：1MHz/40KHzAnnex List1.Mainframe 1set2.Power supply line 1pc3. Use manual 1 c opy4. big ultrasound head 1pc5.Medium Ultrasound head (with wire) 1pc6.Small Ult r asound head (with wire) 1pc7.Ann e x shelf 1pc8.Hexa g onal screws 3pc—5 —。

GS88237AB-200I资料

元器件交易网
GS88237AB-250/225/200/166/150/133
119-Bump BGA Commercial Temp Industrial Temp
256K x 36 9Mb Synchronous Burst SRAMs
250 MHz–133 MHz 2.5 V or 3.3 V VDD 2.5 V or 3.3 V I/O
Core and Interface Voltages The GS88237AB operates on a 2.5 V or 3.3 V power supply. All input are 3.3 V and 2.5 V compatible. Separate output power (VDDQ) pins are used to decouple output noise from the internal circuits and are 3.3 V and 2.5 V compatible.
330 300 270 230 215 190 mA 320 295 265 225 210 185 mA
Rev: 1.02 11/2004
1/28
Specifications cited are subject to change without notice. For latest documentation see .
NC
VDD
VDDQ
K
DQD
DQD
VSS
CK
VSS
DQA
DQA
L
DQD DQD
BD
SCD
BA
DQA
DQA
M
VDDQ
DQD
VSS
BW

GS864418B-250中文资料

GS816273CC-333中文资料

GS816273CC-333/300/250256K x 7218Mb S/DCD Sync Burst SRAMs333 MHz –250 MHz 3.3 V or 2.5 V V DD 3.3 V or 2.5 V I/O209-Bump BGA Commercial Temp Industrial Temp Features• Single/Dual Cycle Deselect selectable• IEEE 1149.1 JTAG-compatible Boundary Scan• ZQ mode pin for user-selectable high/low output drive • 3.3 V or 2.5 V core power supply • 3.3 V or 2.5 V I/O supply• LBO pin for Linear or Interleaved Burst mode• Internal input resistors on mode pins allow floating mode pins • Default to SCD x18/x36 Interleaved Pipeline mode • Byte Write (BW) and/or Global Write (GW) operation • Internal self-timed write cycle• Automatic power-down for portable applications • JEDEC-standard 209-bump BGA package• RoHS-compliant 209-bump BGA package availableFunctional DescriptionApplicationsThe GS816273CC is an 18,874,368-bit high performancesynchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application insynchronous SRAM applications, ranging from DSP main store to networking chip set support.ControlsAddresses, data I/Os, chip enable (E1), address burst control inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive-edge-triggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burst cycles can be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by ADV. The burst address counter may be configured to count in either linear or interleave orderwith the Linear Burst Order (LBO) input. The Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance.SCD and DCD Pipelined ReadsThe GS816273CC is an SCD (Single Cycle Deselect) and DCD (Dual Cycle Deselect) pipelined synchronous SRAM. DCD SRAMs pipeline disable commands to the same degree as read commands. SCD SRAMs pipeline deselect commands one stage less than read commands. SCD RAMs begin turning off their outputs immediately after the deselect command has been captured in the input registers. DCD RAMs hold the deselect command for one full cycle and then begin turning off their outputs just after the second rising edge of clock. The user may configure this SRAM for either mode of operation using the SCD mode input.Byte Write and Global WriteByte write operation is performed by using Byte Write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the Byte Write control inputs.FLXDrive™The ZQ pin allows selection between high drive strength (ZQ low) for multi-drop bus applications and normal drive strength (ZQ floating or high) point-to-point applications. See the Output Driver Characteristics chart for details.Sleep ModeLow power (Sleep mode) is attained through the assertion (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode.Core and Interface VoltagesThe GS816273CC operates on a 3.3 V or 2.5 V power supply. All inputs are 3.3 V or 2.5 V compatible. Separate output power (V DDQ ) pins are used to decouple output noise from the internal circuits and are 3.3 V or 2.5 V compatible.Parameter Synopsis-333-300-250UnitPipeline 3-1-1-1KQ tCycle 3.0 3.3 4.0ns1234567891011ADQG DQG A E2ADSP ADSC ADV E3A DQB DQB B DQG DQG BC BG NC B A BB BF DQB DQB C DQG DQG BH BD NC E1NC BE BA DQB DQB D DQG DQG V SS NC NC G GW NC V SS DQB DQB E DQPG DQPC V DDQ V DDQ V DD V DD V DD V DDQ V DDQ DQPF DQPB F DQC DQC V SS V SS V SS ZQ V SS V SS V SS DQF DQF G DQC DQC V DDQ V DDQ V DD MCH V DD V DDQ V DDQ DQF DQF H DQC DQC V SS V SS V SS MCL V SS V SS V SS DQF DQF J DQC DQC V DDQ V DDQ V DD MCL V DD V DDQ V DDQ DQF DQF K NC NC CK NC V SS MCL V SS NC NC NC NC L DQH DQH V DDQ V DDQ V DD V DDQ /DNU V DD V DDQ V DDQ DQA DQA M DQH DQH V SS V SS V SS MCL V SS V SS V SS DQA DQA N DQH DQH V DDQ V DDQ V DD SCD V DD V DDQ V DDQ DQA DQA P DQH DQH V SS V SS V SS ZZ V SS V SS V SS DQA DQA R DQPD DQPH V DDQ V DDQ V DD V DD V DD V DDQ V DDQ DQPA DQPE T DQD DQD V SS NC NC LBO NC NC V SS DQE DQE U DQD DQD NC A A A A A NC DQE DQE V DQD DQD A A A A1A A A DQE DQE W DQDDQDTMSTDIAA0ATDOTCKDQEDQERev 1011 x 19 Bump BGA —14 x 22 mm 2 Body —1 mm Bump PitchGS816273CC-333/300/250GS816273C Pad Out—209-Bump BGA—Top View (Package C)GS816273CC-333/300/250GS816273C BGA Pin DescriptionSymbolTypeDescriptionA 0, A 1I Address field LSBs and Address Counter Preset Inputs.A IAddress InputsDQ A DQ B DQ C DQ D DQ E DQ F DQ G DQ HI/O Data Input and Output pinsB A , B B , BC ,B D, B E , B F , B G ,B HI Byte Write Enable for DQ A , DQ B , DQ C , DQ D, DQ E ,DQ F , DQ G , DQ H I/Os; active lowNC —No ConnectCK I Clock Input Signal; active highGW I Global Write Enable—Writes all bytes; active lowE 1, E 3I Chip Enable; active low E 2I Chip Enable; active high G I Output Enable; active lowADV I Burst address counter advance enable; active low ADSP, ADSCI Address Strobe (Processor, Cache Controller); active lowZZ I Sleep Mode control; active high LBO I Linear Burst Order mode; active lowSCD I Single Cycle Deselect/Dual Cycle Deselect Mode ControlMCH IMust Connect High MCL Must Connect Low BW I Byte Enable; active lowZQ I FLXDrive Output Impedance Control(Low = Low Impedance [High Drive], High = High Impedance [Low Drive])TMS I Scan Test Mode Select TDI I Scan Test Data In TDO O Scan Test Data Out TCK I Scan Test Clock V DD I Core power supply V SSII/O and Core GroundGS816273CC-333/300/250BPR1999.05.18V DDQ I Output driver power supply V DDQ /DNU—V DDQ or V DDorDo Not Use (must be left floating)GS816273C BGA Pin DescriptionSymbolTypeDescriptionGS816273CC-333/300/250GS816273C Block Diagram A1A0A0A1D0D1Q1Q0Counter LoadD QDQRegisterRegisterDQRegisterDQRegisterDQRegisterD QRegisterD QRegisterD QRegisterDQR e g i s t e rDQRegisterA0–An LBO ADV CK ADSC ADSP GW BW V DDQ /DNUGZZPower Down ControlMemory Array36364AQD DQx1–DQx93636Note: Only x36 version shown for simplicity.SCD3636B AB BB CB DE 1E 3E 2Mode Pin FunctionsMode NamePin NameStateFunctionBurst Order Control LBO L Linear Burst H Interleaved BurstPower Down Control ZZ L or NC Active H Standby, I DD = I SB Single/Dual Cycle Deselect Control SCD L Dual Cycle Deselect H or NC Single Cycle Deselect FLXDrive Output Impedance ControlZQL High Drive (Low Impedance)H or NCLow Drive (High Impedance)GS816273CC-333/300/250Note:There are pull-up devices on the ZQ and SCD pins and a pull-down device on the ZZ pin, so those input pins can be unconnected and the chip will operate in the default states as specified in the above tables.Note:The burst counter wraps to initial state on the 5th clock.Note:The burst counter wraps to initial state on the 5th clock.Linear Burst SequenceA[1:0]A[1:0]A[1:0]A[1:0]1st address 000110112nd address 011011003rd address 101100014th address11000110Interleaved Burst SequenceA[1:0]A[1:0]A[1:0]A[1:0]1st address 000110112nd address 010011103rd address 101100014th address11100100Burst Counter SequencesBPR 1999.05.18GS816273CC-333/300/250Byte Write Truth TableFunctionGWBWB AB BB CB DNotesRead H H X X X X 1Read H L H H H H 1Write byte a H L L H H H 2, 3Write byte b H L H L H H 2, 3Write byte c H L H H L H 2, 3, 4Write byte d H L H H H L 2, 3, 4Write all bytes H L L L L L 2, 3, 4Write all bytesLXXXXXNotes:1.All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.2.Byte Write Enable inputs B A , B B , B C , and/or B D may be used in any combination with BW to write single or multiple bytes.3.All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.4.Bytes “C ” and “D ” are only available on the x36 version.Synchronous Truth TableOperationAddress UsedState Diagram Key 5E 1E 2ADSPADSCADVW 3DQ 4Deselect Cycle, Power Down None X H X X L X X High-Z Read Cycle, Begin Burst External R L F L X X X Q Read Cycle, Begin Burst External R L F H L X F Q Write Cycle, Begin Burst External W L T H L X T D Read Cycle, Continue Burst Next CR X T H H L F Q Read Cycle, Continue Burst Next CR H T X H L F Q Write Cycle, Continue Burst Next CW X X H H L T D Write Cycle, Continue Burst Next CWH X X H L T D Read Cycle, Suspend Burst Current X X H H H F Q Read Cycle, Suspend Burst Current H X X H H F Q Write Cycle, Suspend Burst Current X X H H H T D Write Cycle, Suspend BurstCurrentHXXHHTDNotes:1.X = Don’t Care, H = High, L = Low2. E = T (True) if E 2 = 1 and E 3 = 0; E = F (False) if E 2 = 0 or E 3 = 1.3.W = T (True) and F (False) is defined in the Byte Write Truth Table preceding4.G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shownas “Q” in the Truth Table above).5.All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplishbasic synchronous or synchronous burst operations and may be avoided for simplicity.6.Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.7.Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.GS816273CC-333/300/250First WriteFirst ReadBurst WriteBurst ReadDeselect R WCRCWXXWRRWRXXX S i m p l e S y n c h r o n o u s O p e r a t i o nS i m p l e B u r s t S y n c h r o n o u s O p e r a t i o nCR RCWCRCRNotes:1.The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low.2.The upper portion of the diagram assumes active use of only the Enable (E1) and Write (B A , B B , B C , B D , BW, and GW) control inputs, andthat ADSP is tied high and ADSC is tied low.3.The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs andassumes ADSP is tied high and ADV is tied low.GS816273CC-333/300/250Simplified State DiagramFirst WriteFirst ReadBurst WriteBurst ReadDeselectR WCRCWXXWRRWRXXX CRR CW CRCRW CWW CWNotes:1.The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.e of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from read cycles to write cycles without passingthrough a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles.3.Transitions shown in grey tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meetData Input Set Up Time.GS816273CC-333/300/250Simplified State Diagram with GAbsolute Maximum Ratings(All voltages reference to V SS )SymbolDescriptionValueUnitV DD Voltage on V DD Pins –0.5 to 4.6V V DDQ Voltage in V DDQ Pins –0.5 to V DDV V I/O Voltage on I/O Pins –0.5 to V DDQ +0.5 (≤ 4.6 V max.)V V IN Voltage on Other Input Pins –0.5 to V DD +0.5 (≤ 4.6 V max.)V I IN Input Current on Any Pin +/–20mA I OUT Output Current on Any I/O Pin +/–20mA P D Package Power Dissipation 1.5WT STG Storage Temperature –55 to 125o C T BIASTemperature Under Bias–55 to 125o CGS816273CC-333/300/250Note:Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component. Power Supply Voltage RangesParameterSymbolMin.Typ.Max.Unit3.3 V Supply Voltage V DD3 3.0 3.3 3.6V 2.5 V Supply Voltage V DD2 2.3 2.5 2.7V 3.3 V V DDQ I/O Supply Voltage V DDQ3 3.0 3.3V DD V 2.5 V V DDQ I/O Supply VoltageV DDQ22.32.5V DDVV DDQ3 Range Logic LevelsParameterSymbolMin.Typ.Max.UnitNotesInput High Voltage V IH 2.0—V DD + 0.3V 1,2Input Low Voltage V IL –0.3—0.8V 1,2I/O Input High Voltage V IHQ 2.0—V DD + 0.3V 1,3I/O Input Low VoltageV ILQ–0.3—0.8V1,3Notes:4.Input Under/overshoot voltage must be –2 V > Vi < V DDn +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.5.Applies to input-only pins (e.g., address, clock, or control pins)6.Applies to I/O pins (e.g., DQ pins)GS816273CC-333/300/250V DDQ2 Range Logic LevelsParameterSymbolMin.Typ.Max.UnitNotesInput High Voltage V IH 0.6*V DD —V DD + 0.3V 1,2Input Low Voltage V IL –0.3—0.3*V DD V 1,2I/O Input High Voltage V IHQ 0.6*V DD —V DD + 0.3V 1,3I/O Input Low VoltageV ILQ–0.3—0.3*V DDV1,3Notes:1.Input Under/overshoot voltage must be –2 V > Vi < V DDn +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.2.Applies to input-only pins (e.g., address, clock, or control pins)3.Applies to I/O pins (e.g., DQ pins)20% tKCV SS – 2.0 V50%V SS V IHUndershoot Measurement and TimingOvershoot Measurement and Timing20% tKCV DD + 2.0 V50%V DDV ILRecommended Operating TemperaturesParameterSymbolMin.Typ.Max.UnitAmbient Temperature (Commercial Range Versions)T A 02570°C Ambient Temperature (Industrial Range Versions)T A–402585°CNote:The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device.Capacitanceo C, f = 1 MH Z , V DD ParameterSymbolTest conditionsTyp.Max.UnitInput Capacitance C IN V IN = 0 V 45pF Input/Output Capacitance C I/OV OUT = 0 V67pFNote:These parameters are sample tested.(T A = 25= 2.5 V)AC Test ConditionsParameterConditionsDQV DDQ/250Ω30pF *Output Load 1* Distributed Test Jig CapacitanceInput high level V DD – 0.2 V Input low level 0.2 V Input slew rate 1 V/ns Input reference level V DD /2Output reference levelV DDQ /2Output loadFig. 11.Include scope and jig capacitance.2.Test conditions as specified with output loading as shown in Fig. 1unless otherwise noted.3.Device is deselected as defined by the Truth Table. GS816273CC-333/300/250DC Electrical CharacteristicsParameterSymbolTest ConditionsMinMaxInput Leakage Current (except mode pins)I IL V IN = 0 to V DD –1 uA 1 uA FT, ZZ Input Current I IN V DD ≥ V IN ≥ 0 V –100 uA 100 uA Output Leakage CurrentI OLOutput Disable, V OUT = 0 to V DD–1 uA1 uADC Output CharacteristicsParameterSymbolTest ConditionsMinMax2.5 V Output High Voltage V OH2I OH = –8 mA, V DDQ = 2.375 V 1.7 V —3.3 V Output High Voltage V OH3I OH = –8 mA, V DDQ = 3.135 V2.4 V —Output Low VoltageV OLI OL = 8 mA—0.4 VGS816273CC-333/300/250Operating CurrentsParameterTest ConditionsModeSymbol-333-300-250Unit0to 70°C–40 to 85°C0to °C–40 to 85°C0to 70°C–40 to 85°COperating Current Device Selected; All other inputs ≥V IH o r ≤ V IL Output open PipelineI DD I DDQ 460854708541580425803507536075mAStandby Current ZZ ≥ V DD – 0.2 V Pipeline I SB 405040504050mADeselect CurrentDevice Deselected; All other inputs ≥ V IH or ≤ V ILPipeline I DD859085908590mANotes:1.I DD and I DDQ apply to any combination of V DD3, V DD2, V DDQ3, and V DDQ2 operation.2.All parameters listed are worst case scenario.AC Electrical CharacteristicsParameterSymbol-333-300-250UnitMinMax Min Max Min Max PipelineClock Cycle Time tKC 3.0— 3.3— 4.0—ns Clock to Output Valid tKQ — 2.8— 2.8— 3.0ns Clock to Output Invalid tKQX 1.5— 1.5— 1.5—ns Clock to Output in Low-ZtLZ 1 1.5— 1.5— 1.5—ns Setup time tS 1.0— 1.0— 1.2—ns Hold time tH 0.1—0.1—0.2—ns Clock HIGH Time tKH 1.0— 1.0— 1.3—ns Clock LOW Time tKL 1.2— 1.2— 1.5—ns Clock to Output inHigh-Z tHZ 1 1.5 2.8 1.5 2.8 1.5 3.0ns G to Output Valid tOE — 2.8— 2.8— 3.0ns G to output in Low-Z tOLZ 10—0—0—ns G to output in High-Z tOHZ 1— 2.8— 2.8— 3.0ns ZZ setup time tZZS 25—5—5—ns ZZ hold time tZZH 21—1—1—ns ZZ recoverytZZR20—20—20—nsGS816273CC-333/300/250Notes:1.These parameters are sampled and are not 100% tested.2.ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and holdtimes as specified above.GS816273CC-333/300/250Pipeline Mode Timing (SCD)Begin Read A Cont Cont Deselect Write B Read C Read C+1Read C+2Read C+3ContDeselecttHZtKQX tKQtLZtHtStOHZtOEtHtStHtStHtStHtStHtStStHtStHtStHtSBurst ReadtKCtKL tKH Single Write Single ReadQ(A)D(B)Q(C)Q(C+1)Q(C+2)Q(C+3)ABCDeselected with E1E1 masks ADSPE2 and E3 only sampled with ADSP and ADSCADSC initiated readCK ADSPADSCADVA0–AnGWBWBa–BdE1E2E3GDQa–DQdGS816273CC-333/300/250Pipeline Mode Timing (DCD)Begin Read A Cont Deselect Deselect Write BRead C Read C+1Read C+2Read C+3Cont Deselect DeselecttHZtKQXtKQtLZtHtStOHZtOEtHtStHtStHtStH tStHtStStHtStHtStHtStKCtKL tKHQ(A)D(B)Q(C)Q(C+1)Q(C+2)Q(C+3)ABCHi-ZDeselected with E1E2 and E3 only sampled with ADSCADSC initiated readCK ADSPADSCADVAo–AnGWBWBa–BdE1E2E3GDQa–DQdGS816273CC-333/300/250Sleep ModeDuring normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high, the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM operates normally after ZZ recovery time.Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to I SB 2. The duration of Sleep mode is dictated by the length of time the ZZ is in a High state. After entering Sleep mode, all inputs except ZZ become disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode. When the ZZ pin is driven high, I SB 2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands may be applied while the SRAM is recovering from Sleep mode.Sleep Mode TimingtZZRtZZHtZZSHoldSetup tKLtKHtKCCKADSP ADSCZZApplication TipsSingle and Dual Cycle DeselectSCD devices (like this one) force the use of “dummy read cycles” (read cycles that are launched normally, but that are ended with the output drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance, but their use usually assures there will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste bandwidth on dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at bank address boundary crossings), but greater care must be exercised to avoid excessive bus contention.GS816273CC-333/300/250JTAG Port OperationOverviewThe JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with V DD . The JTAG output drivers are powered by V DDQ .Disabling the JTAG PortIt is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG Port unused, TCK, TDI, and TMS may be left floating or tied to either V DD or V SS . TDO should be left unconnected.JTAG Pin Descriptions PinPin NameI/ODescriptionTCK Test Clock In Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate from the falling edge of TCK.TMSTest Mode SelectInThe TMS input is sampled on the rising edge of TCK. This is the command input for the TAP controller state machine. An undriven TMS input will produce the same result as a logic one input level.TDI Test Data In InThe TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers placed between TDI and TDO. The register placed between TDI and TDO is determined by the state of the TAP Controller state machine and the instruction that is currently loaded in the TAP Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce the same result as a logic one input level.TDO Test Data OutOut Output that is active depending on the state of the TAP state machine. Output changes inresponse to the falling edge of TCK. This is the output side of the serial registers placed betweenTDI and TDO.This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up.JTAG Port RegistersOverviewThe various JTAG registers, refered to as Test Access Port orTAP Registers, are selected (one at a time) via the sequences of 1s and 0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the rising edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the TDI and TDO pins.Instruction RegisterThe Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the controller is placed in Test-Logic-Reset state.Bypass RegisterThe Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through the RAM’s JTAG Port to another device in the scan chain with as little delay as possible.GS816273CC-333/300/250Boundary Scan RegisterThe Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins. The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is inCapture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z, SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.Instruction RegisterID Code RegisterBoundary Scan Register120····313029120Bypass RegisterTDITDOTMS TCKTest Access Port (TAP) ControllerM *·1·········Control Signals·* For the value of M, see the BSDL file, which is available at by contacting us at apps@.JTAG TAP Block DiagramIdentification (ID) RegisterThe ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put inCapture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM. It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.ID Register ContentsNot UsedGSI Technology JEDEC Vendor ID CodeP r e s e n c e R e g i s t e r Bit #313029282726252423222120191817161514131211109876543210XXXXXXXXXXXXXXXXXXXX00110110011GS816273CC-333/300/250Tap Controller Instruction SetOverviewThere are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific (Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must beimplemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load address, data or control signals into the RAM or to preload the I/O buffers.When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01. When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this device is listed in the following table.Select DRCapture DRShift DRExit1 DRPause DRExit2 DRUpdate DRSelect IRCapture IRShift IRExit1 IRPause IRExit2 IRUpdate IRTest Logic ResetRun Test Idle 01111111111111111GS816273CC-333/300/250JTAG Tap Controller State DiagramInstruction DescriptionsBYPASSWhen the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facili-tate testing of other devices in the scan path.SAMPLE/PRELOADSAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and I/O buffers into the Boundary Scan Register. Boundary Scan Register locations are not associated with an input or I/O pin, and are loaded with the default state identified in the Boundary Scan Chain table at the end of this section of the datasheet. Because the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be paused for any other TAP operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then places the boundary scan register between the TDI and TDO pins. EXTESTEXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with all logic 0s. The EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal state is still determined by its input pins.。

GS864436E-150中文资料

Preliminary GS864418/36E-xxxV4M x 18, 2M x 3672Mb S/DCD Sync Burst SRAMs 250 MHz –133MHz 1.8 V or 2.5 V V DD 1.8 V or 2.5 V I/O165-Bump BGA Commercial Temp Industrial Temp Features• FT pin for user-configurable flow through or pipeline operation • Single/Dual Cycle Deselect selectable• IEEE 1149.1 JTAG-compatible Boundary Scan• ZQ mode pin for user-selectable high/low output drive • 1.8 V or 2.5 V core power supply and I/O • LBO pin for Linear or Interleaved Burst mode• Internal input resistors on mode pins allow floating mode pins • Default to SCD x18/x36 Interleaved Pipeline mode • Byte Write (BW) and/or Global Write (GW) operation • Internal self-timed write cycle• Automatic power-down for portable applications • JEDEC-standard 165-bump BGA package• RoHS-compliant 165-bump BGA package availableFunctional DescriptionApplicationsThe GS864418/36E-xxxV is a 75,497,472-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support.ControlsAddresses, data I/Os, chip enable (E1), address burst control inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive-edge-triggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burst cycles can be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by ADV. The burst address counter may be configured to count in either linear or interleave order with the Linear Burst Order (LBO) input. The Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance.Flow Through/Pipeline ReadsThe function of the Data Output register can be controlled by the user via the FT mode . Holding the FT mode pin low places the RAM in Flow Through mode, causing output data to bypass theData Output Register. Holding FT high places the RAM inPipeline mode, activating the rising-edge-triggered Data Output Register.SCD and DCD Pipelined ReadsThe GS864418/36E-xxxV is a SCD (Single Cycle Deselect) and DCD (Dual Cycle Deselect) pipelined synchronous SRAM. DCD SRAMs pipeline disable commands to the same degree as read commands. SCD SRAMs pipeline deselect commands one stage less than read commands. SCD RAMs begin turning off their outputs immediately after the deselect command has been captured in the input registers. DCD RAMs hold the deselect command for one full cycle and then begin turning off their outputs just after the second rising edge of clock. The user may configure this SRAM for either mode of operation using the SCD mode input.Byte Write and Global WriteByte write operation is performed by using Byte Write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the Byte Write control inputs.FLXDrive™The ZQ pin allows selection between high drive strength (ZQ low) for multi-drop bus applications and normal drive strength (ZQ floating or high) point-to-point applications. See the Output Driver Characteristics chart for details.Sleep ModeLow power (Sleep mode) is attained through the assertion (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode.Core and Interface VoltagesThe GS864418/36E-xxxV operates on a 1.8 V or 2.5 V power supply. All inputs are 1.8 V and 2.5 V compatible. Separate output power (V DDQ ) pins are used to decouple output noise from the internal circuits and are 1.8 V and 2.5 V compatible.Parameter Synopsis-250-225-200-166-150-133UnitPipeline 3-1-1-1t KQ tCycle 3.04.0 3.04.4 3.05.0 3.06.0 3.36.7 3.57.5ns ns Curr (x36)450415385345325295mA Flow Through 2-1-1-1t KQ tCycle 6.5 6.5 6.58.08.58.5ns Curr (x36)290290290280265245mAGS864418/36E-xxxV165-Bump BGA—x18 Commom I/O—Top View (Package E)1234567891011A NC A E1BB NC E3BW ADSC ADV A A AB NC A E2NC BA CK GW G ADSP A NC BC NC NC V DDQ V SS V SS V SS V SS V SS V DDQ NC DQPA CD NC DQB V DDQ V DD V SS V SS V SS V DD V DDQ NC DQA DE NC DQB V DDQ V DD V SS V SS V SS V DD V DDQ NC DQA EF NC DQB V DDQ V DD V SS V SS V SS V DD V DDQ NC DQA FG NC DQB V DDQ V DD V SS V SS V SS V DD V DDQ NC DQA GH FT MCL NC V DD V SS V SS V SS V DD NC ZQ ZZ HJ DQB NC V DDQ V DD V SS V SS V SS V DD V DDQ DQA NC JK DQB NC V DDQ V DD V SS V SS V SS V DD V DDQ DQA NC KL DQB NC V DDQ V DD V SS V SS V SS V DD V DDQ DQA NC LM DQB NC V DDQ V DD V SS V SS V SS V DD V DDQ DQA NC MN DQPB SCD V DDQ V SS NC A NC V SS V DDQ NC NC NP NC A A A TDI A1TDO A A A A PR LBO A A A TMS A0TCK A A A A R11 x 15 Bump BGA—15 mm x 17 mm Body—1.0 mm Bump PitchGS864418/36E-xxxV165-Bump BGA—x36 Common I/O—Top View 1234567891011A NC A E1BC BB E3BW ADSC ADV A NC A B NC A E2BD BA CK GW G ADSP A NC B C DQPC NC V DDQ V SS V SS V SS V SS V SS V DDQ NC DQPB C D DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB D E DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB E F DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB F G DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB G H FT MCL NC V DD V SS V SS V SS V DD NC ZQ ZZ H J DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA J K DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA K L DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA L M DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA M N DQPD SCD V DDQ V SS NC A NC V SS V DDQ NC DQPA N P NC A A A TDI A1TDO A A A A P RLBOAAATMSA0TCKAAAAR11 x 15 Bump BGA—15 mm x 17 mm Body—1.0 mm Bump Pitch(Package E)GS864418/36E-xxxVGS864418/36E-xxxV 165-Bump BGA Pin DescriptionSymbolTypeDescriptionA 0, A 1I Address field LSBs and Address Counter Preset InputsA I Address Inputs DQ A DQB DQC DQD I/O Data Input and Output pinsB A , B B , BC , B DI Byte Write Enable for DQ A , DQ B , DQ C , DQ D I/Os; active low (x36 Version)NC —No ConnectCK I Clock Input Signal; active highBW I Byte Write—Writes all enabled bytes; active low GW I Global Write Enable—Writes all bytes; active lowE 1I Chip Enable; active low E 3I Chip Enable; active low E 2I Chip Enable; active high G I Output Enable; active lowADV I Burst address counter advance enable; active l0w ADSC, ADSPI Address Strobe (Processor, Cache Controller); active lowZZ I Sleep mode control; active high FT I Flow Through or Pipeline mode; active low LBO I Linear Burst Order mode; active lowZQ I FLXDrive Output Impedance Control (Low = Low Impedance [High Drive], High = High Impedance [LowDrive])TMS I Scan Test Mode Select TDI I Scan Test Data In TDO O Scan Test Data Out TCK I Scan Test Clock MCL —Must Connect LowSCD —Single Cycle Deselect/Dual Cyle Deselect Mode ControlV DD I Core power supply V SS I I/O and Core Ground V DDQIOutput driver power supplyGS864418/36E-xxxVA1A0A0A1D0D1Q1Q0Counter LoadD QDQRegisterRegisterDQRegisterDQRegisterDQRegisterD QRegisterD QRegisterD QRegisterDQR e g i s t e rDQRegisterA0–An LBO ADV CK ADSC ADSP GW BW E 1FT GZZPower Down ControlMemory Array36364AQD DQx1–DQx93636Note: Only x36 version shown for simplicity.SCD3636B AB BB CB DGS864418/36E-xxxV Block DiagramMode Pin FunctionsMode NamePin NameStateFunctionBurst Order Control LBO L Linear Burst H Interleaved Burst Output Register Control FT L Flow Through H or NC Pipeline Power Down Control ZZ L or NC Active H Standby, I DD = I SB Single/Dual Cycle Deselect Control SCD L Dual Cycle Deselect H or NC Single Cycle Deselect FLXDrive Output Impedance ControlZQL High Drive (Low Impedance)H or NCLow Drive (High Impedance)GS864418/36E-xxxVNote:There are pull-up devices on the ZQ, SCD, and FT pins and a pull-down device on the ZZ pin, so those input pins can be unconnected and the chip will operate in the default states as specified in the above tables.Note:The burst counter wraps to initial state on the 5th clock.Note:The burst counter wraps to initial state on the 5th clock.Linear Burst SequenceA[1:0]A[1:0]A[1:0]A[1:0]1st address 000110112nd address 011011003rd address 101100014th address11000110Interleaved Burst SequenceA[1:0]A[1:0]A[1:0]A[1:0]1st address 000110112nd address 010011103rd address 101100014th address11100100Burst Counter SequencesBPR 1999.05.18GS864418/36E-xxxVByte Write Truth TableFunctionGWBWB AB BB CB DNotesRead H H X X X X 1Read H L H H H H 1Write byte a H L L H H H 2, 3Write byte b H L H L H H 2, 3Write byte c H L H H L H 2, 3, 4Write byte d H L H H H L 2, 3, 4Write all bytesHLLLLL2, 3, 4Write all bytes L X X X X X1.All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.2.Byte Write Enable inputs B A , B B , B C , and/or B D may be used in any combination with BW to write single or multiple bytes.3.All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.4.Bytes “C ” and “D ” are only available on the x36 version.Synchronous Truth TableOperationAddress UsedState Diagram Key 5E 1ADSPADSCADVW 3DQ 4Deselect Cycle, Power Down None X H X L X X High-Z Read Cycle, Begin Burst External R L L X X X Q Read Cycle, Begin Burst External R L H L X F Q Write Cycle, Begin Burst External W L H L X T D Read Cycle, Continue Burst Next CR X H H L F Q Read Cycle, Continue Burst Next CR H X H L F Q Write Cycle, Continue Burst Next CW X H H L T D Write Cycle, Continue Burst Next CWH X H L T D Read Cycle, Suspend Burst Current X H H H F Q Read Cycle, Suspend Burst Current H X H H F Q Write Cycle, Suspend Burst Current X H H H T D Write Cycle, Suspend BurstCurrentHXHHTDNotes:1.X = Don’t Care, H = High, L = Low2.W = T (True) and F (False) is defined in the Byte Write Truth Table preceding3.G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shownas “Q” in the Truth Table above).4.All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplishbasic synchronous or synchronous burst operations and may be avoided for simplicity.5.Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.6.Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.GS864418/36E-xxxVFirst WriteFirst ReadBurst WriteBurst ReadDeselect R WCRCWXXWRRWRXXX S i m p l e S y n c h r o n o u s O p e r a t i o nS i m p l e B u r s t S y n c h r o n o u s O p e r a t i o nCR RCWCRCRNotes:1.The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low.2.The upper portion of the diagram assumes active use of only the Enable (E1) and Write (B A , B B , B C , B D , BW, and GW) control inputs, andthat ADSP is tied high and ADSC is tied low.3.The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs andassumes ADSP is tied high and ADV is tied low.GS864418/36E-xxxVSimplified State DiagramFirst WriteFirst ReadBurst WriteBurst ReadDeselectR WCRCWXXWRRWRXXX CRR CW CRCRW CWW CWNotes:1.The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.e of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from read cycles to write cycles without passingthrough a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles.3.Transitions shown in grey tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meetData Input Set Up Time.GS864418/36E-xxxVSimplified State Diagram with GAbsolute Maximum Ratings(All voltages reference to V SS )SymbolDescriptionValueUnitV DD Voltage on V DD Pins –0.5 to 4.6V V DDQ Voltage on V DDQ Pins –0.5 to V DDV V I/O Voltage on I/O Pins –0.5 to V DDQ +0.5 (≤ 4.6 V max.)V V IN Voltage on Other Input Pins –0.5 to V DD +0.5 (≤ 4.6 V max.)V I IN Input Current on Any Pin +/–20mA I OUT Output Current on Any I/O Pin +/–20mA P D Package Power Dissipation 1.5WT STG Storage Temperature –55 to 125o C T BIASTemperature Under Bias–55 to 125oCGS864418/36E-xxxVNote:Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component. Power Supply Voltage Ranges (1.8 V/2.5 V Version)ParameterSymbolMin.Typ.Max.UnitNotes1.8 V Supply Voltage V DD1 1.7 1.82.0V 2.5 V Supply Voltage V DD2 2.3 2.5 2.7V 1.8 V V DDQ I/O Supply Voltage V DDQ1 1.7 1.8V DD V 2.5 V V DDQ I/O Supply VoltageV DDQ22.32.5V DDVNotes:1.The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-tions quoted are evaluated for worst case in the temperature range marked on the device.2.Input Under/overshoot voltage must be –2 V > Vi < V DDn +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.GS864418/36E-xxxVV DDQ2 & V DDQ1 Range Logic LevelsParameterSymbolMin.Typ.Max.UnitNotesV DD Input High Voltage V IH 0.6*V DD —V DD + 0.3V 1V DD Input Low VoltageV IL–0.3—0.3*V DDV1Notes:1.The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-tions quoted are evaluated for worst case in the temperature range marked on the device.2.Input Under/overshoot voltage must be –2 V > Vi < V DDn +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.Recommended Operating TemperaturesParameterSymbolMin.Typ.Max.UnitNotesAmbient Temperature (Commercial Range Versions)T A 02570°C 2Ambient Temperature (Industrial Range Versions)T A–402585°C2Notes:1.The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-tions quoted are evaluated for worst case in the temperature range marked on the device.2.Input Under/overshoot voltage must be –2 V > Vi < V DDn +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.20% tKCV SS – 2.0 V50%V SS V IHUndershoot Measurement and TimingOvershoot Measurement and Timing20% tKCV DD + 2.0 V50%V DDV ILCapacitanceo C, f = 1 MH Z , V DD ParameterSymbolTest conditionsTyp.Max.UnitInput Capacitance C IN V IN = 0 V 45pF Input/Output Capacitance C I/OV OUT = 0 V67pFNote:These parameters are sample tested.(T A = 25= 2.5 V)AC Test ConditionsParameterConditionsDQV DDQ/250Ω30pF *Output Load 1* Distributed Test Jig CapacitanceFigure 1Input high level V DD – 0.2 V Input low level 0.2 V Input slew rate 1 V/ns Input reference level V DD /2Output reference levelV DDQ /2Output loadFig. 11.Include scope and jig capacitance.2.Test conditions as specified with output loading as shown in Fig. 1unless otherwise noted.3.Device is deselected as defined by the Truth Table. GS864418/36E-xxxVDC Electrical CharacteristicsParameterSymbolTest ConditionsMinMaxInput Leakage Current (except mode pins)I IL V IN = 0 to V DD –1 uA 1 uA FT, SCD, ZQ, ZZ Input Current I IN V DD ≥ V IN ≥ 0 V –100 uA 100 uA Output Leakage CurrentI OLOutput Disable, V OUT = 0 to V DD–1 uA1 uADC Output Characteristics (1.8 V/2.5 V Version)ParameterSymbolTest ConditionsMinMax1.8 V Output High Voltage V OH1I OH = –4 mA, V DDQ = 1.6 V V DDQ – 0.4 V —2.5 V Output High Voltage V OH2I OH = –8 mA, V DDQ = 2.375 V1.7 V —1.8 V Output Low Voltage V OL1I OL = 4 mA —0.4 V2.5 V Output Low VoltageV OL2I OL = 8 mA—0.4 VGS864418/36E-xxxVO p e r a t i n g C u r r e n t sP a r a m e t e r T e s t C o n d i t i o n s M o d eS y m b o l -250-225-200-166-150-133U n i t0t o 70°C –40 t o 85°C0t o 70°C–40 t o 85°C 0t o 70°C –40t o 85°C 0 t o 70°C –40t o 85°C 0 t o 70°C –40t o 85°C 0 t o 70°C –40t o 85°C O p e r a t i n g C u r r e n tD e v i c e S e l e c t e d ; A l l o t h e r i n p u t s ≥V I H o r ≤ V I LO u t p u t o p e n(x 36)P i p e l i n eI D DI D D Q400504355037045405453454038040310353453529530330302702530525m AF l o w T h r o u g hI D DI D D Q270202952027020295202702029520260202852024520270202301525515m A(x 18)P i p e l i n eI D DI D D Q360253952533525370253152035020285203202027520310202501528515m AF l o w T h r o u g hI D DI D D Q250152751525015275152501527515240152601522515250152101523515m AS t a n d b y C u r r e n tZ Z ≥ V D D – 0.2 V—P i p e l i n eI S B 120160120160120160120160120160120160m AF l o w T h r o u g hI S B120160120160120160120160120160120160m AD e s e l e c t C u r r e n tD e v i c e D e s e l e c t e d ; A l l o t h e r i n p u t s ≥ V I H o r ≤ V I L—P i p e l i n eI D D200230190220180210170200170200160190m AF l o w T h r o u g hI D D170200170200160190160190150180140170m AN o t e s : 1.I D D a n d I D D Q a p p l y t o a n y c o m b i n a t i o n o f V D D 1, V D D 2, V D D Q 1, a n d V D D Q 2 o p e r a t i o n .2.A l l p a r a m e t e r s l i s t e d a r e w o r s t c a s e s c e n a r i o .AC Electrical CharacteristicsParameter Symbol -250-225-200-166-150-133Unit Min Max Min Max Min Max Min Max Min Max Min Max PipelineClock Cycle Time tKC 4.0— 4.4— 5.0— 6.0— 6.7—7.5—ns Clock to Output Valid tKQ — 2.3— 2.5— 2.7— 2.9— 3.3— 3.5ns Clock to Output Invalid tKQX 1.0— 1.0— 1.0— 1.0— 1.0— 1.0—ns Clock to Output in Low-Z tLZ 1 1.0— 1.0— 1.0— 1.0— 1.0— 1.0—ns Setup time tS 1.3— 1.3— 1.4— 1.5— 1.5— 1.5—ns Hold time tH 0.2—0.3—0.4—0.5—0.5—0.5—ns Flow ThroughClock Cycle Time tKC 6.5— 6.5— 6.5—7.0—7.5—8.5—ns Clock to Output Valid tKQ — 6.5— 6.5— 6.5—7.0—7.5—8.5ns Clock to Output Invalid tKQX 3.0— 3.0— 3.0— 3.0— 3.0— 3.0—ns Clock to Output in Low-Z tLZ 1 3.0— 3.0— 3.0— 3.0— 3.0— 3.0—ns Setup time tS 1.5— 1.5— 1.5— 1.5— 1.5— 1.5—ns Hold time tH 0.5—0.5—0.5—0.5—0.5—0.5—ns Clock HIGH Time tKH 1.3— 1.3— 1.3— 1.3— 1.5— 1.7—ns Clock LOW Time tKL 1.5— 1.5— 1.5— 1.5— 1.7—2—ns Clock to Output inHigh-ZtHZ 1 1.0 2.3 1.0 2.5 1.0 2.7 1.0 2.9 1.0 3.0 1.0 3.0ns G to Output Valid tOE — 2.3— 2.5— 2.7— 2.9— 3.3— 3.5ns G to output in Low-Z tOLZ 10—0—0—0—0—0—ns G to output in High-Z tOHZ 1— 2.3— 2.5— 2.7— 2.9— 3.0— 3.0ns ZZ setup time tZZS 25—5—5—5—5—5—ns ZZ hold time tZZH 21—1—1—1—1—1—ns ZZ recoverytZZR20—20—20—20—20—20—nsGS864418/36E-xxxVNotes:1.These parameters are sampled and are not 100% tested.2.ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and holdtimes as specified above.GS864418/36E-xxxVPipeline Mode Timing (SCD)Begin Read A Cont Cont Deselect Write B Read C Read C+1Read C+2Read C+3ContDeselecttHZtKQX tKQtLZtHtStOHZtOEtHtStHtStHtStHtStHtStStHtStHtStHtSBurst ReadtKCtKL tKH Single Write Single ReadQ(A)D(B)Q(C)Q(C+1)Q(C+2)Q(C+3)ABCDeselected with E1E1 masks ADSPE2 and E3 only sampled with ADSP and ADSCADSC initiated readCK ADSPADSCADVA0–AnGWBWBa–BdE1E2E3GDQa–DQdGS864418/36E-xxxVFlow Through Mode Timing (SCD)Begin Read A ContCont Write B Read C Read C+1Read C+2Read C+3Read C Cont DeselecttHZtKQXtKQ tLZtH tStOHZtOEtHtS tHtS tHtStHtS tHtS tHtStHtS tHtS tH tS tHtS tKCtKL tKHABCQ(A)D(B)Q(C)Q(C+1)Q(C+2)Q(C+3)Q(C)E2 and E3 only sampled with ADSCADSC initiated readDeselected with E1Fixed HighCK ADSPADSCADVA0–AnGWBWBa–BdE1E2E3GDQa–DQdGS864418/36E-xxxVPipeline Mode Timing (DCD)Begin Read A Cont Deselect Deselect Write BRead C Read C+1Read C+2Read C+3Cont Deselect DeselecttHZtKQXtKQtLZtHtStOHZtOEtHtStHtStHtStH tStHtStStHtStHtStHtStKCtKL tKHQ(A)D(B)Q(C)Q(C+1)Q(C+2)Q(C+3)ABCHi-ZDeselected with E1E2 and E3 only sampled with ADSCADSC initiated readCK ADSPADSCADVAo–AnGWBWBa–BdE1E2E3GDQa–DQdGS864418/36E-xxxVFlow Through Mode Timing (DCD)Begin Read A ContDeselect Write B Read C Read C+1Read C+2Read C+3Read C DeselecttHZtKQX tLZtH tStOHZtOE tKQtHtS tHtS tHtStH tStHtS tHtStHtS tHtS tH tStH tS tHtS tKCtKL tKHABCQ(A)D(B)Q(C)Q(C+1)Q(C+2)Q(C+3)Q(C)E2 and E3 only sampled with ADSP and ADSCE1 masks ADSPADSC initiated readDeselected with E1E1 masks ADSPFixed HighCK ADSPADSCADVAo–AnGWBWBa–BdE1E2E3GDQa–DQdGS864418/36E-xxxVSleep ModeDuring normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high, the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM operates normally after ZZ recovery time.Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to I SB 2. The duration of Sleep mode is dictated by the length of time the ZZ is in a High state. After entering Sleep mode, all inputs except ZZ become disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode. When the ZZ pin is driven high, I SB 2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands may be applied while the SRAM is recovering from Sleep mode.Sleep Mode Timing DiagramtZZRtZZHtZZSHoldSetup tKLtKHtKCCKADSP ADSCZZApplication TipsSingle and Dual Cycle DeselectSCD devices (like this one) force the use of “dummy read cycles” (read cycles that are launched normally, but that are ended with the output drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance, but their use usually assures there will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste bandwidth on dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at bank address boundary crossings), but greater care must be exercised to avoid excessive bus contention.JTAG Port OperationOverviewThe JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with V DD . The JTAG output drivers are powered by V DDQ .Disabling the JTAG PortIt is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG Port unused, TCK, TDI, and TMS may be left floating or tied to either V DD or V SS . TDO should be left unconnected.JTAG Pin DescriptionsPinPin NameI/ODescriptionTCK Test Clock In Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate from the falling edge of TCK.TMSTest Mode SelectInThe TMS input is sampled on the rising edge of TCK. This is the command input for the TAP controller state machine. An undriven TMS input will produce the same result as a logic one input level.TDI Test Data In InThe TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers placed between TDI and TDO. The register placed between TDI and TDO is determined by the state of the TAP Controller state machine and the instruction that is currently loaded in the TAP Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce the same result as a logic one input level.TDO Test Data OutOut Output that is active depending on the state of the TAP state machine. Output changes inresponse to the falling edge of TCK. This is the output side of the serial registers placed betweenTDI and TDO.This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up.GS864418/36E-xxxVJTAG Port RegistersOverviewThe various JTAG registers, refered to as Test Access Port orTAP Registers, are selected (one at a time) via the sequences of 1s and 0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the rising edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the TDI and TDO pins.Instruction RegisterThe Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the controller is placed in Test-Logic-Reset state.Bypass RegisterThe Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through the RAM’s JTAG Port to another device in the scan chain with as little delay as possible.Boundary Scan RegisterThe Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins. The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is inCapture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z, SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.。

BT200中文说明书

智能终端BT200的操作一、功能：测量范围、位号的设置，自诊监控和零点调整等。

二、BT200操作注意事项1、连接：变送器与BT200的连接，既可在变送器接线盒里用BT200挂钩连接，也可通过中断端子板传输线连接。

2、在线通讯条件：回路电阻=R+2R C=250~600Ω回路电容=0.22μF（最大值）三、BT200的操作方法1、键面排列：*用于解释命令*显示于屏幕底部*条目选择*移动光标*输入选择条目*给连接好的仪表输入数据/关键*输入数字shift）结合使用输入字母菜单页页主题种显示）参量功能命令BT200键面图2、操作键的功能⑴ 数字/字母键和利用数字/字母键直接输入数字，结合 a ：输入数字、符号和空格（0—9…）直接按数字/字母键b ：输入字母（A —Z ）选按下shift 键,再同时按数字/字母键,则输入数字/字母键上与shift 键边侧位置相对应的字母.注意在按数字/字母键前必须先按下shift 键。

数字/字母键数字/字母键上的左侧字母上右侧字母 * 用功能键F2键，大小写字形作一次更换并锁定。

*使用功能键[F1]输入符号。

每按一下 1 。

- 、+ * ）（ ’ ＆ % ＄ # ” ！这些符号后面输入字母，要选按[＞]移动光标。

*使用功能键[F1]输 ⑵ 功能键功能命令功能键功能命令表ON/OFF 3、用操作键调示菜单四、BT200的参数设置1、参数总表适用仪表：F：差压变送器……EJA110A，EJA120A，EJA118W，EJA118Y，EJA115 P：压力变送器……EJA310A，EJA430A，EJA438W，EJA438N，EJA530A L：液位变送器……EJA210A，EJA220A*1.EJA120不能检测静压，此处显示值为0kPa，但液值不是测量值。

*2.仪表最大工作压力在主铭牌上标明，B40是膜盒最大工作压力。

2、参数意义和选择※参数设置后30秒内关机，设定参数不被存储，最终值返回原值在讲述参数设置之前，先列表说明在各种情况下参数的意义。

GS8662D36E-200中文资料

GS8662D08/09/18/36E-333/300/250/200/16772Mb SigmaQuad-II Burst of 4 SRAM333 MHz–167 MHz1.8 V V DD1.8 V and 1.5 V I/O165-Bump BGA Commercial Temp Industrial Temp Features• Simultaneous Read and Write SigmaQuad™ Interface • JEDEC-standard pinout and package • Dual Double Data Rate interface• Byte Write controls sampled at data-in time • Burst of 4 Read and Write• 1.8 V +100/–100 mV core power supply • 1.5 V or 1.8 V HSTL Interface • Pipelined read operation• Fully coherent read and write pipelines• ZQ pin for programmable output drive strength • IEEE 1149.1 JTAG-compliant Boundary Scan• Pin-compatible with present 9Mb, 18Mb, and 36Mb and future 144Mb devices• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package • RoHS-compliant 165-bump BGA package availableSigmaQuad ™ Family OverviewThe GS8662D08/09/18/36E are built in compliance with the SigmaQuad-II SRAM pinout standard for Separate I/O synchronous SRAMs. They are 75,497,472-bit (72Mb) SRAMs. The GS8662D08/18/36E SigmaQuad SRAMs are just one element in a family of low power, low voltage HSTL I/O SRAMs designed to operate at the speeds needed toimplement economical high performance networking systems.Clocking and Addressing SchemesThe GS8662D08/09/18/36E SigmaQuad-II SRAMs are synchronous devices. They employ two input register clock inputs, K and K. K and K are independent single-ended clock inputs, not differential inputs to a single differential clock input buffer. The device also allows the user to manipulate theoutput register clock inputs quasi independently with the C andC clock inputs. C and C are also independent single-ended clock inputs, not differential inputs. If the C clocks are tied high, the K clocks are routed internally to fire the output registers instead.Because Separate I/O SigmaQuad-II B4 RAMs always transfer data in four packets, A0 and A1 are internally set to 0 for the first read or write transfer, and automatically incremented by 1 for the next transfers. Because the LSBs are tied off internally, the address field of a SigmaQuad-II B4 RAM is always two address pins less than the advertised index depth (e.g., the 4M x 18 has a 1024K addressable index).Parameter Synopsis- 333-300-250-200-167tKHKH 3.0 ns 3.3 ns 4.0 ns 5.0 ns 6.0 ns tKHQV0.45 ns0.45 ns0.45 ns0.45 ns0.50 ns165-Bump, 15 mm x 17 mm BGA 1 mm Bump Pitch, 11 x 15 Bump ArrayBottom View2M x 36 SigmaQuad-II SRAM—Top View1234567891011ACQ MCL/SA (288Mb)SA W BW2K BW1R SA MCL/SA (144Mb)CQ B Q27Q18D18SA BW3K BW0SA D17Q17Q8C D27Q28D19V SS SA NC SA V SS D16Q7D8D D28D20Q19V SS V SS V SS V SS V SS Q16D15D7E Q29D29Q20 V DDQ V SS V SS V SS V DDQ Q15D6Q6F Q30Q21D21 V DDQ V DD V SS V DD V DDQ D14Q14Q5G D30D22Q22 V DDQ V DD V SS V DD V DDQ Q13D13D5H Doff V REF V DDQ V DDQ V DD V SS V DD V DDQ V DDQ V REF ZQ J D31Q31D23 V DDQ V DD V SS V DD V DDQ D12Q4D4K Q32D32Q23V DDQ V DD V SS V DD V DDQ Q12D3Q3L Q33Q24D24 V DDQ V SS V SS V SS V DDQ D11Q11Q2M D33Q34D25 V SS V SS V SS V SS V SS D10Q1D2N D34D26Q25 V SS SA SA SA V SS Q10D9D1P Q35D35Q26SA SA C SA SA Q9D0Q0RTDOTCKSASASACSASASATMSTDI11 x 15 Bump BGA—15 x 17 mm 2 Body—1 mm Bump PitchNotes:1.BW0 controls writes to D0:D8; BW1 controls writes to D9:D17; BW2 controls writes to D18:D26; BW3 controls writes to D27:D352.MCL = Must Connect LowGS8662D08/09/18/36E-333/300/250/200/1674M x 18 SigmaQuad-II SRAM—Top View1234567891011ACQ MCL/SA (144Mb)SA W BW1K NC R SA SA CQ B NC Q9D9SA NC K BW0SA NC NC Q8C NC NC D10V SS SA NC SA V SS NC Q7D8D NC D11Q10V SS V SS V SS V SS V SS NC NC D7E NC NC Q11 V DDQ V SS V SS V SS V DDQ NC D6Q6F NC Q12D12 V DDQ V DD V SS V DD V DDQ NC NC Q5G NC D13Q13 V DDQ V DD V SS V DD V DDQ NC NC D5H Doff V REF V DDQ V DDQ V DD V SS V DD V DDQ V DDQ V REF ZQ J NC NC D14 V DDQ V DD V SS V DD V DDQ NC Q4D4K NC NC Q14V DDQ V DD V SS V DD V DDQ NC D3Q3L NC Q15D15 V DDQ V SS V SS V SS V DDQ NC NC Q2M NC NC D16 V SS V SS V SS V SS V SS NC Q1D2N NC D17Q16 V SS SA SA SA V SS NC NC D1P NC NC Q17SA SA C SA SA NC D0Q0RTDOTCKSASASACSASASATMSTDI11 x 15 Bump BGA—15 x 17 mm 2 Body—1 mm Bump PitchNotes:1.BW0 controls writes to D0:D8. BW1 controls writes to D9:D17.2.MCL = Must Connect LowGS8662D08/09/18/36E-333/300/250/200/1678M x 9 SigmaQuad-II SRAM—Top View1234567891011ACQ SA SA W NC K NC R SA SA CQ B NC NC NC SA NC K BW0SA NC NC Q4C NC NC NC V SS SA NC SA V SS NC NC D4D NC D5NC V SS V SS V SS V SS V SS NC NC NC E NC NC Q5 V DDQ V SS V SS V SS V DDQ NC D3Q3F NC NC NC V DDQ V DD V SS V DD V DDQ NC NC NC G NC D6Q6 V DDQ V DD V SS V DD V DDQ NC NC NC H D off V REF V DDQ V DDQ V DD V SS V DD V DDQ V DDQ V REF ZQ J NC NC NC V DDQ V DD V SS V DD V DDQ NC Q2D2K NC NC NC V DDQ V DD V SS V DD V DDQ NC NC NC L NC Q7D7 V DDQ V SS V SS V SS V DDQ NC NC Q1M NC NC NC V SS V SS V SS V SS V SS NC NC D1N NC D8NC V SS SA SA SA V SS NC NC NC P NC NC Q8SA SA C SA SA NC D0Q0RTDOTCKSASASACSASASATMSTDI11 x 15 Bump BGA—13 x 15 mm 2 Body—1 mm Bump PitchNotes:1.BW0 controls writes to D0:D8.2.MCL = Must Connect LowGS8662D08/09/18/36E-333/300/250/200/1678M x 8 SigmaQuad-II SRAM—Top View1234567891011ACQ SA SA W NW1K NC R SA SA CQ B NC NC NC SA NC K NW0SA NC NC Q3C NC NC NC V SS SA NC SA V SS NC NC D3D NC D4NC V SS V SS V SS V SS V SS NC NC NC E NC NC Q4 V DDQ V SS V SS V SS V DDQ NC D2Q2F NC NC NC V DDQ V DD V SS V DD V DDQ NC NC NC G NC D5Q5 V DDQ V DD V SS V DD V DDQ NC NC NC H Doff V REF V DDQ V DDQ V DD V SS V DD V DDQ V DDQ V REF ZQ J NC NC NC V DDQ V DD V SS V DD V DDQ NC Q1D1K NC NC NC V DDQ V DD V SS V DD V DDQ NC NC NC L NC Q6D6 V DDQ V SS V SS V SS V DDQ NC NC Q0M NC NC NC V SS V SS V SS V SS V SS NC NC D0N NC D7NC V SS SA SA SA V SS NC NC NC P NC NC Q7SA SA C SA SA NC NC NC RTDOTCKSASASACSASASATMSTDI11 x 15 Bump BGA—15 x 17 mm 2 Body—1 mm Bump PitchNotes:1.NW0 controls writes to D0:D3. NW1 controls writes to D4:D7.2.MCL = Must Connect LowGS8662D08/09/18/36E-333/300/250/200/167Pin Description TableSymbolDescriptionTypeCommentsSA Synchronous Address InputsInput —NC No Connect ——R Synchronous Read Input Active Low W Synchronous Write Input Active Low BW0–BW3Synchronous Byte Writes Input Active Low x9/x18/x36 only NW0–NW1Nybble Write Control PinInput Active Low x8 only K Input Clock Input Active High K Input Clock Input Active Low C Output Clock Input Active High C Output Clock Input Active LowTMS Test Mode Select Input —TDI Test Data Input Input —TCK Test Clock Input Input —TDO Test Data Output Output —V REF HSTL Input Reference Voltage Input —ZQ Output Impedance Matching Input Input —Qn Synchronous Data Outputs Output Dn Synchronous Data Inputs Input D off Disable DLL when low Input Active LowCQ Output Echo Clock Output —CQ Output Echo Clock Output —V DD Power Supply Supply 1.8 V Nominal V DDQ Isolated Output Buffer Supply Supply 1.5 or 1.8 V NominalV SSPower Supply: GroundSupply—GS8662D08/09/18/36E-333/300/250/200/167Note:NC = Not Connected to die or any other pinGS8662D08/09/18/36E-333/300/250/200/167BackgroundSeparate I/O SRAMs, from a system architecture point of view, are attractive in applications where alternating reads and writes are needed. Therefore, the SigmaQuad-II SRAM interface and truth table are optimized for alternating reads and writes. Separate I/O SRAMs are unpopular in applications where multiple reads or multiple writes are needed because burst read or write transfers from Separate I/O SRAMs can cut the RAM’s bandwidth in half.Alternating Read-Write OperationsSigmaQuad-II SRAMs follow a few simple rules of operation.- Read or Write commands issued on one port are never allowed to interrupt an operation in progress on the other port.- Read or Write data transfers in progress may not be interrupted and re-started. - R and W high always deselects the RAM.- All address, data, and control inputs are sampled on clock edges.In order to enforce these rules, each RAM combines present state information with command inputs. See the Truth Table for details.SigmaQuad-II B4 SRAM DDR ReadThe status of the Address Input, W, and R pins are sampled by the rising edges of K. W and R high causes chip disable. A low on the Read Enable-bar pin, R, begins a read cycle. R is always ignored if the previous command loaded was a read command. Data can be clocked out after the next rising edge of K with a rising edge of C (or by K if C and C are tied high), after the following rising edge of K with a rising edge of C (or by K if C and C are tied high), after the next rising edge of K with a rising edge of C, and after the following rising edge of K with a rising edge of C. Clocking in a high on the Read Enable-bar pin, R, begins a read port deselect cycle.SigmaQuad-II B4 Double Data Rate SRAM Read FirstRead ANOPRead BWrite CRead DWrite ENOPABCDEC C+1C+2C+3E E+1CC+1C+2C+3EE+1AA+1A+2A+3BB+1B+2B+3DD+1D+2K K AddressR W BWx D C C Q CQ CQGS8662D08/09/18/36E-333/300/250/200/167SigmaQuad-II B4 SRAM DDR WriteThe status of the Address Input, W, and R pins are sampled by the rising edges of K. W and R high causes chip disable. A low on the Write Enable-bar pin, W, and a high on the Read Enable-bar pin, R, begins a write cycle. W is always ignored if the previous command was a write command. Data is clocked in by the next rising edge of K, the rising edge of K after that, the next rising edge of K, and finally by the next rising edge of K. and by the rising edge of the K that follows.SigmaQuad-II B4 Double Data Rate SRAM Write FirstWrite ANOPRead BWrite CRead DWrite ENOPABCDEA A+1A+2A+3C C+1C+2C+3E E+1E+AA+1A+2A+3CC+1C+2C+3EE+1E+BB+1B+2B+3DD+1D+2K K AddressR W BWx D C C Q CQ CQGS8662D08/09/18/36E-333/300/250/200/167Power-Up Sequence for SigmaQuad-II SRAMsSigmaQuad-II SRAMs must be powered-up in a specific sequence in order to avoid undefined operations.Power-Up Sequence1. Power-up and maintain Doff at low state.1a.Apply V DD .1b. Apply V DDQ .1c. Apply V REF (may also be applied at the same time as V DDQ ).2. After power is achieved and clocks (K, K, C, C) are stablized, change Doff to high.3. An additional 1024 clock cycles are required to lock the DLL after it has been enabled.Note:If you want to tie Doff high with an unstable clock, you must stop the clock for a minimum of 30 seconds to reset the DLL after the clocks become stablized.DLL Constraints•The DLL synchronizes to either K or C clock. These clocks should have low phase jitter (t KCVar on page 21).•The DLL cannot operate at a frequency lower than 119 MHz.•If the incoming clock is not stablized when DLL is enabled, the DLL may lock on the wrong frequency and cause undefined errors or failures during the initial stage.Power-Up Sequence (Doff controlled)Power UP IntervalUnstable Clocking IntervalDLL Locking Interval (1024 Cycles)Normal OperationKKV DDV DDQV REFDoffPower-Up Sequence (Doff tied High)Power UP IntervalUnstable Clocking IntervalStop Clock IntervalDLL Locking Interval (1024 Cycles)Normal OperationKKV DDV DDQV REFDoff30ns MinNote:If the frequency is changed, DLL reset is required. After reset, a minimum of 1024 cycles is required for DLL lock.GS8662D08/09/18/36E-333/300/250/200/167Special FunctionsByte Write and Nybble Write ControlByte Write Enable pins are sampled at the same time that Data In is sampled. A high on the Byte Write Enable pin associated with a particular byte (e.g., BW0 controls D0–D8 inputs) will inhibit the storage of that particular byte, leaving whatever data may be stored at the current address at that byte location undisturbed. Any or all of the Byte Write Enable pins may be driven high or low during the data in sample times in a write sequence.Each write enable command and write address loaded into the RAM provides the base address for a 4 beat data transfer. The x18 version of the RAM, for example, may write 72 bits in association with each address loaded. Any 9-bit byte may be masked in any write sequence.Nybble Write (4-bit) control is implemented on the 8-bit-wide version of the device. For the x8 version of the device, “Nybble Write Enable” and “NBx” may be substituted in all the discussion above.Example x18 RAM Write Sequence using Byte Write EnablesData In SampleTimeBW0BW1D0–D8D9–D17Beat 101Data In Don’t CareBeat 210Don’t Care Data InBeat 300Data In Data InBeat 410Don’t Care Data InResulting Write OperationByte 1 D0–D8Byte 2D9–D17Byte 1D0–D8Byte 2D9–D17Byte 1D0–D8Byte 2D9–D17Byte 1D0–D8Byte 2D9–D17Written Unchanged Unchanged Written Written Written Unchanged Written Beat 1Beat 2Beat 3Beat 4Output Register ControlSigmaQuad-II SRAMs offer two mechanisms for controlling the output data registers. Typically, control is handled by the Output Register Clock inputs, C and C. The Output Register Clock inputs can be used to make small phase adjustments in the firing of the output registers by allowing the user to delay driving data out as much as a few nanoseconds beyond the next rising edges of the K and K clocks. If the C and C clock inputs are tied high, the RAM reverts to K and K control of the outputs, allowing the RAM to function as a conventional pipelined read SRAM.A K RW A 0–AnK W 0D 1–D nBank 0Bank 1Bank 2Bank 3R 0D A K W D A K W D A K W D R R R QQQQCCCCQ 1–Q nC W 1R 1W 2R 2W 3R 3Note:For simplicity BWn, NWn, K, and C are not shown.CQ CQ CQ CQ CQ 0CQ 1CQ 2CQ 3GS8662D08/09/18/36E-333/300/250/200/167Example Four Bank Depth Expansion SchematicΣ2x 2B 4 S i g m a Q u a d-I IS R A M D e p t h E x p a n s i o nR e a d AW r i t e B R e a d C W r i t e D R e a d E W r i t e F N O PAB C D E FDD +1D +2D +3DD +1D +2D +3BB +1B +2B +3FF +1FB B +1B +2B +3FF +1FA A +1A +2A +3E E +1E +2C C +1C +2C +3KKA d d r e s s R (1)R (2)W (1)W (2)B W x (1)D (1)B W x (2)D (2)C [1]C [1]Q (1)C Q (1)C Q [1]C [2]C [2]Q (2)C Q [2]C Q [2]GS8662D08/09/18/36E-333/300/250/200/167GS8662D08/09/18/36E-333/300/250/200/167FLXDrive-II Output Driver Impedance ControlHSTL I/O SigmaQuad-II SRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected to V SS via an external resistor, RQ, to allow the SRAM to monitor and adjust its output driver impedance. The value of RQ must be 5X the value of the desired RAM output impedance. The allowable range of RQ to guarantee impedance matching continuously is between 150Ω and 300Ω. Periodic readjustment of the output driver impedance is necessary as the impedance is affected by drifts in supply voltage and temperature. The SRAM’s output impedance circuitry compensates for drifts in supply voltage and temperature. A clock cycle counter periodically triggers an impedance evaluation, resets and counts again. Each impedance evaluation may move the output driver impedance level one step at a time towards the optimum level. The output driver isimplemented with discrete binary weighted impedance steps. Updates of pull-down drive impedance occur whenever a driver is producing a “1” or is High-Z. Pull-up drive impedance is updated when a driver is producing a “0” or is High-Z.Separate I/O SigmaQuad-II B4 SRAM Truth Table Previous OperationARWCurrent OperationDDDDQQQQK ↑(t n-1)K ↑(t n )K ↑(t n )K ↑(t n )K ↑(t n )K ↑(t n+1)K ↑(t n+1½)K ↑(t n+2)K ↑(t n+2½)K ↑(t n+1)K ↑(t n+1½)K ↑(t n+2)K ↑(t n+2½)Deselect X 11Deselect X X ——Hi-Z Hi-Z ——Write X 1X Deselect D2D3——Hi-Z Hi-Z ——Read X X 1Deselect X X ——Q2Q3——Deselect V 10Write D0D1D2D3Hi-Z Hi-Z ——Deselect V 0X Read X X ——Q0Q1Q2Q3Read V X 0Write D0D1D2D3Q2Q3——WriteVXReadD2D3——Q0Q1Q2Q3Notes:1.“1” = input “high”; “0” = input “low”; “V” = input “valid”; “X” = input “don’t care”2.“—” indicates that the input requirement or output state is determined by the next operation.3.Q0, Q1, Q2, and Q3 indicate the first, second, third, and fourth pieces of output data transferred during Read operations.4.D0, D1, D2, and D3 indicate the first, second, third, and fourth pieces of input data transferred during Write operations.5.Qs are tristated for one cycle in response to Deselect and Write commands, one cycle after the command is sampled, except when pre-ceded by a Read command.ers should not clock in metastable addresses.Byte Write Clock Truth TableBWBWBWBWCurrent OperationDDDDK ↑(t n+1)K ↑(t n+1½)K ↑(t n+2)K ↑(t n+2½)K ↑(t n )K ↑(t n+1)K ↑(t n+1½)K ↑(t n+2)K ↑(t n+2½)T T T TWriteDx stored if BWn = 0 in all four data transfers D0D2D3D4T F F F WriteDx stored if BWn = 0 in 1st data transfer only D0X X XF T F F WriteDx stored if BWn = 0 in 2nd data transfer only X D1X XF F T F WriteDx stored if BWn = 0 in 3rd data transfer only X X D2XF F F T WriteDx stored if BWn = 0 in 4th data transfer only X X X D3F F F F Write AbortNo Dx stored in any of the four data transfersX X X XNotes:1.“1” = input “high”; “0” = input “low”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”.2.If one or more BWn = 0, then BW = “T”, else BW = “F”.GS8662D08/09/18/36E-333/300/250/200/167x36 Byte Write Enable (BWn) Truth TableBW0BW1BW2BW3D0–D8D9–D17D18–D26D27–D351111Don’t Care Don’t Care Don’t Care Don’t Care 0111Data In Don’t Care Don’t Care Don’t Care 1011Don’t Care Data In Don’t Care Don’t Care 0011Data In Data In Don’t Care Don’t Care 1101Don’t Care Don’t Care Data In Don’t Care 0101Data In Don’t Care Data In Don’t Care 1001Don’t Care Data In Data In Don’t Care 0001Data In Data In Data In Don’t Care 1110Don’t Care Don’t Care Don’t Care Data In 0110Data In Don’t Care Don’t Care Data In 1010Don’t Care Data In Don’t Care Data In 0010Data In Data In Don’t Care Data In 1100Don’t Care Don’t Care Data In Data In 0100Data In Don’t Care Data In Data In 1000Don’t Care Data In Data In Data In 0Data InData InData InData Inx18 Byte Write Enable (BWn) Truth Table BW0BW1D0–D8D9–D1711Don’t Care Don’t Care 01Data In Don’t Care 10Don’t Care Data In 0Data InData Inx09 Byte Write Enable (BWn) Truth TableBW0D0–D81Don’t Care 0Data In 1Don’t Care 0Data InGS8662D08/09/18/36E-333/300/250/200/167Nybble Write Clock Truth TableNWNWNWNWCurrent OperationDDDDK ↑(t n+1)K ↑(t n+1½)K ↑(t n+2)K ↑(t n+2½)K ↑(t n )K ↑(t n+1)K ↑(t n+1½)K ↑(t n+2)K ↑(t n+2½)T T T TWriteDx stored if NWn = 0 in all four data transfers D0D2D3D4T F F F WriteDx stored if NWn = 0 in 1st data transfer only D0X X XF T F F WriteDx stored if NWn = 0 in 2nd data transfer only X D1X XF F T F WriteDx stored if NWn = 0 in 3rd data transfer only X X D2XF F F T WriteDx stored if NWn = 0 in 4th data transfer only X X X D3F F F F Write AbortNo Dx stored in any of the four data transfersX X X XNotes :1.“1” = input “high”; “0” = input “low”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”.2.If one or more NWn = 0, then NW = “T”, else NW = “F”.x8 Nybble Write Enable (NWn) Truth Table NW0NW1D0–D3D4–D711Don’t Care Don’t Care 01Data In Don’t Care 10Don’t Care Data In 0Data InData InGS8662D08/09/18/36E-333/300/250/200/167GS8662D08/09/18/36E-333/300/250/200/167State DiagramPower-UpRead NOPLoad New Read Address D Count = 0DDR ReadD Count = D Count + 1Write NOPLoad New Write Address D Count = 0DDR WriteD Count = D Count + 1WRITEREAD READ D Count = 2WRITE D Count = 2READ WRITEAlwaysAlwaysREAD D Count = 2Notes:1.Internal burst counter is fixed as 2-bit linear (i.e., when first address is A0+0, next internal burst address is A0+1.2.“READ” refers to read active status with R = Low, “READ” refers to read inactive status with R = High. The same istrue for “WRITE” and “WRITE”.3.Read and write state machine can be active simultaneously.4.State machine control timing sequence is controlled by K.READ D Count = 1Always Increment Read Address WRITE D Count = 2Increment Write AddressWRITE D Count = 1AlwaysAbsolute Maximum Ratings(All voltages reference to V SS )SymbolDescriptionValueUnitV DD Voltage on V DD Pins –0.5 to 2.9V V DDQ Voltage in V DDQ Pins –0.5 to V DD V V REF Voltage in V REF Pins –0.5 to V DDQV V I/O Voltage on I/O Pins –0.5 to V DDQ +0.5 (≤ 2.9 V max.)V V IN Voltage on Other Input Pins –0.5 to V DDQ +0.5 (≤ 2.9 V max.)V I IN Input Current on Any Pin +/–100mA dc I OUT Output Current on Any I/O Pin +/–100mA dcT J Maximum Junction Temperature125o C T STGStorage Temperature–55 to 125oCNote:Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Recommended Operating Conditions, for an extended period of time, may affect reliability of this component.GS8662D08/09/18/36E-333/300/250/200/167Recommended Operating ConditionsPower SuppliesParameterSymbolMin.Typ.Max.UnitSupply Voltage V DD 1.7 1.8 1.9V I/O Supply Voltage V DDQ 1.4 1.5V DD V Reference VoltageV REF0.68—0.95VNotes:1.The power supplies need to be powered up simultaneously or in the following sequence: V DD , V DDQ , V REF , followed by signalinputs. The power down sequence must be the reverse. V DDQ must not exceed V DD .2.Most speed grades and configurations of this device are offered in both Commercial and Industrial Temperature ranges. Thepart number of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device.Operating TemperatureParameterSymbolMin.Typ.Max.UnitAmbient Temperature (Commercial Range Versions)T A 02570°C Ambient Temperature (Industrial Range Versions)T A–402585°CGS8662D08/09/18/36E-333/300/250/200/167HSTL I/O DC Input CharacteristicsParameterSymbolMinMaxUnitsNotesDC Input Logic High V IH (dc)V REF + 0.1V DD + 0.3 V 1DC Input Logic LowV IL (dc)–0.3V REF – 0.1V1Notes:patible with both 1.8 V and 1.5 V I/O drivers2.These are DC test criteria. DC design criteria is V REF ± 50 mV. The AC V IH /V IL levels are defined separately for measuring timing param-eters.3.V IL (Min)DC = –0.3 V, V IL (Min)AC = –1.5 V (pulse width ≤ 3 ns).4.V IH (Max)DC = V DDQ + 0.3 V, V IH (Max)AC = V DDQ + 0.85 V (pulse width ≤ 3 ns).HSTL I/O AC Input CharacteristicsParameterSymbolMinMaxUnitsNotesAC Input Logic High V IH (ac)V REF + 200—mV 3,4AC Input Logic LowV IL (ac)—V REF – 200mV 3,4V REF Peak to Peak AC VoltageV REF (ac)—5% V REF (DC)mV1Notes:1.The peak to peak AC component superimposed on V REF may not exceed 5% of the DC component of V REF .2.To guarantee AC characteristics, V IH ,V IL , Trise, and Tfall of inputs and clocks must be within 10% of each other.3.For devices supplied with HSTL I/O input buffers. Compatible with both 1.8 V and 1.5 V I/O drivers.20% tKHKHV SS – 1.0 V50%V SS V IHUndershoot Measurement and TimingOvershoot Measurement and Timing20% tKHKHV DD + 1.0 V50%V DDV ILCapacitanceo C, f = 1 MH Z , V DDParameterSymbolTest conditionsTyp.Max.UnitInput Capacitance C IN V IN = 0 V 45pF Output Capacitance C OUT V OUT = 0 V 67pF Clock CapacitanceC CLKV IN = 0 V56pFNote:This parameter is sample tested.GS8662D08/09/18/36E-333/300/250/200/167AC Test ConditionsParameterConditionsInput high level 1.25 V Input low level 0.25 V Max. input slew rate 2 V/ns Input reference level 0.75 V Output reference levelV DDQ /2Note:Test conditions as specified with output loading as shown unless otherwise noted.DQVT = V DDQ /250ΩRQ = 250 Ω (HSTL I/O)V REF = 0.75 VAC Test Load DiagramInput and Output Leakage CharacteristicsParameterSymbolTest ConditionsMin.MaxNotesInput Leakage Current (except mode pins)I IL V IN = 0 to V DD –2 uA 2 uA DoffI INDOFF V DD ≥ V IN ≥ V IL 0 V ≤ V IN ≤ V IL –2 uA –2 uA 2 uA 2 uA Output Leakage CurrentI OLOutput Disable,V OUT = 0 to V DDQ–2 uA2 uA(T A = 25= 1.8 V)GS8662D08/09/18/36E-333/300/250/200/167Programmable Impedance HSTL Output Driver DC Electrical CharacteristicsParameterSymbolMin.Max.UnitsNotesOutput High Voltage V OH1 V DDQ /2 – 0.12V DDQ /2 + 0.12V 1, 3Output Low Voltage V OL1 V DDQ /2 – 0.12V DDQ /2 + 0.12V 2, 3Output High Voltage V OH2 V DDQ – 0.2V DDQ V 4, 5Output Low VoltageV OL2Vss0.2V4, 6Notes:1. I OH = (V DDQ /2) / (RQ/5) +/– 15% @ V OH = V DDQ /2 (for: 175Ω ≤ RQ ≤ 350Ω).2. I OL = (V DDQ /2) / (RQ/5) +/– 15% @ V OL = V DDQ /2 (for: 175Ω ≤ RQ ≤ 350Ω).3.Parameter tested with RQ = 250Ω and V DDQ = 1.5 V or 1.8 V4.Minimum Impedance mode, ZQ = V SS5.I OH = –1.0 mA6.I OL = 1.0 mAOperating CurrentsParameterSymbolTest Conditions-333-300-250-200-167Notes0to 70°C –40 to 85°C 0to 70°C –40 to 85°C 0to 70°C –40 to 85°C 0to 70°C –40 to 85°C 0to 70°C –40 to 85°C Operating Current (x36): DDR I DD V DD = Max, I OUT = 0 mA Cycle Time ≥ t KHKH Min TBDTBDTBDTBDTBDTBDTBDTBDTBDTBD2, 3Operating Current (x18): DDR I DD V DD = Max, I OUT = 0 mA Cycle Time ≥ t KHKH Min TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 2, 3Operating Current (x9): DDR I DD V DD = Max, I OUT = 0 mA Cycle Time ≥ t KHKH Min TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 2, 3Operating Current (x8): DDR I DDV DD = Max, I OUT = 0 mA Cycle Time ≥ t KHKH Min TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 2, 3Standby Current (NOP): DDR I SB1Device deselected,IOUT = 0 mA, f = Max,All Inputs ≤ 0.2 V or ≥ V DD – 0.2 VTBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 2, 4Notes:1.Power measured with output pins floating.2.Minimum cycle, I OUT = 0 mA3.Operating current is calculated with 50% read cycles and 50% write cycles.4.Standby Current is only after all pending read and write burst operations are completed.GS8662D08/09/18/36E-333/300/250/200/167AC Electrical CharacteristicsParameter Symbol-333-300-250-200-167Units Notes Min Max Min Max Min Max Min Max Min MaxClockK, K Clock Cycle Time C, C Clock Cycle Time t KHKHt CHCH3.0 3.5 3.34.2 4.0 6.35.07.886.08.4nstKC Variable t KCVar—0.2—0.2—0.2—0.2—0.2ns5K, K Clock High Pulse Width C, C Clock High Pulse Width t KHKLt CHCL1.2— 1.32— 1.6—2.0— 2.4—nsK, K Clock Low Pulse Width C, C Clock Low Pulse Width t KLKHt CLCH1.2— 1.32— 1.6—2.0— 2.4—nsK to K HighC to C Hight KHKH 1.35— 1.49— 1.8— 2.2— 2.7—nsK, K Clock High to C, C Clock High t KHCH0 1.300 1.450 1.80 2.30 2.8nsDLL Lock Time t KCLock1024—1024—1024—1024—1024—cycle6 K Static to DLL reset t KCReset30—30—30—30—30—ns Output TimesK, K Clock High to Data Output Valid C, C Clock High to Data Output Valid t KHQVt CHQV—0.45—0.45—0.45—0.45—0.5ns3K, K Clock High to Data Output Hold C, C Clock High to Data Output Hold t KHQXt CHQX–0.45—–0.45—–0.45—–0.45—–0.5—ns3K, K Clock High to Echo Clock Valid C, C Clock High to Echo Clock Valid t KHCQVt CHCQV—0.45—0.45—0.45—0.45—0.5nsK, K Clock High to Echo Clock Hold C, C Clock High to Echo Clock Hold t KHCQXt CHCQX–0.45—–0.45—–0.45—–0.45—–0.5—nsCQ, CQ High Output Valid t CQHQV—0.25—0.27—0.30—0.35—0.40ns7 CQ, CQ High Output Hold t CQHQX–0.25—–0.27—–0.30—–0.35—–0.40—ns7K Clock High to Data Output High-Z C Clock High to Data Output High-Z t KHQZt CHQZ—0.45—0.45—0.45—0.45—0.5ns3K Clock High to Data Output Low-Z C Clock High to Data Output Low-Z t KHQX1t CHQX1–0.45—–0.45—–0.45—–0.45—–0.5—ns3Setup TimesAddress Input Setup Time t AVKH0.4—0.4—0.5—0.6—0.7—ns Control Input Setup Time t IVKH0.4—0.4—0.5—0.6—0.7—ns2 Data Input Setup Time t DVKH0.28—0.3—0.35—0.4—0.5—ns。

GS8662Q36GE-200中文资料

GS8662Q08/09/18/36E-300/250/200/16772Mb SigmaQuad-II Burst of 2 SRAM300 MHz–167 MHz1.8 V V DD1.8 V and 1.5 V I/O165-Bump BGA Commercial Temp Industrial Temp Features• Simultaneous Read and Write SigmaQuad™ Interface • JEDEC-standard pinout and package • Dual Double Data Rate interface• Byte Write controls sampled at data-in time • Burst of 2 Read and Write• 1.8 V +100/–100 mV core power supply • 1.5 V or 1.8 V HSTL Interface • Pipelined read operation• Fully coherent read and write pipelines• ZQ pin for programmable output drive strength • IEEE 1149.1 JTAG-compliant Boundary Scan• Pin-compatible with present 9Mb, 18Mb, and 36Mb and future 144Mb devices• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package • RoHS-compliant 165-bump BGA package availableSigmaQuad ™ Family OverviewThe GSQ8662Q08/09/18/36E are built in compliance with the SigmaQuad-II SRAM pinout standard for Separate I/O synchronous SRAMs. They are 75,497,472-bit (72Mb)SRAMs. The GSQ8662Q08/09/18/36E SigmaQuad SRAMs are just one element in a family of low power, low voltage HSTL I/O SRAMs designed to operate at the speeds needed to implement economical high performance networking systems.Clocking and Addressing SchemesThe GSQ8662Q08/09/18/36E SigmaQuad-II SRAMs are synchronous devices. They employ two input register clock inputs, K and K. K and K are independent single-ended clock inputs, not differential inputs to a single differential clock input buffer. The device also allows the user to manipulate theoutput register clock inputs quasi independently with the C andC clock inputs. C and C are also independent single-ended clock inputs, not differential inputs. If the C clocks are tied high, the K clocks are routed internally to fire the output registers instead.Because Separate I/O SigmaQuad-II B2 RAMs always transfer data in two packets, A0 is internally set to 0 for the first read or write transfer, and automatically incremented by 1 for the next transfer. Because the LSB is tied off internally, the address field of a SigmaQuad-II B2 RAM is always one address pin less than the advertised index depth (e.g., the 4M x 18 has a 2048K addressable index).Parameter Synopsis-300-250-200-167tKHKH 3.3 ns 4.0 ns 5.0 ns 6.0 ns tKHQV0.45 ns0.45 ns0.45 ns0.5 ns165-Bump, 15 mm x 17 mm BGA 1 mm Bump Pitch, 11 x 15 Bump ArrayBottom View2M x 36 SigmaQuad-II SRAM—Top View1234567891011ACQ MCL/SA (288Mb)SA W BW2K BW1R SA MCL/SA (144Mb)CQ B Q27Q18D18SA BW3K BW0SA D17Q17Q8C D27Q28D19V SS SA SA SA V SS D16Q7D8D D28D20Q19V SS V SS V SS V SS V SS Q16D15D7E Q29D29Q20 V DDQ V SS V SS V SS V DDQ Q15D6Q6F Q30Q21D21 V DDQ V DD V SS V DD V DDQ D14Q14Q5G D30D22Q22 V DDQ V DD V SS V DD V DDQ Q13D13D5H Doff V REF V DDQ V DDQ V DD V SS V DD V DDQ V DDQ V REF ZQ J D31Q31D23 V DDQ V DD V SS V DD V DDQ D12Q4D4K Q32D32Q23V DDQ V DD V SS V DD V DDQ Q12D3Q3L Q33Q24D24 V DDQ V SS V SS V SS V DDQ D11Q11Q2M D33Q34D25 V SS V SS V SS V SS V SS D10Q1D2N D34D26Q25 V SS SA SA SA V SS Q10D9D1P Q35D35Q26SA SA C SA SA Q9D0Q0RTDOTCKSASASACSASASATMSTDI11 x 15 Bump BGA—15 x 17 mm 2 Body—1 mm Bump PitchNotes:1.BW0 controls writes to D0:D8; BW1 controls writes to D9:D17; BW2 controls writes to D18:D26; BW3 controls writes to D27:D352.MCL = Must Connect LowGS8662Q08/09/18/36E-300/250/200/1674M x 18 SigmaQuad-II SRAM—Top View1234567891011ACQ MCL/SA (144Mb)SA W BW1K NC R SA SA CQ B NC Q9D9SA NC K BW0SA NC NC Q8C NC NC D10V SS SA SA SA V SS NC Q7D8D NC D11Q10V SS V SS V SS V SS V SS NC NC D7E NC NC Q11 V DDQ V SS V SS V SS V DDQ NC D6Q6F NC Q12D12 V DDQ V DD V SS V DD V DDQ NC NC Q5G NC D13Q13 V DDQ V DD V SS V DD V DDQ NC NC D5H Doff V REF V DDQ V DDQ V DD V SS V DD V DDQ V DDQ V REF ZQ J NC NC D14 V DDQ V DD V SS V DD V DDQ NC Q4D4K NC NC Q14V DDQ V DD V SS V DD V DDQ NC D3Q3L NC Q15D15 V DDQ V SS V SS V SS V DDQ NC NC Q2M NC NC D16 V SS V SS V SS V SS V SS NC Q1D2N NC D17Q16 V SS SA SA SA V SS NC NC D1P NC NC Q17SA SA C SA SA NC D0Q0RTDOTCKSASASACSASASATMSTDI11 x 15 Bump BGA—15 x 17 mm 2 Body—1 mm Bump PitchNotes:1.BW0 controls writes to D0:D8. BW1 controls writes to D9:D17.2.MCL = Must Connect LowGS8662Q08/09/18/36E-300/250/200/1678M x 8 SigmaQuad-II SRAM—Top View1234567891011ACQ SA SA W NW1K NC R SA SA CQ B NC NC NC SA NC K NW0SA NC NC Q3C NC NC NC V SS SA SA SA V SS NC NC D3D NC D4NC V SS V SS V SS V SS V SS NC NC NC E NC NC Q4 V DDQ V SS V SS V SS V DDQ NC D2Q2F NC NC NC V DDQ V DD V SS V DD V DDQ NC NC NC G NC D5Q5 V DDQ V DD V SS V DD V DDQ NC NC NC H Doff V REF V DDQ V DDQ V DD V SS V DD V DDQ V DDQ V REF ZQ J NC NC NC V DDQ V DD V SS V DD V DDQ NC Q1D1K NC NC NC V DDQ V DD V SS V DD V DDQ NC NC NC L NC Q6D6 V DDQ V SS V SS V SS V DDQ NC NC Q0M NC NC NC V SS V SS V SS V SS V SS NC NC D0N NC D7NC V SS SA SA SA V SS NC NC NC P NC NC Q7SA SA C SA SA NC NC NC RTDOTCKSASASACSASASATMSTDI11 x 15 Bump BGA—15 x 17 mm 2 Body—1 mm Bump PitchNotes:1.NW0 controls writes to D0:D3. NW1 controls writes to D4:D7.2.MCL = Must Connect LowGS8662Q08/09/18/36E-300/250/200/1678M x 9 SigmaQuad-II SRAM — Top View1234567891011ACQ SA SA W NC K NC R SA SA CQ B NC NC NC SA NC K BW SA NC NC Q4C NC NC NC V SS SA SA SA V SS NC NC D4D NC D5NC V SS V SS V SS V SS V SS NC NC NC E NC NC Q5 V DDQ V SS V SS V SS V DDQ NC D3Q3F NC NC NC V DDQ V DD V SS V DD V DDQ NC NC NC G NC D6Q6 V DDQ V DD V SS V DD V DDQ NC NC NC H Doff V REF V DDQ V DDQ V DD V SS V DD V DDQ V DDQ V REF ZQ J NC NC NC V DDQ V DD V SS V DD V DDQ NC Q2D2K NC NC NC V DDQ V DD V SS V DD V DDQ NC NC NC L NC Q7D7 V DDQ V SS V SS V SS V DDQ NC NC Q1M NC NC NC V SS V SS V SS V SS V SS NC NC D1N NC D8NC V SS SA SA SA V SS NC NC NC P NC NC Q8SA SA C SA SA NC D0Q0RTDOTCKSASASACSASASATMSTDI11 x 15 Bump BGA—15 x 17 mm 2 Body—1 mm Bump PitchNote: MCL = Must Connect LowGS8662Q08/09/18/36E-300/250/200/167Pin Description TableSymbolDescriptionTypeCommentsSA Synchronous Address InputsInput —NC No Connect ——R Synchronous Read Input Active Low W Synchronous Write Input Active Low BW Synchronous Byte Write Input Active Low x9 only BW0–BW3Synchronous Byte Writes Input Active Low x18/x36 only NW0–NW1Nybble Write Control PinInput Active Low x8 only K Input Clock Input Active High K Input Clock Input Active Low C Output Clock Input Active High C Output Clock Input Active LowTMS Test Mode Select Input —TDI Test Data Input Input —TCK Test Clock Input Input —TDO Test Data Output Output —V REF HSTL Input Reference Voltage Input —ZQ Output Impedance Matching Input Input —Qn Synchronous Data Outputs Output Dn Synchronous Data Inputs Input D off Disable DLL when low Input Active LowCQ Output Echo Clock Output —CQ Output Echo Clock Output —V DD Power Supply Supply 1.8 V Nominal V DDQ Isolated Output Buffer Supply Supply 1.5 or 1.8 V NominalV SSPower Supply: GroundSupply—GS8662Q08/09/18/36E-300/250/200/167Note:NC = Not Connected to die or any other pinGS8662Q08/09/18/36E-300/250/200/167BackgroundSeparate I/O SRAMs, from a system architecture point of view, are attractive in applications where alternating reads and writes are needed. Therefore, the SigmaQuad-II SRAM interface and truth table are optimized for alternating reads and writes. Separate I/O SRAMs are unpopular in applications where multiple reads or multiple writes are needed because burst read or write transfers from Separate I/O SRAMs can cut the RAM’s bandwidth in half.Alternating Read-Write OperationsSigmaQuad-II SRAMs follow a few simple rules of operation.- Read or Write commands issued on one port are never allowed to interrupt an operation in progress on the other port.- Read or Write data transfers in progress may not be interrupted and re-started. - R and W high always deselects the RAM.- All address, data, and control inputs are sampled on clock edges.In order to enforce these rules, each RAM combines present state information with command inputs. See the Truth Table for details.SigmaQuad-II B2 SRAM DDR ReadThe read port samples the status of the Address Input and R pins at each rising edge of K. A low on the Read Enable-bar pin, R, begins a read cycle. Data can be clocked out after the next rising edge of K with a rising edge of C (or by K if C and C are tied high), and after the following rising edge of K with a rising edge of C (or by K if C and C are tied high). Clocking in a high on the Read Enable-bar pin, R, begins a read port deselect cycle.SigmaQuad-II B2 Double Data Rate SRAM Read FirstRead ANOPWrite BRead C Write DRead E Write FRead G Write HA B C D E F G HB B+1D D+1F F+1H H+1B B+1D D+1F F+1H H+1A A+1C C+1EKKAddress RWBWx D CCQ CQCQGS8662Q08/09/18/36E-300/250/200/167SigmaQuad-II B2 SRAM DDR WriteThe write port samples the status of the W pin at each rising edge of K and the Address Input pins on the following rising edge of K. A low on the Write Enable-bar pin, W, begins a write cycle. The first of the data-in pairs associated with the write command is clocked in with the same rising edge of K used to capture the write command. The second of the two data in transfers is captured on the rising edge of K along with the write address. Clocking in a high on W causes a write port deselect cycle.SigmaQuad-II B2 Double Data Rate SRAM Write FirstWrite ARead BRead C Write DNOPRead E Write FRead G Write HNOPA B C D E F G HA A+1D D+1F F+1H H+1A A+1D D+1F F+1H H+1B B+1C C+1E E+1KKAddress RWBWx D CCQ CQCQGS8662Q08/09/18/36E-300/250/200/167Power-Up Sequence for SigmaQuad-II SRAMsSigmaQuad-II SRAMs must be powered-up in a specific sequence in order to avoid undefined operations.Power-Up Sequence1. Power-up and maintain Doff at low state.1a.Apply V DD .1b. Apply V DDQ .1c. Apply V REF (may also be applied at the same time as V DDQ ).2. After power is achieved and clocks (K, K, C, C) are stablized, change Doff to high.3. An additional 1024 clock cycles are required to lock the DLL after it has been enabled.Note:If you want to tie Doff high with an unstable clock, you must stop the clock for a minimum of 30 seconds to reset the DLL after the clocks become stablized.DLL Constraints•The DLL synchronizes to either K or C clock. These clocks should have low phase jitter (t KCVar on page 21).•The DLL cannot operate at a frequency lower than 119 MHz.•If the incoming clock is not stablized when DLL is enabled, the DLL may lock on the wrong frequency and cause undefined errors or failures during the initial stage.Power-Up Sequence (Doff controlled)Power UP IntervalUnstable Clocking IntervalDLL Locking Interval (1024 Cycles)Normal OperationKKV DDV DDQV REFDoffPower-Up Sequence (Doff tied High)Power UP IntervalUnstable Clocking IntervalStop Clock IntervalDLL Locking Interval (1024 Cycles)Normal OperationKKV DDV DDQV REFDoff30ns MinNote:If the frequency is changed, DLL reset is required. After reset, a minimum of 1024 cycles is required for DLL lock.GS8662Q08/09/18/36E-300/250/200/167Special FunctionsByte Write and Nybble Write ControlByte Write Enable pins are sampled at the same time that Data In is sampled. A high on the Byte Write Enable pin associated with a particular byte (e.g., BW0 controls D0–D8 inputs) will inhibit the storage of that particular byte, leaving whatever data may be stored at the current address at that byte location undisturbed. Any or all of the Byte Write Enable pins may be driven high or low during the data in sample times in a write sequence.Each write enable command and write address loaded into the RAM provides the base address for a 2 beat data transfer. The x18 version of the RAM, for example, may write 36 bits in association with each address loaded. Any 9-bit byte may be masked in any write sequence.Nybble Write (4-bit) control is implemented on the 8-bit-wide version of the device. For the x8 version of the device, “Nybble Write Enable” and “NBx” may be substituted in all the discussion above.Example x18 RAM Write Sequence using Byte Write EnablesData In SampleTimeBW0BW1D0–D8D9–D17Beat 101Data In Don’t CareBeat 210Don’t Care Data InResulting Write OperationByte 1 D0–D8Byte 2D9–D17Byte 3D0–D8Byte 4D9–D17Written Unchanged Unchanged WrittenBeat 1Beat 2Output Register ControlSigmaQuad-II SRAMs offer two mechanisms for controlling the output data registers. Typically, control is handled by the Output Register Clock inputs, C and C. The Output Register Clock inputs can be used to make small phase adjustments in the firing of the output registers by allowing the user to delay driving data out as much as a few nanoseconds beyond the next rising edges of the K and K clocks. If the C and C clock inputs are tied high, the RAM reverts to K and K control of the outputs, allowing the RAM to function as a conventional pipelined read SRAM.A K RW A 0–AnK W 0D 1–D nBank 0Bank 1Bank 2Bank 3R 0D A K W D A K W D A K W D R R R QQQQCCCCQ 1–Q nC W 1R 1W 2R 2W 3R 3Note:For simplicity BWn, NWn, K, and C are not shown.CQ CQ CQ CQ CQ 0CQ 1CQ 2CQ 3GS8662Q08/09/18/36E-300/250/200/167Example Four Bank Depth Expansion SchematicΣ2x 2B 2 S i g m a Q u a d -I IS R A MD e p t hE x p a n s i o nR e a d A W r i t e BR e a d C W r i t e D R e a d E W r i t e F R e a d G W r i t e H R e a d I W r i t e J R e a d K W r i t e L N O PAB C D E F G H I J K LF F +1H H +1J J +1F F +1H H +1J J +1BB +1D D +1L L +1BB +1D D +1L L +1A A +1G G +1I I +1C C +1E E +1KKA d d r e s s R (B a n k 1)R (B a n k 2)W (B a n k 1)W (B a n k 2)B W x (B a n k 1)D (B a n k 1)B W x (B a n k 2)D (B a n k 2)C (B a n k 1)C (B a n k 1)Q (B a n k 1)C Q (B a n k 1)C Q (B a n k 1)C (B a n k 2)C (B a n k 2)Q (B a n k 2)C Q (B a n k 2)C Q (B a n k 2)GS8662Q08/09/18/36E-300/250/200/167GS8662Q08/09/18/36E-300/250/200/167FLXDrive-II Output Driver Impedance ControlHSTL I/O SigmaQuad-II SRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected to V SS via an external resistor, RQ, to allow the SRAM to monitor and adjust its output driver impedance. The value of RQ must be 5X the value of the desired RAM output impedance. The allowable range of RQ to guarantee impedance matching continuously is between 150Ω and 300Ω. Periodic readjustment of the output driver impedance is necessary as the impedance is affected by drifts in supply voltage and temperature. The SRAM’s output impedance circuitry compensates for drifts in supply voltage and temperature. A clock cycle counter periodically triggers an impedance evaluation, resets and counts again. Each impedance evaluation may move the output driver impedance level one step at a time towards the optimum level. The output driver isimplemented with discrete binary weighted impedance steps. Updates of pull-down drive impedance occur whenever a driver is producing a “1” or is High-Z. Pull-up drive impedance is updated when a driver is producing a “0” or is High-Z.SigmaQuad-II B2 Coherency and Pass Through FunctionsBecause the SigmaQuad-II B2 read and write commands are loaded at the same time, there may be some confusion over what constitutes “coherent” operation. Normally, one would expect a RAM to produce the just-written data when it is read immediately after a write. This is true of the SigmaQuad-II B2 except in one case, as is illustrated in the following diagram. If the user holds the same address value in a given K clock cycle, loading the same address as a read address and then as a matching write address, the SigmaQuad-II B2 will read or “Pass-thru” the latest data input, rather than the data from the previously completed write operation.SigmaQuad-II B2 Coherency and Pass Through FunctionsSeparate I/O SigmaQuad-II B2 SigmaQuad-II SRAM Read Truth TableA R Output Next StateQ Q K ↑(t n )K ↑(t n )K ↑(t n )K ↑(t n+1)K ↑(t n+1½)X 1Deselect Hi-Z Hi-Z VReadQ0Q1Notes:1.X = Don’t Care, 1 = High, 0 = Low, V = Valid.2.R is evaluated on the rising edge of K.3.Q0 and Q1 are the first and second data output transfers in a read.Separate I/O SigmaQuad-II B2 SigmaQuad-II SRAM Write Truth TableA W BWn BWn Input Next State D D K ↑(t n + ½)K ↑(t n )K ↑(t n )K ↑(t n + ½)K ↑, K ↑(t n ), (t n + ½)K ↑(t n )K ↑(t n + ½)V 000Write Byte Dx0, Write Byte Dx1D0D1V 001Write Byte Dx0, Write Abort Byte Dx1D0X V 010Write Abort Byte Dx0, Write Byte Dx1X D1X 011Write Abort Byte Dx0, Write Abort Byte Dx1X X X1XXDeselectXXNotes:1.X = Don’t Care, H = High, L = Low, V = Valid.2.W is evaluated on the rising edge of K.3.D0 and D1 are the first and second data input transfers in a write.4.BWn represents any of the Byte Write Enable inputs (BW0, BW1, etc.).GS8662Q08/09/18/36E-300/250/200/167x36 Byte Write Enable (BWn) Truth TableBW0BW1BW2BW3D0–D8D9–D17D18–D26D27–D351111Don’t Care Don’t Care Don’t Care Don’t Care 0111Data In Don’t Care Don’t Care Don’t Care 1011Don’t Care Data In Don’t Care Don’t Care 0011Data In Data In Don’t Care Don’t Care 1101Don’t Care Don’t Care Data In Don’t Care 0101Data In Don’t Care Data In Don’t Care 1001Don’t Care Data In Data In Don’t Care 0001Data In Data In Data In Don’t Care 1110Don’t Care Don’t Care Don’t Care Data In 0110Data In Don’t Care Don’t Care Data In 1010Don’t Care Data In Don’t Care Data In 0010Data In Data In Don’t Care Data In 1100Don’t Care Don’t Care Data In Data In 0100Data In Don’t Care Data In Data In 1000Don’t Care Data In Data In Data In 0Data InData InData InData Inx18 Byte Write Enable (BWn) Truth Table BW0BW1D0–D8D9–D1711Don’t Care Don’t Care 01Data In Don’t Care 10Don’t Care Data In 0Data InData Inx8 Nybble Write Enable (NWn) Truth Table NW0NW1D0–D3D4–D711Don’t Care Don’t Care 01Data In Don’t Care 10Don’t Care Data In 0Data InData InGS8662Q08/09/18/36E-300/250/200/167GS8662Q08/09/18/36E-300/250/200/167State DiagramPower-UpRead NOPLoad New Read Address DDR Read Write NOPLoad New Write AddressDDR WriteWRITEREAD READ WRITEREAD WRITEAlways (Fixed)Always (Fixed)READWRITENotes:1.Internal burst counter is fixed as 1-bit linear (i.e., when first address is A0+), next internal burst address is A0+1.2.“READ” refers to read active status with R = Low, “READ” refers to read inactive status with R = High. The same istrue for “WRITE” and “WRITE”.3.Read and write state machine can be active simultaneously.4.State machine control timing sequence is controlled by K.Absolute Maximum Ratings(All voltages reference to V SS )SymbolDescriptionValueUnitV DD Voltage on V DD Pins –0.5 to 2.9V V DDQ Voltage in V DDQ Pins –0.5 to V DD V V REF Voltage in V REF Pins –0.5 to V DDQV V I/O Voltage on I/O Pins –0.5 to V DDQ +0.5 (≤ 2.9 V max.)V V IN Voltage on Other Input Pins –0.5 to V DDQ +0.5 (≤ 2.9 V max.)V I IN Input Current on Any Pin +/–100mA dc I OUT Output Current on Any I/O Pin +/–100mA dcT J Maximum Junction Temperature125o C T STGStorage Temperature–55 to 125oCNote:Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Recommended Operating Conditions, for an extended period of time, may affect reliability of this component.GS8662Q08/09/18/36E-300/250/200/167Recommended Operating ConditionsPower SuppliesParameterSymbolMin.Typ.Max.UnitSupply Voltage V DD 1.7 1.8 1.9V I/O Supply Voltage V DDQ 1.4 1.5V DD V Reference VoltageV REF0.68—0.95VNotes:1.The power supplies need to be powered up simultaneously or in the following sequence: V DD , V DDQ , V REF , followed by signalinputs. The power down sequence must be the reverse. V DDQ must not exceed V DD .2.Most speed grades and configurations of this device are offered in both Commercial and Industrial Temperature ranges. Thepart number of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device.Operating TemperatureParameterSymbolMin.Typ.Max.UnitAmbient Temperature (Commercial Range Versions)T A 02570°C Ambient Temperature (Industrial Range Versions)T A–402585°CGS8662Q08/09/18/36E-300/250/200/167HSTL I/O DC Input CharacteristicsParameterSymbolMinMaxUnitsNotesDC Input Logic High V IH (dc)V REF + 0.1V DD + 0.3 V 1DC Input Logic LowV IL (dc)–0.3V REF – 0.1V1Notes:patible with both 1.8 V and 1.5 V I/O drivers2.These are DC test criteria. DC design criteria is V REF ± 50 mV. The AC V IH /V IL levels are defined separately for measuring timing param-eters.3.V IL (Min)DC = –0.3 V, V IL (Min)AC = –1.5 V (pulse width ≤ 3 ns).4.V IH (Max)DC = V DDQ + 0.3 V, V IH (Max)AC = V DDQ + 0.85 V (pulse width ≤ 3 ns).HSTL I/O AC Input CharacteristicsParameterSymbolMinMaxUnitsNotesAC Input Logic High V IH (ac)V REF + 200—mV 3,4AC Input Logic LowV IL (ac)—V REF – 200mV 3,4V REF Peak to Peak AC VoltageV REF (ac)—5% V REF (DC)mV1Notes:1.The peak to peak AC component superimposed on V REF may not exceed 5% of the DC component of V REF .2.To guarantee AC characteristics, V IH ,V IL , Trise, and Tfall of inputs and clocks must be within 10% of each other.3.For devices supplied with HSTL I/O input buffers. Compatible with both 1.8 V and 1.5 V I/O drivers.20% tKHKHV SS – 1.0 V50%V SS V IHUndershoot Measurement and TimingOvershoot Measurement and Timing20% tKHKHV DD + 1.0 V50%V DDV ILCapacitanceo C, f = 1 MH Z , V DDParameterSymbolTest conditionsTyp.Max.UnitInput Capacitance C IN V IN = 0 V 45pF Output Capacitance C OUT V OUT = 0 V 67pF Clock CapacitanceC CLKV IN = 0 V56pFNote:This parameter is sample tested.GS8662Q08/09/18/36E-300/250/200/167AC Test ConditionsParameterConditionsInput high level 1.25 V Input low level 0.25 V Max. input slew rate 2 V/ns Input reference level 0.75 V Output reference levelV DDQ /2Note:Test conditions as specified with output loading as shown unless otherwise noted.DQVT = V DDQ /250ΩRQ = 250 Ω (HSTL I/O)V REF = 0.75 VAC Test Load DiagramInput and Output Leakage CharacteristicsParameterSymbolTest ConditionsMin.MaxNotesInput Leakage Current (except mode pins)I IL V IN = 0 to V DD –2 uA 2 uA DoffI INDOFF V DD ≥ V IN ≥ V IL 0 V ≤ V IN ≤ V IL –2 uA –2 uA 2 uA 2 uA Output Leakage CurrentI OLOutput Disable,V OUT = 0 to V DDQ–2 uA2 uA(T A = 25= 1.8 V)GS8662Q08/09/18/36E-300/250/200/167Programmable Impedance HSTL Output Driver DC Electrical CharacteristicsParameterSymbolMin.Max.UnitsNotesOutput High Voltage V OH1 V DDQ /2 – 0.12V DDQ /2 + 0.12V 1, 3Output Low Voltage V OL1 V DDQ /2 – 0.12V DDQ /2 + 0.12V 2, 3Output High Voltage V OH2 V DDQ – 0.2V DDQ V 4, 5Output Low VoltageV OL2Vss0.2V4, 6Notes:1. I OH = (V DDQ /2) / (RQ/5) +/– 15% @ V OH = V DDQ /2 (for: 175Ω ≤ RQ ≤ 350Ω).2. I OL = (V DDQ /2) / (RQ/5) +/– 15% @ V OL = V DDQ /2 (for: 175Ω ≤ RQ ≤ 350Ω).3.Parameter tested with RQ = 250Ω and V DDQ = 1.5 V or 1.8 V4.Minimum Impedance mode, ZQ = V SS5.I OH = –1.0 mA6.I OL = 1.0 mAOperating CurrentsParameterSymbolTest Conditions-300-250-200-167Notes0to 70°C –40 to 85°C0to 70°C –40 to 85°C0to 70°C –40 to 85°C0to 70°C –40 to 85°C Operating Current (x36): DDR I DD V DD = Max, I OUT = 0 mA Cycle Time ≥ t KHKH Min 900 mA920 mA 800 mA820 mA 670 mA690 mA 590 mA610 mA2, 3Operating Current (x18): DDR I DD V DD = Max, I OUT = 0 mA Cycle Time ≥ t KHKH Min 840 mA 860 mA 740 mA 760 mA 620 mA 640 mA 550 mA 570 mA 2, 3Operating Current (x9): DDR I DD V DD = Max, I OUT = 0 mA Cycle Time ≥ t KHKH Min 840 mA 860 mA 740 mA 760 mA 620 mA 640 mA 550 mA 570 mA 2, 3Operating Current (x8): DDR I DDV DD = Max, I OUT = 0 mA Cycle Time ≥ t KHKH Min 840 mA 860 mA 740 mA 760 mA 620 mA 640 mA 550 mA 570 mA 2, 3Standby Current (NOP): DDR I SB1Device deselected,I OUT = 0 mA, f = Max,All Inputs ≤ 0.2 V or ≥ V DD – 0.2 V330 mA 340 mA 300 mA 310 mA 280 mA 290 mA 260 mA 270 mA 2, 4Notes:1.Power measured with output pins floating.2.Minimum cycle, I OUT = 0 mA3.Operating current is calculated with 50% read cycles and 50% write cycles.4.Standby Current is only after all pending read and write burst operations are completed.GS8662Q08/09/18/36E-300/250/200/167AC Electrical CharacteristicsParameter Symbol-300-250-200-167Units Notes Min Max Min Max Min Max Min MaxClockK, K Clock Cycle Time C, C Clock Cycle Time t KHKHt CHCH3.34.2 4.0 6.35.07.886.08.4nstKC Variable t KCVar—0.2—0.2—0.2—0.2ns5K, K Clock High Pulse Width C, C Clock High Pulse Width t KHKLt CHCL1.32— 1.6—2.0— 2.4—nsK, K Clock Low Pulse Width C, C Clock Low Pulse Width t KLKHt CLCH1.32— 1.6—2.0— 2.4—nsK to K HighC to C Hight KHKH 1.49— 1.8— 2.2— 2.7—nsK, K Clock High to C, C Clock High t KHCH0 1.450 1.80 2.30 2.8nsDLL Lock Time t KCLock1024—1024—1024—1024—cycle6 K Static to DLL reset t KCReset30—30—30—30—ns Output TimesK, K Clock High to Data Output Valid C, C Clock High to Data Output Valid t KHQVt CHQV—0.45—0.45—0.45—0.5ns3K, K Clock High to Data Output Hold C, C Clock High to Data Output Hold t KHQXt CHQX–0.45—–0.45—–0.45—–0.5—ns3K, K Clock High to Echo Clock Valid C, C Clock High to Echo Clock Valid t KHCQVt CHCQV—0.45—0.45—0.45—0.5nsK, K Clock High to Echo Clock Hold C, C Clock High to Echo Clock Hold t KHCQXt CHCQX–0.45—–0.45—–0.45—–0.5—nsCQ, CQ High Output Valid t CQHQV—0.27—0.30—0.35—0.40ns7 CQ, CQ High Output Hold t CQHQX–0.27—–0.30—–0.35—–0.40—ns7K Clock High to Data Output High-Z C Clock High to Data Output High-Z t KHQZt CHQZ—0.45—0.45—0.45—0.5ns3K Clock High to Data Output Low-Z C Clock High to Data Output Low-Z t KHQX1t CHQX1–0.45—–0.45—–0.45—–0.5—ns3Setup TimesAddress Input Setup Time t AVKH0.3—0.35—0.4—0.5—nsControl Input Setup Time t IVKH0.3—0.35—0.4—0.5—ns2 Data Input Setup Time t DVKH0.3—0.35—0.4—0.5—nsGS8662Q08/09/18/36E-300/250/200/167Hold TimesAddress Input Hold Time t KHAX 0.3—0.35—0.4—0.5—ns Control Input Hold Time t KHIX 0.3—0.35—0.4—0.5—ns Data Input Hold Timet KHDX0.3—0.35—0.4—0.5—nsNotes:1.All Address inputs must meet the specified setup and hold times for all latching clock edges.2.Control singles are R, W, BW0, BW1, and (NW0, NW1 for x8) and (BW2, BW3 for x36).3.If C, C are tied high, K, K become the references for C, C timing parameters4.To avoid bus contention, at a given voltage and temperature tCHQX1 is bigger than tCHQZ. The specs as shown do not imply bus contention because tCHQX1 is a MIN parameter that is worst case at totally different test conditions (0°C, 1.9 V) than tCHQZ, which is a MAX parameter (worst case at 70°C, 1.7 V). It is not possible for two SRAMs on the same board to be at such different voltages and temperatures.5.Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.6.V DD slew rate must be less than 0.1 V DC per 50 ns for DLL lock retention. DLL lock time begins once V DD and input clock are stable.7.Echo clock is very tightly controlled to data valid/data hold. By design, there is a ±0.1 ns variation from echo clock to data. The datasheet parameters reflect tester guard bands and test setup variations.AC Electrical Characteristics (Continued)ParameterSymbol-300-250-200-167Units NotesMinMaxMinMaxMinMaxMinMax。

GS88237BB-333I中文资料

Functional Description
Applications The GS88237BB/D is a 9,437,184-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support.
Core and Interface Voltages The GS88237BB/D operates on a 2.5 V or 3.3 V power supply. All input are 3.3 V and 2.5 V compatible. Separate output power (VDDQ) pins are used to decouple output noise from the internal circuits and are 3.3 V and 2.5 V compatible.
Byte Write and Global Write Byte write operation is performed by using Byte Write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the Byte Write control inputs.

GS881E36T-11I中文资料

GS881E18/36T-11/11.5/100/80/66512K x 18, 256K x 36 ByteSafe™8Mb Sync Burst SRAMs100 MHz–66 MHz3.3 V V DD 3.3 V and 2.5 V I/O100-Pin TQFP Commercial TempIndustrial Temp1.10 9/2000Featuresoperation• Dual Cycle Deselect (DCD) operation• IEEE 1149.1 JTAG-compatible Boundary Scan• On-chip write parity checking; even or odd selectable• 3.3 V +10%/–5% core power supply• 2.5 V or 3.3 V I/O supply• Internal input resistors on mode pins allow floating mode pins • Default to Interleaved Pipeline mode• Common data inputs and data outputs• Clock Control, registered, address, data, and control• Internal self-timed write cycle• Automatic power-down for portable applications• 100-lead TQFP packageFunctional DescriptionApplicationsThe GS881E18//36T is a 9,437,184-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support. Controlsand power down control (ZZ) are asynchronous inputs. Burst Burst mode, subsequent burst addresses are generated counter may be configured to count in either linear or interleave order with the Linear Burst Order (LBO) input. The Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance. Flow Through/Pipeline ReadsThe function of the Data Output register can be controlled by the user via the FT mode pin (Pin 14). Holding the FT mode pin low places the RAM in Flow Through mode, causing output data to bypass the Data Output Register. Holding FT high places the RAM in Pipeline mode, activating the rising-edge-triggered Data Output Register.DCD Pipelined ReadsThe GS881E18//36T is a DCD (Dual Cycle Deselect) pipelined synchronous SRAM. SCD (Single Cycle Deselect) versions are also available. DCD SRAMs pipeline disable commands to the same degree as read commands. DCD RAMs hold the deselect command for one full cycle and then begin turning off their outputs just after the second rising edge of clock.Byte Write and Global WriteByte write operation is performed by using Byte Write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the byte write control inputs.ByteSafe™ Parity FunctionsThe GS881E18/36T features ByteSafe data security functions. See detailed discussion following.Sleep ModeLow power (Sleep mode) is attained through the assertion (high) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode.Core and Interface VoltagesThe GS881E18//36T operates on a 3.3 V power supply, and all inputs/outputs are 3.3 V- and 2.5 V-compatible. Separate output power (V DDQ) pins are used to decouple output noise from the internal circuit.-11-11.5-100-80-663-1-1-1t KQI DD4.0 ns225 mA4.0 ns225 mA4.0 ns225 mA4.5 ns200 mA5.0 ns185 mAThrough 2-1-1-1KQtCycleI DD15 ns180 mA15 ns180 mA15 ns180 mA15 ns175 mA20 ns165 mAGS881E18/36T-11/11.5/100/80/66GS881E18 100-Pin TQFP Pinout807978777675747372717069686766656463626160595857565554535251123456789101112131415161718192021222324252627282930V DDQ V SS DQ B1DQ B2V SS V DDQ DQ B3DQ B4FT V DD DP V SS DQ B5DQ B6V DDQ V SS DQ B7DQ B8DQ B9V SS V DDQ V DDQ V SS DQ A8DQ A7V SS V DDQ DQ A6DQ A5V SS QE V DD ZZ DQ A4DQ A3V DDQ V SS DQ A2DQ A1V SS V DDQ L B O A 5A 4A 3A 2A 1A 0T M S T D I V S SV D DT D O T C K A 10A 11A 12A 13A 14A 16A 6A 7E 1E 2 N C N C B BB AA 17C K G W B W VD DV S SG A D S C A D S P A D V A 8A 9A 15512K X 18Top ViewDQ A9A 18NC NC NC NC NC NC NC NCNC NC NC NC NC NC NCNC NC 100999897969594939291908988878685848382813132333435363738394041424344454647484950GS881E18/36T-11/11.5/100/80/66GS881E36 100-Pin TQFP Pinout807978777675747372717069686766656463626160595857565554535251123456789101112131415161718192021222324252627282930V DDQ V SS DQ C4DQ C3V SS V DDQ DQ C2DQ C1FT V DD DP V SS DQ D1DQ D2V DDQ V SS DQ D3DQ D4DQ D5V SS V DDQ V DDQ V SS DQ B4DQ B3V SS V DDQ DQ B2DQ B1V SS QE V DD ZZ DQ A1DQ A2V DDQ V SS DQ A3DQ A4V SS V DDQ L B O A 5A 4A 3A 2A 1A 0T M S T D I V S ST D O T C K A 10A 11A 12A 13A 14A 16A 6A 7E 1E 2 B DB CB BB AA 17C K G W B W VD DV S SG A D S C A D S P A D V A 8A 9A 15256K x 36Top ViewDQ B5DQ B9DQ B7DQ B8DQ B6DQ A6DQ A5DQ A8DQ A7DQ A9DQ C7DQ C8DQ C6DQ D6DQ D8DQ D7DQ D9DQ C5DQ C9100999897969594939291908988878685848382813132333435363738394041424344454647484950V D DGS881E18/36T-11/11.5/100/80/66 TQFP Pin DescriptioPin Location Symbol TypeDescription37, 36A0, A1I Address field LSBs and Address Counter preset Inputs 35, 34, 33, 32, 100, 99, 82, 81, 44, 45,46, 47, 48, 49, 50, 92A2–A17I Address Inputs80A18I Address Inputs63, 62, 59, 58, 57, 56, 53, 52 68, 69, 72, 73, 74, 75, 78, 79 13, 12, 9, 8, 7, 6, 3, 2 18, 19, 22, 23, 24, 25, 28, 29DQ A1–DQ A8DQ B1–DQ B8DQ C1–DQ C8DQ D1–DQ D8I/O Data Input and Output pins ( x36 Version)51, 80, 1, 30DQ A9, DQ B9,DQ C9, DQ D9I/O Data Input and Output pins58, 59, 62, 63, 68, 69, 72, 73, 74 8, 9, 12, 13, 18, 19, 22, 23, 24DQ A1–DQ A9DQ B1–DQ B9I/O Data Input and Output pins51, 52, 53, 56, 5775, 78, 79,1, 2, 3, 6, 725, 28, 29, 30NC—No Connect16DP I Parity Input; 1 = Even, 0 = Odd66QE O Parity Error Out; Open Drain Output87BW I Byte Write—Writes all enabled bytes; active low93, 94B A, B B I Byte Write Enable for DQ A, DQ B Data I/Os; active low95, 96B C, B D I Byte Write Enable for DQ C, DQ D Data I/Os; active low ( x36 Version) 95, 96NC—No Connect (x18 Version)89CK I Clock Input Signal; active high88GW I Global Write Enable—Writes all bytes; active low98E1I Chip Enable; active low97E2I Chip Enable; active high86G I Output Enable; active low83ADV I Burst address counter advance enable; active low84, 85ADSP, ADSC I Address Strobe (Processor, Cache Controller); active lowGS881E18/36T-11/11.5/100/80/6664ZZ I Sleep mode control; active high 14FT I Flow Through or Pipeline mode; active low 31LBO I Linear Burst Order mode; active low38TMS I Scan Test Mode Select 39TDI I Scan Test Data In 42TDO O Scan Test Data Out 43TCK I Scan Test Clock 15, 41, 65, 91V DD I Core power supply 5,10,17, 21, 26, 40, 55, 60, 67, 71, 76, 90V SS I I/O and Core Ground 4, 11, 20, 27, 54, 61, 70, 77V DDQIOutput driver power supplyPin LocationSymbolTyp eDescriptionGS881E18/36T-11/11.5/100/80/66GS881E18/36 Block DiagramA1A0A0A1D0D1Q1Q0Counter LoadD QDQRegisterRegisterDQRegisterDQRegisterDQRegisterD QRegisterD QRegisterD QRegisterD QR e g i s t e rDQ RegisterA0–An LBO ADV CK ADSC ADSP GW BW B AB BB CB DFT GZZPower Down ControlMemory Array36364AQD DQx0–DQx9DPParity QEParity EncodeCompare3643636432Note: Only x36 version shown for simplicity.3636DQR e g i s t e r 4E 1E 2GS881E18/36T-11/11.5/100/80/66ByteSafe ™ Parity FunctionsThis SRAM includes a write data parity check that checks the validity of data coming into the RAM on write cycles. In Flow Through mode, write data errors are reported in the cycle following the data input cycle. In Pipeline mode, write data errors are reported one clock cycle later. (See Write Parity Error Output Timing Diagram .) The Data Parity Mode (DP) pin must be tied high to set the RAM to check for even parity or low to check for odd parity. Read data parity is not checked by the RAM as data. Validity is best established at the data’s destination. The Parity Error Output is an open drain output and drives low to indicate a parity error. Multiple Parity Error Output pins may share a common pull-up resistor.Write Parity Error Output Timing DiagramBPR 1999.05.18CK D In AD In BD In C D In D D In EtKQ tLZDQQEF l o w T h r o u g h M o d eP i p e l i n e d M o d etKQ tLZDQQED In A D In BD In CD In D D In EErr AErr AErr CErr CtHZ tKQX tHZ tKQXGS881E18/36T-11/11.5/100/80/66Note:There are pull-up devices on the LBO, DP and FT pins and a pull down device on the ZZ pin, so those input pins can be unconnected and the chip will operate in the default states as specified in the above table.Burst Counter SequencesBPR 1999.05.18Mode Pin FunctionsMode NamePin NameStateFunctionBurst Order Control LBO L Linear Burst H or NC Interleaved Burst Output Register Control FT L Flow Through H or NC Pipeline Power Down Control ZZ L or NC Active H Standby, I DD = I SB ByteSafe Data Parity ControlDPL Check for Odd Parity H or NCCheck for Even ParityLinear Burst SequenceNote: The burst counter wraps to initial state on the 5th clock.I nterleaved Burst SequenceNote: The burst counter wraps to initial state on the 5th clock.A[1:0]A[1:0]A[1:0]A[1:0]1st address 000110112nd address 011011003rd address 101100014th address11000110A[1:0]A[1:0]A[1:0]A[1:0]1st address 000110112nd address 010011103rd address 101100014th address11100100GS881E18/36T-11/11.5/100/80/66Byte Write Truth TableNotes:1.All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.2.Byte Write Enable inputs B A , B B , B C, and/or B D may be used in any combination with BW to write single or multiple bytes.3.All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.4.Bytes “C ” and “D ” are only available on the x36 version.FunctionGWBWB AB BB CB DNotesRead H H X X X X 1Read H L H H H H 1Write byte a H L L H H H 2, 3Write byte b H L H L H H 2, 3Write byte c H L H H L H 2, 3, 4Write byte d H L H H H L 2, 3, 4Write all bytes H L L L L L 2, 3, 4Write all bytesLXXXXXGS881E18/36T-11/11.5/100/80/66 Synchronous Truth TableOperation AddressUsedStateDiagramKey5E1E22(x36only)ADSP ADSC ADV W3DQ4Deselect Cycle, Power Down None X H X X L X X High-Z Deselect Cycle, Power Down None X L F L X X X High-Z Deselect Cycle, Power Down None X L F H L X X High-Z Read Cycle, Begin Burst External R L T L X X X Q Read Cycle, Begin Burst External R L T H L X F Q Write Cycle, Begin Burst External W L T H L X T D Read Cycle, Continue Burst Next CR X X H H L F Q Read Cycle, Continue Burst Next CR H X X H L F Q Write Cycle, Continue Burst Next CW X X H H L T D Write Cycle, Continue Burst Next CW H X X H L T D Read Cycle, Suspend Burst Current X X H H H F Q Read Cycle, Suspend Burst Current H X X H H F Q Write Cycle, Suspend Burst Current X X H H H T D Write Cycle, Suspend Burst Current H X X H H T D Notes:1.X = Don’t Care, H = High, L = Low.2.For x36 Version, E = T (True) if E2 = 1; E = F (False) if E2 = 0.3.W = T (True) and F (False) is defined in the Byte Write Truth Table preceding.4.G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shownas “Q” in the Truth Table above).5.All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplishbasic synchronous or synchronous burst operations and may be avoided for simplicity.6.Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.7.Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.GS881E18/36T-11/11.5/100/80/66First WriteFirst ReadBurst WriteBurst ReadDeselectR WCRCWX XWRRWRXXX S i m p l e S y n c h r o n o u s O p e r a t i o nS i m p l e B u r s t S y n c h r o n o u s O p e r a t i o nCR RCWCRCRSimplified State DiagramNotes:1.The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low.2.The upper portion of the diagram assumes active use of only the Enable (E1 and E2) and Write (B A , B B , B C , B D , BW, and GW) controlinputs, and that ADSP is tied high and ADSC is tied low.3.The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs, andassumes ADSP is tied high and ADV is tied low.GS881E18/36T-11/11.5/100/80/66First WriteFirst ReadBurst WriteBurst ReadDeselectR WCRCWXXWRRWRXXX CRR CW CRCRW CWW CWSimplified State Diagram with GNotes:1.The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.e of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from Read cycles to Write cycles without passingthrough a Deselect cycle. Dummy Read cycles increment the address counter just like normal Read cycles.3.Transitions shown in grey tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meetData Input Set Up Time.GS881E18/36T-11/11.5/100/80/66Note:Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component.Notes:1.Unless otherwise noted, all performance specifications quoted are evaluated for worst case at both2.75 V ≤ V DDQ ≤ 2.375 V(i.e., 2.5 V I/O) and 3.6 V ≤ V DDQ ≤ 3.135 V (i.e., 3.3 V I/O), and quoted at whichever condition is worst case. 2.This device features input buffers compatible with both 3.3 V and 2.5 V I/O drivers.3.Most speed grades and configurations of this device are offered in both Commercial and Industrial Temperature ranges. The part number ofIndustrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device.4.Input Under/overshoot voltage must be –2 V > Vi < V DD +2 V with a pulse width not to exceed 20% tKC.Absolute Maximum Ratings(All voltages reference to V SS )SymbolDescriptionValueUnitV DD Voltage on V DD Pins –0.5 to 4.6V V DDQ Voltage in V DDQ Pins –0.5 to V DD V V CK Voltage on Clock Input Pin –0.5 to 6V V I/O Voltage on I/O Pins –0.5 to V DDQ +0.5 (≤ 4.6 V max.)V V IN Voltage on Other Input Pins –0.5 to V DD +0.5 (≤ 4.6 V max.)V I IN Input Current on Any Pin +/–20mA I OUT Output Current on Any I/O Pin +/–20mA P D Package Power Dissipation 1.5WT STG Storage Temperature –55 to 125o C T BIASTemperature Under Bias–55 to 125o CRecommended Operating ConditionsParameterSymbolMin.Typ.Max.UnitNotesSupply Voltage V DD 3.135 3.3 3.6V I/O Supply Voltage V DDQ 2.375 2.5V DD V 1Input High Voltage V IH 1.7—V DD +0.3V 2Input Low VoltageV IL –0.3—0.8V 2Ambient Temperature (Commercial Range Versions)T A 02570°C 3Ambient Temperature (Industrial Range Versions)T A–402585°C3GS881E18/36T-11/11.5/100/80/66Note: These parameters are sample tested.Notes:1.Junction temperature is a function of SRAM power dissipation, package thermal resistance, mounting board temperature, ambient. Temper-ature air flow, board density, and PCB thermal resistance.2.SCMI G-38-873.Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1Capacitance(T A = 25o C, f = 1 MH Z , V DD = 3.3 V)ParameterSymbolTest conditionsTyp.Max.UnitInput Capacitance C IN V IN = 0 V 45pF Input/Output CapacitanceC I/OV OUT = 0 V67pFPackage Thermal CharacteristicsRatingLayer BoardSymbolMaxUnitNotesJunction to Ambient (at 200 lfm)single R ΘJA 40°C/W 1,2Junction to Ambient (at 200 lfm)four R ΘJA 24°C/W 1,2Junction to Case (TOP)—R ΘJC9°C/W320% tKCV SS – 2.0 V50%V SS V IHUndershoot Measurement and TimingOvershoot Measurement and Timing20% tKCV DD + 2.0 V50%V DDV ILGS881E18/36T-11/11.5/100/80/66Notes:1.Include scope and jig capacitance.2.Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted.3.Output Load 2 for t LZ , t HZ , t OLZ and t OHZ4.Device is deselected as defined by the Truth Table.AC Test ConditionsParameterConditionsInput high level 2.3 V Input low level 0.2 V Input slew rate 1 V/ns Input reference level 1.25 V Output reference level1.25 V Output loadFig. 1& 2DC Electrical CharacteristicsParameterSymbolTest ConditionsMinMaxInput Leakage Current (except mode pins)I IL V IN = 0 to V DD –1 uA 1 uA ZZ Input Current I INZZ V DD ≥ V IN ≥ V IH 0 V ≤ V IN ≤ V IH –1 uA –1 uA 1 uA 300 uA Mode Pin Input Current I INM V DD ≥ V IN ≥ V IL 0 V ≤ V IN ≤ V IL –300 uA –1 uA 1 uA 1 uA Output Leakage Current I OL Output Disable,V OUT = 0 to V DD –1 uA 1 uA Output High Voltage V OH I OH = –8 mA, V DDQ = 2.375 V 1.7 V —Output High Voltage V OH I OH = –8 mA, V DDQ = 3.135 V2.4 V —Output Low VoltageV OLI OL = 8 mA—0.4 VDQVT = 1.25 V50Ω30pF *DQ2.5 VOutput Load 1Output Load 2225Ω225Ω5pF ** Distributed Test Jig CapacitanceGS881E18/36T-11/11.5/100/80/66 Operating CurrentsParameter Test Conditions Symbol-11-11.5-100-80-66Unit 0to70°C–40to85°Cto70°C–40to85°Cto70°C–40to85°Cto70°C–40to85°Cto70°C–40to85°COperating Current Device Selected;All other inputs≥V IH o r ≤ V ILOutput openI DDPipeline225235225235225235200210185195mAI DDFlow-Thru180 190 180 190 180190175185165175mAStandbyCurrent ZZ≥ V DD- 0.2VI SBPipeline30 40 30 40 304030403040mAI SBFlow-Thru30 40 30 40304030403040mADeselect Current Device Deselected;All other inputs≥ V IH or≤ V ILI DDPipeline80 90 80 90809070806070mAI DDFlow-Thru65 75 65 75657555655060mAGS881E18/36T-11/11.5/100/80/66AC Electrical CharacteristicsNotes:1.These parameters are sampled and are not 100% tested.2.ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and holdtimes as specified above.Parameter Symbol -11-11.5-100-80-66Unit Min Max MinMax MinMax Min Max Min Max PipelineClock Cycle TimetKC 10—10—10—12.5—15—ns Clock to Output Valid tKQ — 4.0— 4.0— 4.0— 4.5—5ns Clock to Output Invalid tKQX 1.5— 1.5— 1.5— 1.5— 1.5—ns Clock to Output in Low-Z tLZ 1 1.5— 1.5— 1.5— 1.5— 1.5—ns Flow-ThruClock Cycle TimetKC 15.0—15.0—15.0—15.0—20—ns Clock to Output Valid tKQ —11.0—11.5—12.0—14.0—18ns Clock to Output Invalid tKQX 3.0— 3.0— 3.0— 3.0— 3.0—ns Clock to Output in Low-Z tLZ 1 3.0— 3.0— 3.0— 3.0— 3.0—ns Clock HIGH Time tKH 1.7— 1.7—2—2— 2.3—ns Clock LOW Time tKL 2—2— 2.2— 2.2— 2.5—ns Clock to Output in High-Z tHZ 1 1.5 4.0 1.5 4.2 1.5 4.5 1.5 4.5 1.5 4.8ns G to Output Valid tOE — 4.0— 4.2— 4.5— 4.5— 4.8ns G to output in Low-Z tOLZ 10—0—0—0—0—ns G to output in High-ZtOHZ 1— 4.0— 4.2— 4.5— 4.5— 4.8ns Setup time tS 1.5— 2.0— 2.0— 2.0— 2.0—ns Hold time tH 0.5—0.5—0.5—0.5—0.5—ns ZZ setup time tZZS 25—5—5—5—5—ns ZZ hold time tZZH 21—1—1—1—1—ns ZZ recoverytZZR20—20—20—20—20—nsGS881E18/36T-11/11.5/100/80/66CKADSPADSCADVGWBWWR2WR3WR1WR1WR2WR3tKCSingle WriteBurst Write t KLt KH tS tHtS tHtS tHtS tHtS tHtStHtS tHWrite specified byte for 2A and all bytes for 2B , 2C & 2DADV must be inactive for ADSP WriteADSC initiated writeADSP is blocked by E inactiveA 0–A nB A –B DDQ A –DQ DWrite DeselectedWR1WR3Write Cycle TimingE 1tS tHE 2 only sampled with ADSP or ADSCE 1 masks ADSPDeselected with E 2GtS tHD2AD2BD2CD2DD3AD1AHi-ZtS tHE 2GS881E18/36T-11/11.5/100/80/66Q1AQ3AQ2DQ2cQ2BQ2AtKQtLZtOEtOHZtOLZtKQXtHZtKQXCKADSP ADSCBW GGWADVBurst ReadRD2RD3tKLtStHtHtS tHtS tHADSC initiated readSuspend Burst Single ReadADSP is blocked by E inactiveA 0–A nB A –B DtKHtKCtS tHtS tStHDQ A –DQ DRD1Hi-ZSuspend BurstFlow Through Read Cycle TimingtHtHE 1 masks ADSPDeselected with E 2E 1tS tS E 2E 2 only sampled with ADSP or ADSCGS881E18/36T-11/11.5/100/80/66Flow Through Read-Write Cycle TimingCKADSPADVGWBWGQ1AD1AQ2AQ2BQ2cQ2DSingle ReadBurst ReadtOEtOHZtS tHtStHtHtS tHtS tHtKH DQ A –DQ DB A –B DtKLtKCtS Single WriteADSP is blocked by E inactivetKQtStHHi-ZQ2ABurst wrap around to it’s initial stateWR1E 1tS tS tHE 1 masks ADSPE 2 only sampled with ADSP and ADSCtHADSCtS tHADSC initiated readRD1WR1RD2tS tHA 0–A nE 2GS881E18/36T-11/11.5/100/80/66Pipelined DCD Read Cycle TimingQ1AQ3AQ2DQ2cQ2BQ2AtKQtLZtOEtOHZtOLZtKQX tHZtKQX CKADSP ADSCBW GGWADVBurst ReadRD2RD3tKLtHtHtStHtHtS tHtS tHADSC initiated readSuspend BurstE 1 masks ADSPE 2 only sampled with ADSP or ADSCSingle ReadADSP is blocked by E 1 inactiveA 0–A nB A –B DE 1tKH tKCtS tHtS tStHDQ A –DQ DtS tS RD1Hi-ZE 2GS881E18/36T-11/11.5/100/80/66Pipelined DCD Read-Write Cycle TimingCKADSPADVGWBW E 1GWR1Q1AD1aQ2A Q2B Q2c Q2DSingle ReadBurst ReadtOEtOHZtS tStHtStH tStHtHtS tHtS tHtKHE 1 masks ADSPE 2 only sampled with ADSP and ADSCDQ A –DQ DtKLtKC tS tHSingle WriteADSP is blocked by E 1 inactivetKQtS tHHi-ZB A –B DADSCtS tHADSC initiated readRD1WR1RD2tS tHA 0–A nE 2GS881E18/36T-11/11.5/100/80/66Application TipsSingle and Dual Cycle DeselectSCD devices force the use of “dummy read cycles” (read cycles that are launched normally but that are ended with the outputdrivers inactive) in a fully synchronous environment. Dummy read cycles waste performance but their use usually assures there will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste bandwidth on dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at bank address boundary crossings) but greater care must be exercised to avoid excessive bus contention.JTAG Port OperationOverviewThe JTAG Port on this RAM operates in a manner consistent with IEEE Standard 1149.1-1990, a serial boundary scan interface standard (commonly referred to as JTAG), but does not implement all of the functions required for 1149.1 compliance. Some functions have been modified or eliminated because they can slow the RAM. Nevertheless, the RAM supports 1149.1-1990 TAP (Test Access Port) Controller architecture, and can be expected to function in a manner that does not conflict with the operation of Standard 1149.1 compliant devices. The JTAG Port interfaces with conventional TTL / CMOS logic level signaling.Disabling the JTAG PortIt is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unlessclocked. TCK, TDI, and TMS are designed with internal pull-up circuits. To assure normal operation of the RAM with the JTAG Port unused, TCK, TDI, and TMS may be left floating or tied to either V DD or V SS . TDO should be left unconnected.CKADSP ADSCtHtKH tKLtKCtS ZZtZZRtZZHtZZS~~~~~~~~~SnoozeSleep Mode Timing DiagramGS881E18/36T-11/11.5/100/80/66JTAG Port RegistersOverviewThe various JTAG registers, refered to as TAP Registers, are selected (one at a time) via the sequences of 1s and 0s applied to TMS as TCK is strobed. Each of the TAP Registers are serial shift registers that capture serial input data on the rising edge of TCK and push serial data out on the next falling edge of TCK. When a register is selected it is placed between the TDI and TDO pins.Instruction RegisterThe Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle or the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the controller is placed in Test-Logic-Reset state.Bypass RegisterThe Bypass Register is a single-bit register that can be placed between TDI and TDO. It allows serial test data to be passed through the RAMs JTAG Port to another device in the scan chain with as little delay as possible.Boundary Scan RegisterBoundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins. The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. TheBoundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. Two TAP instructions can be used to activate the Boundary Scan Register.JTAG Pin Descriptions PinPin NameI/ODescriptionTCK Test Clock In Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate from the falling edge of TCK.TMSTest Mode SelectInThe TMS input is sampled on the rising edge of TCK. This is the command input for the TAP controller state machine. An undriven TMS input will produce the same result as a logic one input level.TDI Test Data In InThe TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers placed between TDI and TDO. The register placed between TDI and TDO is determined by the state of the TAP Controller state machine and the instruction that is currently loaded in the TAP Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce the same result as a logic one input level.TDO Test Data Out OutOutput that is active depending on the state of the TAP state machine. Output changes in response to the falling edge of TCK. This is the output side of the serial registers placed between TDI and TDO.Note:This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up.。

GS88136AD-200资料

GS88118A(T/D)/GS88132A(D)/GS88136A(T/D)512K x 18, 256K x 369Mb Synchronous Burst SRAMs250 MHz –133 MHz 2.5 V or 3.3 V V DD 2.5 V or 3.3 V I/O100-Pin TQFP & 165-Bump BGA Commercial Temp Industrial Temp Features• IEEE 1149.1 JTAG-compatible Boundary Scan • 2.5 V or 3.3 V +10%/–10% core power supply • 2.5 V or 3.3 V I/O supply• LBO pin for Linear or Interleaved Burst mode• Internal input resistors on mode pins allow floating mode pins • Byte Write (BW) and/or Global Write (GW) operation • Internal self-timed write cycle• Automatic power-down for portable applications • JEDEC-standard packagesFunctional DescriptionApplicationsThe GS88118/36AT/D is a 9,437,184-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support. ControlsAddresses, data I/Os, chip enable (E1, E2), address burst control inputs (ADSP, ADSC, ADV) and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive-edge-triggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burst cycles can be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by ADV. The burst address counter may be configured to count in either linear orinterleave order with the Linear Burst Order (LBO) input. The Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance.Flow Through/Pipeline ReadsThe function of the Data Output register can be controlled by the user via the FT mode pin (Pin 14). Holding the FT mode pin low places the RAM in Flow Through mode, causing output data to bypass the Data Output Register. Holding FT high places the RAM in Pipeline mode, activating the rising-edge-triggered Data Output Register.SCD Pipelined ReadsThe GS88118/36AT/D is a SCD (Single Cycle Deselect) pipelined synchronous SRAM. DCD (Dual Cycle Deselect) versions are also available. SCD SRAMs pipeline deselect commands one stage less than read commands. SCD RAMs begin turning off their outputs immediately after the deselect command has been captured in the input registers.Byte Write and Global WriteByte write operation is performed by using Byte Write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the Byte Write control inputs.Sleep ModeLow power (Sleep mode) is attained through the assertion (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode.Core and Interface VoltagesThe GS88118/36AT/D operates on a 2.5 V or 3.3 V power supply. All input are 3.3 V and 2.5 V compatible. Separate output power (V DDQ ) pins are used to decouple output noise from the internal circuits and are 3.3 V and 2.5 V compatible.Parameter Synopsis-250-225-200-166-150-133Unit Pipeline 3-1-1-1t KQ tCycle2.54.0 2.74.43.05.0 3.46.0 3.86.74.07.5ns nsCurr (x18)Curr (x36)280330255300230270200230185215165190mA mA Flow Through 2-1-1-1t KQ tCycle5.55.56.06.0 6.56.57.07.07.57.58.58.5ns ns Curr (x18)Curr (x36)175200165190160180150170145165135150mA mAGS88118A(T/D)/GS88132A(D)/GS88136A(T/D)GS88118A 100-Pin TQFP Pinout (Package T)807978777675747372717069686766656463626160595857565554535251123456789101112131415161718192021222324252627282930V DDQ V SS DQ B DQ B V SS V DDQ DQ B DQ B FT V DD NC V SS DQ B DQ B6V DDQ V SS DQ B DQ B DQP BV SS V DDQ V DDQ V SS DQ A DQ A V SS V DDQ DQ A DQ A V SS NC V DD ZZ DQ A DQ A V DDQ V SS DQ A DQ A V SS V DDQ L B O A 5A AA 1A 0T M S T D I V S SV D DT D O T C K A A A A A AA A E 1E 2N C N C B BB AA C K G WB W V D DV S SG A D S C A D S P A D V A AA 512K x 18Top View DQP A A NC NC NC NC NC NC NC NCNC NC NC NC NC NC NCNC NC 100999897969594939291908988878685848382813132333435363738394041424344454647484950GS88118A(T/D)/GS88132A(D)/GS88136A(T/D)GS88136A 100-Pin TQFP Pinout (Package T)807978777675747372717069686766656463626160595857565554535251123456789101112131415161718192021222324252627282930V DDQ V SS DQ C DQ C V SS V DDQ DQ C DQ C FT V DD NC V SS DQ D DQ D V DDQ V SS DQ D DQ D DQ D V SS V DDQ V DDQ V SS DQ B DQ B V SS V DDQ DQ B DQ B V SS NC V DD ZZ DQ A DQ A V DDQ V SS DQ A DQ A V SS V DDQ L B O A A A A A 1A 0V S SV D DA A A A A AA A E 1E 2B DB CB BB AA C K G WB W V D DV S SG A D S C A D S P A D V A AA 256K x 36Top View DQB DQP B DQ B DQ B DQ B DQ A DQ A DQ A DQ A DQP ADQ C DQ C DQ C DQ D DQ D DQ D DQP DDQ C DQP C 100999897969594939291908988878685848382813132333435363738394041424344454647484950T M S T D I T D O T C KGS88118A(T/D)/GS88132A(D)/GS88136A(T/D)TQFP Pin DescriptionSymbol Type DescriptionA0, A1I Address field LSBs and Address Counter preset InputsA n I Address InputsDQ ADQ BI/O Data Input and Output pinsDQ CDQ DNC—No ConnectBW I Byte Write—Writes all enabled bytes; active lowB A, B B, B C, B D I Byte Write Enable for DQ A, DQ B Data I/Os; active lowCK I Clock Input Signal; active highGW I Global Write Enable—Writes all bytes; active lowE1I Chip Enable; active lowE2I Chip Enable; active highG I Output Enable; active lowADV I Burst address counter advance enable; active low ADSP, ADSC I Address Strobe (Processor, Cache Controller); active low ZZ I Sleep Mode control; active highTMS I Scan Test Mode SelectTDI I Scan Test Data InTDO O Scan Test Data OutTCK I Scan Test ClockFT I Flow Through or Pipeline mode; active lowLBO I Linear Burst Order mode; active lowV DD I Core power supplyV SS I I/O and Core GroundV DDQ I Output driver power supplyGS88118A(T/D)/GS88132A(D)/GS88136A(T/D) 165 Bump BGA—x18 Commom I/O—Top View (Package D)1234567891011A NC A E1B B NC E3BW ADSC ADV A A AB NC A E2NC B A CK GW G ADSP A NC BC NC NC V DDQ V SS V SS V SS V SS V SS V DDQ NC DQA CD NC DQB V DDQ V DD V SS V SS V SS V DD V DDQ NC DQA DE NC DQB V DDQ V DD V SS V SS V SS V DD V DDQ NC DQA EF NC DQB V DDQ V DD V SS V SS V SS V DD V DDQ NC DQA FG NC DQB V DDQ V DD V SS V SS V SS V DD V DDQ NC DQA GH FT MCL NC V DD V SS V SS V SS V DD NC NC ZZ HJ DQB NC V DDQ V DD V SS V SS V SS V DD V DDQ DQA NC JK DQB NC V DDQ V DD V SS V SS V SS V DD V DDQ DQA NC KL DQB NC V DDQ V DD V SS V SS V SS V DD V DDQ DQA NC LM DQB NC V DDQ V DD V SS V SS V SS V DD V DDQ DQA NC MN DQB NC V DDQ V SS NC NC NC V SS V DDQ NC NC NP NC NC A A TDI A1TDO A A A A PR LBO NC A A TMS A0TCK A A A A R11 x 15 Bump BGA—13mm x 15 mm Body—1.0 mm Bump PitchGS88118A(T/D)/GS88132A(D)/GS88136A(T/D) 165 Bump BGA—x32 Common I/O—Top View (Package D)1234567891011A NC A E1BC B B E3BW ADSC ADV A NC AB NC A E2BD B A CK GW G ADSP A NC BC NC NC V DDQ V SS V SS V SS V SS V SS V DDQ NC NC CD DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB DE DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB EF DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB FG DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB GH FT MCL NC V DD V SS V SS V SS V DD NC NC ZZ HJ DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA JK DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA KL DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA LM DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA MN NC NC V DDQ V SS NC NC NC V SS V DDQ NC NC NP NC NC A A TDI A1TDO A A A A PR LBO NC A A TMS A0TCK A A A A R11 x 15 Bump BGA—13mm x 15 mm Body—1.0 mm Bump PitchGS88118A(T/D)/GS88132A(D)/GS88136A(T/D) 165 Bump BGA—x36 Common I/O—Top View (Package D)1234567891011A NC A E1BC B B E3BW ADSC ADV A NC AB NC A E2BD B A CK GW G ADSP A NC BC DQC NC V DDQ V SS V SS V SS V SS V SS V DDQ NC DQB CD DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB DE DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB EF DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB FG DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB GH FT MCL NC V DD V SS V SS V SS V DD NC NC ZZ HJ DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA JK DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA KL DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA LM DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA MN DQD NC V DDQ V SS NC NC NC V SS V DDQ NC DQA NP NC NC A A TDI A1TDO A A A A PR LBO NC A A TMS A0TCK A A A A R11 x 15 Bump BGA—13mm x 15 mm Body—1.0 mm Bump PitchGS88118A(T/D)/GS88132A(D)/GS88136A(T/D)GS88118/32/36AD 165-Bump BGA Pin DescriptionSymbol Type DescriptionA0, A1I Address field LSBs and Address Counter Preset InputsA I Address InputsDQ ADQ BI/O Data Input and Output pinsDQ CDQ DB A, B B, B C, B D I Byte Write Enable for DQ A, DQ B, DQ C, DQ D I/Os; active lowNC—No ConnectCK I Clock Input Signal; active highBW I Byte Write—Writes all enabled bytes; active lowGW I Global Write Enable—Writes all bytes; active lowE1I Chip Enable; active lowE3I Chip Enable; active lowE2I Chip Enable; active highG I Output Enable; active lowADV I Burst address counter advance enable; active l0w ADSC, ADSP I Address Strobe (Processor, Cache Controller); active low ZZ I Sleep mode control; active highFT I Flow Through or Pipeline mode; active lowLBO I Linear Burst Order mode; active lowTMS I Scan Test Mode SelectTDI I Scan Test Data InTDO O Scan Test Data OutTCK I Scan Test ClockMCL—Must Connect LowV DD I Core power supplyV SS I I/O and Core GroundV DDQ I Output driver power supplyGS88118A(T/D)/GS88132A(D)/GS88136A(T/D)GS88118/36A Block DiagramA1A0A0A1D0D1Q1Q0Counter LoadD QDQRegisterRegisterDQRegisterDQRegisterDQRegisterD QRegisterD QRegisterD QRegisterD QR e g i s t e rDQ RegisterA0–AnLBO ADV CK ADSC ADSP GW BW E 1FT GZZPower Down ControlMemory Array36364AQD DQx1–DQx9NCParity NCParity EncodeCompare3643636432Note: Only x36 version shown for simplicity.13636DQR e g i s t e r 4B AB BB CB DGS88118A(T/D)/GS88132A(D)/GS88136A(T/D)Note:There is a pull-up device onthe FT pin and a pull-down device on the ZZ pin, so those input pins can be unconnected and the chip will operate in the default states as specified in the above tables.Burst Counter SequencesBPR 1999.05.18Mode Pin FunctionsMode NamePin NameStateFunctionBurst Order Control LBO L Linear Burst H Interleaved Burst Output Register Control FT L Flow Through H or NC Pipeline Power Down ControlZZL or NC Active HStandby, I DD = I SBNote:The burst counter wraps to initial state on the 5th clock.Note:The burst counter wraps to initial state on the 5th clock.Linear Burst SequenceA[1:0]A[1:0]A[1:0]A[1:0]1st address 000110112nd address 011011003rd address 101100014th address11000110Interleaved Burst SequenceA[1:0]A[1:0]A[1:0]A[1:0]1st address 000110112nd address 010011103rd address 101100014th address11100100GS88118A(T/D)/GS88132A(D)/GS88136A(T/D)1.All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.2.Byte Write Enable inputs B A , B B , B C and/or B D may be used in any combination with BW to write single or multiple bytes.3.All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.4.Bytes “C ” and “D ” are only available on the x32/x36 versions.Byte Write Truth TableFunctionGWBWB AB BB CB DNotesRead H H X X X X 1Read H L H H H H 1Write byte a H L L H H H 2, 3Write byte b H L H L H H 2, 3Write byte c H L H H L H 2, 3, 4Write byte d H L H H H L 2, 3, 4Write all bytesHLLLLL2, 3, 4Write all bytes L X X X X XGS88118A(T/D)/GS88132A(D)/GS88136A(T/D) Synchronous Truth TableOperation Address UsedStateDiagramKey5E1ADSP ADSC ADV W3DQ4Deselect Cycle, Power Down None X H X L X X High-Z Read Cycle, Begin Burst External R L L X X X Q Read Cycle, Begin Burst External R L H L X F Q Write Cycle, Begin Burst External W L H L X T D Read Cycle, Continue Burst Next CR X H H L F Q Read Cycle, Continue Burst Next CR H X H L F Q Write Cycle, Continue Burst Next CW X H H L T D Write Cycle, Continue Burst Next CW H X H L T D Read Cycle, Suspend Burst Current X H H H F Q Read Cycle, Suspend Burst Current H X H H F Q Write Cycle, Suspend Burst Current X H H H T D Write Cycle, Suspend Burst Current H X H H T D Notes:1.X = Don’t Care, H = High, L = Low2.W = T (True) and F (False) is defined in the Byte Write Truth Table preceding.3.G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shownas “Q” in the Truth Table above).4.All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplishbasic synchronous or synchronous burst operations and may be avoided for simplicity.5.Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.6.Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.GS88118A(T/D)/GS88132A(D)/GS88136A(T/D)Simplified State DiagramFirst WriteFirst ReadBurst WriteBurst ReadDeselect R WCRCWX XWRRWRXXX S i m p l e S y n c h r o n o u s O p e r a t i o nS i m p l e B u r s t S y n c h r o n o u s O p e r a t i o nCR RCWCRCRNotes:1.The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low.2.The upper portion of the diagram assumes active use of only the Enable (E1) and Write (B A , B B , B C , B D , BW, and GW) control inputs, andthat ADSP is tied high and ADSC is tied low.3.The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs, andassumes ADSP is tied high and ADV is tied low.GS88118A(T/D)/GS88132A(D)/GS88136A(T/D)Simplified State Diagram with GFirst WriteFirst ReadBurst WriteBurst ReadDeselect R WCRCWXXWRRWRXXX CRR CW CRCRW CWW CWNotes:1.The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.e of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from read cycles to write cycles without passingthrough a deselect cycle. Dummy read cycles increment the address counter just like normal read cycles.3.Transitions shown in gray tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meetData Input Set Up Time.GS88118A(T/D)/GS88132A(D)/GS88136A(T/D)Note:Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component.Absolute Maximum Ratings(All voltages reference to V SS )SymbolDescriptionValueUnitV DD Voltage on V DD Pins –0.5 to 4.6V V DDQ Voltage in V DDQ Pins –0.5 to 4.6V V I/O Voltage on I/O Pins –0.5 to V DDQ +0.5 (≤ 4.6 V max.)V V IN Voltage on Other Input Pins –0.5 to V DD +0.5 (≤ 4.6 V max.)V I IN Input Current on Any Pin +/–20mA I OUT Output Current on Any I/O Pin +/–20mA P D Package Power Dissipation 1.5WT STG Storage Temperature –55 to 125o C T BIASTemperature Under Bias–55 to 125oCPower Supply Voltage RangesParameterSymbolMin.Typ.Max.UnitNotes3.3 V Supply Voltage V DD3 3.0 3.3 3.6V 2.5 V Supply Voltage V DD2 2.3 2.5 2.7V 3.3 V V DDQ I/O Supply Voltage V DDQ3 3.0 3.3 3.6V 2.5 V V DDQ I/O Supply VoltageV DDQ22.32.52.7VNotes:1.The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-tions quoted are evaluated for worst case in the temperature range marked on the device.2.Input Under/overshoot voltage must be –2 V > Vi < V DDn +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.GS88118A(T/D)/GS88132A(D)/GS88136A(T/D)V DDQ3 Range Logic LevelsParameter Symbol Min.Typ.Max.Unit Notes V DD Input High Voltage V IH 2.0—V DD + 0.3V1V DD Input Low Voltage V IL–0.3—0.8V1V DDQ I/O Input High Voltage V IHQ 2.0—V DDQ + 0.3V1,3V DDQ I/O Input Low Voltage V ILQ–0.3—0.8V1,3 Notes:1.The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-tions quoted are evaluated for worst case in the temperature range marked on the device.2.Input Under/overshoot voltage must be –2 V > Vi < V DDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.3.V IHQ (max) is voltage on V DDQ pins plus 0.3 V.V DDQ2 Range Logic LevelsParameter Symbol Min.Typ.Max.Unit Notes V DD Input High Voltage V IH0.6*V DD—V DD + 0.3V1V DD Input Low Voltage V IL–0.3—0.3*V DD V1V DDQ I/O Input High Voltage V IHQ0.6*V DD—V DDQ + 0.3V1,3V DDQ I/O Input Low Voltage V ILQ–0.3—0.3*V DD V1,3 Notes:1.The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-tions quoted are evaluated for worst case in the temperature range marked on the device.2.Input Under/overshoot voltage must be –2 V > Vi < V DDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.3.V IHQ (max) is voltage on V DDQ pins plus 0.3 V.Recommended Operating TemperaturesParameter Symbol Min.Typ.Max.Unit Notes Ambient Temperature (Commercial Range Versions)T A02570°C2 Ambient Temperature (Industrial Range Versions)T A–402585°C2 Notes:1.The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-tions quoted are evaluated for worst case in the temperature range marked on the device.2.Input Under/overshoot voltage must be –2 V > Vi < V DDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.GS88118A(T/D)/GS88132A(D)/GS88136A(T/D)Note:These parameters are sample tested.Capacitance(T A = 25o C, f = 1 MH Z , V DD = 2.5 V)ParameterSymbolTest conditionsTyp.Max.UnitInput Capacitance C IN V IN = 0 V 45pF Input/Output Capacitance C I/OV OUT = 0 V67pFAC Test ConditionsParameterConditionsInput high level V DD – 0.2 V Input low level 0.2 V Input slew rate 1 V/ns Input reference level V DD /2Output reference levelV DDQ /2Output loadFig. 1Notes:1.Include scope and jig capacitance.2.Test conditions as specified with output loading as shown in Fig. 1unless otherwise noted.3.Device is deselected as defined by the Truth Table. 50% tKCV SS – 2.0 V50%V SS V IHUndershoot Measurement and TimingOvershoot Measurement and Timing50% tKCV DD + 2.0 V50%V DDV ILDQV DDQ/250Ω30pF *Output Load 1* Distributed Test Jig CapacitanceGS88118A(T/D)/GS88132A(D)/GS88136A(T/D)DC Electrical CharacteristicsParameter Symbol Test Conditions Min Max Input Leakage Current(except mode pins)I IL V IN = 0 to V DD–1 uA 1 uAZZ Input Current I IN1V DD≥V IN ≥V IH0 V≤ V IN ≤ V IH–1 uA–1 uA1 uA100 uAFT Input Current I IN2V DD≥V IN ≥V IL0 V≤ V IN ≤ V IL–100 uA–1 uA1 uA1 uAOutput Leakage Current I OL Output Disable, V OUT = 0 to V DD–1 uA 1 uA Output High Voltage V OH2I OH = –8 mA, V DDQ = 2.375 V 1.7 V—Output High Voltage V OH3I OH = –8 mA, V DDQ = 3.135 V 2.4 V—Output Low Voltage V OL I OL = 8 mA—0.4 VGS88118A(T/D)/GS88132A(D)/GS88136A(T/D)N o t e s : 1.I D D a n d I D D Q a p p l y t o a n y c o m b i n a t i o n o f V D D 3, V D D 2, V D D Q 3, a n d V D D Q 2 o p e r a t i o n .2.A l l p a r a m e t e r s l i s t e d a r e w o r s t c a s e s c e n a r i o .O p e r a t i n g C u r r e n t sP a r a m e t e r T e s t C o n d i t i o n s M o d eS y m b o l -250-225-200-166-150-133U n i t0t o 70°C –40 t o 85°C0t o 70°C–40 t o 85°C 0t o 70°C –40t o 85°C 0 t o 70°C –40t o 85°C 0 t o 70°C –40t o 85°C 0 t o 70°C –40t o 85°C O p e r a t i n g C u r r e n tD e v i c e S e l e c t e d ; A l l o t h e r i n p u t s ≥V I H o r ≤ V I LO u t p u t o p e n(x 36)P i p e l i n eI D DI D D Q290403004026535275352403025030205252152519025200251702018020m AF l o w T h r o u g hI D DI D D Q180201902017020180201651517515155151651515015160151401015010m A(x 18)P i p e l i n eI D DI D D Q260202702023520245202151522515185151951517015180151551016510m AF l o w T h r o u g hI D DI D D Q165101751015510165101501016010140101501013510145101251013510m AS t a n d b y C u r r e n tZ Z ≥ V D D – 0.2 V—P i p e l i n eI S B 203020302030203020302030m AF l o w T h r o u g hI S B203020302030203020302030m AD e s e l e c t C u r r e n tD e v i c e D e s e l e c t e d ; A l l o t h e r i n p u t s ≥ V I H o r ≤ V I L—P i p e l i n eI D D859080857580647060655055m AF l o w T h r o u g hI D D606560655055505550554550m AGS88118A(T/D)/GS88132A(D)/GS88136A(T/D)Notes:1.These parameters are sampled and are not 100% tested2.ZZ is an asynchronous signal. However, In order to be recognized on any given clock cycle, ZZ must meet the specified setup and holdtimes as specified above.AC Electrical CharacteristicsParameter Symbol -250-225-200-166-150-133Unit Min Max Min Max Min Max Min Max Min Max Min Max PipelineClock Cycle Time tKC 4.0— 4.4— 5.0— 6.0— 6.7—7.5—ns Clock to Output Valid tKQ — 2.5— 2.7— 3.0— 3.4— 3.8— 4.0ns Clock to Output InvalidtKQX 1.5— 1.5— 1.5— 1.5— 1.5— 1.5—ns Clock to Output in Low-ZtLZ 1 1.5— 1.5— 1.5— 1.5— 1.5— 1.5—ns Setup time tS 1.2— 1.3— 1.4— 1.5— 1.5— 1.5—ns Hold time tH 0.2—0.3—0.4—0.5—0.5—0.5—ns Flow ThroughClock Cycle Time tKC 5.5— 6.0— 6.5—7.0—7.5—8.5—ns Clock to Output ValidtKQ — 5.5— 6.0— 6.5—7.0—7.5—8.5ns Clock to Output Invalid tKQX 3.0— 3.0— 3.0— 3.0— 3.0— 3.0—ns Clock to Output in Low-ZtLZ 1 3.0— 3.0— 3.0— 3.0— 3.0— 3.0—ns Setup time tS 1.5— 1.5— 1.5— 1.5— 1.5— 1.5—ns Hold time tH 0.5—0.5—0.5—0.5—0.5—0.5—ns Clock HIGH Time tKH 1.3— 1.3— 1.3— 1.3— 1.5— 1.7—ns Clock LOW Time tKL 1.5—1.5—1.5—1.5— 1.7—2—ns Clock to Output inHigh-Z tHZ 1 1.5 2.3 1.5 2.5 1.5 3.0 1.5 3.0 1.5 3.0 1.5 3.0ns G to Output Valid tOE — 2.3— 2.5— 3.2— 3.5— 3.8— 4.0ns G to output in Low-Z tOLZ 10—0—0—0—0—0—ns G to output in High-Z tOHZ 1— 2.3— 2.5— 3.0— 3.0— 3.0— 3.0ns ZZ setup time tZZS 25—5—5—5—5—5—ns ZZ hold time tZZH 21—1—1—1—1—1—ns ZZ recoverytZZR20—20—20—20—20—20—nsGS88118A(T/D)/GS88132A(D)/GS88136A(T/D)Pipeline Mode TimingBegin Read A Cont Cont Deselect Write B Read C Read C+1Read C+2Read C+3ContDeselecttHZtKQX tKQtLZtHtStOHZtOEtHtStHtStHtStHtStHtStStHtStHtStHtSBurst ReadtKCtKL Single Write tKH Single ReadQ(A)D(B)Q(C)Q(C+1)Q(C+2)Q(C+3)ABCDeselected with E1E1 masks ADSPE2 and E3 only sampled with ADSP and ADSCADSC initiated readCK ADSPADSCADVA0–AnGWBWBa–BdE1E2E3GDQa–DQdGS88118A(T/D)/GS88132A(D)/GS88136A(T/D)Flow Through Mode TimingBegin Read A ContCont Write B Read C Read C+1Read C+2Read C+3Read C Cont DeselecttHZtKQXtKQ tLZtH tStOHZtOEtHtS tHtS tHtStHtS tHtS tHtStHtS tHtS tH tS tHtS tKCtKL tKHABCQ(A)D(B)Q(C)Q(C+1)Q(C+2)Q(C+3)Q(C)E2 and E3 only sampled with ADSCADSC initiated readDeselected with E1Fixed HighCK ADSPADSCADVA0–AnGWBWBa–BdE1E2E3GDQa–DQdGS88118A(T/D)/GS88132A(D)/GS88136A(T/D)Sleep ModeDuring normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high, the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM operates normally after ZZ recovery time.Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to I SB 2. The duration of Sleep mode is dictated by the length of time the ZZ is in a High state. After entering Sleep mode, all inputs except ZZ become disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode. When the ZZ pin is driven high, I SB 2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands may be applied while the SRAM is recovering from Sleep mode.Sleep Mode Timing DiagramApplication TipsSingle and Dual Cycle DeselectSCD devices (like this one) force the use of “dummy read cycles” (read cycles that are launched normally but that are ended with the output drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance but their use usuallyassures there will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste bandwidth on dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at bank address boundary crossings) but greater care must be exercised to avoid excessive bus contention.JTAG Port OperationOverviewThe JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with V DD . The JTAG output drivers are powered by V DDQ .Disabling the JTAG PortIt is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG Port unused, TCK, TDI, and TMS may be left floating or tied to either V DD or V SS . TDO should be left unconnected.tZZRtZZHtZZSHoldSetup tKLtKHtKCCKADSP ADSCZZ。

GS88218BD-250资料

GS88218/36BB/D-333/300/250/200/150512K x 18, 256K x 369Mb SCD/DCD Sync Burst SRAMs333 MHz –150 MHz 2.5 V or 3.3 V V DD 2.5 V or 3.3 V I/O119- and 165-Bump BGA Commercial Temp Industrial Temp Features• FT pin for user-configurable flow through or pipeline operation • Single/Dual Cycle Deselect selectable• IEEE 1149.1 JTAG-compatible Boundary Scan• On-chip read parity checking; even or odd selectable • ZQ mode pin for user-selectable high/low output drive • 2.5 V or 3.3 V +10%/–10% core power supply • 2.5 V or 3.3 V I/O supply• LBO pin for Linear or Interleaved Burst mode• Internal input resistors on mode pins allow floating mode pins • Default to SCD x18/x36 Interleaved Pipeline mode • Byte Write (BW) and/or Global Write (GW) operation • Internal self-timed write cycle• Automatic power-down for portable applications • JEDEC-standard 119- and 165-bump BGA packagesFunctional DescriptionApplicationsThe GS88218/36B is a 9,437,184-bit high performancesynchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support. ControlsAddresses, data I/Os, chip enable (E1), address burst control inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive-edge-triggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burst cycles can be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by ADV. The burst address counter may be configured to count in either linear or interleave order with the Linear Burst Order (LBO) input. The Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance.Flow Through/Pipeline ReadsThe function of the Data Output register can be controlled by the user via the FT mode . Holding the FT mode pin low places the RAM in Flow Through mode, causing output data to bypass theData Output Register. Holding FT high places the RAM inPipeline mode, activating the rising-edge-triggered Data Output Register.SCD and DCD Pipelined ReadsThe GS88218/36B is a SCD (Single Cycle Deselect) and DCD (Dual Cycle Deselect) pipelined synchronous SRAM. DCD SRAMs pipeline disable commands to the same degree as read commands. SCD SRAMs pipeline deselect commands one stage less than read commands. SCD RAMs begin turning off their outputs immediately after the deselect command has been captured in the input registers. DCD RAMs hold the deselect command for one full cycle and then begin turning off their outputs just after the second rising edge of clock. The user may configure this SRAM for either mode of operation using the SCD mode input.Byte Write and Global WriteByte write operation is performed by using Byte Write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the Byte Write control inputs. FLXDrive™The ZQ pin allows selection between high drive strength (ZQ low) for multi-drop bus applications and normal drive strength (ZQ floating or high) point-to-point applications. See the Output Driver Characteristics chart for details.Sleep ModeLow power (Sleep mode) is attained through the assertion (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode. Core and Interface VoltagesThe GS88218/36B operates on a 2.5 V or 3.3 V power supply. All input are 3.3 V and 2.5 V compatible. Separate output power (V DDQ ) pins are used to decouple output noise from the internal circuits and are 3.3 V and 2.5 V compatible.Paramter Synopsis-333-300-250-200-150UnitPipeline 3-1-1-1t KQ tCycle 2.53.0 2.53.3 2.54.0 3.05.0 3.86.7ns ns Curr (x18)Curr (x32/x36)250290230265200230170195140160mA mA Flow Through 2-1-1-1t KQ tCycle 4.54.5 5.05.0 5.55.5 6.56.57.57.5ns ns Curr (x32/x36)230210185160145mA165 Bump BGA—x18 Commom I/O—Top View (Package D)1234567891011A NC A E1BB NC E3BW ADSC ADV A A18AB NC A E2NC BA CK GW G ADSP A NC BC NC NC V DDQ V SS V SS V SS V SS V SS V DDQ NC DQA CD NC DQB V DDQ V DD V SS V SS V SS V DD V DDQ NC DQA DE NC DQB V DDQ V DD V SS V SS V SS V DD V DDQ NC DQA EF NC DQB V DDQ V DD V SS V SS V SS V DD V DDQ NC DQA FG NC DQB V DDQ V DD V SS V SS V SS V DD V DDQ NC DQA GH FT MCL NC V DD V SS V SS V SS V DD NC ZQ ZZ H J DQB NC V DDQ V DD V SS V SS V SS V DD V DDQ DQA NC J K DQB NC V DDQ V DD V SS V SS V SS V DD V DDQ DQA NC K L DQB NC V DDQ V DD V SS V SS V SS V DD V DDQ DQA NC L M DQB NC V DDQ V DD V SS V SS V SS V DD V DDQ DQA NC M N DQB SCD V DDQ V SS NC NC NC V SS V DDQ NC NC N P NC NC A A TDI A1TDO A A A A17P R LBO NC A A TMS A0TCK A A A A R11 x 15 Bump BGA—13mm x 15 mm Body—1.0 mm Bump Pitch165 Bump BGA—x36 Common I/O—Top View (Package D)1234567891011A NC A E1BC BB E3BW ADSC ADV A NC AB NC A E2BD BA CK GW G ADSP A NC BC DQC NC V DDQ V SS V SS V SS V SS V SS V DDQ NC DQB CD DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB DE DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB EF DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB FG DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB GH FT MCL NC V DD V SS V SS V SS V DD NC ZQ ZZ H J DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA J K DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA K L DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA L M DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA M N DQD SCD V DDQ V SS NC NC NC V SS V DDQ NC DQA N P NC NC A A TDI A1TDO A A A A17P R LBO NC A A TMS A0TCK A A A A R11 x 15 Bump BGA—13mm x 15 mm Body—1.0 mm Bump PitchGS88236B Pad Out—119-Bump BGA—Top View (Package B)1234567A V DDQ A A ADSP A A V DDQB NC E2A ADSC A A NCC NC A A V DD A A NCD DQ C DQP C V SS ZQ V SS DQP B DQ BE DQ C DQ C V SS E1V SS DQ B DQ BF V DDQ DQ C V SSG V SS DQ B V DDQG DQ C D Q C B C ADV B B DQ B DQ BH DQ C DQ C V SS GW V SS DQ B DQ B J V DDQ V DD NC V DD NC V DD V DDQ K DQ D DQ D V SS CK V SS DQ A DQ A L DQ D DQ D B D SCD B A DQ A DQ A M V DDQ DQ D V SS BW V SS DQ A V DDQ N DQ D DQ D V SS A1V SS DQ A DQ A P DQ D DQP D V SS A0V SS DQP A DQ A R NC A LBO V DD FT A PE T NC NC A A A NC ZZ U V DDQ TMS TDI TCK TDO NC V DDQGS88218B Pad Out—119-Bump BGA—Top View (Package B)1234567A V DDQ A A ADSP A V DDQB NC E2A ADSC A A NCC NC A A V DD A A16NCD DQ B NC V SS ZQ V SS DQP A NCE NC DQ B V SS E1V SS NC DQ A8F V DDQ NC V SSG V SS DQ A V DDQG NC D Q B B B ADV NC NC DQ AH DQ B N C V SS GW V SS DQ A NC J V DDQ V DD NC V DD NC V DD V DDQ K NC DQ B V SS CK V SS NC DQ A L DQ B NC NC SCD B A DQ A NC M V DDQ DQ B V SS BW V SS NC V DDQ N DQ B NC V SS A1V SS DQ A NC P NC DQP B V SS A0V SS NC DQ A R NC A LBO V DD FT A PE T NC A A NC A A ZZ U V DDQ TMS TDI TCK TDO NC V DDQGS88218/36 BGA Pin DescriptionSymbol Type DescriptionA0, A1I Address field LSBs and Address Counter Preset InputsA I Address InputsDQ ADQ BDQ CDQ DI/O Data Input and Output pinsB A, B B, B C, B D I Byte Write Enable for DQ A, DQ B, DQ C, DQ D I/Os; active lowNC—No ConnectNC—No ConnectCK I Clock Input Signal; active highBW I Byte Write—Writes all enabled bytes; active lowGW I Global Write Enable—Writes all bytes; active lowE1I Chip Enable; active lowE3I Chip Enable; active lowE2I Chip Enable; active highG I Output Enable; active lowADV I Burst address counter advance enable; active l0w ADSC, ADSP I Address Strobe (Processor, Cache Controller); active low ZZ I Sleep mode control; active highFT I Flow Through or Pipeline mode; active lowLBO I Linear Burst Order mode; active lowPE I Parity Enable; active low (119-bump BGA only)ZQ I FLXDrive Output Impedance Control (Low = Low Impedance [High Drive], High = High Impedance [LowDrive])TMS I Scan Test Mode SelectTDI I Scan Test Data InTDO O Scan Test Data OutTCK I Scan Test ClockMCL—Must Connect Low SCD—Single Cycle Deselect/Dual Cyle Deselect Mode Control V DD I Core power supplyV SS I I/O and Core GroundV DDQ I Output driver power supplyGS88218/36B (PE = 0) Block DiagramA1A0A0A1D0D1Q1Q0Counter LoadD QDQRegisterRegisterDQRegisterDQRegisterDQRegisterD QRegisterD QRegisterD QRegisterDQR e g i s t e rDQRegisterA0–An LBO ADV CK ADSC ADSP GW BW E 1FT GZZPower Down ControlMemory Array36364AQD DQx1–DQx93636Note: Only x36 version shown for simplicity.3636B AB BB CB DGS88218/36B (PE = 1) x32 Mode Block DiagramA1A0A0A1D0D1Q1Q0Counter LoadD QDQRegisterRegisterDQRegisterDQRegisterDQRegisterD QRegisterD QRegisterD QRegisterDQR e g i s t e rDQRegisterA0–An LBO ADV CK ADSC ADSP GW BW B AB BB CB DE 1FT GZZPower Down ControlMemory Array36364AQD DQx1–DQx83232Note: Only x36 version shown for simplicity.Parity Encode 3243236Note:There pull-down device on the ZZ pin, so input pin can be unconnected and the chip will operate in the default states as specified in the above tables.Burst Counter SequencesBPR 1999.05.18Mode Pin FunctionsMode NamePin NameStateFunctionBurst Order Control LBO L Linear Burst H Interleaved BurstPower Down ControlZZL or NC Active HStandby, I DD = I SBNote:The burst counter wraps to initial state on the 5th clock.Note:The burst counter wraps to initial state on the 5th clock.Linear Burst SequenceA[1:0]A[1:0]A[1:0]A[1:0]1st address 000110112nd address 011011003rd address 101100014th address11000110Interleaved Burst SequenceA[1:0]A[1:0]A[1:0]A[1:0]1st address 000110112nd address 010011103rd address 101100014th address11100100Byte Write Truth TableFunction GW BW B A B B B C B D Notes Read H H X X X X1Read H L H H H H1 Write byte a H L L H H H2, 3 Write byte b H L H L H H2, 3 Write byte c H L H H L H2, 3, 4 Write byte d H L H H H L2, 3, 4 Write all bytes H L L L L L2,3,4 Write all bytes L X X X X X1.All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.2.Byte Write Enable inputs B A, B B, B C, and/or B D may be used in any combination with BW to write single or multiple bytes.3.All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.4.Bytes “C” and “D” are only available on the x36 version.Synchronous Truth TableOperation Address UsedStateDiagramKey5E1ADSP ADSC ADV W3DQ4Deselect Cycle, Power Down None X H X L X X High-Z Read Cycle, Begin Burst External R L L X X X Q Read Cycle, Begin Burst External R L H L X F Q Write Cycle, Begin Burst External W L H L X T D Read Cycle, Continue Burst Next CR X H H L F Q Read Cycle, Continue Burst Next CR H X H L F Q Write Cycle, Continue Burst Next CW X H H L T D Write Cycle, Continue Burst Next CW H X H L T D Read Cycle, Suspend Burst Current X H H H F Q Read Cycle, Suspend Burst Current H X H H F Q Write Cycle, Suspend Burst Current X H H H T D Write Cycle, Suspend Burst Current H X H H T D Notes:1.X = Don’t Care, H = High, L = Low2.W = T (True) and F (False) is defined in the Byte Write Truth Table preceding3.G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shownas “Q” in the Truth Table above).4.All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplishbasic synchronous or synchronous burst operations and may be avoided for simplicity.5.Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.6.Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.Simplified State DiagramFirst WriteFirst ReadBurst WriteBurst ReadDeselect R WCRCWX XWRRWRXXX S i m p l e S y n c h r o n o u s O p e r a t i o nS i m p l e B u r s t S y n c h r o n o u s O p e r a t i o nCR RCWCRCRNotes:1.The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low.2.The upper portion of the diagram assumes active use of only the Enable (E1) and Write (B A , B B , B C , B D , BW, and GW) control inputs, andthat ADSP is tied high and ADSC is tied low.3.The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs andassumes ADSP is tied high and ADV is tied low.Simplified State Diagram with GFirst WriteFirst ReadBurst WriteBurst ReadDeselect R WCRCWXXWRRWRXXX CRR CW CRCRW CWW CWNotes:1.The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.e of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from read cycles to write cycles without passingthrough a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles.3.Transitions shown in grey tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meetData Input Set Up Time.Absolute Maximum Ratings(All voltages reference to V SS)Symbol Description Value UnitV DD Voltage on V DD Pins–0.5 to 4.6VV DDQ Voltage in V DDQ Pins–0.5 to 4.6VV I/O Voltage on I/O Pins–0.5 to V DDQ +0.5 (≤ 4.6 V max.)VV IN Voltage on Other Input Pins–0.5 to V DD +0.5 (≤ 4.6 V max.)VI IN Input Current on Any Pin+/–20mAI OUT Output Current on Any I/O Pin+/–20mAP D Package Power Dissipation 1.5WT STG Storage Temperature–55 to 125o CT BIAS Temperature Under Bias–55 to 125o C Note:Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component.Power Supply Voltage RangesParameter Symbol Min.Typ.Max.Unit Notes3.3 V Supply Voltage V DD3 3.0 3.3 3.6V2.5 V Supply Voltage V DD2 2.3 2.5 2.7V3.3 V V DDQ I/O Supply Voltage V DDQ3 3.0 3.3 3.6V2.5 V V DDQ I/O Supply Voltage V DDQ2 2.3 2.5 2.7VNotes:1.The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-tions quoted are evaluated for worst case in the temperature range marked on the device.2.Input Under/overshoot voltage must be –2 V > Vi < V DDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.V DDQ3 Range Logic LevelsParameter Symbol Min.Typ.Max.Unit Notes V DD Input High Voltage V IH 2.0—V DD + 0.3V1V DD Input Low Voltage V IL–0.3—0.8V1V DDQ I/O Input High Voltage V IHQ 2.0—V DDQ + 0.3V1,3V DDQ I/O Input Low Voltage V ILQ–0.3—0.8V1,3 Notes:1.The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-tions quoted are evaluated for worst case in the temperature range marked on the device.2.Input Under/overshoot voltage must be –2 V > Vi < V DDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.3.V IHQ (max) is voltage on V DDQ pins plus 0.3 V.V DDQ2 Range Logic LevelsParameter Symbol Min.Typ.Max.Unit Notes V DD Input High Voltage V IH0.6*V DD—V DD + 0.3V1V DD Input Low Voltage V IL–0.3—0.3*V DD V1V DDQ I/O Input High Voltage V IHQ0.6*V DD—V DDQ + 0.3V1,3V DDQ I/O Input Low Voltage V ILQ–0.3—0.3*V DD V1,3 Notes:1.The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-tions quoted are evaluated for worst case in the temperature range marked on the device.2.Input Under/overshoot voltage must be –2 V > Vi < V DDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.3.V IHQ (max) is voltage on V DDQ pins plus 0.3 V.Recommended Operating TemperaturesParameter Symbol Min.Typ.Max.Unit Notes Ambient Temperature (Commercial Range Versions)T A02570°C2 Ambient Temperature (Industrial Range Versions)T A–402585°C2 Notes:1.The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-tions quoted are evaluated for worst case in the temperature range marked on the device.2.Input Under/overshoot voltage must be –2 V > Vi < V DDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.Note:These parameters are sample tested.Capacitance(T A = 25o C, f = 1 MH Z , V DD = 2.5 V)ParameterSymbolTest conditionsTyp.Max.UnitInput Capacitance C IN V IN = 0 V 45pF Input/Output Capacitance C I/OV OUT = 0 V67pFAC Test ConditionsParameterConditionsInput high level V DD – 0.2 V Input low level 0.2 V Input slew rate 1 V/ns Input reference level V DD /2Output reference levelV DDQ /2Output loadFig. 1Notes:1.Include scope and jig capacitance.2.Test conditions as specified with output loading as shown in Fig. 1unless otherwise noted.3.Device is deselected as defined by the Truth Table. 50% tKCV SS – 2.0 V50%V SS V IHUndershoot Measurement and TimingOvershoot Measurement and Timing50% tKCV DD + 2.0 V50%V DDV ILDQV DDQ/250Ω30pF *Output Load 1* Distributed Test Jig CapacitanceDC Electrical CharacteristicsParameter Symbol Test Conditions Min Max Input Leakage Current(except mode pins)I IL V IN = 0 to V DD–1 uA 1 uAZZ Input Current I IN1V DD≥V IN ≥V IH0 V≤ V IN ≤ V IH–1 uA–1 uA1 uA100 uAFT, SCD, ZQ Input Current I IN2V DD≥V IN ≥V IL0 V≤ V IN ≤ V IL–100 uA–1 uA1 uA1 uAOutput Leakage Current I OL Output Disable, V OUT = 0 to V DD–1 uA 1 uA Output High Voltage V OH2I OH = –8 mA, V DDQ = 2.375 V 1.7 V—Output High Voltage V OH3I OH = –8 mA, V DDQ = 3.135 V 2.4 V—Output Low Voltage V OL I OL = 8 mA—0.4 V1.I DD and I DDQ apply to any combination of V DD3, V DD2, V DDQ3, and V DDQ2 operation.2.All parameters listed are worst case scenario.Operating CurrentsParameterTest ConditionsModeSymbol-333-300-250-200-150Unit0to 70°C–40 to 85°C0to 70°C–40 to 85°C0to 70°C–40 to 85°C0to 70°C–40to 85°C0 to 70°C–40to 85°COperating CurrentDevice Selected; All other inputs ≥V IH o r ≤ V IL Output open(x32/x36)Pipeline I DD I DDQ 25040270402303525035200302203017025190251402016020mA Flow Through I DD I DDQ 20525225251852520525160251802514020160201301515015mA (x18)PipelineI DD I DDQ 23020250202102023020185152051515515175151301015010mA Flow Through I DD I DDQ 185152051517015190151451516515130101501012081408mA Standby CurrentZZ ≥ V DD – 0.2 V —PipelineI SB 40504050405040504050mA Flow Through I SB 40504050405040504050mA Deselect CurrentDevice Deselected; All other inputs ≥ V IH or ≤ V IL—PipelineI DD 951009095859075806065mA Flow ThroughI DD65606065606550555055mANotes:1.These parameters are sampled and are not 100% tested.2.ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and holdtimes as specified above.AC Electrical CharacteristicsParameterSymbol-333-300-250-200-150UnitMinMax Min Max Min Max Min Max Min Max PipelineClock Cycle Time tKC 3.0— 3.3— 4.0— 5.0— 6.7—ns Clock to Output Valid tKQ — 2.5— 2.5— 2.5— 3.0— 3.8ns Clock to Output Invalid tKQX 1.5— 1.5— 1.5— 1.5— 1.5—ns Clock to Output in Low-ZtLZ 1 1.5— 1.5— 1.5— 1.5— 1.5—ns Setup time tS 1.0— 1.0— 1.2— 1.4— 1.5—ns Hold time tH 0.1—0.1—0.2—0.4—0.5—ns Flow ThroughClock Cycle Time tKC 4.5— 5.0— 5.5— 6.5—7.5—ns Clock to Output Valid tKQ — 4.5— 5.0— 5.5— 6.5—7.5ns Clock to Output Invalid tKQX 2.0— 2.0— 2.0— 2.0— 2.0—ns Clock to Output in Low-ZtLZ 1 2.0— 2.0— 2.0— 2.0— 2.0—ns Setup time tS 1.3— 1.4— 1.5— 1.5— 1.5—ns Hold time tH 0.3—0.4—0.5—0.5—0.5—ns Clock HIGH Time tKH 1.0— 1.0— 1.3— 1.3— 1.5—ns Clock LOW Time tKL 1.2—1.2—1.5—1.5—1.7—ns Clock to Output inHigh-Z tHZ 1 1.5 2.5 1.5 2.5 1.5 2.5 1.5 3.0 1.5 3.0ns G to Output Valid tOE — 2.5— 2.5— 2.5— 3.0— 3.8ns G to output in Low-Z tOLZ 10—0—0—0—0—ns G to output in High-Z tOHZ 1— 2.5— 2.5— 2.5— 3.0— 3.8ns ZZ setup time tZZS 25—5—5—5—5—ns ZZ hold time tZZH 21—1—1—1—1—ns ZZ recoverytZZR20—20—20—20—20—nsPipeline Mode Timing (SCD)Begin Read A Cont Cont Deselect Write B Read C Read C+1Read C+2Read C+3ContDeselecttHZtKQX tKQtLZtHtStOHZtOEtHtStHtStHtStHtStHtStStHtStHtStHtSBurst ReadtKCtKL Single Write tKH Single ReadQ(A)D(B)Q(C)Q(C+1)Q(C+2)Q(C+3)ABCDeselected with E1E1 masks ADSPE2 and E3 only sampled with ADSP and ADSCADSC initiated readCK ADSPADSCADVA0–AnGWBWBa–BdE1E2E3GDQa–DQdFlow Through Mode Timing (SCD)Begin Read A ContCont Write B Read C Read C+1Read C+2Read C+3Read C Cont DeselecttHZtKQXtKQ tLZtH tStOHZtOEtHtS tHtS tHtStHtS tHtS tHtStHtS tHtS tH tS tHtS tKCtKL tKHABCQ(A)D(B)Q(C)Q(C+1)Q(C+2)Q(C+3)Q(C)E2 and E3 only sampled with ADSCADSC initiated readDeselected with E1Fixed HighCK ADSPADSCADVA0–AnGWBWBa–BdE1E2E3GDQa–DQdPipeline Mode Timing (DCD)Begin Read A Cont Deselect Deselect Write BRead C Read C+1Read C+2Read C+3Cont Deselect DeselecttHZtKQXtKQtLZtHtStOHZtOEtHtStHtStHtStH tStHtStStHtStHtStHtStKCtKL tKHQ(A)D(B)Q(C)Q(C+1)Q(C+2)Q(C+3)ABCHi-ZDeselected with E1E2 and E3 only sampled with ADSCADSC initiated readCK ADSPADSCADVAo–AnGWBWBa–BdE1E2E3GDQa–DQdFlow Through Mode Timing (DCD)Sleep ModeDuring normal operation, ZZ must be pulled low, either by the user or by it’s internal pull down resistor. When ZZ is pulled high, the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM operates normally after ZZ recovery time.Begin Read A ContDeselect Write B Read C Read C+1Read C+2Read C+3Read C DeselecttHZtKQX tLZtH tStOHZtOE tKQtHtS tHtS tHtStH tStHtS tHtStHtS tHtS tH tStH tS tHtS tKCtKL tKHABCQ(A)D(B)Q(C)Q(C+1)Q(C+2)Q(C+3)Q(C)E2 and E3 only sampled with ADSP and ADSCE1 masks ADSPADSC initiated readDeselected with E1E1 masks ADSPFixed HighCK ADSPADSCADVAo–AnGWBWBa–BdE1E2E3GDQa–DQdSleep mode is a low current, power-down mode in which the device is deselected and current is reduced to I SB 2. The duration of Sleep mode is dictated by the length of time the ZZ is in a high state. After entering Sleep mode, all inputs except ZZ become disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode. When the ZZ pin is driven high, I SB 2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands may be applied while the SRAM is recovering from Sleep mode.Sleep Mode Timing DiagramApplication TipsSingle and Dual Cycle DeselectSCD devices (like this one) force the use of “dummy read cycles” (read cycles that are launched normally, but that are ended with the output drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance, but their use usually assures there will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste bandwidth on dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at bank address boundary crossings), but greater care must be exercised to avoid excessive bus contention.JTAG Port OperationOverviewThe JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with V DD . The JTAG output drivers are powered by V DDQ .Disabling the JTAG PortIt is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG Port unused, TCK, TDI, and TMS may be left floating or tied to either V DD or V SS . TDO should be left unconnected.tZZRtZZHtZZSHoldSetup tKLtKHtKCCKADSP ADSCZZJTAG Port Registers OverviewThe various JTAG registers, refered to as Test Access Port orTAP Registers, are selected (one at a time) via the sequences of 1s and 0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the rising edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the TDI and TDO pins.Instruction RegisterThe Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the controller is placed in Test-Logic-Reset state.Bypass RegisterThe Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through the RAM’s JTAG Port to another device in the scan chain with as little delay as possible.Boundary Scan RegisterThe Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins. The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is inCapture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z, SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.JTAG Pin Descriptions PinPin NameI/ODescriptionTCK Test Clock In Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate from the falling edge of TCK.TMSTest Mode SelectInThe TMS input is sampled on the rising edge of TCK. This is the command input for the TAP controller state machine. An undriven TMS input will produce the same result as a logic one input level.TDI Test Data In InThe TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers placed between TDI and TDO. The register placed between TDI and TDO is determined by the state of the TAP Controller state machine and the instruction that is currently loaded in the TAP Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce the same result as a logic one input level.TDO Test Data OutOut Output that is active depending on the state of the TAP state machine. Output changes inresponse to the falling edge of TCK. This is the output side of the serial registers placed betweenTDI and TDO.This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up.。

超同步 GS伺服主轴驱动器使用说明书

ctb gs driver 资料编号：zl-10-808-ibcn本产品在改进的同时，资料可能有所变动，恕不另行通知地址：北京市密云县十里堡镇王各庄产业基地电话：010-********传真：010-********24小时全国免费服务电话：400-888-9055ctb technology 经销商北京超同步科技股份有限公司ctb gs driver资料编号：z l-10-808-i b c n beijing ctb technology & stocking co.,ltd.gs driver使用说明书交流伺服主轴驱动器型号：bksc-□□□□gs 400v 级 1.5~160kw (2.5~200kva)请将此使用说明书，交给最终用户，并妥善保存ctb technology 北京超同步科技股份有限公司序言感谢您惠购北京超同步科技股份有限公司生产的G S 系列伺服驱动器。

G S 系列伺服驱动器是北京超同步科技有限公司研制、开发生产的高品质、多功能、低噪音的交流伺服驱动器。

G S 系列伺服驱动器是交流感应电机（i M）的伺服驱动器，可对普通交流感应电机和变频电机的位置、转速、加速度和输出转矩方便地进行控制，G S 系列伺服驱动器的研制成功为传动控制领域带来了无限生机。

G S 系列伺服驱动器核心采用32位c P U，实现对电机全数字控制。

使交流感应电机具有和同步电机、直流电机一样的调速特性。

是机械制造业最具竞争力的电气传动产品。

GS 系列通用伺服驱动器，是根据自动化领域，针对位置、速度、力矩控制要求而开发，是机床、纺织、塑机、造纸及各种自动化流水线等运动控制领域的首选产品。

在使用GS 系列伺服驱动器之前，请您仔细阅读该手册，以保证正确使用。

错误使用可能造成驱动器运行不正常、发生故障或降低使用寿命，乃至发生人身伤害事故。

因此使用前应反复阅读本说明书，严格按说明使用。

本手册为随机发送的附件，务必请您使用后妥善保管，以备今后对驱动器进行检修和维护时使用。