帧格式头数据检测_VerilogHDL有限状态机

合集下载
  1. 1、下载文档前请自行甄别文档内容的完整性,平台不提供额外的编辑、内容补充、找答案等附加服务。
  2. 2、"仅部分预览"的文档,不可在线预览部分如存在完整性等问题,可反馈申请退款(可完整预览的文档不适用该条件!)。
  3. 3、如文档侵犯您的权益,请联系客服反馈,我们会尽快为您处理(人工客服工作时间:9:00-18:30)。

题目1:串行通讯中,经常要检测数据包的开始标志,例如:USB 数据包的起

始数据是8‘b00101010设计一个电路,能够检测串行数据流中的特殊数据串,并在数据串有效时,给出相应的指示信号;

(1)RTL Code

/*信号定义与说明

Clk:同步时钟

rstb: 异步复位信号,低电平复位

up_down: 加/减计数方向控制信号,1为加计数

Din:串行数据输入

pat_det: 检测结果输出

*/

`timescale 1ns/1ns

module serialdata(din,clk,rstb,pat_det);

input clk,rstb;

input din;

output pat_det;

parameter S0='d0,S1='d1,S2='d2,S3='d3,S4='d4,S5='d5,S6='d6,IDLE='d7;

reg[2:0] state;

assign pat_det=(state= =S6&&din= =0)?1:0;

always@(posedge clk or negedge rstb)

begin

if(!rstb) state<=IDLE;

else

begin

case(state)

IDLE:

begin

if(din==0) state<=S0;

else state<=IDLE;

end

S0:

begin

if(din==0) state<=S1;

else state<=IDLE;

end

S1:

begin

if(din==1) state<=S2;

else state<=S1;

end

S2:

begin

if(din==0) state<=S3;

else state<=IDLE;

end

S3:

begin

if(din==1) state<=S4;

else state<=S1;

end

S4:

begin

if(din==0) state<=S5;

else state<=IDLE;

end

S5:

begin

if(din==1) state<=S6;

else state<=S1;

end

S6: state<=IDLE;

default: state<=IDLE;

endcase

end

end

endmodule

(2)Test File

`timescale 1ns/1ns

`include "serialdata.v"

module tb_serialdata;

reg clk,rstb;

wire din;

wire pat_det;

reg[31:0] data;

assign din=data[31];

serialdata t1(din,clk,rstb,pat_det);

initial begin

clk=1'b0;

rstb=1'b0;

data=32'b1001_0010_1010_1100_1010_1000_1010_1010;

#10 rstb=1'b1;

#640 $stop;

end

always@(posedge clk)

begin

data <={data[30:0],data[31]};

end

always #5 clk=~clk;

endmodule

(3)波形与说明

图示标注地方每个上升沿取得数据din,当检测到00101010之后输出pat_det 置为高电平。

整个32位串行输入数据1001_0010_1010_1100_1010_1000_1010_1010,总共640个时间单位stop,即32位输入数据跑两遍,共输出6个高电平脉冲,符合设计!

题目2:设计一个串行数据检测器,输入数据与时钟同步。要求是:输入连续5

个或5 个以上的1 时输出为1,其他输入情况下输出为0

(1)RTL Code

/*信号定义与说明

clk: 同步输入时钟

nreset: 复位信号,低电平有效

din: 串行数据输入

out:检测结果输出

*/

`timescale 1ns/1ns

module serialfive1(out,din,clk,nreset);

input din;

input clk,nreset;

output out;

parameter M0='d0,M1='d1,M2='d2,M3='d3,M4='d4,IDLE='d5;

reg[2:0] state;

assign out=(state==M4&&din==1)?1:0;

always @(posedge clk)

begin

if(!nreset) state<=IDLE;

else

case(state)

IDLE:

begin

if(din==1) state <= M0;

else state <= IDLE;

end

M0:

begin

if(din==1) state <= M1;

else state <= IDLE;

end

M1:

begin

if(din==1) state <= M2;

else state <= IDLE;

end

M2:

begin

if(din==1) state <= M3;

else state <= IDLE;

end

M3:

begin

if(din==1) state <= M4;

else state <= IDLE;

end

M4:

begin

if(din==1) state <= M4;

else state <= IDLE;

end

default: state <= IDLE;

endcase

end

endmodule

(2)Test File

`include "serialfive1.v"

`timescale 1ns/1ns

module tb_serialfive1;

相关文档
最新文档