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NCL30001High-Efficiency Single Stage Power FactorCorrection and Step-Down Offline LED DriverThe NCL30001 is a highly integrated controller for implementing power factor correction (PFC) and isolated step down ac −dc power conversion in a single stage, resulting in a lower cost and reduced part count solution. This controller is ideal for LED Driver power supplies with power requirements between 40 W and 150 W. The single stage is based on the flyback converter and it is designed to operate in continuous conduction (CCM).The NCL30001 can be configured as as constant current driver or a fixed output driver for two stage LED lighting applications. In addition, the controller features a proprietary Soft −Skip ™ to reduce acoustic noise at light loads. Other features found in the NCL30001include a high voltage startup circuit, voltage feedforward, brown out detector, internal overload timer, latch input and a high accuracy multiplier. The multi −function latch off pin can also be used to implement an overtemperature shutdown circuit.Features•V oltage Feedforward Improves Loop Response •Frequency Jittering Reduces EMI Signature•Proprietary Soft −Skip at Light Loads Reduces Acoustic Noise •Brown Out Detector•Internal 160 ms Fault Timer•Independent Latch −Off Input Facilitates Implementation of Overvoltage and Overtemperature Fault Detectors•Average Current Mode Control (ACMC), Fixed Frequency Operation •High Accuracy Multiplier Reduces Input Line Harmonics •Adjustable Operating Frequency from 20 kHz to 250 kHz •These Devices are Pb −Free and are RoHS Compliant Typical Applications•LED Street Lights•Low Bay LED Lighting •High Power LED Drivers •Architectural LED LightingMARKINGDIAGRAMA = Assembly Location WL = Wafer Lot YY = YearWW = Work WeekG= Pb −Free PackageSOIC −16D SUFFIX CASE 751BNCL30001G AWLYWWSee detailed ordering and shipping information in the package dimensions section on page 30 of this data sheet.ORDERING INFORMATION(Top View )V FF CT Ramp Comp AC IN FB CM AC COMP Latch −Off Startup V CC I spos TESTI avg DRV GND NC PIN CONNECTIONSStartupI sposGNDV CCLatch −DRVI avgTESTV Figure 1. Detailed Block DiagramPIN FUNCTION DESCRIPTIONPin Symbol Description1C T An external timing capacitor (C T) sets the oscillator frequency. A sawtooth between 0.2 V and 4 V sets the oscillator frequency and the gain of the multiplier.2RAMP COMP A resistor (R RC) between this pin and ground adjust the amount of ramp compensation that is added to the current signal. Ramp compensation is required to prevent subharmonic oscillations. This pin should not beleft open.3AC IN The scaled version of the full wave rectified input ac wave is connected to this pin by means of a resistive voltage divider. The line voltage information is used by the multiplier.4FB An error signal from an external error amplifier circuit is fed to this pin via an optocoupler or other isolation circuit. The FB voltage is a proportional of the load of the converter. If the voltage on the FB pin drops be-low 0.41 V (typical) the controller enters Soft−Skip to reduce acoustic noise.5VFF Feedforward input. A scaled version of the filtered rectified line voltage is applied by means of a resistive divider and an averaging capacitor. The information is used by the Reference Generator to regulate thecontroller.6CM Multiplier output. A capacitor is connected between this pin and ground to filter the modulated output of the multiplier.7AC COMP Sets the pole for the ac reference amplifier. The reference amplifier compares the low frequency compon-ent of the input current to the ac reference signal. The response must be slow enough to filter out most ofthe high frequency content of the current signal that is injected from the current sense amplifier, but fastenough to cause minimal distortion to the line frequency information. The pin should not be left open.8Latch Latch−Off input. Pulling this pin below 1.0 V (typical) or pulling it above 7.0 V (typical) latches the controller.This input can be used to implement an overvoltage detector, an overtemperature detector or both. Referto Figure 60 for a typical implementation.9TEST This pin is a TEST pin. A nominal 50K $10% resistor must be connected to GND for proper operation. 10I AVG An external resistor and capacitor connected from this terminal to ground, to set and stabilizes the gain of the current sense amplifier output that drives the ac error amplifier.11I Spos Positive current sense input. Connects to the positive side of the current sense resistor.12V CC Positive input supply. This pin connects to an external capacitor for energy storage. An internal current source supplies current from the STARTUP pin V CC. Once the voltage on V CC reaches approximately 15.3V, the current source turns off and the outputs are enabled. The drivers are disabled once V CC reachesapproximately 10.2 V. If V CC drops below 0.83 V (typical), the startup current is reduced to less than500 m A.13DRV Drive output for the main flyback power MOSFET or IGBT. DRV has a source resistance of 10.8 W (typical) and a sink resistance of 8 W (typical).14NC No Connect15GND Ground reference for the circuit.16HV Connect the rectified input line voltage directly to this pin to enable the internal startup regulator. A con-stant current source supplies current from this pin to the capacitor connected to the V CC pin, eliminatingthe need for a startup resistor. The charge current is typically 5.5 mA. Maximum input voltage is 500 V.MAXIMUM RATINGS (Notes 1 and 2)Rating Symbol Value UnitStart_up Input Voltage Start_up Input Current V HVI HV−0.3 to 500$100VmAPower Supply Input Voltage Power Supply Input Current V CCI CC−0.3 to 20$100VmALatch Input Voltage Latch Input Current V LatchI Latch−0.3 to 10$100VmAAll Other Pins Voltage All Other Pins Current −0.3 to 6.5$100VmAThermal Resistance, Junction−to−Air 0.1 in” Copper0.5 in” Copper q JA130110°C/WThermal Resistance, Junction−to−Lead RΘJL50°C/W Maximum Power Dissipation @ T A = 25°C P MAX0.77W Operating Temperature Range T J−40 to 125°C Storage Temperature Range T STG−55 to 150°C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.1.This device contains ESD protection and exceeds the following tests:Pin 1−15: Human Body Model 2000 V per MIL−Std−883, Method 3015.Machine Model Method 200 VPin 16 is the high voltage startup of the device and is rated to the maximum rating of the part, 500 V.2.This device contains Latchup protection and exceeds ±100 mA per JEDEC Standard JESD78.NCL30001Figure 2. Typical Application SchematicR L E DTEST RC J JParameter Test Condition Symbol Min Typ Max Unit OSCILLATORFrequency f osc90100110kHz– 6.8–% Frequency Modulation in Percentageof f OSCFrequency Modulation Period– 6.8–ms Ramp Peak Voltage V CT(peak)– 4.0–V Ramp Valley Voltage V CT(valley)–0.10–V Maximum Duty Ratio R TEST = open D94−–% Ramp Compensation Peak Voltage V RCOMP(peak)–4–V AC ERROR AMPLIFIERInput Offset Voltage (Note 3)Ramp I AVG, V FB = 0 V ACV IO40–mV Error Amplifier Transconductance g m–100–m SI EA(source)2570–m A Source Current V AC COMP = 2.0 V, V AC IN = 2.0 V,V FF = 1.0 VSink Current V AC COMP = 2.0 V, V A C_IN = 2.0 V,I EA(sink)−25−70–m AV FF = 5.0 VCURRENT AMPLIFIERTEST RC J JParameter UnitMaxTypMinSymbolTest ConditionAC INPUTInput Bias Current Into ReferenceMultiplier & Current CompensationAmplifierI AC IN(IB)–0.01–m A DRIVE OUTPUTDrive Resistance (Thermally Limited)DRV SinkDRV SourceV DRV = 1 VI DRV = 100 mAR SNKR SRC––810.81824WRise Time (10% to 90%)DRV t r–40–ns Fall Time (90% to 10%)DRV t f–20–ns Driver Out Low VoltageDRV I DRV = 100 m A V DRV(low)– 1.0100mV Soft−SkipSkip Synchronization to ac LineVoltage ThresholdV ACIN Increasing, V FB = 1.5 V V SSKIP(SYNC)210267325mVSkip Synchronization to ac Line Voltage Threshold Hysteresis V ACIN Decreasing V SSKIP(SYNCHYS)–40–mVSkip Ramp Period (Note 3)t SSKIP− 2.5–ms Skip Voltage Threshold V SSKIP360410460V Skip Voltage Hysteresis V SSKIP(HYS)4590140mV Skip Transient Load Detect Threshold(Note 3)V SSKIP(TLD)− 1.75−V FEEDBACK INPUTPull−Up Current Source V FB = 0.5 V I FB600750920m A Pull−Up Resistor R FB– 6.7–k W Open Circuit Voltage V FB(open) 5.3 5.7 6.3V STARTUP AND SUPPLY CIRCUITSSupply VoltageStartup ThresholdMinimum Operating VoltageLogic Reset Voltage V CC IncreasingV CC DecreasingV CC DecreasingV CC(on)V CC(off)V CC(reset)14.39.3–15.410.27.016.311.3–VInhibit Threshold Voltage V HV = 40 V, I inhibit = 500 m A V inhibit−0.83 1.15V Inhibit Bias Current V HV = 40 V, V CC = 0.8 * V inhibit I inhibit40-500m A Minimum Startup Voltage I start = 0.5 mA, V CC = V CC(on) – 0.5 V V start(min)––40V Startup Current V CC = V CC(on) – 0.5 V, V FB = Open I start 3.0 5.628.0mAOff−State Leakage Current V HV = 400 V, T J = 25°CT J = −40°C to 125°C I HV(off)––17154080m ASupply CurrentDevice Disabled (Overload) Device SwitchingV FB = Openf OSC[ 100 kHzI CC1I CC2––0.726.251.27.2mAFAULT PROTECTIONOverload Timer t OVLD120160360ms Overload Detect Threshold V OVLD 4.7 4.9 5.2V 3.Guaranteed by DesignTEST RC J JParameter UnitMaxTypMinSymbolTest ConditionFAULT PROTECTIONBrown−Out Detect Threshold (entering fault mode)V FF Decreasing, V FB = 2.5 V,V AC IN = 2.0 VV BO(low)0.410.450.49VBrown−Out Exit Threshold (exiting fault mode)V FF Increasing, V FB = 2.5 V,V AC IN = 2.0 VV BO(high)0.570.630.69VBrown−Out Hysteresis V BO(HYS)−174−mV LATCH INPUTPull−Down Latch Voltage Threshold V Latch Decreasing V latch(low)0.90.98 1.1V Pull−Up Latch Voltage Threshold V Latch Increasing V latch(high) 5.67.08.4V Latch Propagation Delay V Latch =V latch(high)t latch(delay)305690m s Latch Clamp Current (Going Out)V Latch = 1.5 V I latch(clamp)425158m A Latch Clamp Voltage (I Latch Going In)I Latch = 50 m A V latch(clamp) 2.5 3.27 4.5V Latch−Off Current Shutdown(Going In)V Latch Increasing I latch(shdn)−95−m A 3.Guaranteed by DesignFigure 3. Oscillator Frequency (f OSC ) vs.Junction Temperature6.06.57.07.58.0−50−250255075100125150Figure 4. Oscillator Frequency Modulation in Percentage of f OSC vs. Junction TemperatureT J , JUNCTION TEMPERATURE (°C)6.06.57.07.58.0−50−250255075100125150T J , JUNCTION TEMPERATURE (°C)Figure 5. Oscillator Frequency ModulationPeriod vs. Junction Temperature3.83.853.93.954.04.054.1−50−250255075100125150T J , JUNCTION TEMPERATURE (°C)Figure 6. Ramp Peak Voltage vs. JunctionTemperatureV C T (p e a k ), O S C I L L A T O R R A M P P E A K V O L T A G E (V )9092949698100−50−250255075100125150D , M A X I M U M D U T Y R A T I O (%)Figure 7. Maximum Duty Ratio vs. JunctionTemperature T J , JUNCTION TEMPERATURE (°C)−50−2502550751001251503.83.853.93.954.04.054.1T J , JUNCTION TEMPERATURE (°C)V C O M P (p e a k ), R A M P C O M P P E A K V O L T A G E (V )Figure 8. Ramp Compensation Peak Voltagevs. Junction Temperature9095100105110−50−25255075100125150T J , JUNCTION TEMPERATURE (°C)f O S C , O S C I L L A T O R F R E Q U E N C Y (k H z )O S C I L L A T O R F R E Q U E N C Y M O D U L A T I O N P E R I O D (m s )O S C I L L A T O R F R E Q U E N C Y M O D U L A T I O N (%)505560657075808590−50−25255075100125150T J , JUNCTION TEMPERATURE (°C)I E A (S O U R C E ), E R R O R A M P L I F I E R S O U R C E C U R R E N T (m A )Figure 9. Error Amplifier Source Current vs.Junction Temperature505560657075808590−50−25255075100125150Figure 10. Error Amplifier Sink Current vs.Junction TemperatureT J , JUNCTION TEMPERATURE (°C)I E A (S I N K ), E R R O R A M P L I F I E R S I N K C U R R E N T (m A )40.042.545.047.550.052.555.057.560.0−50−25255075100125150Figure 11. Current Amplifier Input Bias Current vs. Junction TemperatureT J , JUNCTION TEMPERATURE (°C)C A V B I A S , C U R R E N T A M P L I F I E R I N P U T B I A S C U R R E N T (m A )700710720730740750760770−50−25255075100125150T J , JUNCTION TEMPERATURE (°C)Figure 12. Current Limit Threshold vs.Junction Temperature V I L I M , C U R R E N T L I M I T T H R E S H O L D (m V )5.05.25.45.65.86.0−50−250255075100125150T J , JUNCTION TEMPERATURE (°C)P W M k , P W M V O L T A G E G A I N (V /V )Figure 13. PWM Output Voltage Gain vs.Junction TemperatureFigure 14. Oscillator CS Limit Voltage Gain vs.Junction Temperature16171819202122−50−250255075100125150T J , JUNCTION TEMPERATURE (°C)I S V k , C U R R E N T L I M I T V O L T A G E G A I N (V /V )5.25T J , JUNCTION TEMPERATURE (°C)Figure 15. Oscillator Reference Generator Output Voltage vs. Junction TemperatureR G o u t , R E F E R E N C E G E N E R A T O R O U T P U T V O L T A G E (V )4.06.08.0101214−50−250255075100125150T J , JUNCTION TEMPERATURE (°C)R S N K 1, D R V S I N K D R I V E R E S I S T A N C E (W )Figure 16. DRV Sink Resistance vs. JunctionTemperature 6.08.010121416−50−250255075100125150Figure 17. DRV Source Drive Resistance vs.Junction TemperatureT J , JUNCTION TEMPERATURE (°C)R S R C 1, D R V S O U R C E R E S I S T A N C E (W )T J , JUNCTION TEMPERATURE (°C)V D R V (l o w ), D R V L O W V O L T A G E (m V )Figure 18. DRV Low Voltage vs. JunctionTemperature200220240260280300−−250255075100125150Figure 19. Skip Synchronization to ac Line Voltage Threshold vs. Junction Temperature T J , JUNCTION TEMPERATURE (°C)V S S K I P (S Y N C ), S K I P S Y N C T O A C L I N E V O L T A G E T H R E S H O L D (m V )T J , JUNCTION TEMPERATURE (°C)V S S K I P , S K I P V O L T A G E T H R E S H O L D (V )Figure 20. Skip Voltage Threshold vs. JunctionTemperature30507090110130−50−2502550751001251500.3900.3920.3940.3960.3980.4000.4020.4040.4060.4080.41080859095100−50−25255075100125150Figure 21. Skip Voltage Hysteresis vs.Junction TemperatureT J , JUNCTION TEMPERATURE (°C)V S S K I P , S K I P V O L T A G E H Y S T E R E S I S (m V )680705730755780−50−250255075100125150T J , JUNCTION TEMPERATURE (°C)I F B , F E E D B A C K P U L L −U P C U R R E N T S O U R C E (m A )Figure 22. Feedback Pull −Up Current Sourcevs. Junction Temperature5.25.45.65.86.06.2−50−250255075100125150V F B (o p e n ), F E E D B A C K O P E N C I R C U I T V O L T A G E (V )T J , JUNCTION TEMPERATURE (°C)Figure 23. Feedback Open Circuit Voltage vs.Junction Temperature14.7514.9515.1515.3515.5515.75−50−250255075100125150T J , JUNCTION TEMPERATURE (°C)V C C (o n ), S T A R T U P T H R E S H O L D (V )Figure 24. Startup Threshold vs. JunctionTemperature9.59.79.910.110.310.5−50−250255075100125150Figure 25. Minimum Operating Voltage vs.Junction TemperatureV C C (o f f ), M I N I M U M O P E R A T I N G V O L T A G E (V )T J , JUNCTION TEMPERATURE (°C)Figure 26. Inhibit Threshold Voltage vs.Junction Temperature6507007508008509009501000−50−25T J , JUNCTION TEMPERATURE (°C)V i n h i b i t , I N H I B I T T H R E S H O L D V O L T A G E (V )250270290310330350−50−250255075100125150I i n h i b i t , I N H I B I T B I A S C U R R E N T (m A )T J , JUNCTION TEMPERATURE (°C)Figure 27. Inhibit Bias Current vs. JunctionTemperature22.022.523.023.524.024.525.0V s t a r t u p (m i n ), M I N I M U M S T A R T U P V O L T A G E (V )T J , JUNCTION TEMPERATURE (°C)Figure 28. Minimum Startup Voltage vs.Junction Temperature5.05.25.45.65.86.0−50−250255075100125150T J , JUNCTION TEMPERATURE (°C)s t a r t Figure 29. Startup Current vs. JunctionTemperature1015202530−50−250255075100125150Figure 30. Off −State Leakage Current vs.Junction Temperature T J , JUNCTION TEMPERATURE (°C)I H V (o f f ), O F F −S T A T E L E A K A G E C U R R E N T (m A )650675700725750775800825850−50−250255075100125150T J , JUNCTION TEMPERATURE (°C)Figure 31. Supply Current Device Disabled (Overload) vs. Junction TemperatureI C C 1, S U P P L Y C U R R E N T D E V I C E D I S A B L E D (m A )5.755.956.156.356.556.75−50−25255075100125150T J , JUNCTION TEMPERATURE (°C)I C C 2, S U P P L Y C U R R E N T D E V I C E S W I T C H I N G (m A )Figure 32. Supply Current Device Switchingvs. Junction Temperature100120140160180200−50−250255075100125150Figure 33. Overload Timer vs. JunctionTemperatureT J , JUNCTION TEMPERATURE (°C)t O V L D , O V E R L O A D T I M E R (m s )4.54.74.95.15.35.5−50−250255075100125150T J , JUNCTION TEMPERATURE (°C)V O V L D , O V E R L O A D D E T E C T T H R E S H O L D (V )Figure 34. Overload Detect Threshold vs.Junction Temperature400420440460480500−50−250255075100125150Figure 35. Brown −Out Detect Threshold vs.Junction TemperatureT J , JUNCTION TEMPERATURE (°C)V B O (l o w ), B R O W N −O U T D E T E C T T H R E S H O L D (m V )600610620630640650−50−250255075100125150V B O (h i g h ), B R O W N −O U T E X I T T H R E S H O L D (m V )Figure 36. Brown −Out Exit Threshold vs.Junction Temperature T J , JUNCTION TEMPERATURE (°C)160165170175180−50−250255075100125150T J , JUNCTION TEMPERATURE (°C)V B O (H Y S ), B R O W N −O U T H Y S T E R E S I S (m V )Figure 37. Brown −Out Hysteresis vs. JunctionTemperature9009209409609801000−50−25255075100125150V L A T C H (l o w ), L A T C H P U L L −D O W N V O L T A G E T H R E S H O L D (m V )Figure 38. Latch Pull −Down Voltage Thresholdvs. Junction TemperatureT J , JUNCTION TEMPERATURE (°C)−50−2502550751001251506.56.76.97.17.37.5T J , JUNCTION TEMPERATURE (°C)V L A T C H (l o w _H Y S ), L A T C H P U L L −U P T H R E S H O L D (V )Figure 39. Latch Pull −Up Threshold vs.Junction Temperature6.56.76.97.17.37.5−50−250255075100125150Figure 40. Latch Pull −Up Voltage Thresholdvs. Junction TemperatureT J , JUNCTION TEMPERATURE (°C)V L A T C H (l h i g h ), L A T C H P U L L −U P V O L T A G E T H R E S H O L D (V )505254565860−50−250255075100125150T J , JUNCTION TEMPERATURE (°C)V L A T C H (d e l a y ), L A T C H P R O P A G A T I O N D E L A Y (m s )Figure 41. Latch Propagation Delay vs.Junction Temperature505152535455−50−250255075100125150Figure 42. Latch Clamp Current vs. JunctionTemperatureT J , JUNCTION TEMPERATURE (°C)I L A T C H (c l a m p ), L A T C H C L A M P C U R R E N T (m A )3.03.13.23.33.43.5−50−25255075100125150T J , JUNCTION TEMPERATURE (°C)V L A T C H (c l a m p ), L A T C H C L A M P V O L T A G E (V )Figure 43. Latch Clamp Voltage vs. JunctionTemperature 9092949698100−50−250255075100125150T J , JUNCTION TEMPERATURE (°C)V L A T C H (s h d n ), L A T C H −O F F C U R R E N T S H U T D O W N (m A )Figure 44. Latch −Off Current Shutdown vs.Junction TemperatureDETAILED DEVICE DESCRIPTIONIntroductionThe NCL30001 is a highly integrated controller combining PFC and isolated step down power conversion in a single stage, resulting in a lower cost and reduced part count solution. This controller is ideal for LED Lighting applications with power requirements between 40 W and 150 W with an output voltage greater than 12 V . The single stage is based on the flyback converter and it is designed to operate in CCM mode.Power Factor Correction (PFC) IntroductionPower factor correction shapes the input current of off −line power supplies to maximize the real power available from the mains. Ideally, the electrical appliance should present a load that emulates a pure resistor, in which case the reactive power drawn by the device is zero. Inherent in this scenario is the freedom from input current harmonics.The current is a perfect replica of the input voltage (usually a sine wave) and is exactly in phase with it. In this case the current drawn from the mains is at a minimum for the real power required to perform the needed work, and this minimizes losses and costs associated not only with the distribution of the power, but also with the generation of the power and the capital equipment involved in the process.The freedom from harmonics also minimizes interference with other devices being powered from the same source.Another reason to employ PFC in many of today’s power supplies is to comply with regulatory requirements. Today,lighting equipment in Europe must comply with IEC61000−3−2 Class C. This requirement applies to most lighting applications with input power of 25 W or greater,and it specifies the maximum amplitude of line −frequency harmonics up to and including the 39th harmonic. Moreover power factor requirements for commercial lighting is included within the ENERGY STAR ® Solid State Lighting Luminaire standard regardless of the applications power level.Typical Power Supply with PFCA typical power supply consists of a boost PFC preregulator creating an intermediate X 400 V bus and an isolated dc −dc converter producing the desired output voltage as shown in Figure 45. This architecture has two power stages.Figure 45. Typical Two Stage Power ConverterRectifier &FilterPFC PreregulatorDC −DC Converter with isolationAC Input V outA two stage architecture allows optimization of each individual power stage. It is commonly used because of designer familiarity and a vast range of availablecomponents. But, because it processes the power twice, the search is always on for a more compact and power efficient solution.The NCL30001 controller offers the convenience of shrinking the front −end converter (PFC preregulator) and the dc −dc converter into a single power processing stage as shown in Figure 46.Figure 46. Single Stage Power ConverterRectifier &FilterNCL30001 Based Single −Stage Flyback ConverterAC InputV outThis approach significantly reduces the component count.The NCL30001 based solution requires only one each of MOSFET, magnetic element, output rectifier (low voltage)and output capacitor (low voltage). In contrast, the 2−stage solution requires two or more of the above −listed components. Elimination of certain high −voltage components (e.g. high voltage capacitor and high voltage PFC diode) has significant impact on the system design. The resultant cost savings and reliability improvement are often worth the effort of designing a new converter.Single PFC StageWhile the single stage offers certain benefits, it is important to recognize that it is not a recommended solution for all requirements. The following three limitations apply to the single stage approach:•The output voltage ripple will have a 2x line frequency component (120 Hz for North American applications)that can not be eliminated easily. The cause of this ripple is the elimination of the energy storage element that is typically the boost output capacitor in the2−stage solution. The only way to reduce the ripple is to increase the output filter capacitance. The required value of capacitance is inversely proportional to the output voltage. Normally the presence of this ripple is not a issue for most LED lighting applications.•The hold −up time will not be as good as the 2−stage approach – again due to the lack of an intermediate energy storage element.•In a single stage converter, one FET processes all the power – that is both a benefit and a limitation as the stress on that main MOSFET is relatively higher.Similarly, the magnetic component (flybacktransformer/inductor) can not be optimized as well as in the 2−stage solution. As a result, potentially higher leakage inductance induces higher voltage spikes (like the one shown in Figure 47) on the MOSFET drain.This may require a MOSFET with a higher voltagerating compared to similar dc −input flybackapplications.Figure 47. Typical Drain Voltage Waveform of aFlyback Main SwitchThere are two methods to clamp the voltage spike on the main switch, a resistor −capacitor −diode (RCD) clamp or a transient voltage suppressor (TVS).RCD V outTVS V outFigure 49. TVS ClampBoth methods result in dissipation of the leakage energy in the clamping circuits – the dissipation is proportional to LI 2 where L is the leakage inductance of the transformer and I is the peak of the switch current at turn −off. An RCD snubber is simple and has the lowest cost, but constantly dissipates power. A TVS provides good voltage clamping ata slightly higher cost and dissipates power only when the drain voltage exceeds the voltage rating of the TVS.Other features found in the NCL30001 include a high voltage startup circuit, voltage feedforward, brown out detector, internal overload timer, latch input and a high accuracy multiplier.NCL30001 PFC LoopThe NCL30001 incorporates a modified version of average current mode control used for achieving the unity power factor. The PFC section includes a variable reference generator, a low frequency voltage regulation error amplifier (AC error AMP), ramp compensation (Ramp Comp) and current shaping network. These blocks are shown in the lower portion of the bock diagram (Figure 45).The inputs to the reference generator include feedback signal (FB), scaled AC input signal (AC_IN) and feedforward input (V FF ). The output of the reference generator is a rectified version of the input sine −wave scaled by the FB and V FF values. The reference amplitude is proportional to the FB and inversely proportional to the square of the V FF . This, for higher load levels and/or lower input voltage, the signal would be higher.The function of the AC error amp is to force the average current output of the current sense amplifier to match the reference generator output. The output of the AC error amplifier is compensated to prevent response to fast events.This output (V error ) is fed into the PWM comparator through a reference buffer. The PWM comparator sums the V error and the instantaneous current and compares it to a 4.0 V threshold to provide the desired duty cycle control. Ramp compensation is also added to the input signal to allow CCM operation above 50% duty cycle.High Voltage Startup CircuitThe NCL30001 internal high voltage startup circuit eliminates the need for external startup components and provides a faster startup time compared to an external startup resistor. The startup circuit consists of a constant current source that supplies current from the HV pin to the supply capacitor on the V CC pin (C CC ). The startup current (I start ) is typically 5.5 mA.The DRV driver is enabled and the startup current source is disabled once the V CC voltage reaches V CC(on), typically 15.4 V . The controller is then biased by the V CC capacitor.The drivers are disabled if V CC decays to its minimum operating threshold (V CC(off)) typically 10.2 V . Upon reaching V CC(off) the gate driver is disabled. The V CC capacitor should be sized such V CC is kept above V CC(off)while the auxiliary voltage is building up. Otherwise, the system will not start.The controller operates in double hiccup mode while in overload or V CC(off). A double hiccup fault disables the drivers, sets the controller in a low current mode and allows V CC to discharge to V CC(off). This cycle is repeated twice to minimize power dissipation in external components during。

IC datasheet pdf-MX25L1005C pdf,datasheet

MX25L1005C DATASHEET1M-BIT [x 1] CMOS SERIAL FLASH FEATURESGENERAL• Serial Peripheral Interface compatible -- Mode 0 and Mode 3• 1,048,576 x 1 bit structure• 32 Equal Sectors with 4K byte each- Any Sector can be erased individually• 2 Equal Blocks with 64K byte each- Any Block can be erased individually• Single Power Supply Operation- 2.7 to 3.6 volt for read, erase, and program operations• Latch-up protected to 100mA from -1V to Vcc +1VPERFORMANCE• High Performance- Fast access time: 85MHz serial clock- Fast program time: 1.4ms(typ.) and 5ms(max.)/page (256-byte per page)- Fast erase time: 60ms(typ.)/sector (4K-byte per sector) ; 1s(typ.) and 2s(max.)/block (64K-byte per block)• Low Power Consumption- Low active read current: 12mA(max.) at 85MHz and 4mA(max.) at 33MHz- Low active programming current: 15mA (max.)- Low active erase current: 15mA (max.)- Low standby current: 10uA (max.)• Minimum 100,000 erase/program cycles• 20 years data retentionSOFTWARE FEATURES• I nput Data Format- 1-byte Command code• Block Lock protection- The BP0~BP1 status bit defines the size of the area to be software protected against Program and Erase instructions.• A uto Erase and Auto Program Algorithm- Automatically erases and verifies data at selected sector- Automatically programs and verifies data at selected page by an internal algorithm that automatically times the program pulse widths (Any page to be programed should have page in the erased state first)• Status Register Feature• Electronic Identification- JEDEC 2-byte Device ID- RES command, 1-byte Device IDHARDWARE FEATURES• S CLK Input- Serial clock input• SI Input- Serial Data Input• SO Output- Serial Data Output• WP# pin- Hardware write protection• HOLD# pin- pause the chip without diselecting the chip• PACKAGE- 8-pin SOP (150mil)- 8-land USON (2x3x0.6mm)- All Pb-free devices are RoHS CompliantGENERAL DESCRIPTIONMX25L1005C is a CMOS 1,048,576 bit serial Flash memory, which is configured as 131,072 x 8 internally.The MX25L1005C feature a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus. The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Serial access to the device is enabled by CS# input.The MX25L1005C provide sequential read operation on whole chip.After program/erase command is issued, auto program/ erase algorithms which program/ erase and verify the speci-fied page or sector/block locations will be executed. Program command is executed on page (256 bytes) basis, and erase command is executes on chip or sector(4K-bytes) or block(64K-bytes).To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read command can be issued to detect completion status of a program or erase operation via WIP bit.When the device is not in operation and CS# is high, it is put in standby mode and draws less than 10uA DC cur-rent.The MX25L1005C utilize Macronix's proprietary memory cell, which reliably stores memory contents even after 100,000 program and erase cycles.PIN CONFIGURATIONSPIN DESCRIPTION8-PIN SOP (150mil)8-LAND USON (2x3mm)CS#SO WP#GNDVCC HOLD#SCLK SICS#SO WP#GNDVCC HOLD#SCLK SISYMBOL DESCRIPTION CS#Chip SelectSI Serial Data Input SO Serial Data Output SCLK Clock InputHOLD#Hold, to pause the device without deselecting the device VCC + 3.3V Power Supply GNDGroundDATA PROTECTIONThe MX25L1005C is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transition. During power up the device automatically resets the state machine in the standby mode. In addition, with its control register architecture, alteration of the memory con-tents only occurs after successful completion of specific command sequences. The device also incorporates sev-eral features to prevent inadvertent write cycles resulting from VCC power-up and power-down transition or system noise.• Valid command length checking: The command length will be checked whether it is at byte base and completed on byte boundary.• Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before other command to change data. The WEL bit will return to reset stage under following situation:- Power-up- Write Disable (WRDI) command completion- Write Status Register (WRSR) command completion- Page Program (PP) command completion- Sector Erase (SE) command completion- Block Erase (BE) command completion- Chip Erase (CE) command completion• Software Protection Mode (SPM): by using BP0-BP1 bits to set the part of Flash protected from data change.• Hardware Protection Mode (HPM): by using WP# going low to protect the BP0-BP1 bits and SRWD bit from data change.• Deep Power Down Mode: By entering deep power down mode, the flash device also is under protected from writing all commands except Release from deep power down mode command (RDP) and Read Electronic Sig-nature command (RES).Table 1. Protected Area SizesHOLD FEATUREHOLD# pin signal goes low to hold any serial communications with the device. The HOLD feature will not stop the operation of write status register, programming, or erasing in progress.The operation of HOLD requires Chip Select(CS#) keeping low and starts on falling edge of HOLD# pin signal while Serial Clock (SCLK) signal is being low (if Serial Clock signal is not being low, HOLD operation will not start until Serial Clock signal being low). The HOLD condition ends on the rising edge of HOLD# pin signal while Se-rial Clock(SCLK) signal is being low( if Serial Clock signal is not being low, HOLD operation will not end until Serial Clock being low), see Figure 1.Figure 1. Hold Condition OperationThe Serial Data Output (SO) is high impedance, both Serial Data Input (SI) and Serial Clock (SCLK) are don't care during the HOLD operation. If Chip Select (CS#) drives high during HOLD operation, it will reset the internal logic of the device. To re-start communication with chip, the HOLD# must be at high and CS# must be at low.Status bitProtect level 1Mb BP1 BP00 0 0 (none) None 0 1 1 (1 block) Block 1 1 0 2 (2 blocks) All 113 (All)AllTable 2. COMMAND DEFINITION(1) ADD=00H will output the manufacturer's ID first and ADD=01H will output device ID first.(2) It is not allowed to adopt any other code which is not in the above command definition table.Command (byte)WREN (write enable)WRDI (write disable)RDID (read identification)RDSR (read status register)WRSR (write status register)READ (read data)FAST READ(fast readdata)SE (sectorerase)1st byte 06 (hex)04 (hex)9F (hex)05 (hex)01 (hex)03 (hex)0B (hex)20 (hex)2nd byte AD1 AD1AD13rd byte AD2 AD2AD24th byte AD3 AD3AD35th byte xAction sets the (WEL) write enable latch bit resets the (WEL) write enable latch bit outputs JEDEC ID: 1-byte Manufacturer ID & 2-byte Device IDto read out the values of the status register to write new values of the status registern bytes read out until CS# goes high n bytes read out until CS# goes high to erase the selected sectorCommand(byte)BE (block erase)CE (chip erase)PP (page program)DP (Deep power down)RDP (Releasefrom deeppower down)RES (read electronic ID)REMS (readelectronicmanufacturer &device ID)1st byte D8 (hex)60 or C7 (hex)02 (hex)B9 (hex)AB (hex)AB (hex)90 (hex)2nd byte AD1 AD1 x x 3rd byte AD2 AD2 x x 4th byteAD3 AD3x ADD (1)Actionto erase the selected block to erase whole chip to program the selected pageenters deeppower down moderelease from deep power down mode to read out 1-byte Device ID output the Manufacturer ID & Device IDTable 3. Memory OrganizationBlock Sector Address Range13101F000h01FFFFh ::: 16010000h010FFFh01500F000h00FFFFh ::: 3003000h003FFFh 2002000h002FFFh 1001000h001FFFh 0000000h000FFFhDEVICE OPERATION1. Before a command is issued, status register should be checked to ensure device is ready for the intended op-eration.2. When incorrect command is inputted to this LSI, this LSI becomes standby mode and keeps the standby mode until next CS# falling edge. In standby mode, SO pin of this LSI should be High-Z.3. When correct command is inputted to this LSI, this LSI becomes active mode and keeps the active mode until next CS# rising edge.4. Input data is latched on the rising edge of Serial Clock(SCLK) and data shifts out on the falling edge of SCLK. The difference of Serial mode 0 and mode 3 is shown as Figure 2.5. For the following instructions: RDID, RDSR, READ, FAST_READ, RES and REMS the shifted-in instruction se-quence is followed by a data-out sequence. After any bit of data being shifted out, the CS# can be high. For the following instructions: WREN, WRDI, WRSR, SE, BE, CE, PP , RDP and DP the CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.6. During the progress of Write Status Register, Program, Erase operation, to access the memory array is neglect-ed and not affect the current operation of Write Status Register, Program, Erase.Figure 2. Serial Modes SupportedNote:CPOL indicates clock polarity of Serial master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which Serial mode is supported.SCLKMSBCPHA shift inshift outSI 01CPOL(Serial mode 0)(Serial mode 3)1SO SCLKMSBCOMMAND DESCRIPTION(1) Write Enable (WREN)The Write Enable (WREN) instruction is for setting Write Enable Latch (WEL) bit. For those instructions like PP, SE, BE, CE, and WRSR, which are intended to change the device content, should be set every time after the WREN in-struction setting the WEL bit.The sequence of issuing WREN instruction is: CS# goes low→ sending WREN instruction code→ CS# goes high. (see Figure 11)(2) Write Disable (WRDI)The Write Disable (WRDI) instruction is for resetting Write Enable Latch (WEL) bit.The sequence of issuing WRDI instruction is: CS# goes low→ sending WRDI instruction code→ CS# goes high. (see Figure 12)The WEL bit is reset by following situations:- Power-up- Write Disable (WRDI) instruction completion- Write Status Register (WRSR) instruction completion- Page Program (PP) instruction completion- Sector Erase (SE) instruction completion- Block Erase (BE) instruction completion- Chip Erase (CE) instruction completion(3) Read Identification (RDID)The RDID instruction is for reading the manufacturer ID of 1-byte and followed by Device ID of 2-byte. The MXIC Manufacturer ID is C2(hex), the memory type ID is 20(hex) as the first-byte device ID, and the individual device ID of second-byte ID is as followings: 11(hex) for MX25L1005C.The sequence of issuing RDID instruction is: CS# goes low→ sending RDID instruction code → 24-bits ID data out on SO→ to end RDID operation can use CS# to high at any time during data out. (see Figure. 13)While Program/Erase operation is in progress, it will not decode the RDID instruction, so there's no effect on the cy-cle of program/erase operation which is currently in progress. When CS# goes high, the device is at standby stage.(4) Read Status Register (RDSR)The RDSR instruction is for reading Status Register Bits. The Read Status Register can be read at any time (even in program/erase/write status register condition) and continuously. It is recommended to check the Write in Progress (WIP) bit before sending a new instruction when a program, erase, or write status register operation is in progress. The sequence of issuing RDSR instruction is: CS# goes low→ sending RDSR instruction code→ Status Register data out on SO (see Figure. 14)The definition of the status register bits is as below:WIP bit. The Write in Progress (WIP) bit, a volatile bit, indicates whether the device is busy in program/erase/write status register progress. When WIP bit sets to 1, which means the device is busy in program/erase/write status register progress. When WIP bit sets to 0, which means the device is not in progress of program/erase/write status register cycle.WEL bit. The Write Enable Latch (WEL) bit, a volatile bit, indicates whether the device is set to internal write enable latch. When WEL bit sets to 1, which means the internal write enable latch is set, the device can accept program/erase/write status register instruction. When WEL bit sets to 0, which means no internal write enable latch; the de-vice will not accept program/erase/write status register instruction.BP1, BP0 bits. The Block Protect (BP1, BP0) bits, non-volatile bits, indicate the protected area(as defined in table 1) of the device to against the program/erase instruction without hardware protection mode being set. To write the Block Protect (BP1, BP0) bits requires the Write Status Register (WRSR) instruction to be executed. Those bits define the protected area of the memory to against Page Program (PP), Sector Erase (SE), Block Erase (BE) and Chip Erase(CE) instructions (only if all Block Protect bits set to 0, the CE instruction can be executed)SRWD bit. The Status Register Write Disable (SRWD) bit, non-volatile bit, is operated together with Write Protec-tion (WP#) pin for providing hardware protection mode. The hardware protection mode requires SRWD sets to 1 and WP# pin signal is low stage. In the hardware protection mode, the Write Status Register (WRSR) instruction is no longer accepted for execution and the SRWD bit and Block Protect bits (BP1, BP0) are read only.Note: 1. See the table "Protected Area Sizes".2. The endurance cycles of protect bits are 100,000 cycles; however, the tW time out spec of protect bits isrelaxed as tW = N x 15ms (N is a multiple of 10,000 cycles, ex. N = 2 for 20,000 cycles) after 10,000 cycles on those bits.bit7bit6bit5bit4bit3bit2bit1bit0SRWD (status register write protect)00)BP1 (level of protected block)BP0 (level of protected block)WEL (write enable latch)WIP (write inprogress bit)1=status register write disable(note 1)(note 1)1=write enable 0=not write enable 1=write operation 0=not in write operation(5) Write Status Register (WRSR)The WRSR instruction is for changing the values of Status Register Bits. Before sending WRSR instruction, the Write Enable (WREN) instruction must be decoded and executed to set the Write Enable Latch (WEL) bit in ad-vance. The WRSR instruction can change the value of Block Protect (BP1, BP0) bits to define the protected area of memory (as shown in table 1). The WRSR also can set or reset the Status Register Write Disable (SRWD) bit in accordance with Write Protection (WP#) pin signal. The WRSR instruction cannot be executed once the Hardware Protected Mode (HPM) is entered.The sequence of issuing WRSR instruction is: CS# goes low→ sending WRSR instruction code→ Status Register data on SI→ CS# goes high. (see Figure 15)The WRSR instruction has no effect on b6, b5, b4, b1, b0 of the status register.The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. The self-timed Write Status Register cycle time (tW) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Write Status Register cycle is in progress. The WIP sets 1 during the tW timing, and sets 0 when Write Status Register Cycle is completed, and the Write Enable Latch (WEL) bit is reset.Table 4. Protection ModesNote:1. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown in Table 1.As the above table showing, the summary of the Software Protected Mode (SPM) and Hardware Protected Mode (HPM). Software Protected Mode (SPM):- When SRWD bit=0, no matter WP# is low or high, the WREN instruction may set the WEL bit and can changethe values of SRWD, BP1, BP0. The protected area, which is defined by BP1, BP0, is at software protected mode (SPM).- When SRWD bit=1 and WP# is high, the WREN instruction may set the WEL bit can change the values ofSRWD, BP1, BP0. The protected area, which is defined by BP1, BP0, is at software protected mode (SPM)Note: If SRWD bit=1 but WP# is low, it is impossible to write the Status Register even if the WEL bit has previously been set. It is rejected to write the Status Register and not be executed.ModeStatus register condition WP# and SRWD bit status Memory Software protectionmode(SPM)Status register can be written in (WEL bit is set to "1") andthe SRWD, BP0-BP1bits can be changed WP#=1 and SRWD bit=0, or WP#=0 and SRWD bit=0, or WP#=1 and SRWD=1The protected areacannotbe program or erase.Hardware protectionmode (HPM)The SRWD, BP0-BP1 of status register bits cannot bechangedWP#=0, SRWD bit=1The protected areacannotbe program or erase.Hardware Protected Mode (HPM):- When SRWD bit=1, and then WP# is low (or WP# is low before SRWD bit=1), it enters the hardware protected mode (HPM). The data of the protected area is protected by software protected mode by BP1, BP0 and hard-ware protected mode by the WP# to against data modification.Note: to exit the hardware protected mode requires WP# driving high once the hardware protected mode is entered. If the WP# pin is permanently connected to high, the hardware protected mode can never be entered; only can use software protected mode via BP1, BP0.(6) Read Data Bytes (READ)The read instruction is for reading data out. The address is latched on rising edge of SCLK, and data shifts out on the falling edge of SCLK at a maximum frequency fR. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single READ instruction. The address counter rolls over to 0 when the highest address has been reached.The sequence of issuing READ instruction is: CS# goes low→ sending READ instruction code→ 3-byte address on SI→data out on SO→ to end READ operation can use CS# to high at any time during data out. (see Figure. 16) (7) Read Data Bytes at Higher Speed (FAST_READ)The FAST_READ instruction is for quickly reading data out. The address is latched on rising edge of SCLK, and data of each bit shifts out on the falling edge of SCLK at a maximum frequency fC. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single FAST_READ instruction. The address counter rolls over to 0 when the highest address has been reached.The sequence of issuing FAST_READ instruction is: CS# goes low→ sending FAST_READ instruction code→3-byte address on SI→1-dummy byte address on SI→data out on SO→ to end FAST_READ operation can use CS# to high at any time during data out. (see Figure. 17)While Program/Erase/Write Status Register cycle is in progress, FAST_READ instruction is rejected without any im-pact on the Program/Erase/Write Status Register current cycle.(8) Sector Erase (SE)The Sector Erase (SE) instruction is for erasing the data of the chosen sector to be "1". A Write Enable (WREN) in-struction must execute to set the Write Enable Latch (WEL) bit before sending the Sector Erase (SE). Any address of the sector (see table 3) is a valid address for Sector Erase (SE) instruction. The CS# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed.Address bits [Am-A12] (Am is the most significant address) select the sector address.The sequence of issuing SE instruction is: CS# goes low→ sending SE instruction code→ 3-byte address on SI →CS# goes high. (see Figure 19)The self-timed Sector Erase Cycle time (tSE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1 during the tSE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the page is protected by BP1, BP0 bits, the Sector Erase (SE) instruction will not be executed on the page.(9) Block Erase (BE)The Block Erase (BE) instruction is for erasing the data of the chosen block to be "1". A Write Enable (WREN) in-struction must execute to set the Write Enable Latch (WEL) bit before sending the Block Erase (BE). Any address of the block (see table 3) is a valid address for Block Erase (BE) instruction. The CS# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed.The sequence of issuing BE instruction is: CS# goes low→ sending BE instruction code→ 3-byte address on SI → CS# goes high. (see Figure 20)The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1 during the tBE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the page is protected by BP1, BP0 bits, the Block Erase (BE) instruction will not be executed on the page.(10) Chip Erase (CE)The Chip Erase (CE) instruction is for erasing the data of the whole chip to be "1". A Write Enable (WREN) instruc-tion must execute to set the Write Enable Latch (WEL) bit before sending the Chip Erase (CE). Any address of the sector (see table 3) is a valid address for Chip Erase (CE) instruction. The CS# must go high exactly at the byte boundary( the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not ex-ecuted.The sequence of issuing CE instruction is: CS# goes low→sending CE instruction code→ CS# goes high. (see Fig-ure 20)The self-timed Chip Erase Cycle time (tCE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Chip Erase cycle is in progress. The WIP sets 1 during the tCE timing, and sets 0 when Chip Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the chip is protected by BP1, BP0 bits, the Chip Erase (CE) instruction will not be executed. It will be only executed when BP1, BP0 all set to "0".(11) Page Program (PP)The Page Program (PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Page Program (PP). If the eight least sig-nificant address bits (A7-A0) are not all 0, all transmitted data which goes beyond the end of the current page are programmed from the start address if the same page (from the address whose 8 least significant address bits (A7-A0) are all 0). The CS# must keep during the whole Page Program cycle. The CS# must go high exactly at the byte boundary( the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed. If more than 256 bytes are sent to the device, the data of the last 256-byte is programmed at the request page and previous data will be disregarded. If less than 256 bytes are sent to the device, the data is programmed at the request address of the page without effect on other address of the same page.The sequence of issuing PP instruction is: CS# goes low→ sending PP instruction code→ 3-byte address on SI→at least 1-byte on data on SI→CS# goes high. (see Figure 18)The self-timed Page Program Cycle time (tPP) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Page Program cycle is in progress. The WIP sets 1 during the tPP timing, and sets 0 when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the page is protected by BP1, BP0 bits, the Page Program (PP) instruction will not be executed.(12) Deep Power-down (DP)The Deep Power-down (DP) instruction is for setting the device on the minimizing the power consumption (to enter-ing the Deep Power-down mode), the standby current is reduced from ISB1 to ISB2). The Deep Power-down mode requires the Deep Power-down (DP) instruction to enter, during the Deep Power-down mode, the device is not ac-tive and all Write/Program/Erase instruction are ignored. When CS# goes high, it's only in standby mode not deep power-down mode. It's different from Standby mode.The sequence of issuing DP instruction is: CS# goes low→ sending DP instruction code→CS# goes high. (see Fig-ure 22)Once the DP instruction is set, all instruction will be ignored except the Release from Deep Power-down mode (RDP) and Read Electronic Signature (RES) instruction. (RES instruction to allow the ID been read out). When Power-down, the deep power-down mode automatically stops, and when power-up, the device automatically is in standby mode. For RDP instruction the CS# must go high exactly at the byte boundary (the latest eighth bit of instruction code been latched-in); otherwise, the instruction will not executed. As soon as Chip Select (CS#) goes high, a delay of tDP is required before entering the Deep Power-down mode and reducing the current to ISB2.(13) Release from Deep Power-down (RDP), Read Electronic Signature (RES)The Release from Deep Power-down (RDP) instruction is terminated by driving Chip Select (CS#) High. When Chip Select (CS#) is driven High, the device is put in the Stand-by Power mode. If the device was not previously in the Deep Power-down mode, the transition to the Stand-by Power mode is immediate. If the device was previously in the Deep Power-down mode, though, the transition to the Stand-by Power mode is delayed by tRES2, and Chip Select (CS#) must remain High for at least tRES2(max), as specified in Table 6. Once in the Stand-by Power mode, the device waits to be selected, so that it can receive, decode and execute instructions.RES instruction is for reading out the old style of 8-bit Electronic Signature, whose values are shown as table of ID Definitions. This is not the same as RDID instruction. It is not recommended to use for new design. For new deisng, please use RDID instruction. Even in Deep power-down mode, the RDP and RES are also allowed to be executed, only except the device is in progress of program/erase/write cycle; there's no effect on the current program/erase/ write cycle in progress.The sequence is shown as Figure 23,24.The RES instruction is ended by CS# goes high after the ID been read out at least once. The ID outputs repeat-edly if continuously send the additional clock cycles on SCLK while CS# is at low. If the device was not previously in Deep Power-down mode, the device transition to standby mode is immediate. If the device was previously in Deep Power-down mode, there's a delay of tRES2 to transit to standby mode, and CS# must remain to high at least tRES2(max). Once in the standby mode, the device waits to be selected, so it can be receive, decode, and execute instruction.The RDP instruction is for releasing from Deep Power Down Mode.。

IC datasheet pdf-LT3652HV PDF DATASHEET

13652hvfT YPICAL APPLICATIOND ESCRIPTION ChargerThe LT ®3652HV is a complete monolithic step-down bat-tery charger that operates over a 4.95V to 34V input range. The LT3652HV provides a constant-current/constant-voltage charge characteristic, with maximum charge current externally programmable up to 2A. The charger employs a 3.3V ﬂ oat voltage feedback reference, so any desired battery ﬂ oat voltage up to 18V can be programmed with a resistor divider.The LT3652HV employs an input voltage regulation loop, which reduces charge current if the input voltage falls below a programmed level, set with a resistor divider. When the LT3652HV is powered by a solar panel, the input regulation loop is used to maintain the panel at peak output power.The L T3652HV c an b e c onﬁ gured t o t erminate c harging w hen charge c urrent f alls b elow 1/10 o f t he p rogrammed m aximum (C/10). Once charging is terminated, the LT3652HV enters a low-current (85μA) standby mode. An auto-recharge feature starts a new charging cycle if the battery voltage falls 2.5% below the programmed ﬂ oat voltage. The LT3652HV also contains a programmable safety timer, used to terminate charging after a desired time is reached. This allows top-off charging at currents less than C/10.F EATURESA PPLICATIONS nInput Supply Voltage Regulation Loop for Peak Power T racking in (MPPT) Solar Applicationsn Wide Input Voltage Range: 4.95V to 34V (40V Abs Max)n Programmable Charge Rate Up to 2An User Selectable Termination: C/10 or On-Board Termination Timern Resistor Programmable Float Voltage Up to 18V Accommodates 4-Cell Li-Ion/Polymer , 5-Cell LiFePO 4, Lead-Acid Chemistriesn Parallelable for Higher Output Current n 1MHz Fixed Frequencyn 0.5% Float Voltage Reference Accuracy n 5% Charge Current Accuracy n 2.5% C/10 Detection Accuracyn Binary-Coded Open-Collector Status PinsnSolar Powered Applications n Remote Monitoring Stations n Portable Handheld Instruments n 12V to 24V Automotive SystemsnBattery Charging from Current Limited AdapterL , L T , L TC, L TM, Linear Technology and the Linear logo are registered trademarks and PowerPath is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners.V IN_REG Loop Servos Maximum Charge Current to Prevent AC Adapter Output from Drooping Lower Than 24V 5-Cell LiFePO 4 Charger (18V at 1.5A) with C/10 TerminationPowered by Inexpensive 24VDC/1A Unregulated Wall Adapter.SYSTEM LOADD3ADAPTER OUTPUT CURRENT (A)00.2A D A P T E R O U T P U T V O L T A G E (V )12151833302724210.61 1.23652 TA01b360.40.8 1.61.421.81A/24VDC Unregulated AdapterI vs V CharacteristicLT3652HV23652hvfP IN CONFIGURATIONA BSOLUTE MAXIMUM RATINGS Voltages:V IN ........................................................................40V V IN_REG , SHDN , CHRG , FAUL T ............V IN + 0.5V , 40V SW ........................................................................40V SW-V IN .................................................................4.5V BOOST ...................................................SW+10V , 50V BAT , SENSE .. (20V)(Note 1)ORDER INFORMATIONLEAD FREE FINISH TAPE AND REEL PART MARKING*PACKAGE DESCRIPTION TEMPERATURE RANGE LT3652HVEDD#PBF LT3652HVEDD#TRPBF LFRG 12-Lead Plastic DFN 3mm × 3mm –40°C to 125°C LT3652HVIDD#PBF LT3652HVIDD#TRPBF LFRG 12-Lead Plastic DFN 3mm × 3mm –40°C to 125°C LT3652HVEMSE#PBF LT3652HVEMSE#TRPBF 3652HV 12-Lead Plastic MSOP –40°C to 125°C LT3652HVIMSE#PBFLT3652HVIMSE#TRPBF3652HV12-Lead Plastic MSOP–40°C to 125°CConsult LTC Marketing for parts speciﬁ ed with wider operating temperature ranges. *The temperature grade is identiﬁ ed by a label on the shipping container.Consult LTC Marketing for information on non-standard lead based ﬁ nish parts.For more information on lead free part marking, go to: /leadfree/ For more information on tape and reel speciﬁ cations, go to: /tapeandreel/TOP VIEWDD PACKAGE12-LEAD (3mm × 3mm) PLASTIC DFN1211891045321SW BOOST SENSE BAT NTCV FBV IN V IN_REG SHDN CHRG FAUL T TIMER6713123456V IN V IN_REG SHDN CHRG FAUL T TIMER 121110987SW BOOST SENSE BAT NTC V FBTOP VIEW13MSE PACKAGE12-LEAD PLASTIC MSOPT JMAX = 125°C, θJA = 43°C/W , θJC = 3°C/WEXPOSED PAD (PIN 13) IS GND, MUST BE SOLDERED TO PCBT JMAX = 125°C, θJA = 43°C/W , θJC = 3°C/WEXPOSED PAD (PIN 13) IS GND, MUST BE SOLDERED TO PCBBAT-SENSE .........................................–0.5V to +0.5VNTC, TIMER, ........................................................2.5V V FB ..........................................................................5V Operating Junction Temperature Range(Note 2) .............................................–40°C to 125°C Storage Temperature Range ...................–65°C to 150°CLT3652HV33652hvfE LECTRICAL CHARACTERISTICSSYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITSV IN V IN Operating RangeV IN Start Voltage V BAT = 4.2 (Notes 3, 4)V BAT = 4.2 (Note 4)l l 4.957.534V V V IN(OVLO)OVLO Threshold OVLO Hysteresis V IN Rising l3435140V V V IN(UVLO)UVLO Threshold UVLO Hysteresis V IN Rising 4.60.24.95V V V FB(FL T)Float Voltage Reference (Note 6)l 3.2823.263.3 3.3183.34V V ΔV RECHARGE Recharge Reference Threshold Voltage Relative to V FB(FL T) (Note 6)82.5mV V FB(PRE)Reference Precondition Threshold V FB Rising (Note 6)2.3V V FB(PREHYST)Reference Precondition Threshold HysteresisVoltage Relative to V FB(PRE) (Note 6)70mVV IN_REG(TH)Input Regulation Reference V FB = 3V; V SENSE – V BAT = 50mV l 2.65 2.7 2.75V I IN_REG Input Regulation Reference Bias Current V IN_REG = V IN_REG(TH)l 35100nA I VINOperating Input Supply CurrentCC/CV Mode, I SW = 0Standby ModeShutdown (SHDN = 0)l 2.58515 3.5mA μA μA I BOOST BOOST Supply Current Switch On, I SW = 0,2.5 < V (BOOST – SW) < 8.520mA I BOOST/I SW BOOST Switch Drive I SW = 2A30mA/A V SW(ON)Switch-On Voltage Drop V IN – V SW , I SW = 2A350mV I SW(MAX)Switch Current Limit l 2.53A V SENSE(PRE)Precondition Sense Voltage V SENSE – V BAT ; V FB = 2V 15mVV SENSE(DC)Maximum Sense Voltage V SENSE – V BAT ; V FB = 3V (Note 7)l 95100105mV V SENSE(C/10)C/10 T rigger Sense Voltage V SENSE – V BAT , Falling l7.51012.5mV I BAT BAT Input Bias Current Charging Terminated 0.11μA I SENSE SENSE Input Bias Current Charging Terminated 0.11μA I VFB V FB Input Bias Current Charging Terminated 65nA I VFB V FB Input Bias Current CV Operation (Note 5)110nAV NTC(H)NTC Range Limit (High)V NTC Rising l 1.25 1.36 1.45V V NTC(L)NTC Range Limit (Low)V NTC Falling l 0.270.290.315V V NTC(HYST)NTC Threshold Hysteresis % of threshold 20%R NTC(DIS)NTC Disable Impedance Impedance to ground l 250500kΩI NTC NTC Bias Current V NTC = 0.8V l 47.55052.5μA V SHDN Shutdown Threshold Risingl 1.151.2 1.25V V SHDN (HYST)Shutdown Hysteresis 120mV I SHDN SHDN Input Bias Current –10nAV CHRG , V FAUL T Status Low Voltage 10mA Load l 0.4V I TIMER Charge/Discharge Current 25μA V TIMER(DIS)Timer Disable Thresholdl0.10.25VThe l denotes the speciﬁ cations which apply over the full operating junction temperature range, otherwise speciﬁ cations are at T A = 25°C. V IN = 20V, Boost – SW = 4V, SHDN = 2V, V FB = 3.3V, C TIMER= 0.68μF.LT3652HV43652hvfSYMBOL PARAMETERCONDITIONS MIN TYP MAX UNITSt TIMERFull Charge Cycle Timeout 3hr Precondition Timeout 22.5minTimer Accuracyl–1010%f O Operating Frequency 1MHz DCDuty Cycle RangeContinuous Operationl 1590%E LECTRICAL CHARACTERISTICS The l denotes the speciﬁ cations which apply over the full operating junction temperature range, otherwise speciﬁ cations are at T A = 25°C. V IN = 20V, Boost – SW = 4V, SHDN = 2V, V FB = 3.3V, C TIMER = 0.68μF.Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime.Note 2: The L T3652HV is tested under pulsed load conditions such that T J ≅ T A . The L T3652HVE is guaranteed to meet performance speciﬁ cations from 0°C to 85°C junction temperature. Speciﬁ cations over the –40°C to 125°C operating junction temperature range are assured by design, characterization, and correlation with statistical process controls. The L T3652HVI speciﬁ cations are guaranteed over the full –40°C to 125°C operating junction temperature range. High junction temperatures degrade operating lifetimes; operating lifetime is derated for junction temperatures greater than 125°C.Note 3: V IN minimum voltages below the start threshold are only supported if (V BOOST -V SW ) > 2V .Note 4: This parameter is valid for programmed output battery ﬂ oat voltages ≤ 4.2V . V IN operating range minimum is 0.75V above the programmed output battery ﬂ oat voltage (V BAT(FL T) + 0.75V). V IN Start Voltage is 3.3V above the programmed output battery ﬂ oat voltage (V BAT(FL T) + 3.3V).Note 5: Output battery ﬂ oat voltage (V BAT(FL T)) programming resistor divider equivalent resistance = 250k compensates for input bias current. Note 6: All V FB voltages measured through 250k series resistance.Note 7: V SENSE(DC) is reduced by thermal foldback as junction temperature approaches 125°C.LT3652HV53652hvfT YPICAL PERFORMANCE CHARACTERISTICS Switch Forward Drop (V IN – V SW ) vs TemperatureCC/CV Charging; SENSE Pin Bias Current vs V SENSEC/10 Threshold (V SENSE –V BAT ) vs TemperatureV FB Reference Voltage vs TemperatureV IN Standby Mode Current vs TemperatureSwitch Drive (I SW /I BOOST ) vs Switch CurrentT J = 25°C, unless otherwise noted.TEMPERATURE (°C)–50V F B (F L T )3.2963.2983.3003.302050753652 G01a3.304–2525100125TEMPERATURE (°C)–5065I V I N C U R R E N T (μA )70758010090050753652 G029585–2525100SWITCH CURRENT (A)I S W /I B O O S T18243036 1.6126021273315930.40.8 1.20.2 1.80.6 1.0 1.4 2.03652 G03TEMPERATURE (°C)–50320V S W (O N ) (m V )340360380480420050753652 G04440460400–2525100125V SENSE (V)–350I S E N S E (μA )–250–150–5010050–300–200–10003652 G05TEMPERATURE (°C)–508V S E N S E (C /10) (m V )9101112050753652 G06–2525100125TEMPERATURE (°C)–50V I N _R E G (T H ) (V )2.6802.6852.6902.7152.7102.7052.7002.695050753652 G012.720–2525100125V IN_REG Thresholdvs Temperature: I CHG at 50%LT3652HV63652hvfTYPICAL PERFORMANCE CHARACTERISTICSMaximum Charge Current (V SENSE –V BAT ) vs TemperatureThermal Foldback – Maximum Charge Current (V SENSE –V BAT ) vs TemperatureCC/CV Charging; BAT Pin Bias Current vs V BATT A = 25°C, unless otherwise noted.TEMPERATURE (°C)–5099.0V S E N S E (D C ) (m V )99.299.699.8100.0101.0100.4050753652 G0799.4100.6100.8100.2–2525100125TEMPERATURE (°C)V S E N S E (D C )(m V )4080206010012045658510512535135255575951153652 G08V BAT (V)–0.4I B A T (m A )0.00.40.82.21.62.01.2–0.20.20.61.01.81.43652 G09V IN_REG (V)2.65V S E N S E (D C ) (m V )208060402.67 2.692.73652 G101002.66 2.682.722.71 2.732.742.75V BAT(FL T) (V)020I R F B (μA )861012183652 G114264810121614TIME (MINUTES)EFFICIENCY (%)C H A R G E C U R R E N T (A ); P OW E R L O S S (W )0.52.02.51.51.040801003652 G123.0354575655595852060140120160180200Maximum Charge Current(V SENSE –V BAT ) vs V IN_REG VoltageV FLOAT Programming Resistor Current vs V FLOAT for 2-Resistor NetworkCharge Current, Efﬁ ciency, and Power Loss vs Time(I CHG(MAX) = 2A; V FLOAT = 8.2V)Charger Efﬁ ciency vs Battery Voltage (I CHG= 2A)V BAT (V)70E F F I C I E N C Y (%)7680828486887472789057911134141536810123652 G13LT3652HV73652hvfP IN FUNCTIONS V IN (Pin 1): Charger Input Supply. V IN operating range is 4.95V to 34V. V IN must be 3.3V greater than the pro-grammed output battery ﬂ oat voltage (V BAT(FLT)) for reli-able start-up. (V IN – V BAT(FLT)) ≥ 0.75V is the minimum operating voltage, provided (V BOOST – V SW ) ≥ 2V. I VIN ~ 85μA after charge termination. This pin is typically con-nected to the cathode of a blocking diode.V IN_REG (Pin 2): Input Voltage Regulation Reference. Maxi-mum charge current is reduced when this pin is below 2.7V. Connecting a resistor divider from V IN to this pin enables programming of minimum operational V IN voltage. This is typically used to program the peak power voltage for a solar panel. The LT3652HV servos the maximum charge current required to maintain the programmed operational V IN voltage, through maintaining the voltage on V IN_REG at or above 2.7V. If the voltage regulation feature is not used, connect the pin to V IN .SHDN (Pin 3): Precision Threshold Shutdown Pin. The enable threshold is 1.2V (rising), with 120mV of input hysteresis. When in shutdown mode, all charging functions are disabled. The precision threshold allows use of the SHDN pin to incorporate UVLO functions. If the SHDN pin is pulled below 0.4V, the IC enters a low current shutdown mode where V IN current is reduced to 15μA. Typical SHDN pin input bias current is 10nA. If the shutdown function is not desired, connect the pin to V IN .CHRG (Pin 4): Open-Collector Charger Status Output; typically pulled up through a resistor to a reference volt-age. This status pin can be pulled up to voltages as high as V IN when disabled, and can sink currents up to 10mA when enabled. During a battery charging cycle, if required charge current is greater than 1/10 of the programmed maximum current (C/10), CHRG is pulled low. A tem-perature fault also causes this pin to be pulled low. After C/10 charge termination or, if the internal timer is used for termination and charge current is less than C/10, the CHRG pin remains high-impedance.FAULT (Pin 5): Open-Collector Charger Status Output; typically pulled up through a resistor to a reference volt-age. This status pin can be pulled up to voltages as high as V IN when disabled, and can sink currents up to 10mA when enabled. This pin indicates fault conditions during abattery charging cycle. A temperature fault causes this pin to be pulled low. If the internal timer is used for termina-tion, a bad battery fault also causes this pin to be pulled low. If no fault conditions exist, the FAULT pin remains high-impedance.TIMER (Pin 6): End-Of-Cycle Timer Programming Pin. If a timer-based charge termination is desired, connect a capacitor from this pin to ground. Full charge end-of-cycle time (in hours) is programmed with this capacitor following the equation: t EOC = C TIMER • 4.4 • 106A bad battery fault is generated if the battery does not achieve the precondition threshold voltage within one-eighth of t EOC , or: t PRE = C TIMER • 5.5 • 105A 0.68μF capacitor is typically used, which generates a timer EOC at three hours, and a precondition limit time of 22.5 minutes. If a timer-based termination is not desired, the timer function is disabled by connecting the TIMER pin to ground. With the timer function disabled, charging terminates when the charge current drops below a C/10 threshold, or I CHG(MAX)/10V FB (Pin 7): Battery Float Voltage Feedback Reference. The charge function operates to achieve a ﬁ nal ﬂ oat voltage of 3.3V on this pin. Output battery ﬂ oat voltage (V BAT(FLT)) is programmed using a resistor divider. V BAT(FLT) can be programmed up to 18V.The auto-restart feature initiates a new charging cyclewhen the voltage at the V FB pin falls 2.5% below the ﬂoat voltage reference.The V FB pin input bias current is 110nA. Using a resistor divider with an equivalent input resistance at the V FB pin of 250k compensates for input bias current error.Required resistor values to program desired V BAT(FLT) follow the equations:R1 = (V BAT(FLT) • 2.5 • 105)/3.3 (Ω) R2 = (R1 • 2.5 • 105)/(R1 - (2.5 • 105))(Ω)R1 is connected from BAT to V FB , and R2 is connected from V FBto ground.LT3652HV 83652hvfNTC (Pin 8): Battery Temperature Monitor Pin. This pin is the input to the NTC (Negative Temperature Coefﬁ cient) thermistor temperature monitoring circuit. This function is enabled by connecting a 10kΩ, B = 3380 NTC thermistor from the NTC pin to ground. The pin sources 50μA, and monitors the voltage across the 10kΩ thermistor. When the voltage on this pin is above 1.36 (T < 0°C) or below 0.29V (T > 40°C), charging is disabled and the CHRG and FAULT pins are both pulled low. If internal timer termina-tion is being used, the timer is paused, suspending the charging cycle. Charging resumes when the voltage on NTC returns to within the 0.29V to 1.36V active region. There is approximately 5°C of temperature hysteresis associated with each of the temperature thresholds. The temperature monitoring function remains enabled while the thermistor resistance to ground is less than 250k, so if this function is not desired, leave the NTC pin unconnected.BAT (Pin 9): Charger Output Monitor Pin. Connect a 10μF decoupling capacitance (C BAT ) to ground. Depend-ing on application requirements, larger value decoupling capacitors may be required. The charge function operates to achieve the programmed output battery ﬂ oat voltage (V BAT(FLT)) at this pin. This pin is also the reference for the current sense voltage. Once a charge cycle is termi-nated, the input bias current of the BAT pin is reduced to < 0.1μA, to minimize battery discharge while the charger remains connected.SENSE (Pin 10): Charge Current Sense Pin. Connect the inductor sense resistor (R SENSE ) from the SENSE pin to the BAT pin. The voltage across this resistor sets the averagecharge current. The maximum charge current (I CHG(MAX)) corresponds to 100mV across the sense resistor. This resistor can be set to program maximum charge cur-rent as high as 2A. The sense resistor value follows the relation:R SENSE = 0.1/I CHG(MAX) (Ω)Once a charge cycle is terminated, the input bias current of the SENSE pin is reduced to < 0.1μA, to minimize battery discharge while the charger remains connected.BOOST (Pin 11): Bootstrapped Supply Rail for Switch D rive. This pin facilitates saturation of the switch transistor. Connect a 1μF or greater capacitor from the BOOST pin to the SW pin. Operating range of this pin is 0V to 8.5V, referenced to the SW pin. The voltage on the decoupling capacitor is refreshed through a rectifying diode, with the anode connected to either the battery output voltage or an external source, and the cathode connected to the BOOST pin.SW (Pin 12): Switch Output Pin. This pin is the output of the charger switch, and corresponds to the emitter of the switch transistor. When enabled, the switch shorts the SW pin to the V IN supply. The drive circuitry for this switch is bootstrapped above the V IN supply using the BOOST supply pin, allowing saturation of the switch for maximum efﬁ ciency. The effective on-resistance of the boosted switch is 0.175Ω.SGND (Pin 13): Ground Reference and Backside Exposed Lead Frame Thermal Connection. Solder the exposed lead frame to the PCB ground plane.P IN FUNCTIONSLT3652HV93652hvfB LOCK DIAGRAM+–LT3652HV103652hvfA PPLICATIONS INFORMATION OverviewL T3652HV is a complete monolithic, mid-power , multi-chemistry buck battery charger , addressing high input voltage applications with solutions that require a minimum of external components. The IC uses a 1MHz constant fre-quency, average-current mode step-down architecture.The L T3652HV incorporates a 2A switch that is driven by a bootstrapped supply to maximize efficiency during charging cycles. Wide input range allows operation to full charge from voltages as high as 34V . A precision threshold shutdown pin allows incorporation of UVLO functionality using a simple resistor divider . The IC can also be put into a low-current shutdown mode, in which the input supply bias is reduced to only 15μA.The L T3652HV employs an input voltage regulation loop, which reduces charge current if a monitored input voltage falls below a programmed level. When the L T3652HV is powered by a solar panel, the input regulation loop is used to maintain the panel at peak output power .The L T3652HV automatically enters a battery precondition mode if the sensed battery voltage is very low. In this mode, the charge current is reduced to 15% of the programmed maximum, as set by the inductor sense resistor , R SENSE . Once the battery voltage reaches 70% of the fully charged float voltage, the IC automatically increases maximum charge current to the full programmed value.The L T3652HV can use a charge-current based C/10 termination scheme, which ends a charge cycle when the battery charge current falls to one tenth of the pro-grammed maximum charge current. The L T3652HV also contains an internal charge cycle control timer , for timer-based termination. When using the internal timer , the IC combines C/10 detection with a programmable time constraint, during which the charging cycle can continue beyond the C/10 level to top-off a battery. The charge cycle terminates when a specific time elapses, typically 3 hours. When the timer-based scheme is used, the IC also supports bad battery detection, which triggers a system fault if a battery stays in precondition mode for more than one eighth of the total charge cycle time.Once charging is terminated, the L T3652HV automati-cally enters a low-current standby mode where supply bias currents are reduced to 85μA. The IC continues tomonitor the battery voltage while in standby, and if that voltage falls 2.5% from the full-charge float voltage, the L T3652HV engages an automatic charge cycle restart. The IC also automatically restarts a new charge cycle after a bad battery fault once the failed battery is removed and replaced with another battery.The L T3652HV contains provisions for a battery tem-perature monitoring circuit. This feature monitors battery temperature using a thermistor during the charging cycle. If the battery temperature moves outside a safe charg-ing range of 0°C to 40°C, the IC suspends charging and signals a fault condition until the temperature returns to the safe charging range.The L T3652HV contains two digital open-collector outputs, which provide charger status and signal fault conditions. These binary-coded pins signal battery charging, standby or shutdown modes, battery temperature faults, and bad battery faults.General Operation (See Block Diagram)The L T3652HV uses average current mode control loop architecture, such that the IC servos directly to average charge current. The L T3652HV senses charger output voltage through a resistor divider via the V FB pin. The difference between the voltage on this pin and an internal 3.3V voltage reference is integrated by the voltage error amplifier (V-EA). This amplifier generates an error volt-age on its output (I TH ), which corresponds to the average current sensed across the inductor current sense resistor , R SENSE , which is connected between the SENSE and BAT pins. The I TH voltage is then divided down by a factor of 10, and imposed on the input of the current error amplifier (C-EA). The difference between this imposed voltage and the current sense resistor voltage is integrated, with the resulting voltage (V C ) used as a threshold that is compared against an internally generated ramp. The output of this comparison controls the charger’s switch.The I TH error voltage corresponds linearly to average current sensed across the inductor current sense resistor , allowing maximum charge current control by limiting the effective voltage range of I TH . A clamp limits this voltage to 1V which, in turn, limits the current sense voltage to 100mV . This sets the maximum charge current, or the current delivered while the charger is operating in con-A PPLICATIONS INFORMATIONstant-current (CC) mode, which corresponds to 100mV across R SENSE. The I TH voltage is pulled down to reduce this maximum charge current should the voltage on the V IN_REG pin falls below 2.7V (V IN_REG(TH)) or the die tem-perature approaches 125°C.If the voltage on the V FB pin is below 2.3V (V FB(PRE)), the L T3652HV engages precondition mode. D uring the precondition interval, the charger continues to operate in constant-current mode, but the maximum charge current is reduced to 15% of the maximum programmed value as set by R SENSE.When the charger output voltage approaches the float volt-age, or the voltage on the V FB pin approaches 3.3V (V FB(FL T)), the charger transitions into constant-voltage (CV) mode and charge current is reduced from the maximum value. As this occurs, the I TH voltage falls from the limit clamp and servos to lower voltages. The IC monitors the I TH volt-age as it is reduced, and detection of C/10 charge current is achieved when I TH = 0.1V. If the charger is configured for C/10 termination, this threshold is used to terminate the charge cycle. Once the charge cycle is terminated, the CHRG status pin becomes high-impedance and the charger enters low-current standby mode.The L T3652HV contains an internal charge cycle timer that terminates a successful charge cycle after a programmed amount of time. This timer is typically programmed to achieve end-of-cycle (EOC) in 3 hours, but can be con-figured for any amount of time by setting an appropriate timing capacitor value (C TIMER). When timer termination is used, the charge cycle does not terminate when C/10 is achieved. Because the CHRG status pin responds to the C/10 current level, the IC will indicate a fully-charged battery status, but the charger continues to source low currents into the battery until the programmed EOC time has elapsed, at which time the charge cycle will terminate. At EOC when the charging cycle terminates, if the battery did not achieve at least 97.5% of the full float voltage, charging is deemed unsuccessful, the L T3652HV re-initiates, and charging continues for another full timer cycle.Use of the timer function also enables bad-battery detec-tion. This fault condition is achieved if the battery does not respond to preconditioning, such that the charger remains in (or enters) precondition mode after 1/8th of the programmed charge cycle time. A bad battery fault halts the charging cycle, the CHRG status pin goes high-impedance, and the FAUL T pin is pulled low.When the L T3652HV terminates a charging cycle, whether through C/10 detection or by reaching timer EOC, the average current mode analog loop remains active, but the internal float voltage reference is reduced by 2.5%. Because the voltage on a successfully charged battery is at the full float voltage, the voltage error amp detects an over-voltage condition and I TH is pulled low. When the voltage error amp output drops below 0.3V, the IC enters standby mode, where most of the internal circuitry is dis-abled, and the V IN bias current is reduced to 85μA. When the voltage on the V FB pin drops below the reduced float reference level, the output of the voltage error amp will climb, at which point the IC comes out of standby mode and a new charging cycle is initiated.V IN Input SupplyThe L T3652HV is biased through a reverse-current block-ing element from the charger input supply to the V IN pin. This supply provides large switched currents, so a high-quality, low ESR decoupling capacitor is recommended to minimize voltage glitches on V IN. The V IN decoupling capacitor (C VIN) absorbs all input switching ripple current in the charger, so it must have an adequate ripple current rating. RMS ripple current (I CVIN(RMS)) is:I CVIN(RMS)≅ I CHG(MAX) • (V BAT / V IN)•([V IN / V BAT] – 1)1/2,where I CHG(MAX) is the maximum average charge current (100mV/R SENSE). The above relation has a maximum at V IN = 2 • V BAT, where:I CVIN(RMS) = I CHG(MAX)/2.The simple worst-case of ½ • I CHG(MAX) is commonly used for design.。

GL823K Datasheet

GL823KUSB 2.0 SD Card Reader ControllerDatasheetRevision HistoryTable of ContentsCHAPTER 1GENERAL DESCRIPTION (6)CHAPTER 2FEATURES (7)CHAPTER 3PIN ASSIGMENT (8)3.1SSOP16 Pinout (8)3.2Pin Description (9)CHAPTER 4BLOCK DIAGRAM (10)4.1OCCS USB PHY (10)4.2SIE (10)4.3EPFIFO (10)4.4MCU (10)4.5MHE (11)4.6Regulator (11)4.7PMOS (11)CHAPTER 5ELECTRICAL CHARACTERISTICS (12)5.1Temperature Conditions (12)5.2Operating Conditions (12)5.3DC Characteristics (12)5.4Memory Card Clock Frequency (12)5.5Maximum Ratings (13)CHAPTER 6PACKAGE DIMENSION (14)CHAPTER 7ORDERING INFORMATION (15)List of FiguresFigure 3.1 – SSOP 16 Pinout Diagram (8)Figure 6.1 – SSOP 16 Pin Package (150 mil) (14)List of TablesTable 3.1 – Pin Description (9)Table 4.1 – Functional Block Diagram (10)Table 5.1 – Temperature Conditions (12)Table 5.2 – Operating Conditions (12)Table 5.3 – DC Characteristics (12)Table 5.4 – SD/MMC Card Clock Frequency (12)Table 5.5 – Maximum Ratings (13)Table 7.1 – Ordering Information (15)CHAPTER 1GENERAL DESCRIPTIONThe GL823K is a USB 2.0 Single-LUN card reader controller which can support SD/MMC Flash Memory Cards. It supports USB 2.0 high-speed transmission to Secure Digital TM(SD), SDHC, SDXC, miniSD TM, microSD TM(T-Flash), MultiMediaCard TM (MMC), RS MultiMediaCard TM (RS MMC), MMCmicro , HS-MMC and MMCmobile. As a single chip solution for USB 2.0 flash card reader, the GL823K complies with Universal Serial Bus specification rev. 2.0, USB Storage Class Specification ver.1.0, and each flash card interface specification.The GL823K integrates a high speed 8051 microprocessor and a high efficiency hardware engine for the best data transfer performance between USB and flash card interfaces. Its pin assignment design fits to card sockets to provide easier PCB layout. Inside the chip, it integrates 5V to 3.3V regulator, 3.3V to 1.8V regulator and power MOSFETs and it enables the function of on-chip clock source (OCCS) which means no external 12MHz XTAL is needed and that effectively reduces the total BOM cost.The GL823K implements USB disconnect function; it can be used for Mobile cable/ OTG reader/ PC card reader application.CHAPTER 2FEATURES●USB specification compliance-Comply with 480Mbps Universal Serial Bus specification rev. 2.0-Comply with USB Storage Class specification rev. 1.0-Support one device address and up to four endpoints: Control (0)/Bulk Read (1)/Bulk Write (2)/Interrupt (3) ●Integrated USB building blocks-USB2.0 transceiver macro (UTM), Serial Interface Engine (SIE), Build-in power-on reset (POR) and low-voltage detector (LVD)●Embedded 8051 micro-controller-Operate @ 60 MHz clock, 12 clocks per instruction cycle-Embedded mask ROM and internal SRAM●Secure Digital TM (SD) and MultiMediaCard TM (MMC)-Supports SD specification v1.0 / v1.1 / v2.0 / SDHC (Up to 32GB)-Compatible with SDXC (Up to 2TB)-Supports MMC specification v3.x / v4.0 / v4.1 / v4.2-Supports 1 / 4 bit data bus-Compliant with Secure Digital TM v5.0●Support boost mode for SD3.0 for better performance●Support non-SD Card Detect pin, non-MS Insertion/Removal pin design to save BOM cost●Support non-SD Write Protection pin design to save BOM cost●Support LED function to indicate power and access status●On chip clock source and no need of 12MHz Crystal Clock input●On-Chip 5V to 3.3V and 3.3V to 1.8V regulators●On-Chip power MOSFET for supplying flash media card power●Support USB disconnection by memory card unplug or manual switch for Mobile cable/ OTG reader/ PCcard reader application●Available in SSOP16 package (150 mil)CHAPTER 3 PIN ASSIGMENT3.1 SSOP16 Pinout38765214D 0D 2P M O S C M D V S S D 1D 3C L KFigure 3.1 – SSOP 16 Pinout Diagram3.2Pin DescriptionTable 3.1 – Pin DescriptionNotation:Type O OutputI InputB Bi-directionalpu internal pull-up when inputpd internal pull-down when inputP Power / GroundA AnalogCHAPTER 4BLOCK DIAGRAMTable 4.1 – Functional Block Diagram4.1OCCS USB PHYThe USB 2.0 Transceiver Macrocell is the analog circuitry that handles the low level USB protocol and signaling, and shifts the clock domain of the data from the USB 2.0 rate to one that is compatible with the general logic. On chip clock source and no need of 12MHz Crystal Clock input.4.2SIEThe Serial Interface Engine, which contains the USB PID and address recognition logic, and other sequencing and state machine logic to handle USB packets and transactions.4.3EPFIFOEndpoint FIFO includes Control FIFO (FIFO0) and Bulk In/Out FIFO●EP0 FIFO FIFO of control endpoint 0. It is 64-byte FIFO and used for endpoint 0 data transfer.●Interrupt FIFO 64-byte depth FIFO of endpoint 3 for status interrupt●Bulk FIFO It can be in the TX mode or RX mode:1. It contains ping-pong FIFO (512 bytes each bank) for transmit/receive data continuously.2. It can be directly accessed by micro-controller4.4MCU8051 micro-controller inside.●8051 Core Compliant with Intel 8051 high speed micro-controller●ROM FW code on ROM●SRAM Internal RAM area for MCU access4.5MHE●MIF Media Interface: SD/MMC●MCFIFO It can access by MCU for memory card short data packet.4.6Regulator●5V to 3.3V Band Gap Regulator for stable voltage supply for USB PHY, PMOS●3.3V to 1.8V For core logic and internal memory.4.7PMOSOn-Chip power MOSFETs for memory card powerCHAPTER 5ELECTRICAL CHARACTERISTICS 5.1Temperature ConditionsTable 5.1 – Temperature Conditions5.2Operating ConditionsTable 5.2 – Operating Conditions5.3DC CharacteristicsTable 5.3 – DC Characteristics5.4Memory Card Clock FrequencyTable 5.4 – SD/MMC Card Clock Frequency5.5Maximum RatingsTable 5.5 – Maximum RatingsCHAPTER 6PACKAGE DIMENSIONInternalNo.Lot CodeDateGL823KAAAAAAAAAAYWWXXXXVersionNo.Figure 6.1 – SSOP 16 Pin Package (150 mil)CHAPTER 7ORDERING INFORMATIONTable 7.1 – Ordering Information。

IC datasheet pdf-CAT3606 pdf,datasheet

CAT36066-Channel Low Noise Charge Pump White LED DriverDescriptionThe CAT3606 controls up to four LEDs for the main display and two LEDs for the sub-display in cellular phones. The device is capable of operating in either 1x (LDO) mode or 1.5x charge pump mode. All LED pin currents are regulated and tightly matched to achieve uniformity of brightness across the LCD backlight. An external resistor (R SET) sets the nominal output current.The device can deliver as much as 20 mA per channel during low voltage operation (3 V), and 30 mA per channel during nominal operation (3.3 V). A constant high-frequency switching scheme (1MHz) provides low noise and allows the use of very small value ceramic capacitors.A “zero” quiescent current mode can be achieved via the chip enable pin EN. The Main and Sub LEDs each have their own dedicated ON/OFF control pins ENM, ENS. Dimming can be achieved using either a DC voltage to control the R SET pin current, or by applying a PWM signal on the ENM and ENS pins.The device is available in a 16−pad TQFN package with a max height of 0.8 mm.Features•Drives up to 4 Main LEDs and 2 Sub LEDs•Separate Control for Main and Sub LEDs •Compatible with Supply V oltage of 3 V to 5.5 V•Power Efficiency up to 90%•Output Current up to 30 mA per LED•High−frequency Operation at 1 MHz•2 Modes of Operation 1x and 1.5x•White LED Detect Circuitry on All Channels •Shutdown Current less than 1 m A•Small Ceramic Capacitors•Soft Start and Current Limiting•Short Circuit Protection•16−pad TQFN Package, 0.8 mm Max Height•These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS CompliantApplications•Cell Phone Main and Sub−display Backlight•Navigation •PDAs •Digital CamerasTQFN−16HV4 SUFFIXCASE 510AEPIN CONNECTIONS (Note 1)G366MARKING DIAGRAMSDevice Package ShippingORDERING INFORMATIONCAT3606HV4−T2TQFN−16(Note 2)2,000/Tape & ReelG366 = CAT3606HV4−T2CDBB = CAT3606HV4−GT21.The “exposed pad” under the package must beconnected to the ground plane on the PCB.2.Matte−Tin Plated Finish (RoHS−compliant).3.NiPdAu Plated Finish (RoHS−compliant).LED5LED4LED3LED2LED1C2+C2−C1−LED6ENENMENSRSETVOUTVINC1+1(4 x 4 mm) (Top View)CDBBCAT3606HV4−GT2TQFN−16(Note 3)GNDFigure 1. Typical Application Circuitm FLi −OUT Table 1. PIN DESCRIPTIONPin #Name Function1LED6LED6 cathode terminal2EN Enable/shutdown input, active high3ENM Enable “main” input for LED1 to LED4, active low 4ENS Enable “sub” input for LED5 and LED6, active low5RSET The LED output current is set by the current sourced out of the RSET pin 6VOUT Charge pump output connected to the LED anodes 7VIN Supply voltage8C1+Bucket capacitor 1 terminal 9C1Bucket capacitor 1 terminal 10C2Bucket capacitor 2 terminal 11C2+Bucket capacitor 2 terminal 12LED1LED 1 cathode terminal 13LED2LED 2 cathode terminal 14LED3LED 3 cathode terminal 15LED4LED 4 cathode terminal 16LED5LED 5 cathode terminal PADGNDGround referenceTable 2. ABSOLUTE MAXIMUM RATINGSParameter Rating Unit VIN, VOUT, LEDx voltage−0.3 to 7.0V EN, ENM, ENS voltage−0.3 to VIN V RSET voltage−0.3 to VIN V RSET current±1mA Ambient Temperature Range−40 to +85_C Storage Temperature Range−65 to +160_C Lead Temperature300_C ESD Rating HBM (Human Body Model)2,000V ESD Rating MM (Machine Model) (Note 4)200V Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.4.Machine model is with 200 pF capacitor discharged directly into each pin.Table 3. RECOMMENDED OPERATING CONDITIONSParameter Range Unit VIN 3.0 to 5.5V Ambient Temperature Range−40 to +85_C Input/Output/Bucket Capacitors 1 ±20% Typical m FI LED per LED pin0 to 30mAI OUT Total Output Current0 to 150mA Table 4. ELECTRICAL OPERATING CHARACTERISTICS(Limits over recommended operating conditions unless specified otherwise. Typical values at T A = 25°C, V IN = 3.5 V, I RSET = 5 m A.) Symbol Parameter Conditions Min Typ Max UnitI Q Quiescent Current V EN= 0 V1x Mode, No Load1.5x Mode, No Load 0.10.32.6115m AmAmAV RSET RSET Regulated Voltage 1.17 1.2 1.23VI LED Programmed LED Current I RSET = 5 m AI RSET = 37 m AI RSET = 78 m A 2.415.030.0mAI LED LED Current Range with 6 LEDs 3.3 ≤ VIN ≤ 4.5 V3.0 ≤ VIN ≤4.5 V 3020mAI LED LED Current Range with 4 LEDs 3.3 ≤ VIN ≤ 4.5 V30mAI LED−ACC LED Current Accuracy0.5 mA ≤ I LED≤ 3 mA3 mA ≤ I LED≤ 30 mA ±15±5%I LED−DEV LED Channel Matching(I LED – I LEDAVG) / I LEDAVG±3%R OUT Output Resistance(Open Loop)1x Mode,1.5x Mode, I OUT = 100 mA1.46.52.510Wf OSC Charge Pump Frequency0.8 1.0 1.3MHz T DROPOUT1x to 1.5x Mode Transition Dropout Delay0.40.60.9ms I EN−CTR Input Leakage Current On Inputs EN, ENM, ENS1m AV EN−CTR High Detect ThresholdLow Detect Threshold On Inputs EN, ENM, ENS0.40.80.71.3VI SC Input Current Limit VOUT = GND304560mA I LIM Maximum Input Current VOUT > 1 V200400600mABlock DiagramFigure 2. CAT3606 Functional Block Diagramm FVBasic OperationAt power-up, the CA T3606 starts operation in 1x mode. If it is able to drive the programmed LED current, it continues in 1x mode. If the battery voltage drops to a level where the LED current cannot be met, the driver automatically switches into 1.5x mode, to boost the output voltage high enough to achieve the nominal LED current.The above sequence is reinitialized each and every time the chip is powered up or is taken out of shutdown mode (via EN pin). The use of the Main and Sub display enable pins (ENM or ENS) does not affect the mode of operation. LED Current SettingThe LED current is set by the external resistor R SET connected between the RSET pin and ground. Table 5 lists various LED currents and the associated R SET resistor value for standard 1% precision surface mount resistors.Table 5. RSET Resistor SelectionLED Current (mA)R SET (k W)1649228751021049.91532.42023.73015.4The enable lines ENM and ENS allow to turn On or Off a group of LEDs as shown in Table 6.Table 6. LED SelectionControl Lines LED Outputs EN ENM ENSMainLED1 − LED4SubLED5 −LED6 0X X––111––101ON−110−ON100ON ON NOTES:1 = logic high (or VIN)0 = logic low (or GND)– = LED output OFFX = don’t careThe unused LED channels can also be turned off by connecting the respective LED pins to VOUT. In which case, the corresponding LED driver is disabled and the typical LED sink current is only about 0.2 mA. When the following equation is true on any channel, the driver turns off the LED channel:VOUT*V LED v1V(LED channel OFF) Note: The CA T3606 is designed to drive LEDs with forward voltage greater than 1 V and is not compatible with resistive loads.Figure 3. Efficiency vs. Input Voltage(6 LEDs)Figure 4. Efficiency vs. Total LED Current(6 LEDs)INPUT VOLTAGE (V)TOTAL LED CURRENT (mA)405060708090100405060708090100Figure 5. LED Current vs. Input VoltageFigure 6. LED Current Change vs.TemperatureINPUT VOLTAGE (V)TEMPERATURE (°C)−−−0.51.5−−Figure 7. Ground Current vs. Input Voltage(1x Mode)Figure 8. Ground Current vs. Temperature(1x Mode)INPUT VOLTAGE (V)TEMPERATURE (°C)0.10.20.30.40.500.10.20.30.40.5E F F I C I E N C Y (%)E F F I C I E N C Y (%)L E D C U R R E N T C H A N G E (%)L E D C U R R E N T C H A N G E (%)G R O U N D C U R R E N T (m A )G R O U N D C U R R E N T (m A )01.0−−Figure 9. Ground Current vs. Input Voltage(1.5x Mode)Figure 10. Supply Current vs. Input VoltageINPUT VOLTAGE (V)INPUT VOLTAGE (V)134580120140Figure 11. Oscillator Frequency vs. InputVoltageFigure 12. Oscillator Frequency vs.TemperatureINPUT VOLTAGE (V)TEMPERATURE (°C)0.900.951.001.051.100.900.951.001.051.10Figure 13. Output Resistance vs. Input Voltage(1x Mode)Figure 14. Output Resistance vs. Input Voltage(1.5x Mode)INPUT VOLTAGE (V)INPUT VOLTAGE (V)1234246810G R O U N D C U R R E N T (m A )G R O U N D C U R R E N T (m A )C L O C K F R E Q U E N C Y (M H z )C L O C K F R E Q U E N C Y (M H z )O U T P U T R E S I S T A N C E (W )O U T P U T R E S I S T A N C E (W )2100Figure 15. Switching Waveforms in 1.5x Mode Figure 16. Operating Waveforms in 1x Mode400 nsec/div400 nsec/divCurrent Input 50mV/VIN 50mV/divVOUT Input 50mV/div VIN Figure 17. Power Up 6 LEDs at 15 mA,VIN = 3 V (1.5x Mode)Figure 18. Power Up 6 LEDs at 15 mA,VIN = 3.6 V (1x Mode)400 m sec/div400 m sec/div2V/divVOUT 2V/div EN 2V/divVOUT 100mA/divInput 2V/divEN Figure 19. LED Current vs. R SETFigure 20. Line Transient Responsein 1x ModeRSET (k W )200 m sec/div10,000100100.1101002V/div VOUT 5mA/div Input 1V/div3.6V to4.9VVinL E D C U R R E N T (m A )10mA/Input Current 100mA/divAC coupledCurrent 10mA/div AC coupledAC coupledVOUT 50mV/divdiv divCurrent Current 10001(V IN = 3.6 V, EN = V IN , ENM = ENS = GND, C IN = C OUT = 1 m F, T AMB = 25°C, unless otherwise specified.)Figure 21. Foldback Current Limiting OUTPUT CURRENT (mA)5004003002001000012345O U TP U T V O L T A G E (V )1x ModeFigure 22. RSET Pin Voltage vs. Temperature−50−2502550751001251.161.181.201.221.24R S E T P I N V O L T A G E (V )Figure 23. PWM Dimming at 1 kHz on ENM and ENS50mA/divCurrent Tot. LED 1V/divVOUT ENM & ENS5V/div200 m sec/divTEMPERATURE (°C)Recommended LayoutWhen the driver is in the 1.5x charge pump mode, the 1MHz switching frequency operation requires to minimize trace length and impedance to ground on all 4 capacitors. A ground plane should cover the area on the bottom side of the PCB opposite to the IC and the bypass capacitors.Capacitors Cin and Cout require short connection to ground which can be done with multiple vias as shown on Figure 24.A square copper area matches the QFN16 exposed pad (GND) and must be connected to the ground plane underneath. The use of multiple via will improve the heat dissipation.Figure 24. PCB LayoutPACKAGE DIMENSIONSTQFN16, 4x4CASE 510AE−01ISSUE AA3A1SIDE VIEWTOP VIEW BOTTOM VIEWDETAIL AFRONT VIEWNotes:(1) All dimensions are in millimeters.(2) Complies with JEDEC MO-220.SYMBOL MIN NOM MAXA0.700.750.80A10.000.020.05A30.20 REFb0.250.300.35D 3.90 4.00 4.10D2 2.00−−− 2.25E 4.00E2 2.00−−− 2.25e3.900.65 BSC4.10L0.45−−−0.65CAT3606Example of Ordering Information (Note 7)PrefixDevice #Suffix 5.All packages are RoHS −compliant (Lead −free, Halogen −free).6.The standard lead finish is NiPdAu.7.The device used in the above example is a CAT3606HV4−GT2 (TQFN, NiPdAu Plated Finish, Tape & Reel, 2,000/Reel).8.For Matte −Tin package option, please contact your nearest ON Semiconductor Sales office.9.For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.PUBLICATION ORDERING INFORMATION。

IC datasheet pdf-NCP5603 pdf,datasheet

MAXIMUM RATINGS
Rating Power Supply Voltage Power Supply Current Digital Input Pins Digital Input Pins Output Voltage ESD Capability (Note 3) Human Body Model Machine Model DFN10, 3x3 Package Power Dissipation @ Tamb = +85°C Thermal Resistance, Junction-to-Air (RqJA) Operating Ambient Temperature Range Operating Junction Temperature Range Maximum Junction Temperature Storage Temperature Range Latchup Current Maximum Rating Moisture Sensitivity Level (MSL) Symbol Vbat Ibat Vin Iin Vout VESD 2.5 200 PDS RqJA TA TJ TJmax Tstg 580 68.5 -40 to +85 -40 to +125 +150 -65 to +150 100 mA per JEDEC standard, JESD78 1 per IPC/JEDEC standard, J-STD-020A kV V mW °C/W °C °C °C °C Value 7.0 800 -0.5 V < Vbat < Vbat +0.5 V < 6.0 V "5.0 5.5 Unit V mA V mA V

IC datasheet pdf-DM13A pdf,16-bit Constant Current LED Driver

OUT11 OUT10 OUT9 OUT8 OUT7 OUT6 OUT5 OUT4
25 26 27 28 29 30 31 32
24
1
23
2
22
3
21
QFN32
4
20
5
19
(bottom view)
6
18
7
17
8
16 15 14 13 12 11 10 9
GND GND VDD VDD GND GND GND GND
MIN. 3.3
1.0
⎯
5 ⎯ ⎯ 0.8VDD 0.0 ⎯ 15 15 10 10 10 10
Rth(j-a)
50.0 (PDIP24 )
79.2 (SOP24 )
90.2 (SSOP24 )
Operating Temperature
Top
-40 ~ 85
Storage Temperature
Tstg
-55 ~ 150
UNIT V V mA V
MHz mA
W
°C/W
°C °C
Recommended Operating Condition
Issue Date : 2007/05/21
File Name : SP-DM13A-PRE.001.doc
Total Pages : 23
16-bit Constant Current LED Driver
新竹市科學園區展業一路 9 號 7 樓之 1
SILICON TOUCH TECHNOLOGY INC.
Page 1
點晶科技股份有限公司 SILICON TOUCH TECHNOLOGY INC.

IC datasheet pdf-TLV5604,pdf(2.7-V to 5.5-V 10-Bit 3-uS Quadruple Digital-to-Analog Converters w_Pow

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
SLAS176B – DECEMBER 1997 – REVISED JULY 2002
AVAILABLE OPTIONS PACKAGE TA 0°C to 70°C – 40°C to 85°C SOIC (D) TLV5604CD TLV5604ID TSSOP (PW) TLV5604CPW TLV5604IPW
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SPI and QSPI are trademarks of Motorola, Inc. Microwire is a trademark of National Semiconductor Corporation.
Four 10-Bit D/A Converters Programmable Settling Time of 3 µs or 9 µs Typ TMS320, (Q)SPI, and Microwire Compatible Serial Interface Internal Power-On Reset Low Power Consumption: 5.5 mW, Slow Mode – 5-V Supply 3.3 mW, Slow Mode – 3-V Supply Reference Input Buffers Voltage Output Range . . . 2 × the Reference Input Voltage Monotonic Over Temperature Dual 2.7-V to 5.5-V Supply (Separate Digital and Analog Supplies)

IC datasheet pdf-CD54AC245,CD74AC245,CD54ACT245,CD74ACT245,pdf(Octal-Bus Transceiver,Three-State, No

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
FAST™ is a Trademark of Fairchild Semiconductor.
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA DC Output Source or Sink Current per Output Pin, IO
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
Operating Conditions
Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC (Note 4)
AC Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5V to 5.5V ACT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Slew Rate, dt/dv AC Types, 1.5V to 3V . . . . . . . . . . . . . . . . . . . . . . . . . 50ns (Max) AC Types, 3.6V to 5.5V . . . . . . . . . . . . . . . . . . . . . . . . 20ns (Max) ACT Types, 4.5V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . 10ns (Max)

HIH6130-021-001;HIH6131-021-001;中文规格书,Datasheet资料

Thermal Hysteresis
Total Error Band should not be confused with “Accuracy”, which is actually a component of Total Error Band. Many competitors simply specify the accuracy of their device; however, the specification may exclude hysteresis and temperature effects, and may be calculated over a very narrow range, at only one point in the range, or at their absolute best accuracy level. It is then up to the customer to calibrate the device to make sure it has the accuracy needed for the life of the application. Honeywell’s industry-leading Total Error Band provides the following benefits to the customer: Eliminates individually testing and calibrating every sensor, which can increase their manufacturing time and process Supports system accuracy and warranty requirements Helps to optimize system uptime Provides excellent sensor interchangeability—the customer can remove one sensor from the tape, remove the next sensor from the tape, and there is no part-to-part variation in accuracy For more information about Total Error Band, please see the related Technical Note “Explanation of the Total Error Band Specification for Honeywell’s Digital Humidity/Temperature Sensors.”

IC datasheet pdf-MAXQ2010评估套件

BIT 3 COM3 1A 1H 2A 2H 3A 3H 4A 4H 5A 5H 6A 6H 7A 7H 8A 8H
BIT 2 COM2 1B 1G 2B 2G 3B 3G 4B 4G 5B 5G 6B 6G 7B 7G 8B 8G
BIT 1 COM1 1C 1N 2C 2N 3C 3N 4C 4N 5C 5N 6C 6N 7C 7N 8C 8N
QTY
DESCRIPTION 100nF ±10%, 10V ceramic capacitors (0805) Murata GRM219R71C104KA01D 10nF ±5%, 10V ceramic capacitors (0805) Murata GRM21BR72A103KA01L 22pF ±5%, 10V ceramic capacitors (0805) Murata GRM2195C2A220JZ01D 4.7μF ±10%, 10V ceramic capacitors (0805) Murata GRM219R61A475KE19D 10μF ±10%, 10V capacitors (0805) Murata GRM21BR61A106KE19L Empty capacitor footprint (0805) 1μF ±10%, 10V ceramic capacitors (0805) Murata GRM21BR71C105KA01L Green surface-mount LEDs Lumex SML-LX0805SUGC-TR Red surface-mount LED Lumex SML-LX0805SIC-TR
BIT 6 COM2 1F 1J 2F 2J 3F 3J 4F 4J 5F 5J 6F 6J 7F 7J 8F 8J

数字IC电源静噪和去耦应用手册

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C39C.pdf 10.11.29
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C39C.pdf 10.11.29
配电网（PDN） IC2 返回信号电流信号电流去耦电路电源电流供电电源IC 平滑电路噪声排放噪声进入 IC3 IC1 目标 IC 此图仅仅以集成电路的去耦电路操作为重点。噪声产生噪声接收 IC 接收 IC 去耦电路工作： (1) 抑制噪声 (2) 供应临时电流 (3) 形成信号返回通道
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IC datasheet pdf-TPA6100A2,pdf(50-mW Ultralow Voltage Stereo Headphone Audio Power Amplifier)

FEATURESO 1DD O 2DGK PACKAGE(TOP VIEW)O 1DD O 2D PACKAGE (TOP VIEW)DESCRIPTIONTYPICAL APPLICATION CIRCUITTPA6100A2DSLOS269B–JUNE 2000–REVISED SEPTEMBER 200450-mW ULTRALOW VOLTAGE STEREO HEADPHONE AUDIO POWER AMPLIFIER•50-mW Stereo Output•Low Supply Current ...0.75mA •Low Shutdown Current ...50nA•Pin Compatible With LM4881and TPA102(1)•Pop Reduction Circuitry •Internal Midrail Generation•Thermal and Short-Circuit Protection •Surface-Mount Packaging –MSOP and SOIC•1.6-V to 3.6-V Supply Voltage Range(1)The polarity of the SHUTDOWN pin is reversed.The TPA6100A2D is a stereo audio power amplifier packaged in either an 8-pin SOIC package or an 8-pin MSOP package capable of delivering 50mW of continuous RMS power per channel into 16-Ωloads.Amplifier gain is externally configured by a means of three resistors per input channel and does not require external compensation for settings of 1to 10.The TPA6100A2D is optimized for battery applications because of its low supply current,shutdown current,and THD+N.To obtain the low-supply voltage range,the TPA6100A2D biases BYPASS to V DD /4.A resistor with a resistance equal to R F must be added from the inputs to ground to allow the output to be biased at V DD /2.When driving a 16-Ωload with 45-mW output power from 3.3V,THD+N is 0.04%at 1kHz,and less than 0.2%across the audio band of 20Hz to 20kHz.For 28mW into 32-Ωloads,the THD+N is reduced to less than 0.03%at 1kHz,and is less than 0.2%across the audio band of 20Hz to 20kHz.Please be aware that an important notice concerning availability,standard warranty,and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.ABSOLUTE MAXIMUM RATINGSDISSIPATION RATING TABLERECOMMENDED OPERATING CONDITIONSTPA6100A2DSLOS269B–JUNE 2000–REVISED SEPTEMBER 2004These devices have limited built-in ESD protection.The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.AVAILABLE OPTIONSPACKAGED DEVICEMSOPT ASYMBOLIZATIONSMALL OUTLINE (D)MSOP(DGK)–40°C to 85°CTPA6100A2DTPA6100A2DGKAJLTerminal FunctionsTERMINALI/O DESCRIPTIONNAME NO.BYPASS 1I Tap to voltage divider for internal mid-supply bias supply.BYPASS is set at V DD /4.Connect to a 0.1-µF to 1-µF low-ESR capacitor for best performance.GND 2I GND is the ground connection.IN1-8I IN1-is the inverting input for channel 1.IN2-4I IN2-is the inverting input for channel 2.SHUTDOWN 3I Active-low input.When held low,the device is placed in a low supply current mode.V DD 6I V DD is the supply voltage terminal.V O 17O V O 1is the audio output for channel 1.V O 25OV O 2is the audio output for channel 2.over operating free-air temperature range (unless otherwise noted)(1)UNITV DD Supply voltage 4VV I Input voltage–0.3V to V DD +0.3V Continuous total power dissipation Internally limited T J Operating junction temperature range –40°C to 150°C T stg Storage temperature range–65°C to 150°CLead temperature 1,6mm (1/16inch)from case for 10seconds260°C(1)Stresses beyond thoselisted under "absolute maximum ratings”may cause permanent damage to thedevice.These are stress ratings only,and functional operation of the deviceat these or any other conditions beyond those indicated under "recommendedoperating conditions”is not implied.Exposure to absolute-maximum-ratedconditions for extended periods may affect devicereliability.T A ≤25°C DERATING FACTOR T A =70°C T A =85°C PACKAGEPOWER RATINGABOVE T A =25°CPOWER RATINGPOWER RATINGD 710mW 5.68mW/°C 454mW 369mW DGK469mW3.75mW/°C300mW244mWMINMAX UNIT V DD Supply voltage 1.6 3.6V T A Operating free-air temperature –4085°C V IH High-level input voltage SHUTDOWN 0.6x V DDVV ILLow-level input voltageSHUTDOWN0.25x V DDDC ELECTRICAL CHARACTERISTICS AC OPERATING CHARACTERISTICS AC OPERATING CHARACTERISTICSTPA6100A2D SLOS269B–JUNE2000–REVISED SEPTEMBER2004at TA =25°C,VDD=3.6V(Unless otherwise noted)PARAMETER TEST CONDITIONS MIN TYP MAX UNITV OO Output offset voltage A V=2V/V540mV PSRR Power supply rejection ratio V DD=3.0V to3.6V72dB I DD Supply current SHUTDOWN=3.6V0.75 2.0mA I DD(SD)Supply current in SHUTDOWN mode SHUTDOWN=0V50250nA |I IH|High-level input current(SHUTDOWN)V DD=3.6V,V I=V DD1µA |I IL|Low-level input current(SHUTDOWN)V DD=3.6V,V I=0V1µA Z I Input impedance(IN1-,IN2-)>1MΩV DD =3.3V,TA=25°C,RL=16ΩPARAMETER TEST CONDITIONS MIN TYP MAX UNITP O Output power(each channel)THD≤0.1%,f=1kHz50mW THD+N Total harmonic distortion+noise P O=45mW,20Hz–20kHz0.2%B OM Maximum output power BW G=1,THD<0.5%>20kHz k SVR Supply ripple rejection f=1kHz52dB SNR Signal-to-noise ratio P O=50mW90dBV n Noise output voltage(no noise-weighting filter)28µV(rms)V DD =3.3V,TA=25°C,RL=32ΩPARAMETER TEST CONDITIONS MIN TYP MAX UNITP O Output power(each channel)THD≤0.1%,f=1kHz35mW THD+N Total harmonic distortion+noise P O=30mW,20Hz–20kHz0.2%B OM Maximum output power BW G=1,THD<0.2%>20kHz k SVR Supply ripple rejection f=1kHz52dB SNR Signal-to-noise ratio P O=35mW91dBV n Noise output voltage(no noise-weighting filter)28µV(rms)DC ELECTRICAL CHARACTERISTICSAC OPERATING CHARACTERISTICSAC OPERATING CHARACTERISTICSTPA6100A2DSLOS269B–JUNE 2000–REVISED SEPTEMBER 2004at T A =25°C,V DD =1.6V (Unless otherwise noted)PARAMETERTEST CONDITIONSMINTYP MAX UNIT V OO Output offset voltage A V =2V/V540mV PSRR Power supply rejection ratio V DD =1.5V to 1.7V 80dB I DD Supply currentSHUTDOWN =1.6V 1.2 1.5mA I DD(SD)Supply current in SHUTDOWN mode SHUTDOWN =0V 50250nA |I IH |High-level input current (SHUTDOWN)V DD =1.6V,V I =V DD 1µA |I IL |Low-level input current (SHUTDOWN)V DD =1.6V,V I =0V1µA Z IInput impedance (IN1-,IN2-)>1M ΩV DD =1.6V,T A =25°C,R L =16ΩPARAMETERTEST CONDITIONS MINTYP MAXUNIT P O Output power (each channel)THD ≤0.1%,f =1kHz 9.5mWTHD+N Total harmonic distortion +noise P O =9.5mW,20Hz–20kHz 0.4%B OM Maximum output power BW G =0dB,THD <0.4%>20kHz k SVR Supply ripple rejection f =1kHz 53dB SNR Signal-to-noise ratioP O =9.5mW86dB V nNoise output voltage (no noise-weighting filter)18µV(rms)V DD =1.6V,T A =25°C,R L =32ΩPARAMETERTEST CONDITIONS MINTYP MAXUNIT P O Output power (each channel)THD ≤0.1%,f =1kHz 7.1mWTHD+N Total harmonic distortion +noise P O =6.5mW,20Hz–20kHz 0.3%B OM Maximum output power BW G =0dB,THD <0.3%>20kHz k SVR Supply ripple rejection f =1kHz 53dB SNR Signal-to-noise ratioP O =7.1mW88dB V nNoise output voltage (no noise-weighting filter)18µV(rms)APPLICATION INFORMATIONGAIN SETTING RESISTORS,R F ,R I,and RGain +*ǒR F R IǓor Gain (dB)+20logǒR F R IǓ(1)Effective Impedance +R F R IR F )R I(2)f c +12p R F C F (3)INPUT CAPACITOR,C If c +12p R I C I (4)C I +12p R I f c(5)TPA6100A2DSLOS269B–JUNE 2000–REVISED SEPTEMBER 2004The voltage gain for the TPA6100A2D is set by resistors R F and R I according to Equation 1.Given that the TPA6100A2D is an MOS amplifier,the input impedance is high.Consequently,input leakage currents are not generally a concern,although noise in the circuit increases as the value of R F increases.In addition,a certain range of R F values is required for proper start-up operation of the amplifier.Taken together,it is recommended that the effective impedance seen by the inverting node of the amplifier be set between 5k Ωand 20k Ω.The effective impedance is calculated in Equation 2.As an example,consider an input resistance of 20k Ωand a feedback resistor of 20k Ω.The gain of the amplifier would be –1and the effective impedance at the inverting terminal would be 10k Ω,which is within the recommended range.For high-performance applications,metal film resistors are recommended because they tend to have lower noise levels than carbon resistors.For values of R F above 50k Ω,the amplifier tends to become unstable due to a pole formed from R F and the inherent input capacitance of the MOS input structure.For this reason,a small compensation capacitor of approximately 5pF should be placed in parallel with R F .In effect,this creates a low-pass filter network with the cutoff frequency defined in Equation 3.For example,if R F is 100k Ωand C F is 5pF,then f c is 318kHz,which is well outside the audio range.For maximum signal swing and output power at low supply voltages like 1.6V to 3.3V,BYPASS is biased to V DD /4.However,to allow the output to be biased at V DD /2,a resistor,R,equal to R F must be placed from the negative input to ground.In the typical application,an input capacitor,C I ,is required to allow the amplifier to bias the input signal to the proper dc level for optimum operation.In this case,C I and R I form a high-pass filter with the corner frequency determined in Equation 4.The value of C I is important to consider,as it directly affects the bass (low-frequency)performance of the circuit.Consider the example where R I is 20k Ωand the specification calls for a flat bass response down to 20Hz.Equation 4is reconfigured as Equation 5.In this example,C I is 0.4µF,so one would likely choose a value in the range of 0.47µF to 1µF.A further consideration for this capacitor is the leakage path from the input source through the input network (R I ,C I )and the feedback resistor (R F )to the load.This leakage current creates a dc offset voltage at the input to the amplifier that reduces useful headroom,especially in high-gain applications (>10).For this reason a low-leakage tantalum or ceramic capacitor is the best choice.When polarized capacitors are used,the positive side of the capacitor should face the amplifier input in most applications,as the dc level there is held at V DD /4,which is likely higher than the source dc level.It is important to confirm the capacitor polarity in the application.POWER SUPPLY DECOUPLING,C SMIDRAIL BYPASS CAPACITOR,C B1ǒC B 55k ΩǓv 1ǒC I R I Ǔ(6)OUTPUT COUPLING CAPACITOR,C Cf c +12p R L C C (7)TPA6100A2DSLOS269B–JUNE 2000–REVISED SEPTEMBER 2004APPLICATION INFORMATION (continued)The TPA6100A2D is a high-performance CMOS audio amplifier that requires adequate power supply decoupling to ensure that the output total harmonic distortion (THD)is as low as possible.Power supply decoupling also prevents oscillations for long lead lengths between the amplifier and the speaker.The optimum decoupling is achieved by using two capacitors of different types that target different types of noise on the power supply leads.For higher frequency transients,spikes,or digital hash on the line,a good low equivalent-series-resistance (ESR)ceramic capacitor,typically 0.1µF,placed as close as possible to the device V DD lead,works best.For filtering lower frequency noise signals,a larger aluminum electrolytic capacitor of 10µF or greater placed near the power amplifier is recommended.The midrail bypass capacitor (C B )serves several important functions.During start-up,C B determines the rate at which the amplifier starts up.This helps to push the start-up pop noise into the subaudible range (so low it can not be heard).The second function is to reduce noise produced by the power supply caused by coupling into the output drive signal.This noise is from the midrail generation circuit internal to the amplifier.The capacitor is fed from a 55-k Ωsource inside the amplifier.To keep the start-up pop as low as possible,the relationship shown in Equation 6should be maintained.As an example,consider a circuit where C B is 1µF,C I is 1µF,and R I is 20k Ω.Inserting these values into Equation 6results in:18.18≤50which satisfies the rule.Bypass capacitor (C B )values of 0.47-µF to 1-µF ceramic or tantalum low-ESR capacitors are recommended for the best THD and noise performance.In the typical single-supply,single-ended (SE)configuration,an output coupling capacitor (C C )is required to block the dc bias at the output of the amplifier,thus preventing dc currents in the load.As with the input coupling capacitor,the output coupling capacitor and impedance of the load form a high-pass filter governed by Equation 7.The main disadvantage,from a performance standpoint,is that the typically small load impedances drive the low-frequency corner rge values of C C are required to pass low frequencies into the load.Consider the example where a C C of 68µF is chosen and loads vary from 32Ωto 47k Ω.Table 1summarizes the frequency response characteristics of each configuration.Table mon Load Impedances vs Low FrequencyOutput Characteristics in SE ModeR L C C LOWEST FREQUENCY32Ω68µF 73Hz 10,000Ω68µF 0.23Hz 47,000Ω68µF0.05HzAs Table 1indicates,headphone response is adequate and drive into line level inputs (a home stereo for example)is good.The output coupling capacitor required in single-supply,SE mode also places additional constraints on the selection of other components in the amplifier circuit.With the rules described earlier still valid,add the following relationship:1ǒCB 55kΩǓv1ǒCIR IǓƠ1R L C C(8)USING LOW-ESR CAPACITORS 3.3-V VERSUS1.6-V OPERATIONTPA6100A2D SLOS269B–JUNE2000–REVISED SEPTEMBER2004Low-ESR capacitors are recommended throughout this application.A real capacitor can be modeled simply as a resistor in series with an ideal capacitor.The voltage drop across this resistor minimizes the beneficial effects of the capacitor in the circuit.The lower the equivalent value of this resistance,the more the real capacitor behaves like an ideal capacitor.The TPA6100A2D was designed for operation over a supply range of1.6V to3.6V.There are no special considerations for1.6-V versus3.3-V operation as far as supply bypassing,gain setting,or stability.The most important consideration is that of output power.Each amplifier can produce a maxium output voltage swing within a few hundred millivolts of the rails with a10-kΩload.However,this voltage swing decreases as the load resistance decreases and the r DS(on)as the output stage transistors becomes more significant.For example,for a 32-Ωload,the maximum peak output voltage with V DD=1.6V is approximately0.7V with no clipping distortion. This reduced voltage swing effectively reduces the maximum undistorted output power.PACKAGING INFORMATIONOrderable Device Status (1)Package Type Package DrawingPins Package Qty Eco Plan (2)Lead/Ball Finish MSL Peak Temp (3)TPA6100A2D ACTIVE SOIC D 875Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM TPA6100A2DG4ACTIVE SOIC D 875Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM TPA6100A2DGK ACTIVE MSOP DGK 880Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM TPA6100A2DGKG4ACTIVE MSOP DGK 880Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM TPA6100A2DGKR ACTIVE MSOP DGK 82500Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM TPA6100A2DGKRG4ACTIVE MSOP DGK 82500Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM TPA6100A2DR ACTIVE SOIC D 82500Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM TPA6100A2DRG4ACTIVESOICD82500Green (RoHS &no Sb/Br)CU NIPDAULevel-1-260C-UNLIM(1)The marketing status values are defined as follows:ACTIVE:Product device recommended for new designs.LIFEBUY:TI has announced that the device will be discontinued,and a lifetime-buy period is in effect.NRND:Not recommended for new designs.Device is in production to support existing customers,but TI does not recommend using this part in a new design.PREVIEW:Device has been announced but is not in production.Samples may or may not be available.OBSOLETE:TI has discontinued the production of the device.(2)Eco Plan -The planned eco-friendly classification:Pb-Free (RoHS),Pb-Free (RoHS Exempt),or Green (RoHS &no Sb/Br)-please check /productcontent for the latest availability information and additional product content details.TBD:The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS):TI's terms "Lead-Free"or "Pb-Free"mean semiconductor products that are compatible with the current RoHS requirements for all 6substances,including the requirement that lead not exceed 0.1%by weight in homogeneous materials.Where designed to be soldered at high temperatures,TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1)lead-based flip-chip solder bumps used between the die and package,or 2)lead-based die adhesive used between the die and leadframe.The component is otherwiseconsidered Pb-Free (RoHS compatible)as defined above.Green (RoHS &no Sb/Br):TI defines "Green"to mean Pb-Free (RoHS compatible),and free of Bromine (Br)and Antimony (Sb)based flame retardants (Br or Sb do not exceed 0.1%by weight in homogeneous material)(3)MSL,Peak Temp.--The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications,and peak solder temperature.Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.TI bases its knowledge and belief on information provided by third parties,and makes no representation or warranty as to the accuracy of such information.Efforts are underway to better integrate information from third parties.TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary,and thus CAS numbers and other limited information may not be available for release.In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s)at issue in this document sold by TI to Customer on an annual basis.PACKAGE OPTION ADDENDUM21-Apr-2010TAPE AND REEL INFORMATION*All dimensions are nominalDevicePackage Type Package Drawing Pins SPQReel Diameter (mm)Reel Width W1(mm)A0(mm)B0(mm)K0(mm)P1(mm)W (mm)Pin1Quadrant TPA6100A2DGKR MSOP DGK 82500330.012.4 5.3 3.4 1.48.012.0Q1TPA6100A2DRSOICD82500330.012.46.45.22.18.012.0Q1*All dimensions are nominalDevice Package Type Package Drawing Pins SPQ Length(mm)Width(mm)Height(mm) TPA6100A2DGKR MSOP DGK82500358.0335.035.0TPA6100A2DR SOIC D8*******.0346.029.0IMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries(TI)reserve the right to make corrections,modifications,enhancements,improvements, and other changes to its products and services at any time and to discontinue any product or service without notice.Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty.Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty.Except where mandated by government requirements,testing of all parameters of each product is not necessarily performed.TI assumes no liability for applications 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IC datasheet pdf-TPA6203A1,pdf(1.25-W Mono Fully Differential Audio Power Amplifier)

RECOMMENDED OPERATING CONDITIONS
MIN Supply voltage, VDD High-level input voltage, VIH Low-level input voltage, VIL Common-mode input voltage, VIC Operating free-air temperature, TA Load impedance, ZL SHUTDOWN SHUTDOWN VDD = 2.5 V, 5.5 V, CMRR ≤ -60 dB 0.5 -40 6.4 8 2.5 2 0.8 VDD-0.8 85 TYP MAX 5.5 UNIT V V V V °C Ω
1.25-W MONO FULLY DIFFERENTIAL AUDIO POWER AMPLIFIER
1
FEATURES
APPLICATIONS
• Designed for Wireless or Cellular Handsets and PDAs
• 1.25 W Into 8 Ω From a 5-V Supply at THD = 1% (Typical) • Low Supply Current: 1.7 mA Typical • Shutdown Control < 10 µA • Only Five External Components – Improved PSRR (90 dB) and Wide Supply Voltage (2.5 V to 5.5 V) for Direct Battery Operation – Fully Differential Design Reduces RF Rectification – Improved CMRR Eliminates Two Input Coupling Capacitors – C(BYPASS) Is Optional Due to Fully Differential Design and High PSRR • Avaliable in a 2 mm x 2 mm MicroStar Junior ™ BGA Package (GQV, ZQV) • Available in 3 mm x 3 mm QFN Package (DRB) • Available in an 8-Pin PowerPAD™ MSOP (DGN)

IC datasheet pdf-TAS5705,pdf(20-W stereo Digital Audio Power Amplifier)

TAS5705................................................................................................................................................SLOS549A–JUNE2008–REVISED SEPTEMBER2009 20-W STEREO DIGITAL AUDIO POWER AMPLIFIER WITH EQ AND DRCCheck for Samples:TAS5705FEATURES Sample Rates•Audio Input/Output–Thermal and Short-Circuit Protection –20-W Into an8-ΩLoad From an18-V Supply•Benefits–Wide Power-Supply Range From(8V to–EQ:Speaker Equalization Improves Audio 23V)Performance–Efficient Class-D Operation Eliminates–DRC:Dynamic Range Compression.Need for Heat Sinks Enables Power Limiting,SpeakerProtection,Easy Listening,Night-Mode –Requires Only Two Power-Supply RailsListening–Two Serial Audio Inputs(Four Audio–Autobank Switching:Preload Coefficients Channels)for Different Sample Rates.No Need to –Supports32-kHz–192-kHz Sample RatesWrite Any Coefficients to the Part When (LJ/RJ/I2S)Sample Rate Changes.–Headphone PWM Outputs–Autodetect:Automatically Detects –Subwoofer PWM Outputs Sample-Rate Changes.No Need for •Audio/PWM Processing External Microprocessor Intervention –Independent Channel Volume Controls With24-dB to–100-dB Range DESCRIPTION–Soft Mute(50%Duty Cycle)The TAS5705is a20-W,efficient,digital audio poweramplifier for driving stereo bridge-tied speakers.Two –Programmable Dynamic Range Controlserial data inputs allow processing of up to four –16Adaptable Biquads for Speaker EQdiscrete audio channels and seamless integration to –Seven Biquads for Left and Right most digital audio processors and MPEG decoders.Channels The device accepts a wide range of input data andclock rates.A fully programmable data path allows –Two Biquads for Subwoofer Channelthese channels to be routed to the internal speaker –Adaptive Coefficients for DRC Filtersdrivers or output via the line-level subwoofer or –Programmable Input and Output Mixers headphone PWM outputs.–DC Blocking FiltersThe TAS5705is a slave-only device receiving clocks –Loudness Compensation for Subwoofer from external sources.The TAS5705operates at a384-kHz switching rate for32-,48-,96-,and192-kHz –Automatic Sample Rate Detection anddata and352.8-kHz switching rate for44.1-,88.2-Coefficient Banking for DRC and EQand176.4-kHz data.The8×oversampling combined •General Featureswith the fourth-order noise shaper provides a flat –Serial Control Interface Operational Without noise floor and excellent dynamic range from20Hz MCLK to20kHz.–Factory-Trimmed Internal OscillatorEnables Automatic Detection of IncomingPlease be aware that an important notice concerning availability,standard warranty,and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.Digital is a trademark of Texas Instruments.All other trademarks are the property of their respective owners.PRODUCTION DATA information is current as of publication date.Copyright©2008–2009,Texas Instruments Incorporated Products conform to specifications per the terms of the TexasInstruments standard warranty.Production processing does notnecessarily include testing of all parameters.TAS5705SLOS549A–JUNE2008–REVISED SIMPLIFIED APPLICATION DIAGRAMB0264-012Submit Documentation Feedback Copyright©2008–2009,Texas Instruments IncorporatedProduct Folder Link(s):TAS5705TAS5705 ................................................................................................................................................SLOS549A–JUNE2008–REVISED SEPTEMBER2009 FUNCTIONAL VIEWCopyright©2008–2009,Texas Instruments Incorporated Submit Documentation Feedback3Product Folder Link(s):TAS5705TAS5705SLOS549A–JUNE2008–REVISED Figure1.Power Stage Functional Block Diagram4Submit Documentation Feedback Copyright©2008–2009,Texas Instruments IncorporatedProduct Folder Link(s):TAS5705BKND_ERR VALIDDVDDD V S SD V S S O S D I N 1S D I N 2L R C L K S C L K MCLK M U TE H P S E L O S C _R E SP D N S D A S C L V R _D I GV R E G _E N S T E S T T E S T 2HPL_PWM HPR_PWM SUB_PWM–SUB_PWM+GNDGND GVDD_CD V D D _B V D D _B V D D _C V D D _C PVDD_D PVDD_D G N D _A BG N D _A B G N D _C D G N D _C D VREG U T _AU T _B U T _B U T _C U T _C OUT_D U T _DS T _B S T _C BST_D P0071-01PAP Package (Top View)TAS5705 ................................................................................................................................................SLOS549A –JUNE 2008–REVISED SEPTEMBER 200964-PIN,HTQFP PACKAGE (TOP VIEW)TERMINAL FUNCTIONSTERMINAL TYPE5-V TERMINATIONDESCRIPTION(1)TOLERANT(2)NAME NO.AVDD 10P 3.3-V analog power supply.Needs close decoupling capacitor.AVSS 11P Analog 3.3-V supply groundBKND_ERR35DIPullupActive-low.A back-end error sequence is generated by applying logic LOW to this terminal.This pin is connected to an external power stage.If no external power stage is used,connect this pin directly to DVDD.BST_A 4P High-side bootstrap supply for half-bridge A BST_B 57P High-side bootstrap supply for half-bridge B BST_C 56P High-side bootstrap supply for half-bridge C BST_D 45PHigh-side bootstrap supply for half-bridge D(1)TYPE:A =analog;D =3.3-V digital;P =power/ground/decoupling;I =input;O =output(2)All pullups are 20-μA weak pullups and all pulldowns are 20-μA weak pulldowns.The pullups and pulldowns are included to assure proper input logic levels if the terminals are left unconnected (pullups →logic 1input;pulldowns →logic 0input).Devices that drive inputs with pullups must be able to sink 50μA while maintaining a logic-0drive level.Devices that drive inputs with pulldowns must be able to source 50μA while maintaining a logic-1drive level.Copyright ©2008–2009,Texas Instruments IncorporatedSubmit Documentation Feedback5Product Folder Link(s):TAS5705TAS5705SLOS549A–JUNE2008–REVISED TERMINAL FUNCTIONS(continued)TERMINAL TYPE5-V TERMINATIONDESCRIPTION(1)TOLERANT(2)NAME NO.DVDD15,33P 3.3-V digital power supplyDVSS20P Digital groundDVSSO26P Oscillator groundFAULT9DO Pullup Overtemperature,overcurrent,and undervoltage fault reporting.Active-low indicates fault.If high,normal operation.GND41,42P Analog ground for power stageGVDD_AB5P Gate drive internal regulated output for AB channelsGVDD_CD44P Gate drive internal regulated output for CD channelsHPL_PWM37DO Headphone left-channel PWM output.HPR_PWM38DO Headphone right-channel PWM output.HPSEL30DI5-V Headphone select,active-high.When a logic high is applied,deviceenters headphone mode and speakers are MUTED(HARD MUTE).When a logic LOW is applied,device is in speaker mode andheadphone outputs become line outputs or are disabled.When in lineout mode,this terminal functionality is disabled(see system controlregister2.LRCLK22DI5-V Input serial audio data left/right clock(sampling rate clock)MCLK34DI5-V MCLK is the clock master input.The input frequency of this clock canrange from4.9MHz to49.2MHz.MUTE21DI5-V Pullup Performs a soft mute of outputs,active-low.A logic low on this pinsets the outputs equal to50%duty cycle.A logic high on this pinallows normal operation.The mute control provides a noiselessvolume ramp to silence.Releasing mute provides a noiseless ramp toprevious volume.OC_ADJ8AO Analog overcurrent programming.Requires22-kΩresistor to ground. OSC_RES19AO Oscillator trim resistor.Connect an18.2-kΩ,1%tolerance resistor toDVSSO.OUT_A1,64O Output,half-bridge AOUT_B60,61O Output,half-bridge BOUT_C52,53O Output,half-bridge COUT_D48,49O Output,half-bridge DPDN17DI5-V Pullup Power down,active-low.PDN powers down all logic,stops all clocks,and stops output switching whenever a logic low is applied.WhenPDN is released,the device powers up all logic,starts all clocks,andperforms a soft start that returns to the previous configurationdetermined by register settings.PGND_AB62,63P Power ground for half-bridges A and BPGND_CD50,51P Power ground for half-bridges C and DPLL_FLTM12AO PLL negative loop filter terminalPLL_FLTP13AI PLL positive loop filter terminalPVDD_A2,3P Power supply input for half-bridge output A(8V–23V)PVDD_B58,59P Power supply input for half-bridge output B(8V–23V)PVDD_C54,55P Power supply input for half-bridge output C(8V–23V)PVDD_D46,47P Power supply input for half-bridge output D(8V–23V)RESET16DI5-V Pullup Reset,active-low.A system reset is generated by applying a logiclow to this terminal.RESET is an asynchronous control signal thatrestores the DAP to its default conditions,sets the VALID outputslow,and places the PWM in the hard-mute state(stops switching).Master volume is immediately set to full attenuation.Upon the releaseof RESET,if PDN is high,the system performs a4–5-ms deviceinitialization and sets the volume at mute.SCL29DI5-V I2C serial control clock input6Submit Documentation Feedback Copyright©2008–2009,Texas Instruments IncorporatedProduct Folder Link(s):TAS5705TAS5705 ................................................................................................................................................SLOS549A–JUNE2008–REVISED SEPTEMBER2009TERMINAL FUNCTIONS(continued)TERMINAL TYPE5-V TERMINATIONDESCRIPTION(1)TOLERANT(2)NAME NO.SCLK23DI5-V Serial audio data clock(shift clock).SCLK is the serial audio portinput data bit clock.SDA28DIO5-V I2C serial control data interface input/outputSDIN125DI5-V Serial audio data1input is one of the serial data input ports.SDIN1supports three discrete(stereo)data formats.SDIN224DI5-V Serial audio data2input is one of the serial data input ports.SDIN2supports three discrete(stereo)data formats.SSTIMER6AI Controls ramp time of OUT_X for pop-free operation.Leave this pinfloating for BD mode.Requires capacitor of2.2nF to GND in ADmode.The capacitor determines the ramp time of PWM outputs from0%to50%.For2.2nF,start/stop time is~10ms.STEST31DI Test pin.Connect directly to GND.SUB_PWM–39DO Subwoofer negative PWM outputSUB_PWM+40DO Subwoofer positive PWM outputTEST17DI Test pin.Connect directly to GND.TEST232DI Test pin.Connect directly to DVDD.VALID36DO Output indicating validity of ALL PWM channels,active-high.This pinis connected to an external power stage.If no external power stage isused,leave this pin floating.VR_ANA14P Internally regulated1.8-V analog supply voltage.This terminal mustnot be used to power external devices.VR_DIG27P Internally regulated1.8V digital supply voltage.This terminal must notbe used to power external devices.VREG43P 3.3Regulator output.Not to be used as s supply or connected to anyother components other than decoupling caps.Add decouplingcapacitors with pins42and41.VREG_EN18DI Pulldown Voltage regulator enable.Connect directly to GND.ABSOLUTE MAXIMUM RATINGSover operating free-air temperature range(unless otherwise noted)(1)VALUE UNIT DVDD,AVDD–0.3to3.6V Supply voltagePVDD_X–0.3to30VOC_ADJ–0.3to4.2VInput voltage 3.3-V digital input–0.5to DVDD+0.5V 5-V tolerant(2)digital input–0.5to DVDD+2.5VOUT_x to PGND_X32(3)VBST_x to PGND_X43(3)VInput clamp current,I IK(V I<0or V I>1.8V)±20mA Output clamp current,I OK(V O<0or V O>1.8V)±20mA Operating free-air temperature0to85°C Operating junction temperature range0to150°C Storage temperature range,T stg–40to125°C (1)Stresses beyond those listed under absolute ratings may cause permanent damage to the device.These are stress ratings only andfunctional operation of the device at these or any other conditions beyond those indicated under recommended operation conditions are not implied.Exposure to absolute-maximum conditions for extended periods may affect device reliability.(2)5-V tolerant inputs are SCLK,LRCLK,MCLK,SDIN1,SDIN2,SDA,SCL,and HPSEL.(3)DC voltage+peak ac waveform measured at the pin should be below the allowed limit for all conditions.Copyright©2008–2009,Texas Instruments Incorporated Submit Documentation Feedback7Product Folder Link(s):TAS5705TAS5705SLOS549A–JUNE2008–REVISED DISSIPATION RATINGSDERATING FACTOR T A≤25°C T A=70°C T A=85°C PACKAGEABOVE T A=25°C POWER RATING POWER RATING POWER RATING10-mm×10-mm QFP40mW/°C5W 3.2W 2.6W RECOMMENDED OPERATING CONDITIONSMIN NOM MAX UNIT Digital/analog supply voltage DVDD,AVDD3 3.3 3.6VHalf-bridge supply voltage PVDD_X823VV IH High-level input voltage 3.3-V TTL,5-V tolerant2 5.5VV IL Low-level input voltage 3.3-V TTL,5-V tolerant0.8VT A Operating ambient temperature range085°CT J Operating junction temperature range0150°CR L(BTL)68Load impedance Output filter:L=15μH,C=0.68μFΩR L(SE) 3.24L O(BTL)10Minimum output inductance underOutput-filter inductanceμHshort-circuit conditionL O(SE)10PWM OPERATION AT RECOMMENDED OPERATING CONDITIONSPARAMETER TEST CONDITIONS MODE VALUE UNIT32–kHz data rate±2%12×sample rate384kHz Output sample rate2×–1×44.1-,88.2-,176.4-kHz data rate±2%8×,4×,and2×sample rates352.8kHz oversampled48-,96-,192-kHz data rate±2%8×,4×,and2×sample rates384kHz PLL INPUT PARAMETERS AND EXTERNAL FILTER COMPONENTSPARAMETER TEST CONDITIONS MIN TYP MAX UNITf MCLKI Frequency,MCLK(1/t cyc2) 4.949.2MHzMCLK duty cycle40%50%60%MCLK minimum high time8nsMCLK minimum low time8nsLRCLK allowable drift before LRCLK reset4MCLKs External PLL filter capacitor C1SMD0603Y5V47nFExternal PLL filter capacitor C2SMD0603Y5V 4.7nFExternal PLL filter resistor R SMD0603,metal film470Ω8Submit Documentation Feedback Copyright©2008–2009,Texas Instruments IncorporatedProduct Folder Link(s):TAS5705TAS5705 ................................................................................................................................................SLOS549A–JUNE2008–REVISED SEPTEMBER2009 ELECTRICAL CHARACTERISTICSDC CharacteristicsT A=25°,PVCC_X=18V,DVDD=AVDD=3.3V,R L=8Ω,BTL mode(unless otherwise noted)PARAMETER TEST CONDITIONS MIN TYP MAX UNITV OH High-level output voltage 3.3-V TTL and5-V tolerant(1)I OH=–4mA 2.4VV OL Low-level output voltage 3.3-V TTL and5-V tolerant(1)I OL=4mA0.5V3.3-V TTL V I=V IL±2I IL(2)Low-level input currentμA5-V tolerant(1)V I=0V,DVDD=3V±23.3-V TTL V I=V IH±2I IH(2)High-level input currentμA5-V tolerant V I=5.5V,DVDD=3V±20Normal Mode6583Digital supply voltage(DVDD,Power down(PDN=823I DD Digital supply current mAAVDD)low)Reset(RESET=low)2338.5I PVDD Analog supply current No load(all PVDD inputs)3060Power down(PDN=5 6.3I PVDD(PDN)Power-down current No load(all PVDD inputs)mAlow)I PVDD(RESET)Reset current No load(all PVDD inputs)Reset(RESET=low)5 6.3Drain-to-source resistance,180T J=25°C,includes metallization resistanceLSr DS(on)mΩDrain-to-source resistance,T J=25°C,includes metallization resistance180HSI/O ProtectionV uvp Undervoltage protection limit PVDD falling7.2VV uvp,hyst Undervoltage protection limit PVDD rising7.6V OTE(3)Overtemperature error150°C Extra temperature dropOTE HYST(3)required to recover from30°C errorOLPC Overload protection counter f PWM=384kHz0.63msResistor—programmable,max.current, 4.5I OC Overcurrent limit protection AR OCP=22kΩI OCT Overcurrent response time150nsResistor tolerance=5%for typical value;the minimumOC programming resistorR OCP resistance should not be less than20kΩ.This value is2022kΩrangenot adjustable.It must be fixed at22kΩ.Internal pulldown resistor at Connected when RESET is active to provide bootstrapR PD3kΩthe output of each half-bridge capacitor charge.(1)5-V tolerant inputs are PDN,RESET,MUTE,SCLK,LRCLK,MCLK,SDIN1,SDIN2,SDA,SCL,and HPSEL.(2)I IL or I IH for pins with internal pullup can go up to50μA.(3)Specified by designCopyright©2008–2009,Texas Instruments Incorporated Submit Documentation Feedback9Product Folder Link(s):TAS5705TAS5705SLOS549A–JUNE2008–REVISED AC Characteristics(BTL)PVDD_X=18V,BTL mode,R L=8Ω,R OC=22KΩ,C BST=33nF,audio frequency=1kHz,AES17filter,f PWM=384kHz,T A=25°C(unless otherwise noted).All performance is in accordance with recommended operating conditions,unless otherwise specified.PARAMETER TEST CONDITIONS MIN TYP MAX UNITPVDD=18V,10%THD,1-kHz input signal20.0PVDD=18V,7%THD,1-kHz input signal18.6PVDD=12V,10%THD,1-kHz input9signalP O Power output per channel WPVDD=12V,7%THD,1-kHz input signal8.3PVDD=8V,10%THD,1-kHz input signal 3.9PVDD=8V,7%THD,1-kHz input signal 3.7PVDD=18V;P O=10W(half-power)0.12%THD+N Total harmonic distortion+noise PVDD=12V;P O=4.5W(half-power)0.1%PVDD=8V;P O=2W(half-power)0.24%V n Output integrated noise A-weighted50μV Crosstalk P O=1W,f=1kHz–73dBA-weighted,f=1kHz,maximum power atSNR Signal-to-noise ratio(1)105dBTHD<0.1%P D Power dissipation due to idle losses(I PVDD_X)P O=0W,4channels switching(2)0.6W(1)SNR is calculated relative to0-dBFS input level.(2)Actual system idle losses are affected by core losses of output inductors.AC Characteristics(Single-Ended Output)PVDD_X=18V,SE mode,R L=4Ω,R OC=22kΩ,C BST=33-nF,audio frequency=1kHz,AES17filter,f PWM=384kHz, ambient temperature=25°C(unless otherwise noted).All performance is in accordance with recommended operating conditions,unless otherwise specified.PARAMETER TEST CONDITIONS MIN TYP MAX UNITPVDD=18V,10%THD10PVDD=18V,7%THD9P O Power output per channel WPVDD=12V,10%THD 4.5PVDD=12V,7%THD4PVDD=18V,Po=5W(half-power)0.2THD+Total harmonic distortion+noise%N PVDD=12V,Po=2.25W(half-power)0.2V n Output integrated noise A-weighted50μV SNR Signal-to-noise ratio(1)A-weighted105dB DNR Dynamic range A-weighted,input level=–60dBFS using TAS5086modulator105dBPower dissipation due to idleP D P O=0W,4channels switching(2)0.6W losses(IPVDD_X)(1)SNR is calculated relative to0-dBFS input level.(2)Actual system idle losses are affected by core losses of output inductors.10Submit Documentation Feedback Copyright©2008–2009,Texas Instruments IncorporatedProduct Folder Link(s):TAS5705SERIAL AUDIO PORTS SLAVE MODEover recommended operating conditions(unless otherwise noted)TESTPARAMETER MIN TYP MAX UNITCONDITIONSf SCLKIN Frequency,SCLK32×f S,48×f S,64×f S C L=30pF 1.02412.288MHz t su1Setup time,LRCLK to SCLK rising edge10ns t h1Hold time,LRCLK from SCLK rising edge10ns t su2Setup time,SDIN to SCLK rising edge10ns t h2Hold time,SDIN from SCLK rising edge10ns LRCLK frequency3248192kHz SCLK duty cycle40%50%60%LRCLK duty cycle40%50%60%SCLK SCLK rising edges between LRCLK rising edges3264edgest(edge)SCLK LRCLK clock edge with respect to the falling edge of SCLK–1/41/4periodFigure2.Slave Mode Serial Data Interface TimingSCLSDAT0027-01 SCLSDAStart ConditionStopConditionT0028-01I2C SERIAL CONTROL PORT OPERATIONTiming characteristics for I2C Interface signals over recommended operating conditions(unless otherwise noted)PARAMETER TEST CONDITIONS MIN MAX UNIT f SCL Frequency,SCL No wait states400kHz t w(H)Pulse duration,SCL high0.6μs t w(L)Pulse duration,SCL low 1.3μs t r Rise time,SCL and SDA300ns t f Fall time,SCL and SDA300ns t su1Setup time,SDA to SCL100ns t h1Hold time,SCL to SDA0ns t(buf)Bus free time between stop and start condition 1.3μs t su2Setup time,SCL to start condition0.6μs t h2Hold time,start condition to SCL0.6μs t su3Setup time,SCL to stop condition0.6μs C L Load capacitance for each bus line400pFFigure3.SCL and SDA TimingFigure4.Start and Stop Conditions TimingRESETVALIDtStart systemSystem initialization.Enable via I C.2T0029-05PDNVALIDt T0030-04RESET TIMING (RESET)Control signal parameters over recommended operating conditions (unless otherwise noted)PARAMETERMIN TYP MAX UNIT t d(VALID_LOW)Time to assert VALID (reset to power stage)low 100ns t w(RESET)Pulse duration,RESET active 100200ns t d(I2C_ready)Time to enable I 2C3.5ms t d(run)Device start-up time (after start-up command via I 2C)10msNOTE:On power up,it is recommended that the TAS5705be held LOW for at least 100μs after DVDD has reached3.0V.RESET assertion is ignored if applied while part is powered downFigure 5.Reset TimingPOWER-DOWN (PDN)TIMINGControl signal parameters over recommended operating conditions (unless otherwise noted)PARAMETERMINTYP MAXUNIT t d(VALID_LOW)Time to assert VALID (reset to power stage)low 725μs t d(STARTUP)Device startup time650μs t wMinimum pulse duration required1μsNOTE:PDNZ assertion is ignored if applied when part is in RESETFigure 6.Power-Down TimingDVDD PVDDT0317-01DVDDRESETPDNT0318-01Figure7.Power Up and Power Down of Power SuppliesNOTE:t power_down=time to wait before powering down the supplies after assertion=725μs+power-stage stop time defined by register0x1AFigure8.Terminal Control and DVDDBKND_ERRVALIDVOLUMEMUTET0032-03BACK-END ERROR (BKND_ERR)Control signal parameters over recommended operating conditions (unless otherwise noted)PARAMETERMIN TYP MAX UNIT t w(ER)Minimum pulse duration,BKND_ERR active (active-low)350nst p(valid_high)Programmable.Time to stay in the VALID (reset to the power stage)low state.After t p(valid_high),the TAS5705attempts to bring the system out of the VALID low state if 300ms BKND_ERR is high.t p(valid_low)Time TAS5705takes to bring VALID (reset to the power stage)low after BKND_ERR ns400assertion.Figure 9.Error Recovery TimingMUTE TIMING Control signal parameters over recommended operating conditions (unless otherwise noted)PARAMETERMINTYP MAXUNIT Volume ramp time (=number of steps ×step size).Number of steps is defined by volume t d(VOL)configuration register 0x0E (see Volume Configuration Register ).Step size =4LRCLKs if 1024stepsf S ≤48kHz;else 8LRCLKs if f S ≤96kHz ;else 16LRCLKsFigure 10.Mute TimingHP VolumeHPSELVALIDSpkr VolumeSpkr VolumeHPSELVALIDHP VolumeHEADPHONE SELECT (HPSEL)PARAMETERMIN MAX UNIT t w(MUTE)Pulse duration,HPSEL active 350ns t d(VOL)Soft volume update timeSee(1)ms t (SW)Switch-over time (controlled by start/stop period register,0x1A)0.2ms(1)Defined by the volume slew rate setting (see the volume configuration register ,0x0E).Figure 11and Figure 12show functionality when bit 4in the HP configuration register is set to DISABLE (not in line-out mode).See register 0x05for details.If bit 4is not set,than the HP PWM outputs are not disabled when HPSEL is brought low.Figure 11.HPSEL Timing for Headphone InsertionFigure 12.HPSEL Timing for Headphone Extractionf − Frequency − Hz 201001k10k T H D +N − T o t a l H a r m o n i c D i s t o r t i o n + N o i s e − %20kG0030.0010.01100.11f − Frequency − Hz 201001k10k T H D +N − T o t a l H a r m o n i c D i s t o r t i o n + N o i s e − %20kG0020.0010.01100.11f − Frequency − Hz201001k10k T H D +N − T o t a l H a r m o n i c D i s t o r t i o n + N o i s e − %20kG0010.0010.01100.11P O − Output Power − W0.010.1110T H D +N − T o t a l H a r m o n i c D i s t o r t i o n + N o i s e − %40G006TYPICAL CHARACTERISTICS,BTL CONFIGURATIONTOTAL HARMONIC DISTORTION +NOISE (BTL)TOTAL HARMONIC DISTORTION +NOISE (BTL)vsvsFREQUENCYFREQUENCYFigure 13.Figure 14.TOTAL HARMONIC DISTORTION +NOISE (BTL)TOTAL HARMONIC DISTORTION +NOISE (BTL)vsvsFREQUENCY OUTPUT POWERFigure 15.Figure 16.P O − Output Power − W 0.010.111040G005P O − Output Power − W 0.010.111040G004P O − Total Output Power − W0.00.51.01.52.02.53.0510152025303540G008P O − Output Power (Per Channel) − W010203040506070809010002468101214161820E f f i c i e n c y − %G007TOTAL HARMONIC DISTORTION +NOISE (BTL)TOTAL HARMONIC DISTORTION +NOISE (BTL)vsvsOUTPUT POWEROUTPUT POWERFigure 17.Figure 18.EFFICIENCYSUPPLY CURRENTvsvsOUTPUT POWERTOTAL OUTPUT POWERFigure 19.Figure 20.PVDD − Supply Voltage − V051015202568101214161820P O − O u t p u t P o w e r − WG009−100−95−90−85−80−75−70−65−60 f − Frequency − Hz C r o s s t a l k − d BG012201001k10k 20kOUTPUT POWERCROSSTALKvsvsSUPPLY VOLTAGEFREQUENCYFigure 21.Figure 22.f − Frequency − Hz 201001k10k T H D +N − T o t a l H a r m o n i c D i s t o r t i o n + N o i s e − %0.0011020k0.1G01210.01f − Frequency − Hz 201001k10k T H D +N − T o t a l H a r m o n i c D i s t o r t i o n + N o i s e − %0.0011020k0.1G01210.01V CC − Supply Voltage − V369121518510152025P O − O u t p u t P o w e r − WG014P O − Output Power − W 0.010.111040G013TYPICAL CHARACTERISTICS,SE CONFIGURATIONTOTAL HARMONIC DISTORTION +NOISETOTAL HARMONIC DISTORTION +NOISEvsvsFREQUENCYFREQUENCYFigure 23.Figure 24.TOTAL HARMONIC DISTORTION +NOISEOUTPUT POWERvsvsOUTPUT POWER SUPPLY VOLTAGEFigure 25.Figure 26.TAS5705 ................................................................................................................................................SLOS549A–JUNE2008–REVISED SEPTEMBER2009DETAILED DESCRIPTIONPOWER SUPPLYTo facilitate system design,the TAS5705needs only a3.3-V digital supply in addition to the(typical)18-V power-stage supply.An internal voltage regulator provides suitable voltage levels for the gate drive circuitry. Additionally,all circuitry requiring a floating voltage supply,e.g.,the high-side gate drive,is accommodated by built-in bootstrap circuitry requiring only a few external capacitors.In order to provide good electrical and acoustical characteristics,the PWM signal path for the output stage is designed as identical,independent half-bridges.For this reason,each half-bridge has separate bootstrap pins (BST_X),and power-stage supply pins(PVDD_X).The gate drive voltages(GVDD_AB and GVDD_CD)are derived from the PVDD voltage.Separate,internal voltage regulators reduce and regulate the PVDD voltage to a voltage appropriate for efficient gave drive operation.Special attention should be paid to placing all decoupling capacitors as close to their associated pins as possible.In general,inductance between the power-supply pins and decoupling capacitors must be avoided.For a properly functioning bootstrap circuit,a small ceramic capacitor must be connected from each bootstrap pin (BST_X)to the power-stage output pin(OUT_X).When the power-stage output is low,the bootstrap capacitor is charged through an internal diode connected between the gate-drive power-supply pin(GVDD_X)and the bootstrap pin.When the power-stage output is high,the bootstrap capacitor potential is shifted above the output potential and thus provides a suitable voltage supply for the high-side gate driver.In an application with PWM switching frequencies in the range from352kHz to384kHz,it is recommended to use33-nF ceramic capacitors, size0603or0805,for the bootstrap supply.These33-nF capacitors ensure sufficient energy storage,even during minimal PWM duty cycles,to keep the high-side power stage FET(LDMOS)fully turned on during the remaining part of the PWM cycle.Special attention should be paid to the power-stage power supply;this includes component selection,PCB placement,and routing.As indicated,each half-bridge has independent power-stage supply pins(PVDD_X).For optimal electrical performance,EMI compliance,and system reliability,it is important that each PVDD_X pin is decoupled with a100-nF ceramic capacitor placed as close as possible to each supply pin.The TAS5705is fully protected against erroneous power-stage turnon due to parasitic gate charging.SYSTEM POWER-UP/POWER-DOWN SEQUENCEPowering UpThe outputs of the H-bridges remain in a low-impedance state until the internal gate-drive supply voltage (GVDD_XY)and external VREG voltages are above the undervoltage protection(UVP)voltage threshold(see the DC Characteristics section of this data sheet).It is recommended to hold PVDD_X low until DVDD(3.3V)is powered up while powering up the device.This allows an internal circuit to charge the external bootstrap capacitors by enabling a weak pulldown of the half-bridge output.The output impedance is approximately3kΩ. This means that the TAS5705should be held in reset for at least100μs to ensure that the bootstrap capacitors are charged.This also assumes that the recommended0.033-μF bootstrap capacitors are used.Changes to bootstrap capacitor values change the bootstrap capacitor charge time.See Figure7and Figure8.Powering DownApply PDN(assert low).Wait for the power stage to shut down.Power down PVDD.Then power down DVDD. Then de-assert See Figure8for recommended timing.ERROR REPORTINGThe pin is an active-low,open-drain output.Its function is for protection-mode signaling to a system-control device.Any fault resulting in device shutdown is signaled by the pin going low(see Table1).。

MF_RC500_datasheet(中文)

I
2 3
4Leabharlann 55.2.3.1 页寄存器 ....................................................................................... 16 5.2.3.2 TxControl 寄存器 ........................................................................ 16 5.2.3.3 CwConductance 寄存器 ................................................................ 16 5.2.3.4 PreSet13 寄存器 .......................................................................... 17 5.2.3.5 PreSet14 寄存器 .......................................................................... 17 5.2.3.6 ModWidth 寄存器 .......................................................................... 17 5.2.3.7 PreSet16 寄存器 .......................................................................... 17 5.2.3.8 PreSet17 寄存器 .......................................................................

IC datasheet pdf-ATA6140 pdf,datasheet

Features•Temperature and Voltage Compensated Frequency (Fully Integrated Oscillator)•Warning Indication of Lamp Failure by Means of Frequency Doubling•Voltage Dependence of the Indicator Lamps also Compensated for Lamp Failure •Relay Output with High Current Capability and Low Saturation Voltage •Frequency Doubling only During Direction Mode•Temperature Compensated Threshold for Lamp Failure Detection •Overvoltage and Undervoltage Shut Down of the Relay Outputs •Quiescent Current I ≤ 10 µA (Switches Open)•EMI Protection According to ISO TR 7637/1, Test Level 4 (Exclusive Load Dump)•Reversed Battery Protection by Means of a Serial Resistor and Relay Coil Connected •Load Dump Protection 80V with External Protection Components •12V/24V Application •Package: SO16Electrostatic sensitive device.Observe precautions for handling.1.DescriptionThe integrated circuit ATA6140 is used in relay-controlled automotive flashers. With two output stages, each side of the vehicle is controlled separately. A left and a right direction indicator input with only a small control current makes switch contacts for small loads possible. The separate hazard warning input simplifies the construction ofthe hazard switch. Lamp outage is indicated by frequency doubling during direction mode. Thanks to the extreme low current consumption the ATA6140 can be con-nected to the battery directly.24560E–AUTO–09/05ATA6140Figure 1-1.Block Diagram34560E–AUTO–09/05ATA61402.Pin ConfigurationFigure 2-1.Pinning SO16Table 2-1.Pin DescriptionPin Symbol DirectionFunction1TS1G In Input left turn switch to ground (1)2TS1B In Input left turn switch to battery (1)3TS2G In Input right turn switch to ground 4TS2B In Input right turn switch to battery 5OUTPUT RIGHTOut Relay driver right side 6BA TT Supply Power battery voltage Battery force 7OUTPUT LEFTOut Relay driver left side 8IGN In Ignition input9LEDInOpen: regular frequencySwitch to IC-ground: LED outage left side, external signal frequency doubling left side (2)10LED In Open: normal workSwitch to IC-ground: LED outage right side, external signal frequency doubling right side (2)11HAZIn Input switch to hazard warning 12MEASURE INPUTIn Voltage drop at the shunt resistor1324VIn Switch to 24V version:Open enables overvoltage shut down function, connecting to IC-ground disables overvoltage shut down function14BA TTERY SENSEInSense battery voltage for the internal comparator with high precision 15TEST PIN Either not connected or connected to IC-ground16IC-GROUNDSupplyIC-groundNote:e either switches to ground pin 1 and 3 or switches to battery pin 2 and 42.These pins can be connected optional by using LED flashlights to indicate outage. If a LED pin is on low level, frequencydoubling is active, independent of pin MEASURE INPUT.44560E–AUTO–09/05ATA61403.Absolute Maximum RatingsStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.Parameters Symbol Value Unit Supply voltage, pin 6V VS 6 to 40V Ambient temperature range T amb –40 to +105°C Junction temperature range T j –40 to +150°C Storage temperature rangeT stg–55 to +150°C4.Thermal ResistanceParametersSymbol Value Unit Maximum thermal resistance SO16R thJA110K/W5.Operating RangeParameters Symbol Value Unit Supply voltage, pin 6V VS 6 to 24V Supply voltage, pin 6(24V version, pin 13 to GND)V VS18 to 33V6.Noise and Surge ImmunityParametersTest Conditions Value Conducted interferences (1)ISO 7637-1Level 4ESD (Human Body Model)MIL-STD-883D Method 3015.7(2)2 kV MIL-STD-883D Method 3015.7 (pin 12 and pin 14) 1 kV ESD FCDM (Field induced Charge Device Model)ESD - S. 5.3500VNote:1.At both outputs a relay of minimum 130 Ω should be added (for details see application circuits Figure 11-2 on page 8 toFigure 11-9 on page 12).2.Exclusive pin 12 and pin 14.54560E–AUTO–09/05ATA61407.Electrical CharacteristicsNo.ParametersTest ConditionsPinSymbolMin.Typ.Max.UnitType*1Supply Voltage Range1.1Supply voltage 6V VS 816V C 1.1Supply voltage (24V version)6V VS1833VC2Current Consumption 2.1Quiescent current (V S )V VS < 16V switches open 6I VS 10µA A 2.1Quiescent current (V S , 24V version)V VS < 33V switches open 6I VS 20µA A 2.2Supply current (V S )V VS < 16V6I VS 6mA A 2.2Supply current(V S , 24V version)V VS < 33V6I VS8mAA3Under and Overvoltage Detection 3.1Undervoltage detection threshold6V VU 68V A 3.2Undervoltage detection delay timet dUV2.510ms A3.3Overvoltage detection threshold6V VO 1822V A 3.3Overvoltage detection threshold (24V version)Disabled in 24V version (pin 13 to GND)6V VOVA4RelayOutputs 4.1Current output right 5I I5170mA A 4.2Current output left7I I7170mA A 4.3Saturation voltage right 170 mA at 23°C 5V SATR 1V A 4.4Saturation voltage left 170 mA at 23°C 7V SA TL 1V A 4.5Leakage current right 5I LEAKR 3µA A 4.5Leakage current right (24V version)5I LEAKR 6µA A 4.6Leakage current left 7I LEAKL 3µA A 4.6Leakage current left (24V version)7I LEAKL 6µA A 4.7Start delay time right 5T DR 1040ms A 4.8Start delay time left 7T DL 1040ms A 5Control Signal Thresholds 5.1Frequency doubling V S = 9V 12V THFD9424548mV A 5.2Frequency doubling V S = 15V 12V THFD15505357mV A 5.2Frequency doubling (24V version)V S = 24V 12V THFD2465mVA 5.3Short circuit detection V S = 13.5V 12V THSC 425475525mVB 5.3Short circuit detection (24V version)V S = 24V 12V THSC650mVB*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter64560E–AUTO–09/05ATA61408.Short Circuit or Overload Detection DelayDirection mode:100 ms during the first bright phase, 50 ms during all following bright phases Hazard mode: 100 ms during all bright phasesIn case of overload the relay output switches off (not stored)9.Bulb Outage DetectionThe detection of bulb outage takes place during the bright phase. There is a delay time of typi-cally 128 ms before ATA6140 measures the bulb current with a debounce period of 5 ms. After this time the inrush current dropped significantly.Application hint:It has to be considered that a slow relay contact may shorten the inrush current decay time and too high current would be measured and falsely an outage may not be detected. If operated with low supply voltage (e.g., 8V) the relay speed could be even slower.5.4Temperature coefficient –40°C to +105°C12C TH 30µV/K C 5.5Input current V S = 13.5 V 12I TH 2µA A 5.5Input current (24V version)V S = 24V12I TH4µAA6LED Inputs 6.1Threshold left V S = 13.5V 9V LEDL 1 4.5V A 6.2Threshold right V S = 13.5V10V LEDR 1 4.5V A 6.3Pull-up resistor left 9R LEDL 1075k ΩA 6.4Pull-up resistor right 10R LEDR1075k ΩA7Timing 7.1Basic frequency 1/f = 706 msF B–10.5+12%A 7.2Bright period50%A 7.3Bright period in failure mode40%A 7.4Failure frequency F F2.2 × F BA7.5Debounce timeBulb outage detection123.656.2ms7.Electrical Characteristics (Continued)No.Parameters Test Conditions Pin Symbol Min.Typ.Max.Unit Type**) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter74560E–AUTO–09/05ATA614010.Flasher Operating ModeIgnition Input Left Ground Input Right Ground Input Left Ignition Input Right Ignition Input Hazard Left Lamps (1)Right Lamps (1)Frequency in Case of Lamp Failure (1)Off Open Open IC-ground IC-ground Open x x x Off Ground Open IC-ground IC-ground Open x x x Off Open Ground IC-ground IC-ground Open x x x Off Open Open IC-ground IC-ground Ground Flash Flash Normal Off Ground Open IC-ground IC-ground Ground Flash Flash Normal Off Open Ground IC-ground IC-ground Ground Flash Flash Normal Off Ground Ground IC-ground IC-ground Ground Flash Flash Normal Off Ground Ground IC-ground IC-ground Open x x x (2)On Open Open IC-ground IC-ground Open x x x On Ground Open IC-ground IC-ground Open Flash x Double On Open Ground IC-ground IC-ground Open x Flash Double On Open Open IC-ground IC-ground Ground Flash Flash Normal On Ground Open IC-ground IC-ground Ground Flash Flash Normal On Open Ground IC-ground IC-ground Ground Flash Flash Normal On Ground Ground IC-ground IC-ground Ground Flash Flash Normal On Ground Ground IC-ground IC-ground Open Flash Flash Normal Off V BATT V BATT Open Open Open x x x Off V BATT V BATT Ignition Open Open x x x Off V BATT V BATT Open Ignition Open x x x Off V BATT V BATT Open Open Ground Flash Flash Normal Off V BATT V BATT Ignition Open Ground Flash Flash Normal Off V BATT V BATT Open Ignition Ground Flash Flash Normal Off V BATT V BATT Ignition Ignition Ground Flash Flash Normal Off V BATT V BATT Ignition Ignition Open x x x (3)On V BATT V BATT Open Open Open x x x On V BATT V BATT Ignition Open Open Flash x Double On V BATT V BATT Open Ignition Open x Flash Double On V BATT V BATT Open Open Ground Flash Flash Normal On V BATT V BATT Ignition Open Ground Flash Flash Normal On V BATT V BATT Open Ignition Ground Flash Flash Normal On V BATT V BATT Ignition Ignition Ground Flash Flash Normal On V BATTV BATTIgnitionIgnitionOpenFlashFlashNormalNotes:1.x = no flashing2.If ignition is OFF , the input level cannot be sensed (the IC is in the sleep mode). For hazard mode use the input hazard.3.For hazard mode use input hazard or switch to battery as shown in Figure 11-4 on page 9 and Figure 11-8 on page 11.84560E–AUTO–09/05ATA614011.DiagramsFigure 11-1.Timing DiagramFigure 11-2.Application 1: 12V Version, Turn Signal Switches to GND, Hazard Switch to GND94560E–AUTO–09/05ATA6140Figure 11-3.Application 2: 12V Version, Turn Signal Switches to Ignition, Hazard Switch to GNDFigure 11-4.Application 3: 12V Version, Turn Signal Switches to Ignition, Hazard Switch to Battery104560E–AUTO–09/05ATA6140Figure 11-5.Application 4: 12V Version, Turn Signal Switches to Ignition, Hazard Switch to GND, additional LED OutageFigure 11-6.Application 1: 24V Version, Turn Signal Switches to GND, Hazard Switch to GND114560E–AUTO–09/05ATA6140Figure 11-7.Application 2: 24V Version, Turn Signal Switches to Ignition, Hazard Switch to GNDFigure 11-8.Application 3: 24V Version, Turn Signal Switches to Ignition, Hazard Switch to Battery124560E–AUTO–09/05ATA6140Figure 11-9.Application 4: 24V Version, Turn Signal Switches to Ignition, Hazard Switch to GND, additional LED Outage134560E–AUTO–09/05ATA614013.Package Information14.Revision History12.Ordering InformationExtended Type Number Package RemarksA T A6140-TBQYSO16Taped and reeled, Pb-freePlease note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document.Revision No.History4560E-AUTO-09/05• Put datasheet in a new template • Pb-free logo on page 1 added• Ordering Information on page 13 changed4560E–AUTO–09/05© Atmel Corporation 2005. All rights reserved. Atmel ®, logo and combinations thereof, Everywhere You Are ® and others, are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others.Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL ’S TERMS AND CONDI-TIONS OF SALE LOCATED ON ATMEL ’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDEN-TAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life.Atmel CorporationAtmel Operations2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311Fax: 1(408) 487-2600Regional HeadquartersEuropeAtmel SarlRoute des Arsenaux 41Case Postale 80CH-1705 Fribourg SwitzerlandTel: (41) 26-426-5555Fax: (41) 26-426-5500AsiaRoom 1219Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong KongTel: (852) 2721-9778Fax: (852) 2722-1369Japan9F, Tonetsu Shinkawa Bldg.1-24-8 ShinkawaChuo-ku, Tokyo 104-0033JapanTel: (81) 3-3523-3551Fax: (81) 3-3523-7581Memory2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311Fax: 1(408) 436-4314Microcontrollers2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311Fax: 1(408) 436-4314La Chantrerie BP 7060244306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18Fax: (33) 2-40-18-19-60ASIC/ASSP/Smart CardsZone Industrielle13106 Rousset Cedex, France Tel: (33) 4-42-53-60-00Fax: (33) 4-42-53-60-011150 East Cheyenne Mtn. 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深圳市知用知用电子 VP6130高压差分探头说明书

CYBERTEK深圳市知用电子有限公司深圳市知用电子有限公司知用高压差分探头 VP6130 说明书深圳市知用电子有限公司深圳市知用电子有限公司知用深圳市南山区蛇口沿山路 10 号 4，5 楼 Tel：0755-******** Fax：0755-********CYBERTEK1. 概述深圳市知用电子有限公司深圳市知用电子有限公司知用VP6130 是一款高性价比的高压差分探头，差动测量电压高达 1300V（DC+Peak AC）。

探头必须与示波器的 BNC 头(BNC 必须提供地电位)连接使用。

探头具备良好共模噪声抑制能力，两个输入端都有较高的输入阻抗和较低电容，可以准确高速地测量差分电压信号.2. 特性频宽衰减比例精度输入电压范围最大输入差动电压最大共模输入电压 (正端与地之间电压或者负端与地之间电压) 共模抑制比(CMRR) 输入阻抗(单端) 电源指示过压指示尺寸配件 30MHz(-3dB) ×50, ×500 ±2% ×50 时，≦±130V ×500 时，≦±1300V 1300V 1000V60Hz:80dB 1MHz:50dB 4M/7pF 绿灯红灯 135mm(长) ×70mm(宽) ×25mm(高) DC 12V/1A 适配器；绝缘活塞电夹3. 应用■ ■ ■ ■ ■ ■ 浮地电压测量开关电源设计电机驱动设计电子镇流器设计 CRT 显示器设计电源转换等相关设计深圳市南山区蛇口沿山路 10 号 4，5 楼 Tel：0755-********Fax：0755-********CYBERTEK产品及 4. 产品及附件说明深圳市知用电子有限公司深圳市知用电子有限公司知用电源指示灯：当电源插入时，绿色指示灯亮。

电源指示灯过载指示灯：过载指示灯：当输入电压超过测试量程时，红色指示灯亮。

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RTJYZHFEATURESAPPLICATIONS DESCRIPTIONSIMPLIFIED APPLICATION DIAGRAMTPA6130A2SLOS488B–NOVEMBER2006–REVISED FEBRUARY2008 138-mW DIRECTPATH™STEREO HEADPHONE AMPLIFIER WITH I2C VOLUME CONTROL•Digital I2C Bus Control•DirectPath™Ground-Referenced Outputs–Per Channel Mute and Enable –Eliminates Output DC Blocking Capacitors–Software Shutdown–Reduces Board Area–Multi-Mode Support:Stereo HP,Dual MonoHP,and Single-Channel BTL Operation –Reduces Component Height and Cost–Amplifier Status–Full Bass Response Without Attenuation•Space Saving Packages•Power Supply Voltage Range:2.5V to5.5V–20Pin,4mm x4mm QFN•64Step Audio Taper Volume Control–16ball,2mm x2mm WCSP•High Power Supply Rejection Ratio(>100dB PSRR)•ESD Protection of8kV HBM and IEC Contact •Differential Inputs for Maximum NoiseRejection(68dB CMRR)•Mobile Phones•High-Impedance Outputs When Disabled•Portable Media Players•Advanced Pop and Click Suppression•Notebook ComputersCircuitry•High Fidelity ApplicationsThe TPA6130A2is a stereo DirectPath™headphone amplifier with I2C digital volume control.The TPA6130A2 has minimal quiescent current consumption,with a typical I DD of4mA,making it optimal for portable applications.The I2C control allows maximum flexibility with a64step audio taper volume control,channel independent enables and mutes,and the ability to configure the outputs into stereo,dual mono,or a single receiver speaker BTL amplifier that drives300mW of power into16Ωloads.The TPA6130A2is a high fidelity amplifier with an SNR of98dB.A PSRR greater than100dB enables direct-to-battery connections without compromising the listening experience.The output noise of9µVrms(typical A-weighted)provides a minimal noise background during periods of silence.Configurable differential inputs and high CMRR allow for maximum noise rejection in the noisy environment of a mobile device.TPA6130A2packaging includes a2by2mm chip-scale package,and a4by4mm QFN package.Please be aware that an important notice concerning availability,standard warranty,and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.DirectPath is a trademark of Texas Instruments.PRODUCTION DATA information is current as of publication date.Copyright©2006–2008,Texas Instruments Incorporated Products conform to specifications per the terms of the TexasInstruments standard warranty.Production processing does notnecessarily include testing of all parameters.CPPCPNLEFTINMLEFTINPCPVSSHPLEFTRIGHTINMRIGHTINPSDSDASCLHPRIGHTHeadphone channels are independently enabled and muted.The I2C interface controls channel gain,device TPA6130A2SLOS488B–NOVEMBER2006–REVISED FEBRUARY2008These devices have limited built-in ESD protection.The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.FUNCTIONAL BLOCK DIAGRAMmodes,and charge pump activation.The charge pump generates a negative supply voltage for the output amplifiers.This allows a0V bias at the outputs,eliminating the need for bulky output capacitors.The thermal block detects faults and shuts down the device before damage occurs.The I2C register records thermal fault conditions.The current limit block prevents the output current from getting high enough to damage the device. The De-Pop block eliminates audible pops during power-up,power-down,and amplifier enable and disable events.2Copyright©2006–2008,Texas Instruments IncorporatedProduct Folder Link(s):TPA6130A2Top (Symbol Side) View WCSPPackage (YZH)Bottom (Ball Side) View WCSP Package (YZH)DDNDPPPNPVSSTop View QFN Package (RTJ)TPA6130A2SLOS488B–NOVEMBER2006–REVISED FEBRUARY2008 TERMINAL FUNCTIONSTERMINAL INPUT/OUTPUT/DESCRIPTIONBALL POWERNAME PIN QFNWCSP(I/O/P)Charge pump voltage supply.V DD must be connected to the common V DD voltageV DD A420Psupply.Decouple to GND(pin19on the QFN)with its own1µF capacitor.Charge pump ground.GND must be connected to common supply GND.It isGND A319P recommended that this pin be decoupled to the V DD of the charge pump pin(pin20onthe QFN).Charge pump flying capacitor positive terminal.Connect one side of the flying capacitor CPP A218Pto CPP.Charge pump flying capacitor negative terminal.Connect one side of the flying capacitor CPN A117Pto CPN.Left channel negative differential input.Impedance must be matched to LEFTINP. LEFTINM B41IConnect the left input to LEFTINM when using single-ended inputs.Left channel positive differential input.Impedance must be matched to LEFTINM.AC LEFTINP B32I ground LEFTINP near signal source while maintaining matched impedance to LEFTINMwhen using single-ended inputs.Negative supply generated by the charge pump.Decouple to pin19on the QFN or a CPVSS B215,16PGND e a1µF capacitor.HPLEFT B114O Headphone left channel output.Connect to left terminal of headphone jack.Right channel negative differential input.Impedance must be matched to RIGHTINP. RIGHTINM C45IConnect the right input to RIGHTINM when using single-ended inputs.Right channel positive differential input.Impedance must be matched to RIGHTINM.AC RIGHTINP C34I ground RIGHTINP near signal source while maintaining matched impedance toRIGHTINM when using single-ended inputs.Analog ground.Must be connected to common supply GND.It is recommended that this 3,9,10,GND C2P pin be used to decouple V DD for e pin13to decouple pin12on the QFN13package.Analog V DD.V DD must be connected to common V DD supply.Decouple with its own1-µF V DD C112Pcapacitor to analog ground(pin13on the QFN).SD D46I Shutdown.Active low logic.5V tolerant input.SDA D37I/O SDA-I2C Data.5V tolerant input.SCL D28I SCL-I2C Clock.5V tolerant input.HPRIGHT D111O Headphone light channel output.Connect to the right terminal of the headphone jack.Thermal Solder the thermal pad on the bottom of the QFN package to the GND plane of the PCB.N/A Die Pad Ppad It is required for mechanical stability and will enhance thermal performance.Copyright©2006–2008,Texas Instruments Incorporated3Product Folder Link(s):TPA6130A2ABSOLUTE MAXIMUM RATINGS (1)DISSIPATION RATINGS TABLERECOMMENDED OPERATING CONDITIONSTPA6130A2SLOS488B–NOVEMBER 2006–REVISED FEBRUARY 2008over operating free-air temperature range,T A =25°C (unless otherwise noted)VALUE /UNITSupply voltage,V DD–0.3V to 6.0V RIGHTINx,LEFTINx –2.7V to 3.6V V IInput voltageSD,SCL,SDA–0.3V to 7VOutput continuous total power dissipationSee Dissipation Rating TableT A Operating free-air temperature range –40°C to 85°C T J Operating junction temperature range –40°C to 125°C T stgStorage temperature range–65°C to 150°CLead temperature 1,6mm (1/16inch)from case for 10seconds 260°C HBM Output Pins 8kV ESD ProtectionHBM All Other Pins 3.5kV No External Protection8kV IEC Contact ESD Protection (2)V14MLA0603Varistors Used for External Protection 15kV Minimum Load Impedance12.8Ω(1)Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device.These are stress ratings only,and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied.Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2)Tested to IEC 61000-4-2standards on a TPA6130A2EVM.T A ≤25°C DERATING T A =70°C T A =85°C PACKAGEPOWER RATINGFACTOR (1)(2)POWER RATINGPOWER RATINGRTJ 4100mW 41mW/°C 2250mW 1640mW YZH970mW9.7mW/°C530mW390mW(1)Derating factor measured with JEDEC High K board:1S2P -One signal layer and two plane layers.(2)See JEDEC Standard 51-3for Low-K board,JEDEC Standard 51-7for High-K board,and JEDEC Standard 51-12for using package thermal information.Please see JEDEC document page for downloadable copies:/download/default.cfm .AVAILABLE OPTIONST APACKAGED DEVICES (1)PART NUMBER SYMBOL 20-pin,4mm ×4mm QFN TPA6130A2RTJ (2)BSG –40°C to 85°C 16-ball,1,98mm ×1.98mm TPA6130A2YZHBRU(+0,01mm,–0,09mm)(1)For the most current package and ordering information,see the Package Option Addendum at the end of this document,or see the TI Web site at .(2)The RTJ package is only available taped and reeled.To order,add the suffix “R”to the end of the part number for a reel of 3000,or add the suffix “T”to the end of the part number for a reel of 250(e.g.,TPA6130A2RTJR).MINMAX UNIT Supply voltage,V DD2.5 5.5V V IH High-level input voltage SCL,SDA,SD 1.3V SCL,SDA 0.6V V IL Low-level input voltageSD0.35V T AOperating free-air temperature–4085°C4Copyright ©2006–2008,Texas Instruments IncorporatedProduct Folder Link(s):TPA6130A2ELECTRICAL CHARACTERISTICSTIMING CHARACTERISTICS (1)(2)TPA6130A2SLOS488B–NOVEMBER 2006–REVISED FEBRUARY 2008T A =25°C (unless otherwise noted)PARAMETERTEST CONDITIONSMINTYP MAX UNIT |VOS|Output offset voltage V DD =2.5V to 5.5V,inputs grounded 150400µV PSRR Power supply rejection ratio V DD =2.5V to 5.5V,inputs grounded –109–90dB CMRR Common mode rejection ratio V DD =2.5V to 5.5V –68dB SCL,SDA 1|I IH |High-level input current V DD =5.5V,V I =V DD µA SD10|I IL |Low-level input currentV DD =5.5V,V I =0VSCL,SDA,SD1µA V DD =2.5V to 5.5V,SD =V DD46mA Shutdown mode,V DD =2.5V to 5.5V,SD =0V0.41µA I DDSupply currentSW Shutdown mode,V DD =2.5V to 5.5V,SWS =12575µA Both HP amps disabled,V DD =2.5V to 5.5V, 1.42.5mASWS =0,Charge Pump enabled,SD =V DDFor I 2C Interface Signals Over Recommended Operating Conditions (unless otherwise noted)PARAMETERTEST CONDITIONSMINTYPMAX UNIT f SCL Frequency,SCL No wait states400kHz t w(H)Pulse duration,SCL high 0.6µs t w(L)Pulse duration,SCL low 1.3µs t su1Setup time,SDA to SCL 300ns t h1Hold time,SCL to SDA10ns t (buf)Bus free time between stop and start condition 1.3µs t su2Setup time,SCL to start condition 0.6µs t h2Hold time,start condition to SCL 0.6µs t su3Setup time,SCL to stop condition0.6µs(1)V Pull-up =V DD(2)A pull-up resistor ≤2k Ωis required for a 5V I 2C bus voltage.Figure 1.SCL and SDA TimingCopyright ©2006–2008,Texas Instruments Incorporated 5Product Folder Link(s):TPA6130A2OPERATING CHARACTERISTICSTPA6130A2SLOS488B–NOVEMBER 2006–REVISED FEBRUARY 2008Figure 2.Start and Stop Conditions TimingV DD =3.6V ,T A =25°C,R L =16Ω(unless otherwise noted)6Copyright ©2006–2008,Texas Instruments IncorporatedProduct Folder Link(s):TPA6130A2TYPICAL CHARACTERISTICSTable of Graphs100m1m 10m 100m 1P - Output Power - WO T H D +N - T o t a l H a r m o n i c D i s t o r t i o n + N o i s e - %100m1m 100m 10m 1P - Output Power - WO T H D +N - T o t a l H a r m o n i c D i s t o r t i o n + N o i s e - %1100.010.10.001100m1m10m100m1P - Output Power - WO T H D +N - T o t a l H a r m o n i c D i s t o r t i o n + N o i s e - %1100.010.10.001100m1m10m100m1P - Output Power - W O T H D +N - T o t a l H a r m o n i c D i s t o r t i o n + N o i s e - %100mP - Output Power - W O T H D +N - T o t a l H a r m o n i c D i s t o r t i o n + N o i s e - %100mP - Output Power - WO T H D +N - T o t a l H a r m o n i c D i s t o r t i o n + N o i s e - %TPA6130A2SLOS488B–NOVEMBER 2006–REVISED FEBRUARY 2008C (PUMP,DECOUPLE,,BYPASS,CPVSS)=1µF,C I =2.2µF.All THD +N graphs taken with outputs out of phase (unless otherwise noted).FIGURETotal harmonic distortion +noise vs Output power 3–8Total harmonic distortion +noise vs Frequency 9–22Supply voltage rejection ratio vs Frequency 23-25Common mode rejection ratio vs Frequency 26-27Output power vs Load 28-29Output voltage vs Load 30-31Power Dissipationvs Output power 32Differential Input Impedance vs Gain33Shutdown time 34Startup time35TOTAL HARMONIC DISTORTION +TOTAL HARMONIC DISTORTION +TOTAL HARMONIC DISTORTION +NOISE NOISE NOISE vsvsvsOUTPUT POWEROUTPUT POWEROUTPUT POWERFigure 3.Figure 4.Figure 5.TOTAL HARMONIC DISTORTION +TOTAL HARMONIC DISTORTION +TOTAL HARMONIC DISTORTION +NOISE NOISE NOISE vsvsvsOUTPUT POWEROUTPUT POWEROUTPUT POWERFigure 6.Figure 7.Figure 8.Copyright ©2006–2008,Texas Instruments Incorporated 7Product Folder Link(s):TPA6130A21000.010.001T H D +N - T o t a l H a r m o n i c D i s t o r t i o n + N o i s e - %f - Frequency - Hz201001k10k 20kf - Frequency - HzT H D +N - T o t a l H a r m o n i c D i s t o r t i o n + N o i s e - %f - Frequency - HzT H D +N - T o t a l H a r m o n i c D i s t o r t i o n + N o i s e - %f - Frequency - HzT H D +N - T o t a l H a r m o n i c D i s t o r t i o n + N o i s e - %201001k10k 20kf - Frequency - HzT H D +N - T o t a l H a r m o n i c D i s t o r t i o n + N o i s e - %f - Frequency - HzT H D +N - T o t a l H a r m o n i c D i s t o r t i o n + N o i s e - %f - Frequency - HzT H D +N - T o t a l H a r m o n i c D i s t o r t i o n + N o i s e - %f - Frequency - HzT H D +N - T o t a l H a r m o n i c D i s t o r t i o n + N o i s e - %f - Frequency - HzT H D +N - T o t a l H a r m o n i c D i s t o r t i o n + N o i s e - %TPA6130A2SLOS488B–NOVEMBER 2006–REVISED FEBRUARY 2008TOTAL HARMONIC DISTORTION +TOTAL HARMONIC DISTORTION +TOTAL HARMONIC DISTORTION +NOISE NOISE NOISE vsvsvsFREQUENCYFREQUENCYFREQUENCYFigure 9.Figure 10.Figure 11.TOTAL HARMONIC DISTORTION +TOTAL HARMONIC DISTORTION +TOTAL HARMONIC DISTORTION +NOISE NOISE NOISE vsvsvsFREQUENCYFREQUENCYFREQUENCYFigure 12.Figure 13.Figure 14.TOTAL HARMONIC DISTORTION +TOTAL HARMONIC DISTORTION +TOTAL HARMONIC DISTORTION +NOISE NOISE NOISE vsvsvsFREQUENCYFREQUENCYFREQUENCYFigure 15.Figure 16.Figure 17.8Copyright ©2006–2008,Texas Instruments IncorporatedProduct Folder Link(s):TPA6130A2f - Frequency - HzT H D +N - T o t a l H a r m o n i c D i s t o r t i o n + N o i s e - %201001k10k 20kf - Frequency - HzT H D +N - T o t a l H a r m o n i c D i s t o r t i o n + N o i s e - %201001k10k 20kf - Frequency - HzT H D +N - T o t a l H a r m o n i c D i s t o r t i o n + N o i s e - %f - Frequency - HzT H D +N - T o t a l H a r m o n i c D i s t o r t i o n + N o i s e - %f - Frequency - HzT H D +N - T o t a l H a r m o n i c D i s t o r t i o n + N o i s e- %-100-80-60-40-20-120201001k 10k 20kf - Frequency - Hzk - S u p p l y V o l t a g e R e j e c t i o n R a t i o - VS V R-100-80-60-40-20-120f - Frequency - Hz k - S u p p l y V o l t ag e R e j e c t i o n R a t i o - VS V R 0-100-80-60-40-20-120f - Frequency - Hz k - S u p p l y V o l t ag e R e j e c t i o n R a t i o - VS V R 0-70-60-50-40-30-20-10-80f - Frequency - HzC M R R - C o m m o n -M o d e R e j e c t i o n R a t i o - d BTPA6130A2SLOS488B–NOVEMBER 2006–REVISED FEBRUARY 2008TOTAL HARMONIC DISTORTION +TOTAL HARMONIC DISTORTION +TOTAL HARMONIC DISTORTION +NOISE NOISE NOISE vsvsvsFREQUENCYFREQUENCYFREQUENCYFigure 18.Figure 19.Figure 20.TOTAL HARMONIC DISTORTION +TOTAL HARMONIC DISTORTION +SUPPLY VOLTAGE REJECTIONNOISE NOISE RATIO vsvsvsFREQUENCYFREQUENCYFREQUENCYFigure 21.Figure 22.Figure 23.SUPPLY VOLTAGE REJECTIONSUPPLY VOLTAGE REJECTIONRATIO RATIO COMMON MODE REJECTION RATIOvsvsvsFREQUENCYFREQUENCYFREQUENCYFigure 24.Figure 25.Figure 26.Copyright ©2006–2008,Texas Instruments Incorporated 9Product Folder Link(s):TPA6130A2Load -W P - O u t p u t P o w e r - m WOLoad -WP - O u t p u t P o w e r - m WO 0-70-60-50-40-30-20-10-80201001k 10k 20kf - Frequency - Hz C M R R - C o m m o n -Mo d e R e j e c t i o n R a t i o - d B51310Load -WV - O u t p u t V o l t a g e - V O P P24100Load -WV - O u t p u t V o l t a g e - V O P P10.20.40.60.8P - Output Power - mWO P - P o w e r D i s s i p a t i o n - WD10060405070809030Gain - dBD i f f e r e n t i a l I n p u t I m p e d a n c e - k WTPA6130A2SLOS488B–NOVEMBER 2006–REVISED FEBRUARY 2008COMMON MODE REJECTION RATIOOUTPUT POWEROUTPUT POWERvsvs vs FREQUENCYLOADLOADFigure 27.Figure 28.Figure 29.OUTPUT VOLTAGEOUTPUT VOLTAGEPOWER DISSIPATIONvs vs vsLOADLOADOUTPUT POWERFigure 30.Figure 31.Figure 32.DIFFERENTIAL INPUT IMPEDANCEvs GAINFigure 33.10Copyright ©2006–2008,Texas Instruments IncorporatedProduct Folder Link(s):TPA6130A210.50.750.250-0.25-0.5-0.75-10400m200m600m800m1m1.2m1.6m1.4m1.8m2mt - Time - sV o l t a g e - V10.50.750.250-0.25-0.5-0.75-102m1m3m4m5m6m8m7m9m10mt - Time - sV o l t a g e - VFigure 34.Shutdown TimeFigure 35.Startup TimeCopyright ©2006–2008,Texas Instruments Incorporated 11APPLICATION INFORMATIONHeadphone Amplifiersf c +12p R L C O(1)C O +12p R L f c(2)SIMPLIFIED APPLICATIONS CIRCUITSingle-supply headphone amplifiers typically require dc-blocking capacitors.The capacitors are required because most headphone amplifiers have a dc bias on the outputs pin.If the dc bias is not removed,the output signal is severely clipped,and large amounts of dc current rush through the headphones,potentially damaging them.The top drawing in Figure 36illustrates the conventional headphone amplifier connection to the headphone jack and output signal.DC blocking capacitors are often large in value.The headphone speakers (typical resistive values of 16Ωor 32Ω)combine with the dc blocking capacitors to form a high-pass filter.Equation 1shows the relationship between the load impedance (R L ),the capacitor (C O ),and the cutoff frequency C C O can be determined using Equation 2,where the load impedance and the cutoff frequency are known.If f c is low,the capacitor must then have a large value because the load resistance is rge capacitance values require large package rge package sizes consume PCB area,stand high above the PCB,increase cost of assembly,and can reduce the fidelity of the audio output signal.Two different headphone amplifier applications are available that allow for the removal of the output dc blocking capacitors.The Capless amplifier architecture is implemented in the same manner as the conventional amplifier with the exception of the headphone jack shield pin.This amplifier provides a reference voltage,which isCVOUTVOUTGNDGNDVDDVDDV/2DDVBIAS ConventionalCaplessGNDVDDVSSBIASDirectPath TMInput-Blocking Capacitorsconnected to the headphone jack shield pin.This is the voltage on which the audio output signals are centered. This voltage reference is half of the amplifier power supply to allow symmetrical swing of the output voltages.Do not connect the shield to any GND reference or large currents will result.The scenario can happen if,for example,an accessory other than a floating GND headphone is plugged into the headphone connector.See the second block diagram and waveform in Figure36.Figure36.Amplifier ApplicationsThe DirectPath™amplifier architecture operates from a single supply but makes use of an internal charge pump to provide a negative voltage bining the user provided positive rail and the negative rail generated by the IC,the device operates in what is effectively a split supply mode.The output voltages are now centered at zero volts with the capability to swing to the positive rail or negative rail.The DirectPath™amplifier requires no output dc blocking capacitors,and does not place any voltage on the sleeve.The bottom block diagram and waveform of Figure36illustrate the ground-referenced headphone architecture.This is the architecture of the TPA6130A2.DC input-blocking capacitors block the dc portion of the audio source,and allow the inputs to properly bias. Maximum performance is achieved when the inputs of the TPA6130A2are properly biased.Performance issues such as pop are optimized with proper input capacitors.The dc input-blocking capacitors may be removed provided the inputs are connected differentially and within the input common mode range of the amplifier,the audio signal does not exceed±3V,and pop performance is sufficient.Copyright©2006–2008,Texas Instruments Incorporated13C(DCINPUT-BLOCKING)12C IN =(3)fc IN +12p R IN C IN C IN +12p fc IN R INor (4)Charge Pump Flying Capacitor and CPVSS CapacitorDecoupling CapacitorsLayout RecommendationsExposed Pad On TPA6130A2RTJ Package OptionGND ConnectionsI 2C CONTROL INTERFACE DETAILSAddressing the TPA6130A2C IN is a theoretical capacitor used for mathematical calculations only.Its value is the series combination of the dc input-blocking capacitors,C (DCINPUT-BLOCKING).Use Equation 3to determine the value of C (DCINPUT-BLOCKING).For example,if C IN is equal to 0.22µF,then C (DCINPUT-BLOCKING)to about 0.47µF.The two C (DCINPUT-BLOCKING)capacitors form a high-pass filter with the input impedance of the e Equation 3to calculate C IN ,then calculate the cutoff frequency using C IN and the differential input impedance of R IN ,using Equation 4.Note that the differential input impedance changes with gain.See Figure 33for input frequency and/or capacitance can be determined when one of the two given.If a high pass filter with a -3dB point of no more than 20Hz is desired over all gain settings,the minimum impedance would be used in the above equation.Figure 33shows this to be 37k Ω.The capacitor value by the above equation would be 0.215µF.However,IN ,and the desired value is for C (DCINPUT-BLOCKING).Multiplying C IN by 2yields 0.43µF,which is close to the standard capacitor value of 0.47µF.Place 0.47µF capacitors at each input terminal of the TPA6130A2to complete the filter.The charge pump flying capacitor serves to transfer charge during the generation of the negative supply voltage.The CP VSS capacitor must be at least equal to the flying capacitor in order to allow maximum charge transfer.Low ESR capacitors are an ideal selection,and a value of 1µF is typical.The TPA6130A2is a DirectPath™headphone amplifier that requires adequate power supply decoupling to ensure that the noise and total harmonic distortion (THD)are e good low equivalent-series-resistance (ESR)ceramic capacitors,typically 1.0µF.Find the smallest package possible,and place as close as possible to the device V DD lead.Placing the decoupling capacitors close to the TPA6130A2is important for the performance of the e a 10µF or greater capacitor near the TPA6130A2to filter lower frequency noise signals.The high PSRR of the TPA6130A2will make the 10µF capacitor unnecessary in most applications.Solder the exposed metal pad on the TPA6130A2RTJ QFN package to the a pad on the PCB.The pad on the PCB may be grounded or may be allowed to float (not be connected to ground or power).If the pad is grounded,it must be connected to the same ground as the GND pins (3,9,10,13,and 19).See the layout and mechanical drawings at the end of the datasheet for proper sizing.Soldering the thermal pad improves mechanical reliability,improves grounding of the device,and enhances thermal conductivity of the package.The GND pin for charge pump should be decoupled to the charge pump V DD pin,and the GND pin adjacent to the Analog V DD pin should be separately decoupled to each other.The device operates only as a slave device whose address is 1100000binary.GENERAL I 2COPERATIONSINGLE-AND MULTIPLE-BYTE TRANSFERSSINGLE-BYTE WRITEThe I 2C bus employs two signals;SDA (data)and SCL (clock),to communicate between integrated circuits in a system.Data is transferred on the bus serially,one bit at a time.The address and data are transferred in byte (8-bit)format with the most-significant bit (MSB)transferred first.In addition,each byte transferred on the bus is acknowledged by the receiving device with an acknowledge bit.Each transfer operation begins with the master device driving a start condition on the bus and ends with the master device driving a stop condition on the bus.The bus uses transitions on the data terminal (SDA)while the clock is high to indicate start and stop conditions.A high-to-low transition on SDA indicates a start and a low-to-high transition indicates a stop.Normal data-bit transitions must occur within the low time of the clock period.These conditions are shown in Figure 37.The master generates the 7-bit slave address and the read/write (R/W)bit to open device and then wait for an acknowledge condition.The TPA6130A2holds SDA low during acknowledge clock period to indicate an acknowledgment.When this occurs,the master transmits the next byte of the sequence.Each device is addressed by a unique 7-bit slave address plus R/W bit (1byte).All compatible devices share the same signals via a bidirectional bus using a wired-AND connection.An external pull-up resistor must be used for the SDA and SCL signals to set the HIGH level for the bus.When the bus level is 5V,pull-up resistors between 1k Ωand 2k Ωin value must be used.Figure 37.Typical I 2C SequenceThere is no limit on the number of bytes that can be transmitted between start and stop conditions.When the last word transfers,the master generates a stop condition to release the bus.A generic data transfer sequence is shown in Figure 37.The serial control interface supports both single-byte and multi-byte read/write operations for all registers.During multiple-byte read operations,the TPA6130A2responds with data,a byte at a time,starting at the register assigned,as long as the master device continues to respond with acknowledges.The TPA6130A2supports sequential I 2C addressing.For write transactions,if a register is issued followed by data for that register and all the remaining registers that follow,a sequential I 2C write transaction has taken place.For I 2C sequential write transactions,the register issued then serves as the starting point,and the amount of data subsequently transmitted,before a stop or start is transmitted,determines to how many registers are written.As shown in Figure 38,a single-byte data write transfer begins with the master device transmitting a start condition I 2C device address and the read/write bit.The read/write bit determines the direction of the data transfer.For a write data transfer,the read/write bit must be set to 0.After receiving the correct I 2C device address and the read/write bit,the TPA6130A2responds with an acknowledge bit.Next,the master transmits the register byte corresponding to the TPA6130A2internal memory address being accessed.After receiving the register byte,the TPA6130A2again responds with an acknowledge bit.Next,the master device transmits the data byte to be written to the memory address being accessed.After receiving the data byte,the TPA6130A2again responds with an acknowledge bit.Finally,the master device transmits a stop condition to complete the single-byte data write transfer.Copyright ©2006–2008,Texas Instruments Incorporated 15。