第五章(part_I)

Homeworks:5.4 5.155.5 5.185.9 5.195.10 (Q10: J=1) 5.221Chapter 5. Flip-flop第五章. 触发器23§5.1 Overview 概述l f ：y(t) Sequential logic, G(t-1) depends on y(t-1)x(t )G(t-1)Input x(t)Output y(t)of previous state y(t-1)1. if G is combinational ？y(t) G(t) ≠ G(t-1), 不符合要求；2.G should maintain the previous state: 记忆功能触发器lQ: What type of feedback circuit is G ?l本章内容：基本时序单元—触发器(Flip-flop , FF)4a)two stable states: 1 and 0FFFlip-flop could store one bit of binary (state) information and labelled as latch as well 触发器能够存储1位二进制信息，又称做锁存器(latch)b) state would switch (flip-flop) in the presence of external input signalsc)is able to maintain the state information when input signals disappearFlip-flop : a circuit of two stable states and can be used to store state information 具有双稳态的记忆单元lContent 本章内容：1. Basic RS-FF and gated FF 基本RS 触发器及时钟触发器2. Edge-triggered FF 边沿触发器3. Coversions and applications 触发器相互转换及应用5Two cross-over NAND gates 两个交叉耦合的与非门Inputs:SSet 置位端RReset 复位端Outputs:=0 “1” 态High=1 “0” 态Low Q Q =0,Q Q =1,Q is defined as the state (状态) of FF§5.1 Simple Reset-Set (RS) FF. 基本RS 触发器Q G 1G 2&&S RQ1. Circuits5.1.1RS NAND FF 与非门构成的基本RS 触发器:Note ::S QR Q6Symbol:2. Working principle G 1locked,S =0,R =11)保持状态: No-change (NC)Previous state of FF remains unchanged 触发器保持上一状态不变(Storage of state information)Q =1, Q =0If S switch to 1, S = R = 1011G 1is locked as Q = 0, Q = 11Set (置1）QG 1G2&&SR Q7,1==R S 2)No-change Q = 0G 2locked 10Q = 1,Q = 010If R switch to 1,1Q = 0,G 2lockedS = R = 1Truth table 真值表S RQ QFF state0 00 11 01 1 1 0Set (1)0 1Reset (0)NC NC No-changeReset (置0)&&QQ SRG 1G 280,1,S R Q Q ====当3)FORCED TO BE LOGIC HIGH,R SWhen switch from 0 to 1 simultaneously Outputs depend on the transfer delay of NANDpd t 011t pd1< t pd2(G 1fast) Q = 0t pd1> t pd2(G 2fast) Q = 1S RQ Q FF state0 00 11 01 1 1 0Set (1)0 1Reset (0)NC NCNo-change1 1Uncertain: S R 0→1同时11都是稳定状态，但不知是哪种. 在S R 同时从0变到1时，状态不定&&QQ S R G 1G 295.1.2 Describing a RS-FFTo describe the function of a RS-FF, we are actually depicting the logic relationships among the following variables 描述如下变量之间的逻辑关系Truth table状态转移真值表（状态表）State equation (Characteristic equation)状态方程（特征方程）State diagram and Transition table 状态转移图和激励表Waveforms (Timing diagrams ) 波形图（时序图）RS Q n +1: Next steady state （次态）Q n : Current steady state （现态）输入信号( , for RS-FF)101．Truth table 功能表真值表&&QQSRG 1G 2Describing a RS-FFQ n +10 0uncertain0 1 01 011 1Q nSR112．State equation (Characterastic equation)Q n+1Q n 00 01 11 1001R S ΦΦ00111011n n Q S RQS R +ì=+ïí+=ïîR S 注意：将和看作整体输入信号符号上面的横线表示低电平有效不同时为0123.State diagram and State table用图形表示输出状态转换的条件和规律State diagramState diagram describes the process and conditions for state switchesCombinational logic: Truth table –one-to-one correspondence between inputs and outputs 输入输出之间的一一对应关系Sequential logic: State diagram （状态图）–Transitions of states and the conditions 状态转换及转换条件nQ1n Q+01ConditionTransition from one state to another 从一个状态转换为另一个状态States01Φ/11/ Φ1/00/1ConditionX/Z 转换条件R/S13Transition Table 激励表Transition table for basic RS-FFA table to list all known transitions of states and the conditions. Transition table take current state Q n and next state Q n +1as variables and corresponding inputs R, S as functions 列出已知状态转换和所需要的输入条件的表称为激励表。

激励表是以现态Q n 和次态Q n +1 为变量，以对应的输入R, S 为函数的关系表.表示出在什么样的激励下，才能使现态Q n 转换到次态Q n +1.Q n +1Q n144. Waveforms (时序波形)Waveforms of outputs corresponding to input waveforms 与输入波形图一一对应的输出波形图. (Q 的初始值为0)QQSR1100uncertainS RQ Q FF state0 00 11 01 1 1 0Set (1)0 1Reset (0)NC NCNo-change1 1S R 0→1不定S ≠R Q =R tV15Q≥1≥1QSR 5.1.3 Simple NOR RS-FF 或非门构成的RS 触发器SR Q n +10 0Q n0 101 011 1uncertainTruth table of NOR Gates RS-FFInputs S , R : Active highS = 1, R = 0, Q = 1, S : set 1R = 1, S = 0, Q = 0, R : reset 016Rising (positive) edge 时钟信号: CLKFalling (negative) edge§5.2 Clocked (Synchronous) FF, 时钟触发器( 同步触发器)In digital systems, we often require some FF ’s to act at the same time. Synchronous signals are introduced as clocks for these FF ’s to this end, such that state transitions for clocked FF ’s happen only when the synchronous signals appear.在数字系统中，为协调各部分动作，需要某些FF 在同一时刻动作。

因此引入同步信号，使这些FF 只有在同步信号到达时才根据输入信号改变状态。

同步信号被称时钟脉冲信号。

Periodical square wave pulses 周期性方波脉冲信号17Add G 3 and G 4to a simple RS-FF, G 3and G 4are unlocked only when CLK =1, and locked when CLK = 0Definition:n Q n+1Q : State before the active edge: current state (现态): State after the active edge: next state (次态)nQ 1n Q +nQ 1n Q +Thus the clocked RS-FF works only when CLK =11Active –positive edge 正边沿有效CLK12QCurrent state and next state exist for each clock 每一个时钟周期CLK 都有现态和次态Q n , Q n+1G 1G 3G 2G 4RCLK ＆＆＆＆QQS 5.2.1 Clocked RS-FF18l S =R =0 FF no changeQ n+1=Q n010011φφS =R =0Q n+1=Q n R ≠S Q n+1=S 0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1CommentsQ n+1S R Q n S RQ Q FF state0 00 11 01 11 0Set (1)0 1Reset (0)NC NC No-change1 1S R 0→1不定RCLK＆＆＆＆QQ SG 3G 4R S Truth table of clocked RS-FFl S =0, R =1G 3=1, G 4=0Q n+1=0l S =1, R =0G 3=0, G 4=1 Q n+1=1R =S =1, Q =Q =1S R 1 →0 φl S =1, R =1 G 3=G 4=0, Q =Q S and R 1→0, Q uncertain19Q QS CLKRSymbolQ n+1Q Inputs ~ Outputs 输入和输出的关系（不同时为1）同步RS-FF 特征方程Drawbacks:Uncertain states 存在不确定状态Q n+1= S + RQ n S •R = 0205.2.2 Clocked D-FF, 时钟D 触发器(同步D-FF)D =1, (S =1, R =0) Q n+1= 1时钟D-FF 的特征方程:Q n+1= DSymbol:1&&&&CLKDS RQQConnect S and R with a NOT gateS ≠R Function:CLK =0, FF locked CLK =1, FF working S =D , R = D to eliminate uncertain statesD =0, (S =0, R =1) Q n+1= 0DCLKQQIEEEQ Q 1DC1DCLKcontrol215.2.3 Clocked JK-FFTwo feedback lines to the inputs,nnS JQ R KQ ==&&&&CLKJKQ Q01110Q 111Q 10 2 inputs: J , K CLK =0, locked;CLK =1, workingQ , Q 不同时为1，R S 不同时0→1no uncertain stateSR 011Q 001101Q1001110022State equation (Characteristic equation)From RS-FF :1n n n nnnnQS RQJ Q KQ Q J Q KQ+=+=+=+SymbolQ n+1Q Q n+1= JQ + KQ nJCLKKQQCLK 高电平有效23JK-FF 激励表JK-FF 状态图f ==0J K ==0Φ1 11Φ1 0Φ10 1Φ00 0K J Q n →Q n +1FF input Output transitions0 000 0 10 1 00 1 11 0 01 0 11 1 01 1 1Q n+1J K Q n 01001110JK-FF 真值表245.2.4 Clocked T-FF （Toggle ）J = K = TTCharacteristics equation1nn n nQTQ TQ T Q +=+=ÅT =1,1n n QQ+=1nn QQ+=Q QTCLKKCLKJQQT =0,No change Toggle255.2.5 Drawbacks of synchronous FF 时钟触发器的缺点Clocked FF ’s are triggered when CLK =1, and the states would switch as the changes of input signals. Hence, the states of clocked FF ’s would switch multiple times during one period. 触发器处于触发状态，其次态Q n+1随输入信号的变化而变化，有可能出现随输入信号变化多次的情况。